1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H 16 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H 17 18 #include "SystemZ.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/SelectionDAG.h" 21 #include "llvm/Target/TargetLowering.h" 22 23 namespace llvm { 24 namespace SystemZISD { 25 enum NodeType : unsigned { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 28 // Return with a flag operand. Operand 0 is the chain operand. 29 RET_FLAG, 30 31 // Calls a function. Operand 0 is the chain operand and operand 1 32 // is the target address. The arguments start at operand 2. 33 // There is an optional glue operand at the end. 34 CALL, 35 SIBCALL, 36 37 // TLS calls. Like regular calls, except operand 1 is the TLS symbol. 38 // (The call target is implicitly __tls_get_offset.) 39 TLS_GDCALL, 40 TLS_LDCALL, 41 42 // Wraps a TargetGlobalAddress that should be loaded using PC-relative 43 // accesses (LARL). Operand 0 is the address. 44 PCREL_WRAPPER, 45 46 // Used in cases where an offset is applied to a TargetGlobalAddress. 47 // Operand 0 is the full TargetGlobalAddress and operand 1 is a 48 // PCREL_WRAPPER for an anchor point. This is used so that we can 49 // cheaply refer to either the full address or the anchor point 50 // as a register base. 51 PCREL_OFFSET, 52 53 // Integer absolute. 54 IABS, 55 56 // Integer comparisons. There are three operands: the two values 57 // to compare, and an integer of type SystemZICMP. 58 ICMP, 59 60 // Floating-point comparisons. The two operands are the values to compare. 61 FCMP, 62 63 // Test under mask. The first operand is ANDed with the second operand 64 // and the condition codes are set on the result. The third operand is 65 // a boolean that is true if the condition codes need to distinguish 66 // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the 67 // register forms do but the memory forms don't). 68 TM, 69 70 // Branches if a condition is true. Operand 0 is the chain operand; 71 // operand 1 is the 4-bit condition-code mask, with bit N in 72 // big-endian order meaning "branch if CC=N"; operand 2 is the 73 // target block and operand 3 is the flag operand. 74 BR_CCMASK, 75 76 // Selects between operand 0 and operand 1. Operand 2 is the 77 // mask of condition-code values for which operand 0 should be 78 // chosen over operand 1; it has the same form as BR_CCMASK. 79 // Operand 3 is the flag operand. 80 SELECT_CCMASK, 81 82 // Evaluates to the gap between the stack pointer and the 83 // base of the dynamically-allocatable area. 84 ADJDYNALLOC, 85 86 // Count number of bits set in operand 0 per byte. 87 POPCNT, 88 89 // Wrappers around the ISD opcodes of the same name. The output is GR128. 90 // Input operands may be GR64 or GR32, depending on the instruction. 91 SMUL_LOHI, 92 UMUL_LOHI, 93 SDIVREM, 94 UDIVREM, 95 96 // Use a series of MVCs to copy bytes from one memory location to another. 97 // The operands are: 98 // - the target address 99 // - the source address 100 // - the constant length 101 // 102 // This isn't a memory opcode because we'd need to attach two 103 // MachineMemOperands rather than one. 104 MVC, 105 106 // Like MVC, but implemented as a loop that handles X*256 bytes 107 // followed by straight-line code to handle the rest (if any). 108 // The value of X is passed as an additional operand. 109 MVC_LOOP, 110 111 // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR). 112 NC, 113 NC_LOOP, 114 OC, 115 OC_LOOP, 116 XC, 117 XC_LOOP, 118 119 // Use CLC to compare two blocks of memory, with the same comments 120 // as for MVC and MVC_LOOP. 121 CLC, 122 CLC_LOOP, 123 124 // Use an MVST-based sequence to implement stpcpy(). 125 STPCPY, 126 127 // Use a CLST-based sequence to implement strcmp(). The two input operands 128 // are the addresses of the strings to compare. 129 STRCMP, 130 131 // Use an SRST-based sequence to search a block of memory. The first 132 // operand is the end address, the second is the start, and the third 133 // is the character to search for. CC is set to 1 on success and 2 134 // on failure. 135 SEARCH_STRING, 136 137 // Store the CC value in bits 29 and 28 of an integer. 138 IPM, 139 140 // Compiler barrier only; generate a no-op. 141 MEMBARRIER, 142 143 // Transaction begin. The first operand is the chain, the second 144 // the TDB pointer, and the third the immediate control field. 145 // Returns chain and glue. 146 TBEGIN, 147 TBEGIN_NOFLOAT, 148 149 // Transaction end. Just the chain operand. Returns chain and glue. 150 TEND, 151 152 // Create a vector constant by filling byte N of the result with bit 153 // 15-N of the single operand. 154 BYTE_MASK, 155 156 // Create a vector constant by replicating an element-sized RISBG-style mask. 157 // The first operand specifies the starting set bit and the second operand 158 // specifies the ending set bit. Both operands count from the MSB of the 159 // element. 160 ROTATE_MASK, 161 162 // Replicate a GPR scalar value into all elements of a vector. 163 REPLICATE, 164 165 // Create a vector from two i64 GPRs. 166 JOIN_DWORDS, 167 168 // Replicate one element of a vector into all elements. The first operand 169 // is the vector and the second is the index of the element to replicate. 170 SPLAT, 171 172 // Interleave elements from the high half of operand 0 and the high half 173 // of operand 1. 174 MERGE_HIGH, 175 176 // Likewise for the low halves. 177 MERGE_LOW, 178 179 // Concatenate the vectors in the first two operands, shift them left 180 // by the third operand, and take the first half of the result. 181 SHL_DOUBLE, 182 183 // Take one element of the first v2i64 operand and the one element of 184 // the second v2i64 operand and concatenate them to form a v2i64 result. 185 // The third operand is a 4-bit value of the form 0A0B, where A and B 186 // are the element selectors for the first operand and second operands 187 // respectively. 188 PERMUTE_DWORDS, 189 190 // Perform a general vector permute on vector operands 0 and 1. 191 // Each byte of operand 2 controls the corresponding byte of the result, 192 // in the same way as a byte-level VECTOR_SHUFFLE mask. 193 PERMUTE, 194 195 // Pack vector operands 0 and 1 into a single vector with half-sized elements. 196 PACK, 197 198 // Likewise, but saturate the result and set CC. PACKS_CC does signed 199 // saturation and PACKLS_CC does unsigned saturation. 200 PACKS_CC, 201 PACKLS_CC, 202 203 // Unpack the first half of vector operand 0 into double-sized elements. 204 // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends. 205 UNPACK_HIGH, 206 UNPACKL_HIGH, 207 208 // Likewise for the second half. 209 UNPACK_LOW, 210 UNPACKL_LOW, 211 212 // Shift each element of vector operand 0 by the number of bits specified 213 // by scalar operand 1. 214 VSHL_BY_SCALAR, 215 VSRL_BY_SCALAR, 216 VSRA_BY_SCALAR, 217 218 // For each element of the output type, sum across all sub-elements of 219 // operand 0 belonging to the corresponding element, and add in the 220 // rightmost sub-element of the corresponding element of operand 1. 221 VSUM, 222 223 // Compare integer vector operands 0 and 1 to produce the usual 0/-1 224 // vector result. VICMPE is for equality, VICMPH for "signed greater than" 225 // and VICMPHL for "unsigned greater than". 226 VICMPE, 227 VICMPH, 228 VICMPHL, 229 230 // Likewise, but also set the condition codes on the result. 231 VICMPES, 232 VICMPHS, 233 VICMPHLS, 234 235 // Compare floating-point vector operands 0 and 1 to preoduce the usual 0/-1 236 // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and 237 // greater than" and VFCMPHE for "ordered and greater than or equal to". 238 VFCMPE, 239 VFCMPH, 240 VFCMPHE, 241 242 // Likewise, but also set the condition codes on the result. 243 VFCMPES, 244 VFCMPHS, 245 VFCMPHES, 246 247 // Test floating-point data class for vectors. 248 VFTCI, 249 250 // Extend the even f32 elements of vector operand 0 to produce a vector 251 // of f64 elements. 252 VEXTEND, 253 254 // Round the f64 elements of vector operand 0 to f32s and store them in the 255 // even elements of the result. 256 VROUND, 257 258 // AND the two vector operands together and set CC based on the result. 259 VTM, 260 261 // String operations that set CC as a side-effect. 262 VFAE_CC, 263 VFAEZ_CC, 264 VFEE_CC, 265 VFEEZ_CC, 266 VFENE_CC, 267 VFENEZ_CC, 268 VISTR_CC, 269 VSTRC_CC, 270 VSTRCZ_CC, 271 272 // Test Data Class. 273 // 274 // Operand 0: the value to test 275 // Operand 1: the bit mask 276 TDC, 277 278 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or 279 // ATOMIC_LOAD_<op>. 280 // 281 // Operand 0: the address of the containing 32-bit-aligned field 282 // Operand 1: the second operand of <op>, in the high bits of an i32 283 // for everything except ATOMIC_SWAPW 284 // Operand 2: how many bits to rotate the i32 left to bring the first 285 // operand into the high bits 286 // Operand 3: the negative of operand 2, for rotating the other way 287 // Operand 4: the width of the field in bits (8 or 16) 288 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE, 289 ATOMIC_LOADW_ADD, 290 ATOMIC_LOADW_SUB, 291 ATOMIC_LOADW_AND, 292 ATOMIC_LOADW_OR, 293 ATOMIC_LOADW_XOR, 294 ATOMIC_LOADW_NAND, 295 ATOMIC_LOADW_MIN, 296 ATOMIC_LOADW_MAX, 297 ATOMIC_LOADW_UMIN, 298 ATOMIC_LOADW_UMAX, 299 300 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP. 301 // 302 // Operand 0: the address of the containing 32-bit-aligned field 303 // Operand 1: the compare value, in the low bits of an i32 304 // Operand 2: the swap value, in the low bits of an i32 305 // Operand 3: how many bits to rotate the i32 left to bring the first 306 // operand into the high bits 307 // Operand 4: the negative of operand 2, for rotating the other way 308 // Operand 5: the width of the field in bits (8 or 16) 309 ATOMIC_CMP_SWAPW, 310 311 // Byte swapping load. 312 // 313 // Operand 0: the address to load from 314 // Operand 1: the type of load (i16, i32, i64) 315 LRV, 316 317 // Byte swapping store. 318 // 319 // Operand 0: the value to store 320 // Operand 1: the address to store to 321 // Operand 2: the type of store (i16, i32, i64) 322 STRV, 323 324 // Prefetch from the second operand using the 4-bit control code in 325 // the first operand. The code is 1 for a load prefetch and 2 for 326 // a store prefetch. 327 PREFETCH 328 }; 329 330 // Return true if OPCODE is some kind of PC-relative address. 331 inline bool isPCREL(unsigned Opcode) { 332 return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET; 333 } 334 } // end namespace SystemZISD 335 336 namespace SystemZICMP { 337 // Describes whether an integer comparison needs to be signed or unsigned, 338 // or whether either type is OK. 339 enum { 340 Any, 341 UnsignedOnly, 342 SignedOnly 343 }; 344 } // end namespace SystemZICMP 345 346 class SystemZSubtarget; 347 class SystemZTargetMachine; 348 349 class SystemZTargetLowering : public TargetLowering { 350 public: 351 explicit SystemZTargetLowering(const TargetMachine &TM, 352 const SystemZSubtarget &STI); 353 354 // Override TargetLowering. 355 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 356 return MVT::i32; 357 } 358 MVT getVectorIdxTy(const DataLayout &DL) const override { 359 // Only the lower 12 bits of an element index are used, so we don't 360 // want to clobber the upper 32 bits of a GPR unnecessarily. 361 return MVT::i32; 362 } 363 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) 364 const override { 365 // Widen subvectors to the full width rather than promoting integer 366 // elements. This is better because: 367 // 368 // (a) it means that we can handle the ABI for passing and returning 369 // sub-128 vectors without having to handle them as legal types. 370 // 371 // (b) we don't have instructions to extend on load and truncate on store, 372 // so promoting the integers is less efficient. 373 // 374 // (c) there are no multiplication instructions for the widest integer 375 // type (v2i64). 376 if (VT.getScalarSizeInBits() % 8 == 0) 377 return TypeWidenVector; 378 return TargetLoweringBase::getPreferredVectorAction(VT); 379 } 380 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, 381 EVT) const override; 382 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 383 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 384 bool isLegalICmpImmediate(int64_t Imm) const override; 385 bool isLegalAddImmediate(int64_t Imm) const override; 386 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 387 unsigned AS) const override; 388 bool isFoldableMemAccessOffset(Instruction *I, int64_t Offset) const override; 389 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, 390 unsigned Align, 391 bool *Fast) const override; 392 bool isTruncateFree(Type *, Type *) const override; 393 bool isTruncateFree(EVT, EVT) const override; 394 const char *getTargetNodeName(unsigned Opcode) const override; 395 std::pair<unsigned, const TargetRegisterClass *> 396 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 397 StringRef Constraint, MVT VT) const override; 398 TargetLowering::ConstraintType 399 getConstraintType(StringRef Constraint) const override; 400 TargetLowering::ConstraintWeight 401 getSingleConstraintMatchWeight(AsmOperandInfo &info, 402 const char *constraint) const override; 403 void LowerAsmOperandForConstraint(SDValue Op, 404 std::string &Constraint, 405 std::vector<SDValue> &Ops, 406 SelectionDAG &DAG) const override; 407 408 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 409 if (ConstraintCode.size() == 1) { 410 switch(ConstraintCode[0]) { 411 default: 412 break; 413 case 'Q': 414 return InlineAsm::Constraint_Q; 415 case 'R': 416 return InlineAsm::Constraint_R; 417 case 'S': 418 return InlineAsm::Constraint_S; 419 case 'T': 420 return InlineAsm::Constraint_T; 421 } 422 } 423 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 424 } 425 426 /// If a physical register, this returns the register that receives the 427 /// exception address on entry to an EH pad. 428 unsigned 429 getExceptionPointerRegister(const Constant *PersonalityFn) const override { 430 return SystemZ::R6D; 431 } 432 433 /// If a physical register, this returns the register that receives the 434 /// exception typeid on entry to a landing pad. 435 unsigned 436 getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 437 return SystemZ::R7D; 438 } 439 440 /// Override to support customized stack guard loading. 441 bool useLoadStackGuardNode() const override { 442 return true; 443 } 444 void insertSSPDeclarations(Module &M) const override { 445 } 446 447 MachineBasicBlock * 448 EmitInstrWithCustomInserter(MachineInstr &MI, 449 MachineBasicBlock *BB) const override; 450 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 451 bool allowTruncateForTailCall(Type *, Type *) const override; 452 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 453 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 454 bool isVarArg, 455 const SmallVectorImpl<ISD::InputArg> &Ins, 456 const SDLoc &DL, SelectionDAG &DAG, 457 SmallVectorImpl<SDValue> &InVals) const override; 458 SDValue LowerCall(CallLoweringInfo &CLI, 459 SmallVectorImpl<SDValue> &InVals) const override; 460 461 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 462 bool isVarArg, 463 const SmallVectorImpl<ISD::OutputArg> &Outs, 464 LLVMContext &Context) const override; 465 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 466 const SmallVectorImpl<ISD::OutputArg> &Outs, 467 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 468 SelectionDAG &DAG) const override; 469 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 470 471 ISD::NodeType getExtendForAtomicOps() const override { 472 return ISD::ANY_EXTEND; 473 } 474 475 bool supportSwiftError() const override { 476 return true; 477 } 478 479 private: 480 const SystemZSubtarget &Subtarget; 481 482 // Implement LowerOperation for individual opcodes. 483 SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode, 484 const SDLoc &DL, EVT VT, 485 SDValue CmpOp0, SDValue CmpOp1) const; 486 SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL, 487 EVT VT, ISD::CondCode CC, 488 SDValue CmpOp0, SDValue CmpOp1) const; 489 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 490 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 491 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 492 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node, 493 SelectionDAG &DAG) const; 494 SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node, 495 SelectionDAG &DAG, unsigned Opcode, 496 SDValue GOTOffset) const; 497 SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const; 498 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node, 499 SelectionDAG &DAG) const; 500 SDValue lowerBlockAddress(BlockAddressSDNode *Node, 501 SelectionDAG &DAG) const; 502 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const; 503 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const; 504 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 505 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 506 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 507 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 508 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 509 SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const; 510 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 511 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 512 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const; 513 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 514 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 515 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const; 516 SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const; 517 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; 518 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const; 519 SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const; 520 SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG, 521 unsigned Opcode) const; 522 SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const; 523 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 524 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; 525 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; 526 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const; 527 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 528 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 529 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 530 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 531 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 532 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 533 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 534 SDValue lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG, 535 unsigned UnpackHigh) const; 536 SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const; 537 538 bool canTreatAsByteVector(EVT VT) const; 539 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp, 540 unsigned Index, DAGCombinerInfo &DCI, 541 bool Force) const; 542 SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op, 543 DAGCombinerInfo &DCI) const; 544 SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const; 545 SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const; 546 SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const; 547 SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const; 548 SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const; 549 SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const; 550 SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const; 551 SDValue combineSHIFTROT(SDNode *N, DAGCombinerInfo &DCI) const; 552 553 // If the last instruction before MBBI in MBB was some form of COMPARE, 554 // try to replace it with a COMPARE AND BRANCH just before MBBI. 555 // CCMask and Target are the BRC-like operands for the branch. 556 // Return true if the change was made. 557 bool convertPrevCompareToBranch(MachineBasicBlock *MBB, 558 MachineBasicBlock::iterator MBBI, 559 unsigned CCMask, 560 MachineBasicBlock *Target) const; 561 562 // Implement EmitInstrWithCustomInserter for individual operation types. 563 MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB, 564 unsigned LOCROpcode) const; 565 MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB, 566 unsigned StoreOpcode, unsigned STOCOpcode, 567 bool Invert) const; 568 MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB, 569 bool ClearEven) const; 570 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI, 571 MachineBasicBlock *BB, 572 unsigned BinOpcode, unsigned BitSize, 573 bool Invert = false) const; 574 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI, 575 MachineBasicBlock *MBB, 576 unsigned CompareOpcode, 577 unsigned KeepOldMask, 578 unsigned BitSize) const; 579 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI, 580 MachineBasicBlock *BB) const; 581 MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB, 582 unsigned Opcode) const; 583 MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB, 584 unsigned Opcode) const; 585 MachineBasicBlock *emitTransactionBegin(MachineInstr &MI, 586 MachineBasicBlock *MBB, 587 unsigned Opcode, bool NoFloat) const; 588 MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI, 589 MachineBasicBlock *MBB, 590 unsigned Opcode) const; 591 592 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override; 593 }; 594 } // end namespace llvm 595 596 #endif 597