1 //===-- SparcAsmBackend.cpp - Sparc Assembler Backend ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/SparcFixupKinds.h" 11 #include "MCTargetDesc/SparcMCTargetDesc.h" 12 #include "llvm/MC/MCAsmBackend.h" 13 #include "llvm/MC/MCELFObjectWriter.h" 14 #include "llvm/MC/MCExpr.h" 15 #include "llvm/MC/MCFixupKindInfo.h" 16 #include "llvm/MC/MCObjectWriter.h" 17 #include "llvm/MC/MCSubtargetInfo.h" 18 #include "llvm/MC/MCValue.h" 19 #include "llvm/Support/TargetRegistry.h" 20 21 using namespace llvm; 22 23 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { 24 switch (Kind) { 25 default: 26 llvm_unreachable("Unknown fixup kind!"); 27 case FK_Data_1: 28 case FK_Data_2: 29 case FK_Data_4: 30 case FK_Data_8: 31 return Value; 32 33 case Sparc::fixup_sparc_wplt30: 34 case Sparc::fixup_sparc_call30: 35 return (Value >> 2) & 0x3fffffff; 36 37 case Sparc::fixup_sparc_br22: 38 return (Value >> 2) & 0x3fffff; 39 40 case Sparc::fixup_sparc_br19: 41 return (Value >> 2) & 0x7ffff; 42 43 case Sparc::fixup_sparc_br16_2: 44 return (Value >> 2) & 0xc000; 45 46 case Sparc::fixup_sparc_br16_14: 47 return (Value >> 2) & 0x3fff; 48 49 case Sparc::fixup_sparc_pc22: 50 case Sparc::fixup_sparc_got22: 51 case Sparc::fixup_sparc_tls_gd_hi22: 52 case Sparc::fixup_sparc_tls_ldm_hi22: 53 case Sparc::fixup_sparc_tls_ie_hi22: 54 case Sparc::fixup_sparc_hi22: 55 return (Value >> 10) & 0x3fffff; 56 57 case Sparc::fixup_sparc_pc10: 58 case Sparc::fixup_sparc_got10: 59 case Sparc::fixup_sparc_tls_gd_lo10: 60 case Sparc::fixup_sparc_tls_ldm_lo10: 61 case Sparc::fixup_sparc_tls_ie_lo10: 62 case Sparc::fixup_sparc_lo10: 63 return Value & 0x3ff; 64 65 case Sparc::fixup_sparc_h44: 66 return (Value >> 22) & 0x3fffff; 67 68 case Sparc::fixup_sparc_m44: 69 return (Value >> 12) & 0x3ff; 70 71 case Sparc::fixup_sparc_l44: 72 return Value & 0xfff; 73 74 case Sparc::fixup_sparc_hh: 75 return (Value >> 42) & 0x3fffff; 76 77 case Sparc::fixup_sparc_hm: 78 return (Value >> 32) & 0x3ff; 79 80 case Sparc::fixup_sparc_tls_ldo_hix22: 81 case Sparc::fixup_sparc_tls_le_hix22: 82 case Sparc::fixup_sparc_tls_ldo_lox10: 83 case Sparc::fixup_sparc_tls_le_lox10: 84 assert(Value == 0 && "Sparc TLS relocs expect zero Value"); 85 return 0; 86 87 case Sparc::fixup_sparc_tls_gd_add: 88 case Sparc::fixup_sparc_tls_gd_call: 89 case Sparc::fixup_sparc_tls_ldm_add: 90 case Sparc::fixup_sparc_tls_ldm_call: 91 case Sparc::fixup_sparc_tls_ldo_add: 92 case Sparc::fixup_sparc_tls_ie_ld: 93 case Sparc::fixup_sparc_tls_ie_ldx: 94 case Sparc::fixup_sparc_tls_ie_add: 95 return 0; 96 } 97 } 98 99 namespace { 100 class SparcAsmBackend : public MCAsmBackend { 101 protected: 102 const Target &TheTarget; 103 bool IsLittleEndian; 104 bool Is64Bit; 105 106 public: 107 SparcAsmBackend(const Target &T) 108 : MCAsmBackend(), TheTarget(T), 109 IsLittleEndian(StringRef(TheTarget.getName()) == "sparcel"), 110 Is64Bit(StringRef(TheTarget.getName()) == "sparcv9") {} 111 112 unsigned getNumFixupKinds() const override { 113 return Sparc::NumTargetFixupKinds; 114 } 115 116 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { 117 const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = { 118 // name offset bits flags 119 { "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel }, 120 { "fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel }, 121 { "fixup_sparc_br19", 13, 19, MCFixupKindInfo::FKF_IsPCRel }, 122 { "fixup_sparc_br16_2", 10, 2, MCFixupKindInfo::FKF_IsPCRel }, 123 { "fixup_sparc_br16_14", 18, 14, MCFixupKindInfo::FKF_IsPCRel }, 124 { "fixup_sparc_hi22", 10, 22, 0 }, 125 { "fixup_sparc_lo10", 22, 10, 0 }, 126 { "fixup_sparc_h44", 10, 22, 0 }, 127 { "fixup_sparc_m44", 22, 10, 0 }, 128 { "fixup_sparc_l44", 20, 12, 0 }, 129 { "fixup_sparc_hh", 10, 22, 0 }, 130 { "fixup_sparc_hm", 22, 10, 0 }, 131 { "fixup_sparc_pc22", 10, 22, MCFixupKindInfo::FKF_IsPCRel }, 132 { "fixup_sparc_pc10", 22, 10, MCFixupKindInfo::FKF_IsPCRel }, 133 { "fixup_sparc_got22", 10, 22, 0 }, 134 { "fixup_sparc_got10", 22, 10, 0 }, 135 { "fixup_sparc_wplt30", 2, 30, MCFixupKindInfo::FKF_IsPCRel }, 136 { "fixup_sparc_tls_gd_hi22", 10, 22, 0 }, 137 { "fixup_sparc_tls_gd_lo10", 22, 10, 0 }, 138 { "fixup_sparc_tls_gd_add", 0, 0, 0 }, 139 { "fixup_sparc_tls_gd_call", 0, 0, 0 }, 140 { "fixup_sparc_tls_ldm_hi22", 10, 22, 0 }, 141 { "fixup_sparc_tls_ldm_lo10", 22, 10, 0 }, 142 { "fixup_sparc_tls_ldm_add", 0, 0, 0 }, 143 { "fixup_sparc_tls_ldm_call", 0, 0, 0 }, 144 { "fixup_sparc_tls_ldo_hix22", 10, 22, 0 }, 145 { "fixup_sparc_tls_ldo_lox10", 22, 10, 0 }, 146 { "fixup_sparc_tls_ldo_add", 0, 0, 0 }, 147 { "fixup_sparc_tls_ie_hi22", 10, 22, 0 }, 148 { "fixup_sparc_tls_ie_lo10", 22, 10, 0 }, 149 { "fixup_sparc_tls_ie_ld", 0, 0, 0 }, 150 { "fixup_sparc_tls_ie_ldx", 0, 0, 0 }, 151 { "fixup_sparc_tls_ie_add", 0, 0, 0 }, 152 { "fixup_sparc_tls_le_hix22", 0, 0, 0 }, 153 { "fixup_sparc_tls_le_lox10", 0, 0, 0 } 154 }; 155 156 const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = { 157 // name offset bits flags 158 { "fixup_sparc_call30", 0, 30, MCFixupKindInfo::FKF_IsPCRel }, 159 { "fixup_sparc_br22", 0, 22, MCFixupKindInfo::FKF_IsPCRel }, 160 { "fixup_sparc_br19", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, 161 { "fixup_sparc_br16_2", 20, 2, MCFixupKindInfo::FKF_IsPCRel }, 162 { "fixup_sparc_br16_14", 0, 14, MCFixupKindInfo::FKF_IsPCRel }, 163 { "fixup_sparc_hi22", 0, 22, 0 }, 164 { "fixup_sparc_lo10", 0, 10, 0 }, 165 { "fixup_sparc_h44", 0, 22, 0 }, 166 { "fixup_sparc_m44", 0, 10, 0 }, 167 { "fixup_sparc_l44", 0, 12, 0 }, 168 { "fixup_sparc_hh", 0, 22, 0 }, 169 { "fixup_sparc_hm", 0, 10, 0 }, 170 { "fixup_sparc_pc22", 0, 22, MCFixupKindInfo::FKF_IsPCRel }, 171 { "fixup_sparc_pc10", 0, 10, MCFixupKindInfo::FKF_IsPCRel }, 172 { "fixup_sparc_got22", 0, 22, 0 }, 173 { "fixup_sparc_got10", 0, 10, 0 }, 174 { "fixup_sparc_wplt30", 0, 30, MCFixupKindInfo::FKF_IsPCRel }, 175 { "fixup_sparc_tls_gd_hi22", 0, 22, 0 }, 176 { "fixup_sparc_tls_gd_lo10", 0, 10, 0 }, 177 { "fixup_sparc_tls_gd_add", 0, 0, 0 }, 178 { "fixup_sparc_tls_gd_call", 0, 0, 0 }, 179 { "fixup_sparc_tls_ldm_hi22", 0, 22, 0 }, 180 { "fixup_sparc_tls_ldm_lo10", 0, 10, 0 }, 181 { "fixup_sparc_tls_ldm_add", 0, 0, 0 }, 182 { "fixup_sparc_tls_ldm_call", 0, 0, 0 }, 183 { "fixup_sparc_tls_ldo_hix22", 0, 22, 0 }, 184 { "fixup_sparc_tls_ldo_lox10", 0, 10, 0 }, 185 { "fixup_sparc_tls_ldo_add", 0, 0, 0 }, 186 { "fixup_sparc_tls_ie_hi22", 0, 22, 0 }, 187 { "fixup_sparc_tls_ie_lo10", 0, 10, 0 }, 188 { "fixup_sparc_tls_ie_ld", 0, 0, 0 }, 189 { "fixup_sparc_tls_ie_ldx", 0, 0, 0 }, 190 { "fixup_sparc_tls_ie_add", 0, 0, 0 }, 191 { "fixup_sparc_tls_le_hix22", 0, 0, 0 }, 192 { "fixup_sparc_tls_le_lox10", 0, 0, 0 } 193 }; 194 195 if (Kind < FirstTargetFixupKind) 196 return MCAsmBackend::getFixupKindInfo(Kind); 197 198 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 199 "Invalid kind!"); 200 if (IsLittleEndian) 201 return InfosLE[Kind - FirstTargetFixupKind]; 202 203 return InfosBE[Kind - FirstTargetFixupKind]; 204 } 205 206 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, 207 const MCValue &Target) override { 208 switch ((Sparc::Fixups)Fixup.getKind()) { 209 default: 210 return false; 211 case Sparc::fixup_sparc_wplt30: 212 if (Target.getSymA()->getSymbol().isTemporary()) 213 return false; 214 LLVM_FALLTHROUGH; 215 case Sparc::fixup_sparc_tls_gd_hi22: 216 case Sparc::fixup_sparc_tls_gd_lo10: 217 case Sparc::fixup_sparc_tls_gd_add: 218 case Sparc::fixup_sparc_tls_gd_call: 219 case Sparc::fixup_sparc_tls_ldm_hi22: 220 case Sparc::fixup_sparc_tls_ldm_lo10: 221 case Sparc::fixup_sparc_tls_ldm_add: 222 case Sparc::fixup_sparc_tls_ldm_call: 223 case Sparc::fixup_sparc_tls_ldo_hix22: 224 case Sparc::fixup_sparc_tls_ldo_lox10: 225 case Sparc::fixup_sparc_tls_ldo_add: 226 case Sparc::fixup_sparc_tls_ie_hi22: 227 case Sparc::fixup_sparc_tls_ie_lo10: 228 case Sparc::fixup_sparc_tls_ie_ld: 229 case Sparc::fixup_sparc_tls_ie_ldx: 230 case Sparc::fixup_sparc_tls_ie_add: 231 case Sparc::fixup_sparc_tls_le_hix22: 232 case Sparc::fixup_sparc_tls_le_lox10: 233 return true; 234 } 235 } 236 237 bool mayNeedRelaxation(const MCInst &Inst) const override { 238 // FIXME. 239 return false; 240 } 241 242 /// fixupNeedsRelaxation - Target specific predicate for whether a given 243 /// fixup requires the associated instruction to be relaxed. 244 bool fixupNeedsRelaxation(const MCFixup &Fixup, 245 uint64_t Value, 246 const MCRelaxableFragment *DF, 247 const MCAsmLayout &Layout) const override { 248 // FIXME. 249 llvm_unreachable("fixupNeedsRelaxation() unimplemented"); 250 return false; 251 } 252 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, 253 MCInst &Res) const override { 254 // FIXME. 255 llvm_unreachable("relaxInstruction() unimplemented"); 256 } 257 258 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override { 259 // Cannot emit NOP with size not multiple of 32 bits. 260 if (Count % 4 != 0) 261 return false; 262 263 uint64_t NumNops = Count / 4; 264 for (uint64_t i = 0; i != NumNops; ++i) 265 OW->write32(0x01000000); 266 267 return true; 268 } 269 }; 270 271 class ELFSparcAsmBackend : public SparcAsmBackend { 272 Triple::OSType OSType; 273 public: 274 ELFSparcAsmBackend(const Target &T, Triple::OSType OSType) : 275 SparcAsmBackend(T), OSType(OSType) { } 276 277 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 278 const MCValue &Target, MutableArrayRef<char> Data, 279 uint64_t Value, bool IsResolved) const override { 280 281 Value = adjustFixupValue(Fixup.getKind(), Value); 282 if (!Value) return; // Doesn't change encoding. 283 284 unsigned Offset = Fixup.getOffset(); 285 286 // For each byte of the fragment that the fixup touches, mask in the bits 287 // from the fixup value. The Value has been "split up" into the 288 // appropriate bitfields above. 289 for (unsigned i = 0; i != 4; ++i) { 290 unsigned Idx = IsLittleEndian ? i : 3 - i; 291 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff); 292 } 293 } 294 295 std::unique_ptr<MCObjectWriter> 296 createObjectWriter(raw_pwrite_stream &OS) const override { 297 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType); 298 return createSparcELFObjectWriter(OS, Is64Bit, IsLittleEndian, OSABI); 299 } 300 }; 301 302 } // end anonymous namespace 303 304 MCAsmBackend *llvm::createSparcAsmBackend(const Target &T, 305 const MCSubtargetInfo &STI, 306 const MCRegisterInfo &MRI, 307 const MCTargetOptions &Options) { 308 return new ELFSparcAsmBackend(T, STI.getTargetTriple().getOS()); 309 } 310