1 //===- RISCVMatInt.cpp - Immediate materialisation -------------*- C++ -*--===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "RISCVMatInt.h" 11 #include "MCTargetDesc/RISCVMCTargetDesc.h" 12 #include "llvm/ADT/SmallVector.h" 13 #include "llvm/Support/MachineValueType.h" 14 #include "llvm/Support/MathExtras.h" 15 #include <cstdint> 16 17 namespace llvm { 18 19 namespace RISCVMatInt { 20 void generateInstSeq(int64_t Val, bool Is64Bit, InstSeq &Res) { 21 if (isInt<32>(Val)) { 22 // Depending on the active bits in the immediate Value v, the following 23 // instruction sequences are emitted: 24 // 25 // v == 0 : ADDI 26 // v[0,12) != 0 && v[12,32) == 0 : ADDI 27 // v[0,12) == 0 && v[12,32) != 0 : LUI 28 // v[0,32) != 0 : LUI+ADDI(W) 29 int64_t Hi20 = ((Val + 0x800) >> 12) & 0xFFFFF; 30 int64_t Lo12 = SignExtend64<12>(Val); 31 32 if (Hi20) 33 Res.push_back(Inst(RISCV::LUI, Hi20)); 34 35 if (Lo12 || Hi20 == 0) { 36 unsigned AddiOpc = (Is64Bit && Hi20) ? RISCV::ADDIW : RISCV::ADDI; 37 Res.push_back(Inst(AddiOpc, Lo12)); 38 } 39 return; 40 } 41 42 assert(Is64Bit && "Can't emit >32-bit imm for non-RV64 target"); 43 44 // In the worst case, for a full 64-bit constant, a sequence of 8 instructions 45 // (i.e., LUI+ADDIW+SLLI+ADDI+SLLI+ADDI+SLLI+ADDI) has to be emmitted. Note 46 // that the first two instructions (LUI+ADDIW) can contribute up to 32 bits 47 // while the following ADDI instructions contribute up to 12 bits each. 48 // 49 // On the first glance, implementing this seems to be possible by simply 50 // emitting the most significant 32 bits (LUI+ADDIW) followed by as many left 51 // shift (SLLI) and immediate additions (ADDI) as needed. However, due to the 52 // fact that ADDI performs a sign extended addition, doing it like that would 53 // only be possible when at most 11 bits of the ADDI instructions are used. 54 // Using all 12 bits of the ADDI instructions, like done by GAS, actually 55 // requires that the constant is processed starting with the least significant 56 // bit. 57 // 58 // In the following, constants are processed from LSB to MSB but instruction 59 // emission is performed from MSB to LSB by recursively calling 60 // generateInstSeq. In each recursion, first the lowest 12 bits are removed 61 // from the constant and the optimal shift amount, which can be greater than 62 // 12 bits if the constant is sparse, is determined. Then, the shifted 63 // remaining constant is processed recursively and gets emitted as soon as it 64 // fits into 32 bits. The emission of the shifts and additions is subsequently 65 // performed when the recursion returns. 66 67 int64_t Lo12 = SignExtend64<12>(Val); 68 int64_t Hi52 = (Val + 0x800) >> 12; 69 int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52); 70 Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount); 71 72 generateInstSeq(Hi52, Is64Bit, Res); 73 74 Res.push_back(Inst(RISCV::SLLI, ShiftAmount)); 75 if (Lo12) 76 Res.push_back(Inst(RISCV::ADDI, Lo12)); 77 } 78 } // namespace RISCVMatInt 79 } // namespace llvm 80