1 //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the RISCV implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "RISCVRegisterInfo.h"
15 #include "RISCV.h"
16 #include "RISCVSubtarget.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/RegisterScavenging.h"
21 #include "llvm/CodeGen/TargetFrameLowering.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 
25 #define GET_REGINFO_TARGET_DESC
26 #include "RISCVGenRegisterInfo.inc"
27 
28 using namespace llvm;
29 
30 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
31     : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
32                            /*PC*/0, HwMode) {}
33 
34 const MCPhysReg *
35 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
36   if (MF->getFunction().hasFnAttribute("interrupt")) {
37     if (MF->getSubtarget<RISCVSubtarget>().hasStdExtD())
38       return CSR_XLEN_F64_Interrupt_SaveList;
39     if (MF->getSubtarget<RISCVSubtarget>().hasStdExtF())
40       return CSR_XLEN_F32_Interrupt_SaveList;
41     return CSR_Interrupt_SaveList;
42   }
43   return CSR_SaveList;
44 }
45 
46 BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
47   BitVector Reserved(getNumRegs());
48 
49   // Use markSuperRegs to ensure any register aliases are also reserved
50   markSuperRegs(Reserved, RISCV::X0); // zero
51   markSuperRegs(Reserved, RISCV::X1); // ra
52   markSuperRegs(Reserved, RISCV::X2); // sp
53   markSuperRegs(Reserved, RISCV::X3); // gp
54   markSuperRegs(Reserved, RISCV::X4); // tp
55   markSuperRegs(Reserved, RISCV::X8); // fp
56   assert(checkAllSuperRegsMarked(Reserved));
57   return Reserved;
58 }
59 
60 bool RISCVRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
61   return PhysReg == RISCV::X0;
62 }
63 
64 const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
65   return CSR_NoRegs_RegMask;
66 }
67 
68 void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
69                                             int SPAdj, unsigned FIOperandNum,
70                                             RegScavenger *RS) const {
71   assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
72 
73   MachineInstr &MI = *II;
74   MachineFunction &MF = *MI.getParent()->getParent();
75   MachineRegisterInfo &MRI = MF.getRegInfo();
76   const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
77   DebugLoc DL = MI.getDebugLoc();
78 
79   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
80   unsigned FrameReg;
81   int Offset =
82       getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) +
83       MI.getOperand(FIOperandNum + 1).getImm();
84 
85   if (!isInt<32>(Offset)) {
86     report_fatal_error(
87         "Frame offsets outside of the signed 32-bit range not supported");
88   }
89 
90   MachineBasicBlock &MBB = *MI.getParent();
91   bool FrameRegIsKill = false;
92 
93   if (!isInt<12>(Offset)) {
94     assert(isInt<32>(Offset) && "Int32 expected");
95     // The offset won't fit in an immediate, so use a scratch register instead
96     // Modify Offset and FrameReg appropriately
97     unsigned ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
98     TII->movImm32(MBB, II, DL, ScratchReg, Offset);
99     BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
100         .addReg(FrameReg)
101         .addReg(ScratchReg, RegState::Kill);
102     Offset = 0;
103     FrameReg = ScratchReg;
104     FrameRegIsKill = true;
105   }
106 
107   MI.getOperand(FIOperandNum)
108       .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
109   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
110 }
111 
112 unsigned RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
113   const TargetFrameLowering *TFI = getFrameLowering(MF);
114   return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
115 }
116 
117 const uint32_t *
118 RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
119                                         CallingConv::ID /*CC*/) const {
120   if (MF.getFunction().hasFnAttribute("interrupt")) {
121     if (MF.getSubtarget<RISCVSubtarget>().hasStdExtD())
122       return CSR_XLEN_F64_Interrupt_RegMask;
123     if (MF.getSubtarget<RISCVSubtarget>().hasStdExtF())
124       return CSR_XLEN_F32_Interrupt_RegMask;
125     return CSR_Interrupt_RegMask;
126   }
127   return CSR_RegMask;
128 }
129