1 //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the RISCV implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "RISCVInstrInfo.h"
15 #include "RISCV.h"
16 #include "RISCVSubtarget.h"
17 #include "RISCVTargetMachine.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/TargetRegistry.h"
25 
26 #define GET_INSTRINFO_CTOR_DTOR
27 #include "RISCVGenInstrInfo.inc"
28 
29 using namespace llvm;
30 
31 RISCVInstrInfo::RISCVInstrInfo()
32     : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP) {}
33 
34 void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
35                                  MachineBasicBlock::iterator MBBI,
36                                  const DebugLoc &DL, unsigned DstReg,
37                                  unsigned SrcReg, bool KillSrc) const {
38   assert(RISCV::GPRRegClass.contains(DstReg, SrcReg) &&
39          "Impossible reg-to-reg copy");
40 
41   BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
42       .addReg(SrcReg, getKillRegState(KillSrc))
43       .addImm(0);
44 }
45 
46 void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
47                                          MachineBasicBlock::iterator I,
48                                          unsigned SrcReg, bool IsKill, int FI,
49                                          const TargetRegisterClass *RC,
50                                          const TargetRegisterInfo *TRI) const {
51   DebugLoc DL;
52   if (I != MBB.end())
53     DL = I->getDebugLoc();
54 
55   if (RISCV::GPRRegClass.hasSubClassEq(RC))
56     BuildMI(MBB, I, DL, get(RISCV::SW))
57         .addReg(SrcReg, getKillRegState(IsKill))
58         .addFrameIndex(FI)
59         .addImm(0);
60   else
61     llvm_unreachable("Can't store this register to stack slot");
62 }
63 
64 void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
65                                           MachineBasicBlock::iterator I,
66                                           unsigned DstReg, int FI,
67                                           const TargetRegisterClass *RC,
68                                           const TargetRegisterInfo *TRI) const {
69   DebugLoc DL;
70   if (I != MBB.end())
71     DL = I->getDebugLoc();
72 
73   if (RISCV::GPRRegClass.hasSubClassEq(RC))
74     BuildMI(MBB, I, DL, get(RISCV::LW), DstReg).addFrameIndex(FI).addImm(0);
75   else
76     llvm_unreachable("Can't load this register from stack slot");
77 }
78