1 //===-- RISCVAsmBackend.cpp - RISCV Assembler Backend ---------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "RISCVAsmBackend.h"
11 #include "RISCVMCExpr.h"
12 #include "llvm/ADT/APInt.h"
13 #include "llvm/MC/MCAssembler.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCDirectives.h"
16 #include "llvm/MC/MCELFObjectWriter.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCObjectWriter.h"
19 #include "llvm/MC/MCSymbol.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/raw_ostream.h"
22 
23 using namespace llvm;
24 
25 // If linker relaxation is enabled, or the relax option had previously been
26 // enabled, always emit relocations even if the fixup can be resolved. This is
27 // necessary for correctness as offsets may change during relaxation.
28 bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
29                                             const MCFixup &Fixup,
30                                             const MCValue &Target) {
31   bool ShouldForce = false;
32 
33   switch ((unsigned)Fixup.getKind()) {
34   default:
35     break;
36   case RISCV::fixup_riscv_pcrel_lo12_i:
37   case RISCV::fixup_riscv_pcrel_lo12_s:
38     // For pcrel_lo12, force a relocation if the target of the corresponding
39     // pcrel_hi20 is not in the same fragment.
40     const MCFixup *T = cast<RISCVMCExpr>(Fixup.getValue())->getPCRelHiFixup();
41     if (!T) {
42       Asm.getContext().reportError(Fixup.getLoc(),
43                                    "could not find corresponding %pcrel_hi");
44       return false;
45     }
46 
47     switch ((unsigned)T->getKind()) {
48     default:
49       llvm_unreachable("Unexpected fixup kind for pcrel_lo12");
50       break;
51     case RISCV::fixup_riscv_pcrel_hi20:
52       ShouldForce = T->getValue()->findAssociatedFragment() !=
53                     Fixup.getValue()->findAssociatedFragment();
54       break;
55     }
56     break;
57   }
58 
59   return ShouldForce || STI.getFeatureBits()[RISCV::FeatureRelax] ||
60          ForceRelocs;
61 }
62 
63 bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup,
64                                                    bool Resolved,
65                                                    uint64_t Value,
66                                                    const MCRelaxableFragment *DF,
67                                                    const MCAsmLayout &Layout,
68                                                    const bool WasForced) const {
69   // Return true if the symbol is actually unresolved.
70   // Resolved could be always false when shouldForceRelocation return true.
71   // We use !WasForced to indicate that the symbol is unresolved and not forced
72   // by shouldForceRelocation.
73   if (!Resolved && !WasForced)
74     return true;
75 
76   int64_t Offset = int64_t(Value);
77   switch ((unsigned)Fixup.getKind()) {
78   default:
79     return false;
80   case RISCV::fixup_riscv_rvc_branch:
81     // For compressed branch instructions the immediate must be
82     // in the range [-256, 254].
83     return Offset > 254 || Offset < -256;
84   case RISCV::fixup_riscv_rvc_jump:
85     // For compressed jump instructions the immediate must be
86     // in the range [-2048, 2046].
87     return Offset > 2046 || Offset < -2048;
88   }
89 }
90 
91 void RISCVAsmBackend::relaxInstruction(const MCInst &Inst,
92                                        const MCSubtargetInfo &STI,
93                                        MCInst &Res) const {
94   // TODO: replace this with call to auto generated uncompressinstr() function.
95   switch (Inst.getOpcode()) {
96   default:
97     llvm_unreachable("Opcode not expected!");
98   case RISCV::C_BEQZ:
99     // c.beqz $rs1, $imm -> beq $rs1, X0, $imm.
100     Res.setOpcode(RISCV::BEQ);
101     Res.addOperand(Inst.getOperand(0));
102     Res.addOperand(MCOperand::createReg(RISCV::X0));
103     Res.addOperand(Inst.getOperand(1));
104     break;
105   case RISCV::C_BNEZ:
106     // c.bnez $rs1, $imm -> bne $rs1, X0, $imm.
107     Res.setOpcode(RISCV::BNE);
108     Res.addOperand(Inst.getOperand(0));
109     Res.addOperand(MCOperand::createReg(RISCV::X0));
110     Res.addOperand(Inst.getOperand(1));
111     break;
112   case RISCV::C_J:
113     // c.j $imm -> jal X0, $imm.
114     Res.setOpcode(RISCV::JAL);
115     Res.addOperand(MCOperand::createReg(RISCV::X0));
116     Res.addOperand(Inst.getOperand(0));
117     break;
118   case RISCV::C_JAL:
119     // c.jal $imm -> jal X1, $imm.
120     Res.setOpcode(RISCV::JAL);
121     Res.addOperand(MCOperand::createReg(RISCV::X1));
122     Res.addOperand(Inst.getOperand(0));
123     break;
124   }
125 }
126 
127 // Given a compressed control flow instruction this function returns
128 // the expanded instruction.
129 unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
130   switch (Op) {
131   default:
132     return Op;
133   case RISCV::C_BEQZ:
134     return RISCV::BEQ;
135   case RISCV::C_BNEZ:
136     return RISCV::BNE;
137   case RISCV::C_J:
138   case RISCV::C_JAL: // fall through.
139     return RISCV::JAL;
140   }
141 }
142 
143 bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst,
144                                         const MCSubtargetInfo &STI) const {
145   return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
146 }
147 
148 bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
149   bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC];
150   unsigned MinNopLen = HasStdExtC ? 2 : 4;
151 
152   if ((Count % MinNopLen) != 0)
153     return false;
154 
155   // The canonical nop on RISC-V is addi x0, x0, 0.
156   uint64_t Nop32Count = Count / 4;
157   for (uint64_t i = Nop32Count; i != 0; --i)
158     OS.write("\x13\0\0\0", 4);
159 
160   // The canonical nop on RVC is c.nop.
161   if (HasStdExtC) {
162     uint64_t Nop16Count = (Count - Nop32Count * 4) / 2;
163     for (uint64_t i = Nop16Count; i != 0; --i)
164       OS.write("\x01\0", 2);
165   }
166 
167   return true;
168 }
169 
170 static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
171                                  MCContext &Ctx) {
172   unsigned Kind = Fixup.getKind();
173   switch (Kind) {
174   default:
175     llvm_unreachable("Unknown fixup kind!");
176   case FK_Data_1:
177   case FK_Data_2:
178   case FK_Data_4:
179   case FK_Data_8:
180     return Value;
181   case RISCV::fixup_riscv_lo12_i:
182   case RISCV::fixup_riscv_pcrel_lo12_i:
183     return Value & 0xfff;
184   case RISCV::fixup_riscv_lo12_s:
185   case RISCV::fixup_riscv_pcrel_lo12_s:
186     return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7);
187   case RISCV::fixup_riscv_hi20:
188   case RISCV::fixup_riscv_pcrel_hi20:
189     // Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
190     return ((Value + 0x800) >> 12) & 0xfffff;
191   case RISCV::fixup_riscv_jal: {
192     if (!isInt<21>(Value))
193       Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
194     if (Value & 0x1)
195       Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned");
196     // Need to produce imm[19|10:1|11|19:12] from the 21-bit Value.
197     unsigned Sbit = (Value >> 20) & 0x1;
198     unsigned Hi8 = (Value >> 12) & 0xff;
199     unsigned Mid1 = (Value >> 11) & 0x1;
200     unsigned Lo10 = (Value >> 1) & 0x3ff;
201     // Inst{31} = Sbit;
202     // Inst{30-21} = Lo10;
203     // Inst{20} = Mid1;
204     // Inst{19-12} = Hi8;
205     Value = (Sbit << 19) | (Lo10 << 9) | (Mid1 << 8) | Hi8;
206     return Value;
207   }
208   case RISCV::fixup_riscv_branch: {
209     if (!isInt<13>(Value))
210       Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
211     if (Value & 0x1)
212       Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned");
213     // Need to extract imm[12], imm[10:5], imm[4:1], imm[11] from the 13-bit
214     // Value.
215     unsigned Sbit = (Value >> 12) & 0x1;
216     unsigned Hi1 = (Value >> 11) & 0x1;
217     unsigned Mid6 = (Value >> 5) & 0x3f;
218     unsigned Lo4 = (Value >> 1) & 0xf;
219     // Inst{31} = Sbit;
220     // Inst{30-25} = Mid6;
221     // Inst{11-8} = Lo4;
222     // Inst{7} = Hi1;
223     Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7);
224     return Value;
225   }
226   case RISCV::fixup_riscv_call: {
227     // Jalr will add UpperImm with the sign-extended 12-bit LowerImm,
228     // we need to add 0x800ULL before extract upper bits to reflect the
229     // effect of the sign extension.
230     uint64_t UpperImm = (Value + 0x800ULL) & 0xfffff000ULL;
231     uint64_t LowerImm = Value & 0xfffULL;
232     return UpperImm | ((LowerImm << 20) << 32);
233   }
234   case RISCV::fixup_riscv_rvc_jump: {
235     // Need to produce offset[11|4|9:8|10|6|7|3:1|5] from the 11-bit Value.
236     unsigned Bit11  = (Value >> 11) & 0x1;
237     unsigned Bit4   = (Value >> 4) & 0x1;
238     unsigned Bit9_8 = (Value >> 8) & 0x3;
239     unsigned Bit10  = (Value >> 10) & 0x1;
240     unsigned Bit6   = (Value >> 6) & 0x1;
241     unsigned Bit7   = (Value >> 7) & 0x1;
242     unsigned Bit3_1 = (Value >> 1) & 0x7;
243     unsigned Bit5   = (Value >> 5) & 0x1;
244     Value = (Bit11 << 10) | (Bit4 << 9) | (Bit9_8 << 7) | (Bit10 << 6) |
245             (Bit6 << 5) | (Bit7 << 4) | (Bit3_1 << 1) | Bit5;
246     return Value;
247   }
248   case RISCV::fixup_riscv_rvc_branch: {
249     // Need to produce offset[8|4:3], [reg 3 bit], offset[7:6|2:1|5]
250     unsigned Bit8   = (Value >> 8) & 0x1;
251     unsigned Bit7_6 = (Value >> 6) & 0x3;
252     unsigned Bit5   = (Value >> 5) & 0x1;
253     unsigned Bit4_3 = (Value >> 3) & 0x3;
254     unsigned Bit2_1 = (Value >> 1) & 0x3;
255     Value = (Bit8 << 12) | (Bit4_3 << 10) | (Bit7_6 << 5) | (Bit2_1 << 3) |
256             (Bit5 << 2);
257     return Value;
258   }
259 
260   }
261 }
262 
263 void RISCVAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
264                                  const MCValue &Target,
265                                  MutableArrayRef<char> Data, uint64_t Value,
266                                  bool IsResolved,
267                                  const MCSubtargetInfo *STI) const {
268   MCContext &Ctx = Asm.getContext();
269   MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
270   if (!Value)
271     return; // Doesn't change encoding.
272   // Apply any target-specific value adjustments.
273   Value = adjustFixupValue(Fixup, Value, Ctx);
274 
275   // Shift the value into position.
276   Value <<= Info.TargetOffset;
277 
278   unsigned Offset = Fixup.getOffset();
279   unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8;
280 
281   assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
282 
283   // For each byte of the fragment that the fixup touches, mask in the
284   // bits from the fixup value.
285   for (unsigned i = 0; i != NumBytes; ++i) {
286     Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
287   }
288 }
289 
290 std::unique_ptr<MCObjectTargetWriter>
291 RISCVAsmBackend::createObjectTargetWriter() const {
292   return createRISCVELFObjectWriter(OSABI, Is64Bit);
293 }
294 
295 MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T,
296                                           const MCSubtargetInfo &STI,
297                                           const MCRegisterInfo &MRI,
298                                           const MCTargetOptions &Options) {
299   const Triple &TT = STI.getTargetTriple();
300   uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
301   return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit());
302 }
303