1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the PPC specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PPCSubtarget.h" 15 #include "PPC.h" 16 #include "PPCRegisterInfo.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/MachineScheduler.h" 19 #include "llvm/IR/Attributes.h" 20 #include "llvm/IR/Function.h" 21 #include "llvm/IR/GlobalValue.h" 22 #include "llvm/Support/CommandLine.h" 23 #include "llvm/Support/Host.h" 24 #include "llvm/Support/TargetRegistry.h" 25 #include "llvm/Target/TargetMachine.h" 26 #include <cstdlib> 27 28 using namespace llvm; 29 30 #define DEBUG_TYPE "ppc-subtarget" 31 32 #define GET_SUBTARGETINFO_TARGET_DESC 33 #define GET_SUBTARGETINFO_CTOR 34 #include "PPCGenSubtargetInfo.inc" 35 36 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness", 37 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden); 38 39 /// Return the datalayout string of a subtarget. 40 static std::string getDataLayoutString(const Triple &T) { 41 bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le; 42 std::string Ret; 43 44 // Most PPC* platforms are big endian, PPC64LE is little endian. 45 if (T.getArch() == Triple::ppc64le) 46 Ret = "e"; 47 else 48 Ret = "E"; 49 50 Ret += DataLayout::getManglingComponent(T); 51 52 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit 53 // pointers. 54 if (!is64Bit || T.getOS() == Triple::Lv2) 55 Ret += "-p:32:32"; 56 57 // Note, the alignment values for f64 and i64 on ppc64 in Darwin 58 // documentation are wrong; these are correct (i.e. "what gcc does"). 59 if (is64Bit || !T.isOSDarwin()) 60 Ret += "-i64:64"; 61 else 62 Ret += "-f64:32:64"; 63 64 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones. 65 if (is64Bit) 66 Ret += "-n32:64"; 67 else 68 Ret += "-n32"; 69 70 return Ret; 71 } 72 73 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, 74 StringRef FS) { 75 initializeEnvironment(); 76 initSubtargetFeatures(CPU, FS); 77 return *this; 78 } 79 80 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, 81 const std::string &FS, const PPCTargetMachine &TM) 82 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), 83 DL(getDataLayoutString(TargetTriple)), 84 IsPPC64(TargetTriple.getArch() == Triple::ppc64 || 85 TargetTriple.getArch() == Triple::ppc64le), 86 TargetABI(PPC_ABI_UNKNOWN), 87 FrameLowering(initializeSubtargetDependencies(CPU, FS)), InstrInfo(*this), 88 TLInfo(TM), TSInfo(&DL) {} 89 90 void PPCSubtarget::initializeEnvironment() { 91 StackAlignment = 16; 92 DarwinDirective = PPC::DIR_NONE; 93 HasMFOCRF = false; 94 Has64BitSupport = false; 95 Use64BitRegs = false; 96 UseCRBits = false; 97 HasAltivec = false; 98 HasSPE = false; 99 HasQPX = false; 100 HasVSX = false; 101 HasP8Vector = false; 102 HasFCPSGN = false; 103 HasFSQRT = false; 104 HasFRE = false; 105 HasFRES = false; 106 HasFRSQRTE = false; 107 HasFRSQRTES = false; 108 HasRecipPrec = false; 109 HasSTFIWX = false; 110 HasLFIWAX = false; 111 HasFPRND = false; 112 HasFPCVT = false; 113 HasISEL = false; 114 HasPOPCNTD = false; 115 HasCMPB = false; 116 HasLDBRX = false; 117 IsBookE = false; 118 HasOnlyMSYNC = false; 119 IsPPC4xx = false; 120 IsPPC6xx = false; 121 IsE500 = false; 122 DeprecatedMFTB = false; 123 DeprecatedDST = false; 124 HasLazyResolverStubs = false; 125 } 126 127 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 128 // Determine default and user specified characteristics 129 std::string CPUName = CPU; 130 if (CPUName.empty()) 131 CPUName = "generic"; 132 #if (defined(__APPLE__) || defined(__linux__)) && \ 133 (defined(__ppc__) || defined(__powerpc__)) 134 if (CPUName == "generic") 135 CPUName = sys::getHostCPUName(); 136 #endif 137 138 // Initialize scheduling itinerary for the specified CPU. 139 InstrItins = getInstrItineraryForCPU(CPUName); 140 141 // Parse features string. 142 ParseSubtargetFeatures(CPUName, FS); 143 144 // If the user requested use of 64-bit regs, but the cpu selected doesn't 145 // support it, ignore. 146 if (IsPPC64 && has64BitSupport()) 147 Use64BitRegs = true; 148 149 // Set up darwin-specific properties. 150 if (isDarwin()) 151 HasLazyResolverStubs = true; 152 153 // QPX requires a 32-byte aligned stack. Note that we need to do this if 154 // we're compiling for a BG/Q system regardless of whether or not QPX 155 // is enabled because external functions will assume this alignment. 156 if (hasQPX() || isBGQ()) 157 StackAlignment = 32; 158 159 // Determine endianness. 160 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le); 161 162 // Determine default ABI. 163 if (TargetABI == PPC_ABI_UNKNOWN) { 164 if (!isDarwin() && IsPPC64) { 165 if (IsLittleEndian) 166 TargetABI = PPC_ABI_ELFv2; 167 else 168 TargetABI = PPC_ABI_ELFv1; 169 } 170 } 171 } 172 173 /// hasLazyResolverStub - Return true if accesses to the specified global have 174 /// to go through a dyld lazy resolution stub. This means that an extra load 175 /// is required to get the address of the global. 176 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV, 177 const TargetMachine &TM) const { 178 // We never have stubs if HasLazyResolverStubs=false or if in static mode. 179 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static) 180 return false; 181 bool isDecl = GV->isDeclaration(); 182 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage()) 183 return false; 184 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || 185 GV->hasCommonLinkage() || isDecl; 186 } 187 188 // Embedded cores need aggressive scheduling (and some others also benefit). 189 static bool needsAggressiveScheduling(unsigned Directive) { 190 switch (Directive) { 191 default: return false; 192 case PPC::DIR_440: 193 case PPC::DIR_A2: 194 case PPC::DIR_E500mc: 195 case PPC::DIR_E5500: 196 case PPC::DIR_PWR7: 197 case PPC::DIR_PWR8: 198 return true; 199 } 200 } 201 202 bool PPCSubtarget::enableMachineScheduler() const { 203 // Enable MI scheduling for the embedded cores. 204 // FIXME: Enable this for all cores (some additional modeling 205 // may be necessary). 206 return needsAggressiveScheduling(DarwinDirective); 207 } 208 209 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 210 bool PPCSubtarget::enablePostMachineScheduler() const { return true; } 211 212 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { 213 return TargetSubtargetInfo::ANTIDEP_ALL; 214 } 215 216 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 217 CriticalPathRCs.clear(); 218 CriticalPathRCs.push_back(isPPC64() ? 219 &PPC::G8RCRegClass : &PPC::GPRCRegClass); 220 } 221 222 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 223 MachineInstr *begin, 224 MachineInstr *end, 225 unsigned NumRegionInstrs) const { 226 if (needsAggressiveScheduling(DarwinDirective)) { 227 Policy.OnlyTopDown = false; 228 Policy.OnlyBottomUp = false; 229 } 230 231 // Spilling is generally expensive on all PPC cores, so always enable 232 // register-pressure tracking. 233 Policy.ShouldTrackPressure = true; 234 } 235 236 bool PPCSubtarget::useAA() const { 237 // Use AA during code generation for the embedded cores. 238 return needsAggressiveScheduling(DarwinDirective); 239 } 240 241 bool PPCSubtarget::enableSubRegLiveness() const { 242 return UseSubRegLiveness; 243 } 244 245