1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the subset of the 32-bit PowerPC instruction set, as used
11// by the PowerPC instruction selector.
12//
13//===----------------------------------------------------------------------===//
14
15include "PPCInstrFormats.td"
16
17//===----------------------------------------------------------------------===//
18// PowerPC specific type constraints.
19//
20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21  SDTCisVT<0, f64>, SDTCisPtrTy<1>
22]>;
23def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24  SDTCisVT<0, f64>, SDTCisPtrTy<1>
25]>;
26
27def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28def SDT_PPCCallSeqEnd   : SDCallSeqEnd<[ SDTCisVT<0, i32>,
29                                         SDTCisVT<1, i32> ]>;
30def SDT_PPCvperm   : SDTypeProfile<1, 3, [
31  SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
32]>;
33
34def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35  SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
36]>;
37
38def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39  SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
40]>;
41
42def SDT_PPClbrx : SDTypeProfile<1, 2, [
43  SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
44]>;
45def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46  SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
47]>;
48
49def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
50  SDTCisPtrTy<0>, SDTCisVT<1, i32>
51]>;
52
53def tocentry32 : Operand<iPTR> {
54  let MIOperandInfo = (ops i32imm:$imm);
55}
56
57def SDT_PPCqvfperm   : SDTypeProfile<1, 3, [
58  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3>
59]>;
60def SDT_PPCqvgpci   : SDTypeProfile<1, 1, [
61  SDTCisVec<0>, SDTCisInt<1>
62]>;
63def SDT_PPCqvaligni   : SDTypeProfile<1, 3, [
64  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>
65]>;
66def SDT_PPCqvesplati   : SDTypeProfile<1, 2, [
67  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>
68]>;
69
70def SDT_PPCqbflt : SDTypeProfile<1, 1, [
71  SDTCisVec<0>, SDTCisVec<1>
72]>;
73
74def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [
75  SDTCisVec<0>, SDTCisPtrTy<1>
76]>;
77
78//===----------------------------------------------------------------------===//
79// PowerPC specific DAG Nodes.
80//
81
82def PPCfre    : SDNode<"PPCISD::FRE",     SDTFPUnaryOp, []>;
83def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
84
85def PPCfcfid  : SDNode<"PPCISD::FCFID",   SDTFPUnaryOp, []>;
86def PPCfcfidu : SDNode<"PPCISD::FCFIDU",  SDTFPUnaryOp, []>;
87def PPCfcfids : SDNode<"PPCISD::FCFIDS",  SDTFPRoundOp, []>;
88def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
89def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
90def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
91def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
92def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
93def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
94                       [SDNPHasChain, SDNPMayStore]>;
95def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
96                       [SDNPHasChain, SDNPMayLoad]>;
97def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
98                       [SDNPHasChain, SDNPMayLoad]>;
99
100// Extract FPSCR (not modeled at the DAG level).
101def PPCmffs   : SDNode<"PPCISD::MFFS",
102                       SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
103
104// Perform FADD in round-to-zero mode.
105def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
106
107
108def PPCfsel   : SDNode<"PPCISD::FSEL",
109   // Type constraint for fsel.
110   SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
111                        SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
112
113def PPChi       : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
114def PPClo       : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
115def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp,
116                         [SDNPMayLoad, SDNPMemOperand]>;
117def PPCvmaddfp  : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
118def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
119
120def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
121
122def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
123def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
124                            [SDNPMayLoad]>;
125def PPCaddTls     : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
126def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
127def PPCaddiTlsgdL   : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
128def PPCgetTlsAddr   : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
129def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR",
130                               SDTypeProfile<1, 3, [
131                                 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
132                                 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
133def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
134def PPCaddiTlsldL   : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
135def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
136def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR",
137                               SDTypeProfile<1, 3, [
138                                 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
139                                 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
140def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;
141def PPCaddiDtprelL   : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
142
143def PPCvperm    : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
144
145def PPCqvfperm   : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>;
146def PPCqvgpci    : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>;
147def PPCqvaligni  : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>;
148def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>;
149
150def PPCqbflt     : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>;
151
152def PPCqvlfsb    : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb,
153                          [SDNPHasChain, SDNPMayLoad]>;
154
155def PPCcmpb     : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>;
156
157// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
158// amounts.  These nodes are generated by the multi-precision shift code.
159def PPCsrl        : SDNode<"PPCISD::SRL"       , SDTIntShiftOp>;
160def PPCsra        : SDNode<"PPCISD::SRA"       , SDTIntShiftOp>;
161def PPCshl        : SDNode<"PPCISD::SHL"       , SDTIntShiftOp>;
162
163// These are target-independent nodes, but have target-specific formats.
164def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
165                           [SDNPHasChain, SDNPOutGlue]>;
166def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_PPCCallSeqEnd,
167                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
168
169def SDT_PPCCall   : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
170def PPCcall  : SDNode<"PPCISD::CALL", SDT_PPCCall,
171                      [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
172                       SDNPVariadic]>;
173def PPCcall_nop  : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
174                          [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
175                           SDNPVariadic]>;
176def PPCmtctr      : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
177                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
178def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
179                      [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
180                       SDNPVariadic]>;
181def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC",
182                               SDTypeProfile<0, 1, []>,
183                               [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
184                                SDNPVariadic]>;
185
186def retflag       : SDNode<"PPCISD::RET_FLAG", SDTNone,
187                           [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
188
189def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
190                        [SDNPHasChain,  SDNPOptInGlue, SDNPVariadic]>;
191
192def PPCeh_sjlj_setjmp  : SDNode<"PPCISD::EH_SJLJ_SETJMP",
193                                SDTypeProfile<1, 1, [SDTCisInt<0>,
194                                                     SDTCisPtrTy<1>]>,
195                                [SDNPHasChain, SDNPSideEffect]>;
196def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
197                                SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
198                                [SDNPHasChain, SDNPSideEffect]>;
199
200def SDT_PPCsc     : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
201def PPCsc         : SDNode<"PPCISD::SC", SDT_PPCsc,
202                           [SDNPHasChain, SDNPSideEffect]>;
203
204def PPCclrbhrb    : SDNode<"PPCISD::CLRBHRB", SDTNone,
205                           [SDNPHasChain, SDNPSideEffect]>;
206def PPCmfbhrbe    : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>;
207def PPCrfebb      : SDNode<"PPCISD::RFEBB", SDT_PPCsc,
208                           [SDNPHasChain, SDNPSideEffect]>;
209
210def PPCvcmp       : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
211def PPCvcmp_o     : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
212
213def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
214                           [SDNPHasChain, SDNPOptInGlue]>;
215
216def PPClbrx       : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
217                           [SDNPHasChain, SDNPMayLoad]>;
218def PPCstbrx      : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
219                           [SDNPHasChain, SDNPMayStore]>;
220
221// Instructions to set/unset CR bit 6 for SVR4 vararg calls
222def PPCcr6set   : SDNode<"PPCISD::CR6SET", SDTNone,
223                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
224def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
225                         [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
226
227// Instructions to support dynamic alloca.
228def SDTDynOp  : SDTypeProfile<1, 2, []>;
229def PPCdynalloc   : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
230
231//===----------------------------------------------------------------------===//
232// PowerPC specific transformation functions and pattern fragments.
233//
234
235def SHL32 : SDNodeXForm<imm, [{
236  // Transformation function: 31 - imm
237  return getI32Imm(31 - N->getZExtValue(), SDLoc(N));
238}]>;
239
240def SRL32 : SDNodeXForm<imm, [{
241  // Transformation function: 32 - imm
242  return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N))
243                           : getI32Imm(0, SDLoc(N));
244}]>;
245
246def LO16 : SDNodeXForm<imm, [{
247  // Transformation function: get the low 16 bits.
248  return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N));
249}]>;
250
251def HI16 : SDNodeXForm<imm, [{
252  // Transformation function: shift the immediate value down into the low bits.
253  return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N));
254}]>;
255
256def HA16 : SDNodeXForm<imm, [{
257  // Transformation function: shift the immediate value down into the low bits.
258  signed int Val = N->getZExtValue();
259  return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N));
260}]>;
261def MB : SDNodeXForm<imm, [{
262  // Transformation function: get the start bit of a mask
263  unsigned mb = 0, me;
264  (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
265  return getI32Imm(mb, SDLoc(N));
266}]>;
267
268def ME : SDNodeXForm<imm, [{
269  // Transformation function: get the end bit of a mask
270  unsigned mb, me = 0;
271  (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
272  return getI32Imm(me, SDLoc(N));
273}]>;
274def maskimm32 : PatLeaf<(imm), [{
275  // maskImm predicate - True if immediate is a run of ones.
276  unsigned mb, me;
277  if (N->getValueType(0) == MVT::i32)
278    return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
279  else
280    return false;
281}]>;
282
283def imm32SExt16  : Operand<i32>, ImmLeaf<i32, [{
284  // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
285  // sign extended field.  Used by instructions like 'addi'.
286  return (int32_t)Imm == (short)Imm;
287}]>;
288def imm64SExt16  : Operand<i64>, ImmLeaf<i64, [{
289  // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
290  // sign extended field.  Used by instructions like 'addi'.
291  return (int64_t)Imm == (short)Imm;
292}]>;
293def immZExt16  : PatLeaf<(imm), [{
294  // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
295  // field.  Used by instructions like 'ori'.
296  return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
297}], LO16>;
298
299// imm16Shifted* - These match immediates where the low 16-bits are zero.  There
300// are two forms: imm16ShiftedSExt and imm16ShiftedZExt.  These two forms are
301// identical in 32-bit mode, but in 64-bit mode, they return true if the
302// immediate fits into a sign/zero extended 32-bit immediate (with the low bits
303// clear).
304def imm16ShiftedZExt : PatLeaf<(imm), [{
305  // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
306  // immediate are set.  Used by instructions like 'xoris'.
307  return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
308}], HI16>;
309
310def imm16ShiftedSExt : PatLeaf<(imm), [{
311  // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
312  // immediate are set.  Used by instructions like 'addis'.  Identical to
313  // imm16ShiftedZExt in 32-bit mode.
314  if (N->getZExtValue() & 0xFFFF) return false;
315  if (N->getValueType(0) == MVT::i32)
316    return true;
317  // For 64-bit, make sure it is sext right.
318  return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
319}], HI16>;
320
321def imm64ZExt32  : Operand<i64>, ImmLeaf<i64, [{
322  // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
323  // zero extended field.
324  return isUInt<32>(Imm);
325}]>;
326
327// Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
328// restricted memrix (4-aligned) constants are alignment sensitive. If these
329// offsets are hidden behind TOC entries than the values of the lower-order
330// bits cannot be checked directly. As a result, we need to also incorporate
331// an alignment check into the relevant patterns.
332
333def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
334  return cast<LoadSDNode>(N)->getAlignment() >= 4;
335}]>;
336def aligned4store : PatFrag<(ops node:$val, node:$ptr),
337                            (store node:$val, node:$ptr), [{
338  return cast<StoreSDNode>(N)->getAlignment() >= 4;
339}]>;
340def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
341  return cast<LoadSDNode>(N)->getAlignment() >= 4;
342}]>;
343def aligned4pre_store : PatFrag<
344                          (ops node:$val, node:$base, node:$offset),
345                          (pre_store node:$val, node:$base, node:$offset), [{
346  return cast<StoreSDNode>(N)->getAlignment() >= 4;
347}]>;
348
349def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
350  return cast<LoadSDNode>(N)->getAlignment() < 4;
351}]>;
352def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
353                              (store node:$val, node:$ptr), [{
354  return cast<StoreSDNode>(N)->getAlignment() < 4;
355}]>;
356def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
357  return cast<LoadSDNode>(N)->getAlignment() < 4;
358}]>;
359
360//===----------------------------------------------------------------------===//
361// PowerPC Flag Definitions.
362
363class isPPC64 { bit PPC64 = 1; }
364class isDOT   { bit RC = 1; }
365
366class RegConstraint<string C> {
367  string Constraints = C;
368}
369class NoEncode<string E> {
370  string DisableEncoding = E;
371}
372
373
374//===----------------------------------------------------------------------===//
375// PowerPC Operand Definitions.
376
377// In the default PowerPC assembler syntax, registers are specified simply
378// by number, so they cannot be distinguished from immediate values (without
379// looking at the opcode).  This means that the default operand matching logic
380// for the asm parser does not work, and we need to specify custom matchers.
381// Since those can only be specified with RegisterOperand classes and not
382// directly on the RegisterClass, all instructions patterns used by the asm
383// parser need to use a RegisterOperand (instead of a RegisterClass) for
384// all their register operands.
385// For this purpose, we define one RegisterOperand for each RegisterClass,
386// using the same name as the class, just in lower case.
387
388def PPCRegGPRCAsmOperand : AsmOperandClass {
389  let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
390}
391def gprc : RegisterOperand<GPRC> {
392  let ParserMatchClass = PPCRegGPRCAsmOperand;
393}
394def PPCRegG8RCAsmOperand : AsmOperandClass {
395  let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
396}
397def g8rc : RegisterOperand<G8RC> {
398  let ParserMatchClass = PPCRegG8RCAsmOperand;
399}
400def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
401  let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
402}
403def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
404  let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
405}
406def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
407  let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
408}
409def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
410  let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
411}
412def PPCRegF8RCAsmOperand : AsmOperandClass {
413  let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
414}
415def f8rc : RegisterOperand<F8RC> {
416  let ParserMatchClass = PPCRegF8RCAsmOperand;
417}
418def PPCRegF4RCAsmOperand : AsmOperandClass {
419  let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
420}
421def f4rc : RegisterOperand<F4RC> {
422  let ParserMatchClass = PPCRegF4RCAsmOperand;
423}
424def PPCRegVRRCAsmOperand : AsmOperandClass {
425  let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
426}
427def vrrc : RegisterOperand<VRRC> {
428  let ParserMatchClass = PPCRegVRRCAsmOperand;
429}
430def PPCRegCRBITRCAsmOperand : AsmOperandClass {
431  let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
432}
433def crbitrc : RegisterOperand<CRBITRC> {
434  let ParserMatchClass = PPCRegCRBITRCAsmOperand;
435}
436def PPCRegCRRCAsmOperand : AsmOperandClass {
437  let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
438}
439def crrc : RegisterOperand<CRRC> {
440  let ParserMatchClass = PPCRegCRRCAsmOperand;
441}
442def crrc0 : RegisterOperand<CRRC0> {
443  let ParserMatchClass = PPCRegCRRCAsmOperand;
444}
445
446def PPCU1ImmAsmOperand : AsmOperandClass {
447  let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
448  let RenderMethod = "addImmOperands";
449}
450def u1imm   : Operand<i32> {
451  let PrintMethod = "printU1ImmOperand";
452  let ParserMatchClass = PPCU1ImmAsmOperand;
453}
454
455def PPCU2ImmAsmOperand : AsmOperandClass {
456  let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
457  let RenderMethod = "addImmOperands";
458}
459def u2imm   : Operand<i32> {
460  let PrintMethod = "printU2ImmOperand";
461  let ParserMatchClass = PPCU2ImmAsmOperand;
462}
463
464def PPCU3ImmAsmOperand : AsmOperandClass {
465  let Name = "U3Imm"; let PredicateMethod = "isU3Imm";
466  let RenderMethod = "addImmOperands";
467}
468def u3imm   : Operand<i32> {
469  let PrintMethod = "printU3ImmOperand";
470  let ParserMatchClass = PPCU3ImmAsmOperand;
471}
472
473def PPCU4ImmAsmOperand : AsmOperandClass {
474  let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
475  let RenderMethod = "addImmOperands";
476}
477def u4imm   : Operand<i32> {
478  let PrintMethod = "printU4ImmOperand";
479  let ParserMatchClass = PPCU4ImmAsmOperand;
480}
481def PPCS5ImmAsmOperand : AsmOperandClass {
482  let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
483  let RenderMethod = "addImmOperands";
484}
485def s5imm   : Operand<i32> {
486  let PrintMethod = "printS5ImmOperand";
487  let ParserMatchClass = PPCS5ImmAsmOperand;
488  let DecoderMethod = "decodeSImmOperand<5>";
489}
490def PPCU5ImmAsmOperand : AsmOperandClass {
491  let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
492  let RenderMethod = "addImmOperands";
493}
494def u5imm   : Operand<i32> {
495  let PrintMethod = "printU5ImmOperand";
496  let ParserMatchClass = PPCU5ImmAsmOperand;
497  let DecoderMethod = "decodeUImmOperand<5>";
498}
499def PPCU6ImmAsmOperand : AsmOperandClass {
500  let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
501  let RenderMethod = "addImmOperands";
502}
503def u6imm   : Operand<i32> {
504  let PrintMethod = "printU6ImmOperand";
505  let ParserMatchClass = PPCU6ImmAsmOperand;
506  let DecoderMethod = "decodeUImmOperand<6>";
507}
508def PPCU10ImmAsmOperand : AsmOperandClass {
509  let Name = "U10Imm"; let PredicateMethod = "isU10Imm";
510  let RenderMethod = "addImmOperands";
511}
512def u10imm  : Operand<i32> {
513  let PrintMethod = "printU10ImmOperand";
514  let ParserMatchClass = PPCU10ImmAsmOperand;
515  let DecoderMethod = "decodeUImmOperand<10>";
516}
517def PPCU12ImmAsmOperand : AsmOperandClass {
518  let Name = "U12Imm"; let PredicateMethod = "isU12Imm";
519  let RenderMethod = "addImmOperands";
520}
521def u12imm  : Operand<i32> {
522  let PrintMethod = "printU12ImmOperand";
523  let ParserMatchClass = PPCU12ImmAsmOperand;
524  let DecoderMethod = "decodeUImmOperand<12>";
525}
526def PPCS16ImmAsmOperand : AsmOperandClass {
527  let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
528  let RenderMethod = "addS16ImmOperands";
529}
530def s16imm  : Operand<i32> {
531  let PrintMethod = "printS16ImmOperand";
532  let EncoderMethod = "getImm16Encoding";
533  let ParserMatchClass = PPCS16ImmAsmOperand;
534  let DecoderMethod = "decodeSImmOperand<16>";
535}
536def PPCU16ImmAsmOperand : AsmOperandClass {
537  let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
538  let RenderMethod = "addU16ImmOperands";
539}
540def u16imm  : Operand<i32> {
541  let PrintMethod = "printU16ImmOperand";
542  let EncoderMethod = "getImm16Encoding";
543  let ParserMatchClass = PPCU16ImmAsmOperand;
544  let DecoderMethod = "decodeUImmOperand<16>";
545}
546def PPCS17ImmAsmOperand : AsmOperandClass {
547  let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
548  let RenderMethod = "addS16ImmOperands";
549}
550def s17imm  : Operand<i32> {
551  // This operand type is used for addis/lis to allow the assembler parser
552  // to accept immediates in the range -65536..65535 for compatibility with
553  // the GNU assembler.  The operand is treated as 16-bit otherwise.
554  let PrintMethod = "printS16ImmOperand";
555  let EncoderMethod = "getImm16Encoding";
556  let ParserMatchClass = PPCS17ImmAsmOperand;
557  let DecoderMethod = "decodeSImmOperand<16>";
558}
559def PPCDirectBrAsmOperand : AsmOperandClass {
560  let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
561  let RenderMethod = "addBranchTargetOperands";
562}
563def directbrtarget : Operand<OtherVT> {
564  let PrintMethod = "printBranchOperand";
565  let EncoderMethod = "getDirectBrEncoding";
566  let ParserMatchClass = PPCDirectBrAsmOperand;
567}
568def absdirectbrtarget : Operand<OtherVT> {
569  let PrintMethod = "printAbsBranchOperand";
570  let EncoderMethod = "getAbsDirectBrEncoding";
571  let ParserMatchClass = PPCDirectBrAsmOperand;
572}
573def PPCCondBrAsmOperand : AsmOperandClass {
574  let Name = "CondBr"; let PredicateMethod = "isCondBr";
575  let RenderMethod = "addBranchTargetOperands";
576}
577def condbrtarget : Operand<OtherVT> {
578  let PrintMethod = "printBranchOperand";
579  let EncoderMethod = "getCondBrEncoding";
580  let ParserMatchClass = PPCCondBrAsmOperand;
581}
582def abscondbrtarget : Operand<OtherVT> {
583  let PrintMethod = "printAbsBranchOperand";
584  let EncoderMethod = "getAbsCondBrEncoding";
585  let ParserMatchClass = PPCCondBrAsmOperand;
586}
587def calltarget : Operand<iPTR> {
588  let PrintMethod = "printBranchOperand";
589  let EncoderMethod = "getDirectBrEncoding";
590  let ParserMatchClass = PPCDirectBrAsmOperand;
591}
592def abscalltarget : Operand<iPTR> {
593  let PrintMethod = "printAbsBranchOperand";
594  let EncoderMethod = "getAbsDirectBrEncoding";
595  let ParserMatchClass = PPCDirectBrAsmOperand;
596}
597def PPCCRBitMaskOperand : AsmOperandClass {
598 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
599}
600def crbitm: Operand<i8> {
601  let PrintMethod = "printcrbitm";
602  let EncoderMethod = "get_crbitm_encoding";
603  let DecoderMethod = "decodeCRBitMOperand";
604  let ParserMatchClass = PPCCRBitMaskOperand;
605}
606// Address operands
607// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
608def PPCRegGxRCNoR0Operand : AsmOperandClass {
609  let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
610}
611def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
612  let ParserMatchClass = PPCRegGxRCNoR0Operand;
613}
614// A version of ptr_rc usable with the asm parser.
615def PPCRegGxRCOperand : AsmOperandClass {
616  let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
617}
618def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
619  let ParserMatchClass = PPCRegGxRCOperand;
620}
621
622def PPCDispRIOperand : AsmOperandClass {
623 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
624 let RenderMethod = "addS16ImmOperands";
625}
626def dispRI : Operand<iPTR> {
627  let ParserMatchClass = PPCDispRIOperand;
628}
629def PPCDispRIXOperand : AsmOperandClass {
630 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
631 let RenderMethod = "addImmOperands";
632}
633def dispRIX : Operand<iPTR> {
634  let ParserMatchClass = PPCDispRIXOperand;
635}
636def PPCDispSPE8Operand : AsmOperandClass {
637 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
638 let RenderMethod = "addImmOperands";
639}
640def dispSPE8 : Operand<iPTR> {
641  let ParserMatchClass = PPCDispSPE8Operand;
642}
643def PPCDispSPE4Operand : AsmOperandClass {
644 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
645 let RenderMethod = "addImmOperands";
646}
647def dispSPE4 : Operand<iPTR> {
648  let ParserMatchClass = PPCDispSPE4Operand;
649}
650def PPCDispSPE2Operand : AsmOperandClass {
651 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
652 let RenderMethod = "addImmOperands";
653}
654def dispSPE2 : Operand<iPTR> {
655  let ParserMatchClass = PPCDispSPE2Operand;
656}
657
658def memri : Operand<iPTR> {
659  let PrintMethod = "printMemRegImm";
660  let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
661  let EncoderMethod = "getMemRIEncoding";
662  let DecoderMethod = "decodeMemRIOperands";
663}
664def memrr : Operand<iPTR> {
665  let PrintMethod = "printMemRegReg";
666  let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
667}
668def memrix : Operand<iPTR> {   // memri where the imm is 4-aligned.
669  let PrintMethod = "printMemRegImm";
670  let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
671  let EncoderMethod = "getMemRIXEncoding";
672  let DecoderMethod = "decodeMemRIXOperands";
673}
674def spe8dis : Operand<iPTR> {   // SPE displacement where the imm is 8-aligned.
675  let PrintMethod = "printMemRegImm";
676  let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
677  let EncoderMethod = "getSPE8DisEncoding";
678}
679def spe4dis : Operand<iPTR> {   // SPE displacement where the imm is 4-aligned.
680  let PrintMethod = "printMemRegImm";
681  let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
682  let EncoderMethod = "getSPE4DisEncoding";
683}
684def spe2dis : Operand<iPTR> {   // SPE displacement where the imm is 2-aligned.
685  let PrintMethod = "printMemRegImm";
686  let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
687  let EncoderMethod = "getSPE2DisEncoding";
688}
689
690// A single-register address. This is used with the SjLj
691// pseudo-instructions.
692def memr : Operand<iPTR> {
693  let MIOperandInfo = (ops ptr_rc:$ptrreg);
694}
695def PPCTLSRegOperand : AsmOperandClass {
696  let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
697  let RenderMethod = "addTLSRegOperands";
698}
699def tlsreg32 : Operand<i32> {
700  let EncoderMethod = "getTLSRegEncoding";
701  let ParserMatchClass = PPCTLSRegOperand;
702}
703def tlsgd32 : Operand<i32> {}
704def tlscall32 : Operand<i32> {
705  let PrintMethod = "printTLSCall";
706  let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
707  let EncoderMethod = "getTLSCallEncoding";
708}
709
710// PowerPC Predicate operand.
711def pred : Operand<OtherVT> {
712  let PrintMethod = "printPredicateOperand";
713  let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
714}
715
716// Define PowerPC specific addressing mode.
717def iaddr  : ComplexPattern<iPTR, 2, "SelectAddrImm",    [], []>;
718def xaddr  : ComplexPattern<iPTR, 2, "SelectAddrIdx",    [], []>;
719def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
720def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4",  [], []>; // "std"
721
722// The address in a single register. This is used with the SjLj
723// pseudo-instructions.
724def addr   : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
725
726/// This is just the offset part of iaddr, used for preinc.
727def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
728
729//===----------------------------------------------------------------------===//
730// PowerPC Instruction Predicate Definitions.
731def In32BitMode  : Predicate<"!PPCSubTarget->isPPC64()">;
732def In64BitMode  : Predicate<"PPCSubTarget->isPPC64()">;
733def IsBookE  : Predicate<"PPCSubTarget->isBookE()">;
734def IsNotBookE  : Predicate<"!PPCSubTarget->isBookE()">;
735def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
736def HasSYNC   : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
737def IsPPC4xx  : Predicate<"PPCSubTarget->isPPC4xx()">;
738def IsPPC6xx  : Predicate<"PPCSubTarget->isPPC6xx()">;
739def IsE500  : Predicate<"PPCSubTarget->isE500()">;
740def HasSPE  : Predicate<"PPCSubTarget->HasSPE()">;
741def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
742def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">;
743def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
744def NaNsFPMath   : Predicate<"!TM.Options.NoNaNsFPMath">;
745def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">;
746def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">;
747
748//===----------------------------------------------------------------------===//
749// PowerPC Multiclass Definitions.
750
751multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
752                    string asmbase, string asmstr, InstrItinClass itin,
753                    list<dag> pattern> {
754  let BaseName = asmbase in {
755    def NAME : XForm_6<opcode, xo, OOL, IOL,
756                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
757                       pattern>, RecFormRel;
758    let Defs = [CR0] in
759    def o    : XForm_6<opcode, xo, OOL, IOL,
760                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
761                       []>, isDOT, RecFormRel;
762  }
763}
764
765multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
766                     string asmbase, string asmstr, InstrItinClass itin,
767                     list<dag> pattern> {
768  let BaseName = asmbase in {
769    let Defs = [CARRY] in
770    def NAME : XForm_6<opcode, xo, OOL, IOL,
771                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
772                       pattern>, RecFormRel;
773    let Defs = [CARRY, CR0] in
774    def o    : XForm_6<opcode, xo, OOL, IOL,
775                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
776                       []>, isDOT, RecFormRel;
777  }
778}
779
780multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
781                      string asmbase, string asmstr, InstrItinClass itin,
782                      list<dag> pattern> {
783  let BaseName = asmbase in {
784    let Defs = [CARRY] in
785    def NAME : XForm_10<opcode, xo, OOL, IOL,
786                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
787                       pattern>, RecFormRel;
788    let Defs = [CARRY, CR0] in
789    def o    : XForm_10<opcode, xo, OOL, IOL,
790                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
791                       []>, isDOT, RecFormRel;
792  }
793}
794
795multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
796                    string asmbase, string asmstr, InstrItinClass itin,
797                    list<dag> pattern> {
798  let BaseName = asmbase in {
799    def NAME : XForm_11<opcode, xo, OOL, IOL,
800                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
801                       pattern>, RecFormRel;
802    let Defs = [CR0] in
803    def o    : XForm_11<opcode, xo, OOL, IOL,
804                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
805                       []>, isDOT, RecFormRel;
806  }
807}
808
809multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
810                    string asmbase, string asmstr, InstrItinClass itin,
811                    list<dag> pattern> {
812  let BaseName = asmbase in {
813    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
814                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
815                       pattern>, RecFormRel;
816    let Defs = [CR0] in
817    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
818                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
819                       []>, isDOT, RecFormRel;
820  }
821}
822
823// Multiclass for instructions for which the non record form is not cracked
824// and the record form is cracked (i.e. divw, mullw, etc.)
825multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
826                      string asmbase, string asmstr, InstrItinClass itin,
827                      list<dag> pattern> {
828  let BaseName = asmbase in {
829    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
830                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
831                       pattern>, RecFormRel;
832    let Defs = [CR0] in
833    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
834                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
835                       []>, isDOT, RecFormRel, PPC970_DGroup_First,
836                       PPC970_DGroup_Cracked;
837  }
838}
839
840multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
841                      string asmbase, string asmstr, InstrItinClass itin,
842                      list<dag> pattern> {
843  let BaseName = asmbase in {
844    let Defs = [CARRY] in
845    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
846                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
847                       pattern>, RecFormRel;
848    let Defs = [CARRY, CR0] in
849    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
850                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
851                       []>, isDOT, RecFormRel;
852  }
853}
854
855multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
856                    string asmbase, string asmstr, InstrItinClass itin,
857                    list<dag> pattern> {
858  let BaseName = asmbase in {
859    def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
860                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
861                       pattern>, RecFormRel;
862    let Defs = [CR0] in
863    def o    : XOForm_3<opcode, xo, oe, OOL, IOL,
864                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
865                       []>, isDOT, RecFormRel;
866  }
867}
868
869multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
870                      string asmbase, string asmstr, InstrItinClass itin,
871                      list<dag> pattern> {
872  let BaseName = asmbase in {
873    let Defs = [CARRY] in
874    def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
875                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
876                       pattern>, RecFormRel;
877    let Defs = [CARRY, CR0] in
878    def o    : XOForm_3<opcode, xo, oe, OOL, IOL,
879                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
880                       []>, isDOT, RecFormRel;
881  }
882}
883
884multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
885                    string asmbase, string asmstr, InstrItinClass itin,
886                    list<dag> pattern> {
887  let BaseName = asmbase in {
888    def NAME : MForm_2<opcode, OOL, IOL,
889                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
890                       pattern>, RecFormRel;
891    let Defs = [CR0] in
892    def o    : MForm_2<opcode, OOL, IOL,
893                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
894                       []>, isDOT, RecFormRel;
895  }
896}
897
898multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
899                    string asmbase, string asmstr, InstrItinClass itin,
900                    list<dag> pattern> {
901  let BaseName = asmbase in {
902    def NAME : MDForm_1<opcode, xo, OOL, IOL,
903                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
904                       pattern>, RecFormRel;
905    let Defs = [CR0] in
906    def o    : MDForm_1<opcode, xo, OOL, IOL,
907                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
908                       []>, isDOT, RecFormRel;
909  }
910}
911
912multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
913                     string asmbase, string asmstr, InstrItinClass itin,
914                     list<dag> pattern> {
915  let BaseName = asmbase in {
916    def NAME : MDSForm_1<opcode, xo, OOL, IOL,
917                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
918                        pattern>, RecFormRel;
919    let Defs = [CR0] in
920    def o    : MDSForm_1<opcode, xo, OOL, IOL,
921                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
922                        []>, isDOT, RecFormRel;
923  }
924}
925
926multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
927                      string asmbase, string asmstr, InstrItinClass itin,
928                      list<dag> pattern> {
929  let BaseName = asmbase in {
930    let Defs = [CARRY] in
931    def NAME : XSForm_1<opcode, xo, OOL, IOL,
932                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
933                       pattern>, RecFormRel;
934    let Defs = [CARRY, CR0] in
935    def o    : XSForm_1<opcode, xo, OOL, IOL,
936                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
937                       []>, isDOT, RecFormRel;
938  }
939}
940
941multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
942                    string asmbase, string asmstr, InstrItinClass itin,
943                    list<dag> pattern> {
944  let BaseName = asmbase in {
945    def NAME : XForm_26<opcode, xo, OOL, IOL,
946                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
947                       pattern>, RecFormRel;
948    let Defs = [CR1] in
949    def o    : XForm_26<opcode, xo, OOL, IOL,
950                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
951                       []>, isDOT, RecFormRel;
952  }
953}
954
955multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
956                    string asmbase, string asmstr, InstrItinClass itin,
957                    list<dag> pattern> {
958  let BaseName = asmbase in {
959    def NAME : XForm_28<opcode, xo, OOL, IOL,
960                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
961                       pattern>, RecFormRel;
962    let Defs = [CR1] in
963    def o    : XForm_28<opcode, xo, OOL, IOL,
964                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
965                       []>, isDOT, RecFormRel;
966  }
967}
968
969multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
970                    string asmbase, string asmstr, InstrItinClass itin,
971                    list<dag> pattern> {
972  let BaseName = asmbase in {
973    def NAME : AForm_1<opcode, xo, OOL, IOL,
974                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
975                       pattern>, RecFormRel;
976    let Defs = [CR1] in
977    def o    : AForm_1<opcode, xo, OOL, IOL,
978                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
979                       []>, isDOT, RecFormRel;
980  }
981}
982
983multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
984                    string asmbase, string asmstr, InstrItinClass itin,
985                    list<dag> pattern> {
986  let BaseName = asmbase in {
987    def NAME : AForm_2<opcode, xo, OOL, IOL,
988                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
989                       pattern>, RecFormRel;
990    let Defs = [CR1] in
991    def o    : AForm_2<opcode, xo, OOL, IOL,
992                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
993                       []>, isDOT, RecFormRel;
994  }
995}
996
997multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
998                    string asmbase, string asmstr, InstrItinClass itin,
999                    list<dag> pattern> {
1000  let BaseName = asmbase in {
1001    def NAME : AForm_3<opcode, xo, OOL, IOL,
1002                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
1003                       pattern>, RecFormRel;
1004    let Defs = [CR1] in
1005    def o    : AForm_3<opcode, xo, OOL, IOL,
1006                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
1007                       []>, isDOT, RecFormRel;
1008  }
1009}
1010
1011//===----------------------------------------------------------------------===//
1012// PowerPC Instruction Definitions.
1013
1014// Pseudo-instructions:
1015
1016let hasCtrlDep = 1 in {
1017let Defs = [R1], Uses = [R1] in {
1018def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
1019                              [(callseq_start timm:$amt)]>;
1020def ADJCALLSTACKUP   : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
1021                              [(callseq_end timm:$amt1, timm:$amt2)]>;
1022}
1023
1024def UPDATE_VRSAVE    : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
1025                              "UPDATE_VRSAVE $rD, $rS", []>;
1026}
1027
1028let Defs = [R1], Uses = [R1] in
1029def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
1030                       [(set i32:$result,
1031                             (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
1032
1033// SELECT_CC_* - Used to implement the SELECT_CC DAG operation.  Expanded after
1034// instruction selection into a branch sequence.
1035let usesCustomInserter = 1,    // Expanded after instruction selection.
1036    PPC970_Single = 1 in {
1037  // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
1038  // because either operand might become the first operand in an isel, and
1039  // that operand cannot be r0.
1040  def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
1041                              gprc_nor0:$T, gprc_nor0:$F,
1042                              i32imm:$BROPC), "#SELECT_CC_I4",
1043                              []>;
1044  def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
1045                              g8rc_nox0:$T, g8rc_nox0:$F,
1046                              i32imm:$BROPC), "#SELECT_CC_I8",
1047                              []>;
1048  def SELECT_CC_F4  : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1049                              i32imm:$BROPC), "#SELECT_CC_F4",
1050                              []>;
1051  def SELECT_CC_F8  : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
1052                              i32imm:$BROPC), "#SELECT_CC_F8",
1053                              []>;
1054  def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
1055                              i32imm:$BROPC), "#SELECT_CC_VRRC",
1056                              []>;
1057
1058  // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
1059  // register bit directly.
1060  def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
1061                          gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
1062                          [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
1063  def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
1064                          g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
1065                          [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
1066  def SELECT_F4  : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
1067                          f4rc:$T, f4rc:$F), "#SELECT_F4",
1068                          [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
1069  def SELECT_F8  : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
1070                          f8rc:$T, f8rc:$F), "#SELECT_F8",
1071                          [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
1072  def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
1073                          vrrc:$T, vrrc:$F), "#SELECT_VRRC",
1074                          [(set v4i32:$dst,
1075                                (select i1:$cond, v4i32:$T, v4i32:$F))]>;
1076}
1077
1078// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
1079// scavenge a register for it.
1080let mayStore = 1 in {
1081def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
1082                     "#SPILL_CR", []>;
1083def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1084                         "#SPILL_CRBIT", []>;
1085}
1086
1087// RESTORE_CR - Indicate that we're restoring the CR register (previously
1088// spilled), so we'll need to scavenge a register for it.
1089let mayLoad = 1 in {
1090def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1091                     "#RESTORE_CR", []>;
1092def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1093                           "#RESTORE_CRBIT", []>;
1094}
1095
1096let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1097  let isReturn = 1, Uses = [LR, RM] in
1098    def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1099                           [(retflag)]>, Requires<[In32BitMode]>;
1100  let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1101    def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1102                            []>;
1103
1104    let isCodeGenOnly = 1 in {
1105      def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1106                               "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1107                               []>;
1108
1109      def BCCTR :  XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1110                                "bcctr 12, $bi, 0", IIC_BrB, []>;
1111      def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1112                                "bcctr 4, $bi, 0", IIC_BrB, []>;
1113    }
1114  }
1115}
1116
1117let Defs = [LR] in
1118  def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1119                   PPC970_Unit_BRU;
1120let Defs = [LR] in
1121  def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1122                    PPC970_Unit_BRU;
1123
1124let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1125  let isBarrier = 1 in {
1126  def B   : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1127                  "b $dst", IIC_BrB,
1128                  [(br bb:$dst)]>;
1129  def BA  : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1130                  "ba $dst", IIC_BrB, []>;
1131  }
1132
1133  // BCC represents an arbitrary conditional branch on a predicate.
1134  // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1135  // a two-value operand where a dag node expects two operands. :(
1136  let isCodeGenOnly = 1 in {
1137    def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1138                    "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1139                    /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1140    def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1141                     "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1142
1143    let isReturn = 1, Uses = [LR, RM] in
1144    def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1145                           "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1146  }
1147
1148  let isCodeGenOnly = 1 in {
1149    let Pattern = [(brcond i1:$bi, bb:$dst)] in
1150    def BC  : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1151             "bc 12, $bi, $dst">;
1152
1153    let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1154    def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1155             "bc 4, $bi, $dst">;
1156
1157    let isReturn = 1, Uses = [LR, RM] in
1158    def BCLR  : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1159                             "bclr 12, $bi, 0", IIC_BrB, []>;
1160    def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1161                             "bclr 4, $bi, 0", IIC_BrB, []>;
1162  }
1163
1164  let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1165   def BDZLR  : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1166                             "bdzlr", IIC_BrB, []>;
1167   def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1168                             "bdnzlr", IIC_BrB, []>;
1169   def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1170                             "bdzlr+", IIC_BrB, []>;
1171   def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1172                             "bdnzlr+", IIC_BrB, []>;
1173   def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1174                             "bdzlr-", IIC_BrB, []>;
1175   def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1176                             "bdnzlr-", IIC_BrB, []>;
1177  }
1178
1179  let Defs = [CTR], Uses = [CTR] in {
1180    def BDZ  : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1181                       "bdz $dst">;
1182    def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1183                       "bdnz $dst">;
1184    def BDZA  : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1185                        "bdza $dst">;
1186    def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1187                        "bdnza $dst">;
1188    def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1189                       "bdz+ $dst">;
1190    def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1191                       "bdnz+ $dst">;
1192    def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1193                        "bdza+ $dst">;
1194    def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1195                        "bdnza+ $dst">;
1196    def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1197                       "bdz- $dst">;
1198    def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1199                       "bdnz- $dst">;
1200    def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1201                        "bdza- $dst">;
1202    def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1203                        "bdnza- $dst">;
1204  }
1205}
1206
1207// The unconditional BCL used by the SjLj setjmp code.
1208let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1209  let Defs = [LR], Uses = [RM] in {
1210    def BCLalways  : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1211                            "bcl 20, 31, $dst">;
1212  }
1213}
1214
1215let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1216  // Convenient aliases for call instructions
1217  let Uses = [RM] in {
1218    def BL  : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1219                    "bl $func", IIC_BrB, []>;  // See Pat patterns below.
1220    def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1221                    "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1222
1223    let isCodeGenOnly = 1 in {
1224      def BL_TLS  : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1225                          "bl $func", IIC_BrB, []>;
1226      def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1227                       "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1228      def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1229                        "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1230
1231      def BCL  : BForm_4<16, 12, 0, 1, (outs),
1232                         (ins crbitrc:$bi, condbrtarget:$dst),
1233                         "bcl 12, $bi, $dst">;
1234      def BCLn : BForm_4<16, 4, 0, 1, (outs),
1235                         (ins crbitrc:$bi, condbrtarget:$dst),
1236                         "bcl 4, $bi, $dst">;
1237    }
1238  }
1239  let Uses = [CTR, RM] in {
1240    def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1241                             "bctrl", IIC_BrB, [(PPCbctrl)]>,
1242                Requires<[In32BitMode]>;
1243
1244    let isCodeGenOnly = 1 in {
1245      def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1246                                "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1247                                []>;
1248
1249      def BCCTRL  : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1250                                 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1251      def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1252                                 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1253    }
1254  }
1255  let Uses = [LR, RM] in {
1256    def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1257                            "blrl", IIC_BrB, []>;
1258
1259    let isCodeGenOnly = 1 in {
1260      def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1261                              "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1262                              []>;
1263
1264      def BCLRL  : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1265                                "bclrl 12, $bi, 0", IIC_BrB, []>;
1266      def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1267                                "bclrl 4, $bi, 0", IIC_BrB, []>;
1268    }
1269  }
1270  let Defs = [CTR], Uses = [CTR, RM] in {
1271    def BDZL  : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1272                        "bdzl $dst">;
1273    def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1274                        "bdnzl $dst">;
1275    def BDZLA  : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1276                         "bdzla $dst">;
1277    def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1278                         "bdnzla $dst">;
1279    def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1280                        "bdzl+ $dst">;
1281    def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1282                        "bdnzl+ $dst">;
1283    def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1284                         "bdzla+ $dst">;
1285    def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1286                         "bdnzla+ $dst">;
1287    def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1288                        "bdzl- $dst">;
1289    def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1290                        "bdnzl- $dst">;
1291    def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1292                         "bdzla- $dst">;
1293    def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1294                         "bdnzla- $dst">;
1295  }
1296  let Defs = [CTR], Uses = [CTR, LR, RM] in {
1297    def BDZLRL  : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1298                               "bdzlrl", IIC_BrB, []>;
1299    def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1300                               "bdnzlrl", IIC_BrB, []>;
1301    def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1302                               "bdzlrl+", IIC_BrB, []>;
1303    def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1304                               "bdnzlrl+", IIC_BrB, []>;
1305    def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1306                               "bdzlrl-", IIC_BrB, []>;
1307    def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1308                               "bdnzlrl-", IIC_BrB, []>;
1309  }
1310}
1311
1312let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1313def TCRETURNdi :Pseudo< (outs),
1314                        (ins calltarget:$dst, i32imm:$offset),
1315                 "#TC_RETURNd $dst $offset",
1316                 []>;
1317
1318
1319let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1320def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1321                 "#TC_RETURNa $func $offset",
1322                 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1323
1324let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1325def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1326                 "#TC_RETURNr $dst $offset",
1327                 []>;
1328
1329
1330let isCodeGenOnly = 1 in {
1331
1332let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1333    isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM]  in
1334def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1335                            []>, Requires<[In32BitMode]>;
1336
1337let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1338    isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1339def TAILB   : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1340                  "b $dst", IIC_BrB,
1341                  []>;
1342
1343let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1344    isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1345def TAILBA   : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1346                  "ba $dst", IIC_BrB,
1347                  []>;
1348
1349}
1350
1351let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1352  let Defs = [CTR] in
1353  def EH_SjLj_SetJmp32  : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1354                            "#EH_SJLJ_SETJMP32",
1355                            [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1356                          Requires<[In32BitMode]>;
1357  let isTerminator = 1 in
1358  def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1359                            "#EH_SJLJ_LONGJMP32",
1360                            [(PPCeh_sjlj_longjmp addr:$buf)]>,
1361                          Requires<[In32BitMode]>;
1362}
1363
1364let isBranch = 1, isTerminator = 1 in {
1365  def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1366                        "#EH_SjLj_Setup\t$dst", []>;
1367}
1368
1369// System call.
1370let PPC970_Unit = 7 in {
1371  def SC     : SCForm<17, 1, (outs), (ins i32imm:$lev),
1372                      "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1373}
1374
1375// Branch history rolling buffer.
1376def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB,
1377                      [(PPCclrbhrb)]>,
1378                      PPC970_DGroup_Single;
1379// The $dmy argument used for MFBHRBE is not needed; however, including
1380// it avoids automatic generation of PPCFastISel::fastEmit_i(), which
1381// interferes with necessary special handling (see PPCFastISel.cpp).
1382def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD),
1383                         (ins u10imm:$imm, u10imm:$dmy),
1384                         "mfbhrbe $rD, $imm", IIC_BrB,
1385                         [(set i32:$rD,
1386                               (PPCmfbhrbe imm:$imm, imm:$dmy))]>,
1387                         PPC970_DGroup_First;
1388
1389def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm",
1390                     IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>,
1391                     PPC970_DGroup_Single;
1392
1393// DCB* instructions.
1394def DCBA   : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1395                      IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1396                      PPC970_DGroup_Single;
1397def DCBF   : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1398                      IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1399                      PPC970_DGroup_Single;
1400def DCBI   : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1401                      IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1402                      PPC970_DGroup_Single;
1403def DCBST  : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1404                      IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1405                      PPC970_DGroup_Single;
1406def DCBZ   : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1407                      IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1408                      PPC970_DGroup_Single;
1409def DCBZL  : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1410                      IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1411                      PPC970_DGroup_Single;
1412
1413let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in {
1414def DCBT   : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst),
1415                      "dcbt $dst, $TH", IIC_LdStDCBF, []>,
1416                      PPC970_DGroup_Single;
1417def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst),
1418                      "dcbtst $dst, $TH", IIC_LdStDCBF, []>,
1419                      PPC970_DGroup_Single;
1420} // hasSideEffects = 0
1421
1422def ICBT  : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1423                       "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1424
1425def : Pat<(int_ppc_dcbt xoaddr:$dst),
1426          (DCBT 0, xoaddr:$dst)>;
1427def : Pat<(int_ppc_dcbtst xoaddr:$dst),
1428          (DCBTST 0, xoaddr:$dst)>;
1429
1430def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1431          (DCBT 0, xoaddr:$dst)>;   // data prefetch for loads
1432def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1433          (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores
1434def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1435          (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
1436
1437// Atomic operations
1438let usesCustomInserter = 1 in {
1439  let Defs = [CR0] in {
1440    def ATOMIC_LOAD_ADD_I8 : Pseudo<
1441      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1442      [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1443    def ATOMIC_LOAD_SUB_I8 : Pseudo<
1444      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1445      [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1446    def ATOMIC_LOAD_AND_I8 : Pseudo<
1447      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1448      [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1449    def ATOMIC_LOAD_OR_I8 : Pseudo<
1450      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1451      [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1452    def ATOMIC_LOAD_XOR_I8 : Pseudo<
1453      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1454      [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1455    def ATOMIC_LOAD_NAND_I8 : Pseudo<
1456      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1457      [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1458    def ATOMIC_LOAD_ADD_I16 : Pseudo<
1459      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1460      [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1461    def ATOMIC_LOAD_SUB_I16 : Pseudo<
1462      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1463      [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1464    def ATOMIC_LOAD_AND_I16 : Pseudo<
1465      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1466      [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1467    def ATOMIC_LOAD_OR_I16 : Pseudo<
1468      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1469      [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1470    def ATOMIC_LOAD_XOR_I16 : Pseudo<
1471      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1472      [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1473    def ATOMIC_LOAD_NAND_I16 : Pseudo<
1474      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1475      [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1476    def ATOMIC_LOAD_ADD_I32 : Pseudo<
1477      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1478      [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1479    def ATOMIC_LOAD_SUB_I32 : Pseudo<
1480      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1481      [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1482    def ATOMIC_LOAD_AND_I32 : Pseudo<
1483      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1484      [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1485    def ATOMIC_LOAD_OR_I32 : Pseudo<
1486      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1487      [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1488    def ATOMIC_LOAD_XOR_I32 : Pseudo<
1489      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1490      [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1491    def ATOMIC_LOAD_NAND_I32 : Pseudo<
1492      (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1493      [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1494
1495    def ATOMIC_CMP_SWAP_I8 : Pseudo<
1496      (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1497      [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1498    def ATOMIC_CMP_SWAP_I16 : Pseudo<
1499      (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1500      [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1501    def ATOMIC_CMP_SWAP_I32 : Pseudo<
1502      (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1503      [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1504
1505    def ATOMIC_SWAP_I8 : Pseudo<
1506      (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1507      [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1508    def ATOMIC_SWAP_I16 : Pseudo<
1509      (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1510      [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1511    def ATOMIC_SWAP_I32 : Pseudo<
1512      (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1513      [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1514  }
1515}
1516
1517// Instructions to support atomic operations
1518let mayLoad = 1, hasSideEffects = 0 in {
1519def LBARX : XForm_1<31,  52, (outs gprc:$rD), (ins memrr:$src),
1520                    "lbarx $rD, $src", IIC_LdStLWARX, []>,
1521                    Requires<[HasPartwordAtomics]>;
1522
1523def LHARX : XForm_1<31,  116, (outs gprc:$rD), (ins memrr:$src),
1524                    "lharx $rD, $src", IIC_LdStLWARX, []>,
1525                    Requires<[HasPartwordAtomics]>;
1526
1527def LWARX : XForm_1<31,  20, (outs gprc:$rD), (ins memrr:$src),
1528                    "lwarx $rD, $src", IIC_LdStLWARX, []>;
1529
1530// Instructions to support lock versions of atomics
1531// (EH=1 - see Power ISA 2.07 Book II 4.4.2)
1532def LBARXL : XForm_1<31,  52, (outs gprc:$rD), (ins memrr:$src),
1533                     "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1534                     Requires<[HasPartwordAtomics]>;
1535
1536def LHARXL : XForm_1<31,  116, (outs gprc:$rD), (ins memrr:$src),
1537                     "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1538                     Requires<[HasPartwordAtomics]>;
1539
1540def LWARXL : XForm_1<31,  20, (outs gprc:$rD), (ins memrr:$src),
1541                     "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT;
1542}
1543
1544let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in {
1545def STBCX : XForm_1<31, 694, (outs), (ins gprc:$rS, memrr:$dst),
1546                    "stbcx. $rS, $dst", IIC_LdStSTWCX, []>,
1547                    isDOT, Requires<[HasPartwordAtomics]>;
1548
1549def STHCX : XForm_1<31, 726, (outs), (ins gprc:$rS, memrr:$dst),
1550                    "sthcx. $rS, $dst", IIC_LdStSTWCX, []>,
1551                    isDOT, Requires<[HasPartwordAtomics]>;
1552
1553def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1554                    "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT;
1555}
1556
1557let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1558def TRAP  : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1559
1560def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1561                     "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1562def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1563                 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1564def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1565                     "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1566def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1567                 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1568
1569//===----------------------------------------------------------------------===//
1570// PPC32 Load Instructions.
1571//
1572
1573// Unindexed (r+i) Loads.
1574let PPC970_Unit = 2 in {
1575def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1576                  "lbz $rD, $src", IIC_LdStLoad,
1577                  [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1578def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1579                  "lha $rD, $src", IIC_LdStLHA,
1580                  [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1581                  PPC970_DGroup_Cracked;
1582def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1583                  "lhz $rD, $src", IIC_LdStLoad,
1584                  [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1585def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1586                  "lwz $rD, $src", IIC_LdStLoad,
1587                  [(set i32:$rD, (load iaddr:$src))]>;
1588
1589def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1590                  "lfs $rD, $src", IIC_LdStLFD,
1591                  [(set f32:$rD, (load iaddr:$src))]>;
1592def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1593                  "lfd $rD, $src", IIC_LdStLFD,
1594                  [(set f64:$rD, (load iaddr:$src))]>;
1595
1596
1597// Unindexed (r+i) Loads with Update (preinc).
1598let mayLoad = 1, hasSideEffects = 0 in {
1599def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1600                   "lbzu $rD, $addr", IIC_LdStLoadUpd,
1601                   []>, RegConstraint<"$addr.reg = $ea_result">,
1602                   NoEncode<"$ea_result">;
1603
1604def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1605                   "lhau $rD, $addr", IIC_LdStLHAU,
1606                   []>, RegConstraint<"$addr.reg = $ea_result">,
1607                   NoEncode<"$ea_result">;
1608
1609def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1610                   "lhzu $rD, $addr", IIC_LdStLoadUpd,
1611                   []>, RegConstraint<"$addr.reg = $ea_result">,
1612                   NoEncode<"$ea_result">;
1613
1614def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1615                   "lwzu $rD, $addr", IIC_LdStLoadUpd,
1616                   []>, RegConstraint<"$addr.reg = $ea_result">,
1617                   NoEncode<"$ea_result">;
1618
1619def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1620                  "lfsu $rD, $addr", IIC_LdStLFDU,
1621                  []>, RegConstraint<"$addr.reg = $ea_result">,
1622                   NoEncode<"$ea_result">;
1623
1624def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1625                  "lfdu $rD, $addr", IIC_LdStLFDU,
1626                  []>, RegConstraint<"$addr.reg = $ea_result">,
1627                   NoEncode<"$ea_result">;
1628
1629
1630// Indexed (r+r) Loads with Update (preinc).
1631def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1632                   (ins memrr:$addr),
1633                   "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1634                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1635                   NoEncode<"$ea_result">;
1636
1637def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1638                   (ins memrr:$addr),
1639                   "lhaux $rD, $addr", IIC_LdStLHAUX,
1640                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1641                   NoEncode<"$ea_result">;
1642
1643def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1644                   (ins memrr:$addr),
1645                   "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1646                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1647                   NoEncode<"$ea_result">;
1648
1649def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1650                   (ins memrr:$addr),
1651                   "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1652                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1653                   NoEncode<"$ea_result">;
1654
1655def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1656                   (ins memrr:$addr),
1657                   "lfsux $rD, $addr", IIC_LdStLFDUX,
1658                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1659                   NoEncode<"$ea_result">;
1660
1661def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1662                   (ins memrr:$addr),
1663                   "lfdux $rD, $addr", IIC_LdStLFDUX,
1664                   []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1665                   NoEncode<"$ea_result">;
1666}
1667}
1668
1669// Indexed (r+r) Loads.
1670//
1671let PPC970_Unit = 2 in {
1672def LBZX : XForm_1<31,  87, (outs gprc:$rD), (ins memrr:$src),
1673                   "lbzx $rD, $src", IIC_LdStLoad,
1674                   [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1675def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1676                   "lhax $rD, $src", IIC_LdStLHA,
1677                   [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1678                   PPC970_DGroup_Cracked;
1679def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1680                   "lhzx $rD, $src", IIC_LdStLoad,
1681                   [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1682def LWZX : XForm_1<31,  23, (outs gprc:$rD), (ins memrr:$src),
1683                   "lwzx $rD, $src", IIC_LdStLoad,
1684                   [(set i32:$rD, (load xaddr:$src))]>;
1685
1686
1687def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1688                   "lhbrx $rD, $src", IIC_LdStLoad,
1689                   [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1690def LWBRX : XForm_1<31,  534, (outs gprc:$rD), (ins memrr:$src),
1691                   "lwbrx $rD, $src", IIC_LdStLoad,
1692                   [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1693
1694def LFSX   : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1695                      "lfsx $frD, $src", IIC_LdStLFD,
1696                      [(set f32:$frD, (load xaddr:$src))]>;
1697def LFDX   : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1698                      "lfdx $frD, $src", IIC_LdStLFD,
1699                      [(set f64:$frD, (load xaddr:$src))]>;
1700
1701def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1702                      "lfiwax $frD, $src", IIC_LdStLFD,
1703                      [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1704def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1705                      "lfiwzx $frD, $src", IIC_LdStLFD,
1706                      [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1707}
1708
1709// Load Multiple
1710def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1711                  "lmw $rD, $src", IIC_LdStLMW, []>;
1712
1713//===----------------------------------------------------------------------===//
1714// PPC32 Store Instructions.
1715//
1716
1717// Unindexed (r+i) Stores.
1718let PPC970_Unit = 2 in {
1719def STB  : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1720                   "stb $rS, $src", IIC_LdStStore,
1721                   [(truncstorei8 i32:$rS, iaddr:$src)]>;
1722def STH  : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1723                   "sth $rS, $src", IIC_LdStStore,
1724                   [(truncstorei16 i32:$rS, iaddr:$src)]>;
1725def STW  : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1726                   "stw $rS, $src", IIC_LdStStore,
1727                   [(store i32:$rS, iaddr:$src)]>;
1728def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1729                   "stfs $rS, $dst", IIC_LdStSTFD,
1730                   [(store f32:$rS, iaddr:$dst)]>;
1731def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1732                   "stfd $rS, $dst", IIC_LdStSTFD,
1733                   [(store f64:$rS, iaddr:$dst)]>;
1734}
1735
1736// Unindexed (r+i) Stores with Update (preinc).
1737let PPC970_Unit = 2, mayStore = 1 in {
1738def STBU  : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1739                    "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1740                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1741def STHU  : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1742                    "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1743                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1744def STWU  : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1745                    "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1746                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1747def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1748                    "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1749                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1750def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1751                    "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1752                    RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1753}
1754
1755// Patterns to match the pre-inc stores.  We can't put the patterns on
1756// the instruction definitions directly as ISel wants the address base
1757// and offset to be separate operands, not a single complex operand.
1758def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1759          (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1760def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1761          (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1762def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1763          (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1764def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1765          (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1766def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1767          (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1768
1769// Indexed (r+r) Stores.
1770let PPC970_Unit = 2 in {
1771def STBX  : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1772                   "stbx $rS, $dst", IIC_LdStStore,
1773                   [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1774                   PPC970_DGroup_Cracked;
1775def STHX  : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1776                   "sthx $rS, $dst", IIC_LdStStore,
1777                   [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1778                   PPC970_DGroup_Cracked;
1779def STWX  : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1780                   "stwx $rS, $dst", IIC_LdStStore,
1781                   [(store i32:$rS, xaddr:$dst)]>,
1782                   PPC970_DGroup_Cracked;
1783
1784def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1785                   "sthbrx $rS, $dst", IIC_LdStStore,
1786                   [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1787                   PPC970_DGroup_Cracked;
1788def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1789                   "stwbrx $rS, $dst", IIC_LdStStore,
1790                   [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1791                   PPC970_DGroup_Cracked;
1792
1793def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1794                     "stfiwx $frS, $dst", IIC_LdStSTFD,
1795                     [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1796
1797def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1798                     "stfsx $frS, $dst", IIC_LdStSTFD,
1799                     [(store f32:$frS, xaddr:$dst)]>;
1800def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1801                     "stfdx $frS, $dst", IIC_LdStSTFD,
1802                     [(store f64:$frS, xaddr:$dst)]>;
1803}
1804
1805// Indexed (r+r) Stores with Update (preinc).
1806let PPC970_Unit = 2, mayStore = 1 in {
1807def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1808                    "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1809                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1810                    PPC970_DGroup_Cracked;
1811def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1812                    "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1813                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1814                    PPC970_DGroup_Cracked;
1815def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1816                    "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1817                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1818                    PPC970_DGroup_Cracked;
1819def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1820                    "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1821                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1822                    PPC970_DGroup_Cracked;
1823def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1824                    "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1825                    RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1826                    PPC970_DGroup_Cracked;
1827}
1828
1829// Patterns to match the pre-inc stores.  We can't put the patterns on
1830// the instruction definitions directly as ISel wants the address base
1831// and offset to be separate operands, not a single complex operand.
1832def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1833          (STBUX $rS, $ptrreg, $ptroff)>;
1834def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1835          (STHUX $rS, $ptrreg, $ptroff)>;
1836def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1837          (STWUX $rS, $ptrreg, $ptroff)>;
1838def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1839          (STFSUX $rS, $ptrreg, $ptroff)>;
1840def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1841          (STFDUX $rS, $ptrreg, $ptroff)>;
1842
1843// Store Multiple
1844def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1845                   "stmw $rS, $dst", IIC_LdStLMW, []>;
1846
1847def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1848                        "sync $L", IIC_LdStSync, []>;
1849
1850let isCodeGenOnly = 1 in {
1851  def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1852                           "msync", IIC_LdStSync, []> {
1853    let L = 0;
1854  }
1855}
1856
1857def : Pat<(int_ppc_sync),   (SYNC 0)>, Requires<[HasSYNC]>;
1858def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
1859def : Pat<(int_ppc_sync),   (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1860def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1861
1862//===----------------------------------------------------------------------===//
1863// PPC32 Arithmetic Instructions.
1864//
1865
1866let PPC970_Unit = 1 in {  // FXU Operations.
1867def ADDI   : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1868                     "addi $rD, $rA, $imm", IIC_IntSimple,
1869                     [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1870let BaseName = "addic" in {
1871let Defs = [CARRY] in
1872def ADDIC  : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1873                     "addic $rD, $rA, $imm", IIC_IntGeneral,
1874                     [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1875                     RecFormRel, PPC970_DGroup_Cracked;
1876let Defs = [CARRY, CR0] in
1877def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1878                     "addic. $rD, $rA, $imm", IIC_IntGeneral,
1879                     []>, isDOT, RecFormRel;
1880}
1881def ADDIS  : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1882                     "addis $rD, $rA, $imm", IIC_IntSimple,
1883                     [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1884let isCodeGenOnly = 1 in
1885def LA     : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1886                     "la $rD, $sym($rA)", IIC_IntGeneral,
1887                     [(set i32:$rD, (add i32:$rA,
1888                                          (PPClo tglobaladdr:$sym, 0)))]>;
1889def MULLI  : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1890                     "mulli $rD, $rA, $imm", IIC_IntMulLI,
1891                     [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1892let Defs = [CARRY] in
1893def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1894                     "subfic $rD, $rA, $imm", IIC_IntGeneral,
1895                     [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1896
1897let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1898  def LI  : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1899                       "li $rD, $imm", IIC_IntSimple,
1900                       [(set i32:$rD, imm32SExt16:$imm)]>;
1901  def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1902                       "lis $rD, $imm", IIC_IntSimple,
1903                       [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1904}
1905}
1906
1907let PPC970_Unit = 1 in {  // FXU Operations.
1908let Defs = [CR0] in {
1909def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1910                    "andi. $dst, $src1, $src2", IIC_IntGeneral,
1911                    [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1912                    isDOT;
1913def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1914                    "andis. $dst, $src1, $src2", IIC_IntGeneral,
1915                    [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1916                    isDOT;
1917}
1918def ORI   : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1919                    "ori $dst, $src1, $src2", IIC_IntSimple,
1920                    [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1921def ORIS  : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1922                    "oris $dst, $src1, $src2", IIC_IntSimple,
1923                    [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1924def XORI  : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1925                    "xori $dst, $src1, $src2", IIC_IntSimple,
1926                    [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1927def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1928                    "xoris $dst, $src1, $src2", IIC_IntSimple,
1929                    [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1930
1931def NOP   : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1932                         []>;
1933let isCodeGenOnly = 1 in {
1934// The POWER6 and POWER7 have special group-terminating nops.
1935def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1936                                        "ori 1, 1, 0", IIC_IntSimple, []>;
1937def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1938                                        "ori 2, 2, 0", IIC_IntSimple, []>;
1939}
1940
1941let isCompare = 1, hasSideEffects = 0 in {
1942  def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1943                          "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1944  def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1945                           "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1946}
1947}
1948
1949let PPC970_Unit = 1, hasSideEffects = 0 in {  // FXU Operations.
1950let isCommutable = 1 in {
1951defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1952                     "nand", "$rA, $rS, $rB", IIC_IntSimple,
1953                     [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1954defm AND  : XForm_6r<31,  28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1955                     "and", "$rA, $rS, $rB", IIC_IntSimple,
1956                     [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1957} // isCommutable
1958defm ANDC : XForm_6r<31,  60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1959                     "andc", "$rA, $rS, $rB", IIC_IntSimple,
1960                     [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1961let isCommutable = 1 in {
1962defm OR   : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1963                     "or", "$rA, $rS, $rB", IIC_IntSimple,
1964                     [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1965defm NOR  : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1966                     "nor", "$rA, $rS, $rB", IIC_IntSimple,
1967                     [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1968} // isCommutable
1969defm ORC  : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1970                     "orc", "$rA, $rS, $rB", IIC_IntSimple,
1971                     [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1972let isCommutable = 1 in {
1973defm EQV  : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1974                     "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1975                     [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1976defm XOR  : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1977                     "xor", "$rA, $rS, $rB", IIC_IntSimple,
1978                     [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1979} // isCommutable
1980defm SLW  : XForm_6r<31,  24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1981                     "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1982                     [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1983defm SRW  : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1984                     "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1985                     [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1986defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1987                      "sraw", "$rA, $rS, $rB", IIC_IntShift,
1988                      [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1989}
1990
1991let PPC970_Unit = 1 in {  // FXU Operations.
1992let hasSideEffects = 0 in {
1993defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1994                        "srawi", "$rA, $rS, $SH", IIC_IntShift,
1995                        [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1996defm CNTLZW : XForm_11r<31,  26, (outs gprc:$rA), (ins gprc:$rS),
1997                        "cntlzw", "$rA, $rS", IIC_IntGeneral,
1998                        [(set i32:$rA, (ctlz i32:$rS))]>;
1999defm EXTSB  : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
2000                        "extsb", "$rA, $rS", IIC_IntSimple,
2001                        [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
2002defm EXTSH  : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
2003                        "extsh", "$rA, $rS", IIC_IntSimple,
2004                        [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
2005
2006let isCommutable = 1 in
2007def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2008                   "cmpb $rA, $rS, $rB", IIC_IntGeneral,
2009                   [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>;
2010}
2011let isCompare = 1, hasSideEffects = 0 in {
2012  def CMPW   : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
2013                            "cmpw $crD, $rA, $rB", IIC_IntCompare>;
2014  def CMPLW  : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
2015                            "cmplw $crD, $rA, $rB", IIC_IntCompare>;
2016}
2017}
2018let PPC970_Unit = 3 in {  // FPU Operations.
2019//def FCMPO  : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
2020//                      "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
2021let isCompare = 1, hasSideEffects = 0 in {
2022  def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
2023                        "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
2024  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2025  def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
2026                        "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
2027}
2028
2029let Uses = [RM] in {
2030  let hasSideEffects = 0 in {
2031  defm FCTIW  : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
2032                          "fctiw", "$frD, $frB", IIC_FPGeneral,
2033                          []>;
2034  defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
2035                          "fctiwz", "$frD, $frB", IIC_FPGeneral,
2036                          [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
2037
2038  defm FRSP   : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
2039                          "frsp", "$frD, $frB", IIC_FPGeneral,
2040                          [(set f32:$frD, (fround f64:$frB))]>;
2041
2042  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2043  defm FRIND  : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
2044                          "frin", "$frD, $frB", IIC_FPGeneral,
2045                          [(set f64:$frD, (frnd f64:$frB))]>;
2046  defm FRINS  : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
2047                          "frin", "$frD, $frB", IIC_FPGeneral,
2048                          [(set f32:$frD, (frnd f32:$frB))]>;
2049  }
2050
2051  let hasSideEffects = 0 in {
2052  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2053  defm FRIPD  : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
2054                          "frip", "$frD, $frB", IIC_FPGeneral,
2055                          [(set f64:$frD, (fceil f64:$frB))]>;
2056  defm FRIPS  : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
2057                          "frip", "$frD, $frB", IIC_FPGeneral,
2058                          [(set f32:$frD, (fceil f32:$frB))]>;
2059  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2060  defm FRIZD  : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
2061                          "friz", "$frD, $frB", IIC_FPGeneral,
2062                          [(set f64:$frD, (ftrunc f64:$frB))]>;
2063  defm FRIZS  : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
2064                          "friz", "$frD, $frB", IIC_FPGeneral,
2065                          [(set f32:$frD, (ftrunc f32:$frB))]>;
2066  let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2067  defm FRIMD  : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
2068                          "frim", "$frD, $frB", IIC_FPGeneral,
2069                          [(set f64:$frD, (ffloor f64:$frB))]>;
2070  defm FRIMS  : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
2071                          "frim", "$frD, $frB", IIC_FPGeneral,
2072                          [(set f32:$frD, (ffloor f32:$frB))]>;
2073
2074  defm FSQRT  : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
2075                          "fsqrt", "$frD, $frB", IIC_FPSqrtD,
2076                          [(set f64:$frD, (fsqrt f64:$frB))]>;
2077  defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
2078                          "fsqrts", "$frD, $frB", IIC_FPSqrtS,
2079                          [(set f32:$frD, (fsqrt f32:$frB))]>;
2080  }
2081  }
2082}
2083
2084/// Note that FMR is defined as pseudo-ops on the PPC970 because they are
2085/// often coalesced away and we don't want the dispatch group builder to think
2086/// that they will fill slots (which could cause the load of a LSU reject to
2087/// sneak into a d-group with a store).
2088let hasSideEffects = 0 in
2089defm FMR   : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
2090                       "fmr", "$frD, $frB", IIC_FPGeneral,
2091                       []>,  // (set f32:$frD, f32:$frB)
2092                       PPC970_Unit_Pseudo;
2093
2094let PPC970_Unit = 3, hasSideEffects = 0 in {  // FPU Operations.
2095// These are artificially split into two different forms, for 4/8 byte FP.
2096defm FABSS  : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
2097                        "fabs", "$frD, $frB", IIC_FPGeneral,
2098                        [(set f32:$frD, (fabs f32:$frB))]>;
2099let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2100defm FABSD  : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
2101                        "fabs", "$frD, $frB", IIC_FPGeneral,
2102                        [(set f64:$frD, (fabs f64:$frB))]>;
2103defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
2104                        "fnabs", "$frD, $frB", IIC_FPGeneral,
2105                        [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
2106let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2107defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
2108                        "fnabs", "$frD, $frB", IIC_FPGeneral,
2109                        [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
2110defm FNEGS  : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
2111                        "fneg", "$frD, $frB", IIC_FPGeneral,
2112                        [(set f32:$frD, (fneg f32:$frB))]>;
2113let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2114defm FNEGD  : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
2115                        "fneg", "$frD, $frB", IIC_FPGeneral,
2116                        [(set f64:$frD, (fneg f64:$frB))]>;
2117
2118defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
2119                        "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2120                        [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
2121let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2122defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
2123                        "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2124                        [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
2125
2126// Reciprocal estimates.
2127defm FRE      : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
2128                          "fre", "$frD, $frB", IIC_FPGeneral,
2129                          [(set f64:$frD, (PPCfre f64:$frB))]>;
2130defm FRES     : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
2131                          "fres", "$frD, $frB", IIC_FPGeneral,
2132                          [(set f32:$frD, (PPCfre f32:$frB))]>;
2133defm FRSQRTE  : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
2134                          "frsqrte", "$frD, $frB", IIC_FPGeneral,
2135                          [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
2136defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
2137                          "frsqrtes", "$frD, $frB", IIC_FPGeneral,
2138                          [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
2139}
2140
2141// XL-Form instructions.  condition register logical ops.
2142//
2143let hasSideEffects = 0 in
2144def MCRF   : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
2145                      "mcrf $BF, $BFA", IIC_BrMCR>,
2146             PPC970_DGroup_First, PPC970_Unit_CRU;
2147
2148// FIXME: According to the ISA (section 2.5.1 of version 2.06), the
2149// condition-register logical instructions have preferred forms. Specifically,
2150// it is preferred that the bit specified by the BT field be in the same
2151// condition register as that specified by the bit BB. We might want to account
2152// for this via hinting the register allocator and anti-dep breakers, or we
2153// could constrain the register class to force this constraint and then loosen
2154// it during register allocation via convertToThreeAddress or some similar
2155// mechanism.
2156
2157let isCommutable = 1 in {
2158def CRAND  : XLForm_1<19, 257, (outs crbitrc:$CRD),
2159                               (ins crbitrc:$CRA, crbitrc:$CRB),
2160                      "crand $CRD, $CRA, $CRB", IIC_BrCR,
2161                      [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2162
2163def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2164                               (ins crbitrc:$CRA, crbitrc:$CRB),
2165                      "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2166                      [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2167
2168def CROR   : XLForm_1<19, 449, (outs crbitrc:$CRD),
2169                               (ins crbitrc:$CRA, crbitrc:$CRB),
2170                      "cror $CRD, $CRA, $CRB", IIC_BrCR,
2171                      [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2172
2173def CRXOR  : XLForm_1<19, 193, (outs crbitrc:$CRD),
2174                               (ins crbitrc:$CRA, crbitrc:$CRB),
2175                      "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2176                      [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2177
2178def CRNOR  : XLForm_1<19, 33, (outs crbitrc:$CRD),
2179                              (ins crbitrc:$CRA, crbitrc:$CRB),
2180                      "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2181                      [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2182
2183def CREQV  : XLForm_1<19, 289, (outs crbitrc:$CRD),
2184                               (ins crbitrc:$CRA, crbitrc:$CRB),
2185                      "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2186                      [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2187} // isCommutable
2188
2189def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2190                               (ins crbitrc:$CRA, crbitrc:$CRB),
2191                      "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2192                      [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2193
2194def CRORC  : XLForm_1<19, 417, (outs crbitrc:$CRD),
2195                               (ins crbitrc:$CRA, crbitrc:$CRB),
2196                      "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2197                      [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2198
2199let isCodeGenOnly = 1 in {
2200def CRSET  : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2201              "creqv $dst, $dst, $dst", IIC_BrCR,
2202              [(set i1:$dst, 1)]>;
2203
2204def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2205              "crxor $dst, $dst, $dst", IIC_BrCR,
2206              [(set i1:$dst, 0)]>;
2207
2208let Defs = [CR1EQ], CRD = 6 in {
2209def CR6SET  : XLForm_1_ext<19, 289, (outs), (ins),
2210              "creqv 6, 6, 6", IIC_BrCR,
2211              [(PPCcr6set)]>;
2212
2213def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2214              "crxor 6, 6, 6", IIC_BrCR,
2215              [(PPCcr6unset)]>;
2216}
2217}
2218
2219// XFX-Form instructions.  Instructions that deal with SPRs.
2220//
2221
2222def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2223                      "mfspr $RT, $SPR", IIC_SprMFSPR>;
2224def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2225                      "mtspr $SPR, $RT", IIC_SprMTSPR>;
2226
2227def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2228                     "mftb $RT, $SPR", IIC_SprMFTB>;
2229
2230// A pseudo-instruction used to implement the read of the 64-bit cycle counter
2231// on a 32-bit target.
2232let hasSideEffects = 1, usesCustomInserter = 1 in
2233def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins),
2234                    "#ReadTB", []>;
2235
2236let Uses = [CTR] in {
2237def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2238                          "mfctr $rT", IIC_SprMFSPR>,
2239            PPC970_DGroup_First, PPC970_Unit_FXU;
2240}
2241let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2242def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2243                          "mtctr $rS", IIC_SprMTSPR>,
2244            PPC970_DGroup_First, PPC970_Unit_FXU;
2245}
2246let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2247let Pattern = [(int_ppc_mtctr i32:$rS)] in
2248def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2249                              "mtctr $rS", IIC_SprMTSPR>,
2250                PPC970_DGroup_First, PPC970_Unit_FXU;
2251}
2252
2253let Defs = [LR] in {
2254def MTLR  : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2255                          "mtlr $rS", IIC_SprMTSPR>,
2256            PPC970_DGroup_First, PPC970_Unit_FXU;
2257}
2258let Uses = [LR] in {
2259def MFLR  : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2260                          "mflr $rT", IIC_SprMFSPR>,
2261            PPC970_DGroup_First, PPC970_Unit_FXU;
2262}
2263
2264let isCodeGenOnly = 1 in {
2265  // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2266  // like a GPR on the PPC970.  As such, copies in and out have the same
2267  // performance characteristics as an OR instruction.
2268  def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2269                               "mtspr 256, $rS", IIC_IntGeneral>,
2270                 PPC970_DGroup_Single, PPC970_Unit_FXU;
2271  def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2272                               "mfspr $rT, 256", IIC_IntGeneral>,
2273                 PPC970_DGroup_First, PPC970_Unit_FXU;
2274
2275  def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2276                                (outs VRSAVERC:$reg), (ins gprc:$rS),
2277                                "mtspr 256, $rS", IIC_IntGeneral>,
2278                  PPC970_DGroup_Single, PPC970_Unit_FXU;
2279  def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2280                                (ins VRSAVERC:$reg),
2281                                "mfspr $rT, 256", IIC_IntGeneral>,
2282                  PPC970_DGroup_First, PPC970_Unit_FXU;
2283}
2284
2285// SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2286// so we'll need to scavenge a register for it.
2287let mayStore = 1 in
2288def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2289                     "#SPILL_VRSAVE", []>;
2290
2291// RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2292// spilled), so we'll need to scavenge a register for it.
2293let mayLoad = 1 in
2294def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2295                     "#RESTORE_VRSAVE", []>;
2296
2297let hasSideEffects = 0 in {
2298def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2299                       "mtocrf $FXM, $ST", IIC_BrMCRX>,
2300            PPC970_DGroup_First, PPC970_Unit_CRU;
2301
2302def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2303                      "mtcrf $FXM, $rS", IIC_BrMCRX>,
2304            PPC970_MicroCode, PPC970_Unit_CRU;
2305
2306let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2307def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2308                       "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2309            PPC970_DGroup_First, PPC970_Unit_CRU;
2310
2311def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2312                     "mfcr $rT", IIC_SprMFCR>,
2313                     PPC970_MicroCode, PPC970_Unit_CRU;
2314} // hasSideEffects = 0
2315
2316// Pseudo instruction to perform FADD in round-to-zero mode.
2317let usesCustomInserter = 1, Uses = [RM] in {
2318  def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2319                      [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2320}
2321
2322// The above pseudo gets expanded to make use of the following instructions
2323// to manipulate FPSCR.  Note that FPSCR is not modeled at the DAG level.
2324let Uses = [RM], Defs = [RM] in {
2325  def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2326                        "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2327               PPC970_DGroup_Single, PPC970_Unit_FPU;
2328  def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2329                        "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2330               PPC970_DGroup_Single, PPC970_Unit_FPU;
2331  let isCodeGenOnly = 1 in
2332  def MTFSFb  : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2333                        "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2334                PPC970_DGroup_Single, PPC970_Unit_FPU;
2335}
2336let Uses = [RM] in {
2337  def MFFS   : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2338                         "mffs $rT", IIC_IntMFFS,
2339                         [(set f64:$rT, (PPCmffs))]>,
2340               PPC970_DGroup_Single, PPC970_Unit_FPU;
2341
2342  let Defs = [CR1] in
2343  def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2344                      "mffs. $rT", IIC_IntMFFS, []>, isDOT;
2345}
2346
2347
2348let PPC970_Unit = 1, hasSideEffects = 0 in {  // FXU Operations.
2349// XO-Form instructions.  Arithmetic instructions that can set overflow bit
2350let isCommutable = 1 in
2351defm ADD4  : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2352                       "add", "$rT, $rA, $rB", IIC_IntSimple,
2353                       [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2354let isCodeGenOnly = 1 in
2355def ADD4TLS  : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2356                       "add $rT, $rA, $rB", IIC_IntSimple,
2357                       [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2358let isCommutable = 1 in
2359defm ADDC  : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2360                        "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2361                        [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2362                        PPC970_DGroup_Cracked;
2363
2364defm DIVW  : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2365                          "divw", "$rT, $rA, $rB", IIC_IntDivW,
2366                          [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>;
2367defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2368                          "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2369                          [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>;
2370def DIVWE : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2371                     "divwe $rT, $rA, $rB", IIC_IntDivW,
2372                     [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>,
2373                     Requires<[HasExtDiv]>;
2374let Defs = [CR0] in
2375def DIVWEo : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2376                      "divwe. $rT, $rA, $rB", IIC_IntDivW,
2377                      []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2378                      Requires<[HasExtDiv]>;
2379def DIVWEU : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2380                      "divweu $rT, $rA, $rB", IIC_IntDivW,
2381                      [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>,
2382                      Requires<[HasExtDiv]>;
2383let Defs = [CR0] in
2384def DIVWEUo : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2385                       "divweu. $rT, $rA, $rB", IIC_IntDivW,
2386                       []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2387                       Requires<[HasExtDiv]>;
2388let isCommutable = 1 in {
2389defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2390                       "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2391                       [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2392defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2393                       "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2394                       [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2395defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2396                       "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2397                       [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2398} // isCommutable
2399defm SUBF  : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2400                       "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2401                       [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2402defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2403                        "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2404                        [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2405                        PPC970_DGroup_Cracked;
2406defm NEG    : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2407                        "neg", "$rT, $rA", IIC_IntSimple,
2408                        [(set i32:$rT, (ineg i32:$rA))]>;
2409let Uses = [CARRY] in {
2410let isCommutable = 1 in
2411defm ADDE  : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2412                        "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2413                        [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2414defm ADDME  : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2415                         "addme", "$rT, $rA", IIC_IntGeneral,
2416                         [(set i32:$rT, (adde i32:$rA, -1))]>;
2417defm ADDZE  : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2418                         "addze", "$rT, $rA", IIC_IntGeneral,
2419                         [(set i32:$rT, (adde i32:$rA, 0))]>;
2420defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2421                        "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2422                        [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2423defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2424                         "subfme", "$rT, $rA", IIC_IntGeneral,
2425                         [(set i32:$rT, (sube -1, i32:$rA))]>;
2426defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2427                         "subfze", "$rT, $rA", IIC_IntGeneral,
2428                         [(set i32:$rT, (sube 0, i32:$rA))]>;
2429}
2430}
2431
2432// A-Form instructions.  Most of the instructions executed in the FPU are of
2433// this type.
2434//
2435let PPC970_Unit = 3, hasSideEffects = 0 in {  // FPU Operations.
2436let Uses = [RM] in {
2437let isCommutable = 1 in {
2438  defm FMADD : AForm_1r<63, 29,
2439                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2440                      "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2441                      [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2442  defm FMADDS : AForm_1r<59, 29,
2443                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2444                      "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2445                      [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2446  defm FMSUB : AForm_1r<63, 28,
2447                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2448                      "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2449                      [(set f64:$FRT,
2450                            (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2451  defm FMSUBS : AForm_1r<59, 28,
2452                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2453                      "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2454                      [(set f32:$FRT,
2455                            (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2456  defm FNMADD : AForm_1r<63, 31,
2457                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2458                      "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2459                      [(set f64:$FRT,
2460                            (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2461  defm FNMADDS : AForm_1r<59, 31,
2462                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2463                      "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2464                      [(set f32:$FRT,
2465                            (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2466  defm FNMSUB : AForm_1r<63, 30,
2467                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2468                      "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2469                      [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2470                                                 (fneg f64:$FRB))))]>;
2471  defm FNMSUBS : AForm_1r<59, 30,
2472                      (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2473                      "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2474                      [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2475                                                 (fneg f32:$FRB))))]>;
2476} // isCommutable
2477}
2478// FSEL is artificially split into 4 and 8-byte forms for the result.  To avoid
2479// having 4 of these, force the comparison to always be an 8-byte double (code
2480// should use an FMRSD if the input comparison value really wants to be a float)
2481// and 4/8 byte forms for the result and operand type..
2482let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2483defm FSELD : AForm_1r<63, 23,
2484                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2485                      "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2486                      [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2487defm FSELS : AForm_1r<63, 23,
2488                      (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2489                      "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2490                      [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2491let Uses = [RM] in {
2492  let isCommutable = 1 in {
2493  defm FADD  : AForm_2r<63, 21,
2494                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2495                        "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2496                        [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2497  defm FADDS : AForm_2r<59, 21,
2498                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2499                        "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2500                        [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2501  } // isCommutable
2502  defm FDIV  : AForm_2r<63, 18,
2503                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2504                        "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2505                        [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2506  defm FDIVS : AForm_2r<59, 18,
2507                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2508                        "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2509                        [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2510  let isCommutable = 1 in {
2511  defm FMUL  : AForm_3r<63, 25,
2512                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2513                        "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2514                        [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2515  defm FMULS : AForm_3r<59, 25,
2516                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2517                        "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2518                        [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2519  } // isCommutable
2520  defm FSUB  : AForm_2r<63, 20,
2521                        (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2522                        "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2523                        [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2524  defm FSUBS : AForm_2r<59, 20,
2525                        (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2526                        "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2527                        [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2528  }
2529}
2530
2531let hasSideEffects = 0 in {
2532let PPC970_Unit = 1 in {  // FXU Operations.
2533  let isSelect = 1 in
2534  def ISEL  : AForm_4<31, 15,
2535                     (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2536                     "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
2537                     []>;
2538}
2539
2540let PPC970_Unit = 1 in {  // FXU Operations.
2541// M-Form instructions.  rotate and mask instructions.
2542//
2543let isCommutable = 1 in {
2544// RLWIMI can be commuted if the rotate amount is zero.
2545defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2546                       (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2547                       u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2548                       IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2549                       RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2550}
2551let BaseName = "rlwinm" in {
2552def RLWINM : MForm_2<21,
2553                     (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2554                     "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2555                     []>, RecFormRel;
2556let Defs = [CR0] in
2557def RLWINMo : MForm_2<21,
2558                      (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2559                      "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2560                      []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2561}
2562defm RLWNM  : MForm_2r<23, (outs gprc:$rA),
2563                       (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2564                       "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2565                       []>;
2566}
2567} // hasSideEffects = 0
2568
2569//===----------------------------------------------------------------------===//
2570// PowerPC Instruction Patterns
2571//
2572
2573// Arbitrary immediate support.  Implement in terms of LIS/ORI.
2574def : Pat<(i32 imm:$imm),
2575          (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2576
2577// Implement the 'not' operation with the NOR instruction.
2578def i32not : OutPatFrag<(ops node:$in),
2579                        (NOR $in, $in)>;
2580def        : Pat<(not i32:$in),
2581                 (i32not $in)>;
2582
2583// ADD an arbitrary immediate.
2584def : Pat<(add i32:$in, imm:$imm),
2585          (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2586// OR an arbitrary immediate.
2587def : Pat<(or i32:$in, imm:$imm),
2588          (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2589// XOR an arbitrary immediate.
2590def : Pat<(xor i32:$in, imm:$imm),
2591          (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2592// SUBFIC
2593def : Pat<(sub imm32SExt16:$imm, i32:$in),
2594          (SUBFIC $in, imm:$imm)>;
2595
2596// SHL/SRL
2597def : Pat<(shl i32:$in, (i32 imm:$imm)),
2598          (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2599def : Pat<(srl i32:$in, (i32 imm:$imm)),
2600          (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2601
2602// ROTL
2603def : Pat<(rotl i32:$in, i32:$sh),
2604          (RLWNM $in, $sh, 0, 31)>;
2605def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2606          (RLWINM $in, imm:$imm, 0, 31)>;
2607
2608// RLWNM
2609def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2610          (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2611
2612// Calls
2613def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2614          (BL tglobaladdr:$dst)>;
2615def : Pat<(PPCcall (i32 texternalsym:$dst)),
2616          (BL texternalsym:$dst)>;
2617
2618def : Pat<(PPCtc_return (i32 tglobaladdr:$dst),  imm:$imm),
2619          (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2620
2621def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2622          (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2623
2624def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2625          (TCRETURNri CTRRC:$dst, imm:$imm)>;
2626
2627
2628
2629// Hi and Lo for Darwin Global Addresses.
2630def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2631def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2632def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2633def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2634def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2635def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2636def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2637def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2638def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2639          (ADDIS $in, tglobaltlsaddr:$g)>;
2640def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2641          (ADDI $in, tglobaltlsaddr:$g)>;
2642def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2643          (ADDIS $in, tglobaladdr:$g)>;
2644def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2645          (ADDIS $in, tconstpool:$g)>;
2646def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2647          (ADDIS $in, tjumptable:$g)>;
2648def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2649          (ADDIS $in, tblockaddress:$g)>;
2650
2651// Support for thread-local storage.
2652def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2653                [(set i32:$rD, (PPCppc32GOT))]>;
2654
2655// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2656// This uses two output registers, the first as the real output, the second as a
2657// temporary register, used internally in code generation.
2658def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2659                []>, NoEncode<"$rT">;
2660
2661def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2662                           "#LDgotTprelL32",
2663                           [(set i32:$rD,
2664                             (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2665def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2666          (ADD4TLS $in, tglobaltlsaddr:$g)>;
2667
2668def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2669                         "#ADDItlsgdL32",
2670                         [(set i32:$rD,
2671                           (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2672// LR is a true define, while the rest of the Defs are clobbers.  R3 is
2673// explicitly defined when this op is created, so not mentioned here.
2674let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2675    Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2676def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2677                          "GETtlsADDR32",
2678                          [(set i32:$rD,
2679                            (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2680// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded.  R3 and LR
2681// are true defines while the rest of the Defs are clobbers.
2682let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2683    Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2684def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD),
2685                              (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2686                              "#ADDItlsgdLADDR32",
2687                              [(set i32:$rD,
2688                                (PPCaddiTlsgdLAddr i32:$reg,
2689                                                   tglobaltlsaddr:$disp,
2690                                                   tglobaltlsaddr:$sym))]>;
2691def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2692                          "#ADDItlsldL32",
2693                          [(set i32:$rD,
2694                            (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2695// LR is a true define, while the rest of the Defs are clobbers.  R3 is
2696// explicitly defined when this op is created, so not mentioned here.
2697let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2698    Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2699def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2700                            "GETtlsldADDR32",
2701                            [(set i32:$rD,
2702                              (PPCgetTlsldAddr i32:$reg,
2703                                               tglobaltlsaddr:$sym))]>;
2704// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded.  R3 and LR
2705// are true defines while the rest of the Defs are clobbers.
2706let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2707    Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2708def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD),
2709                              (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2710                              "#ADDItlsldLADDR32",
2711                              [(set i32:$rD,
2712                                (PPCaddiTlsldLAddr i32:$reg,
2713                                                   tglobaltlsaddr:$disp,
2714                                                   tglobaltlsaddr:$sym))]>;
2715def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2716                           "#ADDIdtprelL32",
2717                           [(set i32:$rD,
2718                             (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2719def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2720                            "#ADDISdtprelHA32",
2721                            [(set i32:$rD,
2722                              (PPCaddisDtprelHA i32:$reg,
2723                                                tglobaltlsaddr:$disp))]>;
2724
2725// Support for Position-independent code
2726def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2727                   "#LWZtoc",
2728                   [(set i32:$rD,
2729                      (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2730// Get Global (GOT) Base Register offset, from the word immediately preceding
2731// the function label.
2732def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2733
2734
2735// Standard shifts.  These are represented separately from the real shifts above
2736// so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2737// amounts.
2738def : Pat<(sra i32:$rS, i32:$rB),
2739          (SRAW $rS, $rB)>;
2740def : Pat<(srl i32:$rS, i32:$rB),
2741          (SRW $rS, $rB)>;
2742def : Pat<(shl i32:$rS, i32:$rB),
2743          (SLW $rS, $rB)>;
2744
2745def : Pat<(zextloadi1 iaddr:$src),
2746          (LBZ iaddr:$src)>;
2747def : Pat<(zextloadi1 xaddr:$src),
2748          (LBZX xaddr:$src)>;
2749def : Pat<(extloadi1 iaddr:$src),
2750          (LBZ iaddr:$src)>;
2751def : Pat<(extloadi1 xaddr:$src),
2752          (LBZX xaddr:$src)>;
2753def : Pat<(extloadi8 iaddr:$src),
2754          (LBZ iaddr:$src)>;
2755def : Pat<(extloadi8 xaddr:$src),
2756          (LBZX xaddr:$src)>;
2757def : Pat<(extloadi16 iaddr:$src),
2758          (LHZ iaddr:$src)>;
2759def : Pat<(extloadi16 xaddr:$src),
2760          (LHZX xaddr:$src)>;
2761def : Pat<(f64 (extloadf32 iaddr:$src)),
2762          (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2763def : Pat<(f64 (extloadf32 xaddr:$src)),
2764          (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2765
2766def : Pat<(f64 (fextend f32:$src)),
2767          (COPY_TO_REGCLASS $src, F8RC)>;
2768
2769// Only seq_cst fences require the heavyweight sync (SYNC 0).
2770// All others can use the lightweight sync (SYNC 1).
2771// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
2772// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
2773// versions of Power.
2774def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2775def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2776def : Pat<(atomic_fence (imm),   (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
2777def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2778
2779// Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2780def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2781          (FNMSUB $A, $C, $B)>;
2782def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2783          (FNMSUB $A, $C, $B)>;
2784def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2785          (FNMSUBS $A, $C, $B)>;
2786def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2787          (FNMSUBS $A, $C, $B)>;
2788
2789// FCOPYSIGN's operand types need not agree.
2790def : Pat<(fcopysign f64:$frB, f32:$frA),
2791          (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2792def : Pat<(fcopysign f32:$frB, f64:$frA),
2793          (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2794
2795include "PPCInstrAltivec.td"
2796include "PPCInstrSPE.td"
2797include "PPCInstr64Bit.td"
2798include "PPCInstrVSX.td"
2799include "PPCInstrQPX.td"
2800include "PPCInstrHTM.td"
2801
2802def crnot : OutPatFrag<(ops node:$in),
2803                       (CRNOR $in, $in)>;
2804def       : Pat<(not i1:$in),
2805                (crnot $in)>;
2806
2807// Patterns for arithmetic i1 operations.
2808def : Pat<(add i1:$a, i1:$b),
2809          (CRXOR $a, $b)>;
2810def : Pat<(sub i1:$a, i1:$b),
2811          (CRXOR $a, $b)>;
2812def : Pat<(mul i1:$a, i1:$b),
2813          (CRAND $a, $b)>;
2814
2815// We're sometimes asked to materialize i1 -1, which is just 1 in this case
2816// (-1 is used to mean all bits set).
2817def : Pat<(i1 -1), (CRSET)>;
2818
2819// i1 extensions, implemented in terms of isel.
2820def : Pat<(i32 (zext i1:$in)),
2821          (SELECT_I4 $in, (LI 1), (LI 0))>;
2822def : Pat<(i32 (sext i1:$in)),
2823          (SELECT_I4 $in, (LI -1), (LI 0))>;
2824
2825def : Pat<(i64 (zext i1:$in)),
2826          (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2827def : Pat<(i64 (sext i1:$in)),
2828          (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2829
2830// FIXME: We should choose either a zext or a sext based on other constants
2831// already around.
2832def : Pat<(i32 (anyext i1:$in)),
2833          (SELECT_I4 $in, (LI 1), (LI 0))>;
2834def : Pat<(i64 (anyext i1:$in)),
2835          (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2836
2837// match setcc on i1 variables.
2838def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2839          (CRANDC $s2, $s1)>;
2840def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2841          (CRANDC $s2, $s1)>;
2842def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2843          (CRORC $s2, $s1)>;
2844def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2845          (CRORC $s2, $s1)>;
2846def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2847          (CREQV $s1, $s2)>;
2848def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2849          (CRORC $s1, $s2)>;
2850def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2851          (CRORC $s1, $s2)>;
2852def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2853          (CRANDC $s1, $s2)>;
2854def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2855          (CRANDC $s1, $s2)>;
2856def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2857          (CRXOR $s1, $s2)>;
2858
2859// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2860// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2861// floating-point types.
2862
2863multiclass CRNotPat<dag pattern, dag result> {
2864  def : Pat<pattern, (crnot result)>;
2865  def : Pat<(not pattern), result>;
2866
2867  // We can also fold the crnot into an extension:
2868  def : Pat<(i32 (zext pattern)),
2869            (SELECT_I4 result, (LI 0), (LI 1))>;
2870  def : Pat<(i32 (sext pattern)),
2871            (SELECT_I4 result, (LI 0), (LI -1))>;
2872
2873  // We can also fold the crnot into an extension:
2874  def : Pat<(i64 (zext pattern)),
2875            (SELECT_I8 result, (LI8 0), (LI8 1))>;
2876  def : Pat<(i64 (sext pattern)),
2877            (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2878
2879  // FIXME: We should choose either a zext or a sext based on other constants
2880  // already around.
2881  def : Pat<(i32 (anyext pattern)),
2882            (SELECT_I4 result, (LI 0), (LI 1))>;
2883
2884  def : Pat<(i64 (anyext pattern)),
2885            (SELECT_I8 result, (LI8 0), (LI8 1))>;
2886}
2887
2888// FIXME: Because of what seems like a bug in TableGen's type-inference code,
2889// we need to write imm:$imm in the output patterns below, not just $imm, or
2890// else the resulting matcher will not correctly add the immediate operand
2891// (making it a register operand instead).
2892
2893// extended SETCC.
2894multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2895                       OutPatFrag rfrag, OutPatFrag rfrag8> {
2896  def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2897            (rfrag $s1)>;
2898  def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2899            (rfrag8 $s1)>;
2900  def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2901            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2902  def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2903            (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2904
2905  def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2906            (rfrag $s1)>;
2907  def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2908            (rfrag8 $s1)>;
2909  def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2910            (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2911  def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2912            (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2913}
2914
2915// Note that we do all inversions below with i(32|64)not, instead of using
2916// (xori x, 1) because on the A2 nor has single-cycle latency while xori
2917// has 2-cycle latency.
2918
2919defm : ExtSetCCPat<SETEQ,
2920                   PatFrag<(ops node:$in, node:$cc),
2921                           (setcc $in, 0, $cc)>,
2922                   OutPatFrag<(ops node:$in),
2923                              (RLWINM (CNTLZW $in), 27, 31, 31)>,
2924                   OutPatFrag<(ops node:$in),
2925                              (RLDICL (CNTLZD $in), 58, 63)> >;
2926
2927defm : ExtSetCCPat<SETNE,
2928                   PatFrag<(ops node:$in, node:$cc),
2929                           (setcc $in, 0, $cc)>,
2930                   OutPatFrag<(ops node:$in),
2931                              (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
2932                   OutPatFrag<(ops node:$in),
2933                              (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
2934
2935defm : ExtSetCCPat<SETLT,
2936                   PatFrag<(ops node:$in, node:$cc),
2937                           (setcc $in, 0, $cc)>,
2938                   OutPatFrag<(ops node:$in),
2939                              (RLWINM $in, 1, 31, 31)>,
2940                   OutPatFrag<(ops node:$in),
2941                              (RLDICL $in, 1, 63)> >;
2942
2943defm : ExtSetCCPat<SETGE,
2944                   PatFrag<(ops node:$in, node:$cc),
2945                           (setcc $in, 0, $cc)>,
2946                   OutPatFrag<(ops node:$in),
2947                              (RLWINM (i32not $in), 1, 31, 31)>,
2948                   OutPatFrag<(ops node:$in),
2949                              (RLDICL (i64not $in), 1, 63)> >;
2950
2951defm : ExtSetCCPat<SETGT,
2952                   PatFrag<(ops node:$in, node:$cc),
2953                           (setcc $in, 0, $cc)>,
2954                   OutPatFrag<(ops node:$in),
2955                              (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
2956                   OutPatFrag<(ops node:$in),
2957                              (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
2958
2959defm : ExtSetCCPat<SETLE,
2960                   PatFrag<(ops node:$in, node:$cc),
2961                           (setcc $in, 0, $cc)>,
2962                   OutPatFrag<(ops node:$in),
2963                              (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
2964                   OutPatFrag<(ops node:$in),
2965                              (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
2966
2967defm : ExtSetCCPat<SETLT,
2968                   PatFrag<(ops node:$in, node:$cc),
2969                           (setcc $in, -1, $cc)>,
2970                   OutPatFrag<(ops node:$in),
2971                              (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
2972                   OutPatFrag<(ops node:$in),
2973                              (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2974
2975defm : ExtSetCCPat<SETGE,
2976                   PatFrag<(ops node:$in, node:$cc),
2977                           (setcc $in, -1, $cc)>,
2978                   OutPatFrag<(ops node:$in),
2979                              (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
2980                   OutPatFrag<(ops node:$in),
2981                              (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2982
2983defm : ExtSetCCPat<SETGT,
2984                   PatFrag<(ops node:$in, node:$cc),
2985                           (setcc $in, -1, $cc)>,
2986                   OutPatFrag<(ops node:$in),
2987                              (RLWINM (i32not $in), 1, 31, 31)>,
2988                   OutPatFrag<(ops node:$in),
2989                              (RLDICL (i64not $in), 1, 63)> >;
2990
2991defm : ExtSetCCPat<SETLE,
2992                   PatFrag<(ops node:$in, node:$cc),
2993                           (setcc $in, -1, $cc)>,
2994                   OutPatFrag<(ops node:$in),
2995                              (RLWINM $in, 1, 31, 31)>,
2996                   OutPatFrag<(ops node:$in),
2997                              (RLDICL $in, 1, 63)> >;
2998
2999// SETCC for i32.
3000def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
3001          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3002def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
3003          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3004def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
3005          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3006def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
3007          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3008def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
3009          (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3010def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
3011          (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3012
3013// For non-equality comparisons, the default code would materialize the
3014// constant, then compare against it, like this:
3015//   lis r2, 4660
3016//   ori r2, r2, 22136
3017//   cmpw cr0, r3, r2
3018//   beq cr0,L6
3019// Since we are just comparing for equality, we can emit this instead:
3020//   xoris r0,r3,0x1234
3021//   cmplwi cr0,r0,0x5678
3022//   beq cr0,L6
3023
3024def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
3025          (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3026                                  (LO16 imm:$imm)), sub_eq)>;
3027
3028defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
3029                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3030defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
3031                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3032defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
3033                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3034defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
3035                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3036defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
3037                (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3038defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
3039                (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3040
3041defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
3042                (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3043                                        (LO16 imm:$imm)), sub_eq)>;
3044
3045def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
3046          (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3047def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
3048          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3049def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
3050          (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3051def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
3052          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3053def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
3054          (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3055
3056defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
3057                (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3058defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
3059                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3060defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
3061                (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3062defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
3063                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3064defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
3065                (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3066
3067// SETCC for i64.
3068def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
3069          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3070def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
3071          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3072def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
3073          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3074def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
3075          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3076def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
3077          (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3078def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
3079          (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3080
3081// For non-equality comparisons, the default code would materialize the
3082// constant, then compare against it, like this:
3083//   lis r2, 4660
3084//   ori r2, r2, 22136
3085//   cmpd cr0, r3, r2
3086//   beq cr0,L6
3087// Since we are just comparing for equality, we can emit this instead:
3088//   xoris r0,r3,0x1234
3089//   cmpldi cr0,r0,0x5678
3090//   beq cr0,L6
3091
3092def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
3093          (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3094                                  (LO16 imm:$imm)), sub_eq)>;
3095
3096defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3097                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3098defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
3099                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3100defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
3101                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3102defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
3103                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3104defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
3105                (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3106defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
3107                (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3108
3109defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
3110                (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3111                                        (LO16 imm:$imm)), sub_eq)>;
3112
3113def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
3114          (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3115def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3116          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3117def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3118          (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3119def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
3120          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3121def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
3122          (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3123
3124defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3125                (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3126defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
3127                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3128defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
3129                (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3130defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
3131                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3132defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
3133                (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3134
3135// SETCC for f32.
3136def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
3137          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3138def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
3139          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3140def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
3141          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3142def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
3143          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3144def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
3145          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3146def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
3147          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3148def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
3149          (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3150
3151defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3152                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3153defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
3154                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3155defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
3156                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3157defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
3158                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3159defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
3160                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3161defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
3162                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3163defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
3164                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3165
3166// SETCC for f64.
3167def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
3168          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3169def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
3170          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3171def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
3172          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3173def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
3174          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3175def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
3176          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3177def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
3178          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3179def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
3180          (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3181
3182defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3183                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3184defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
3185                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3186defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
3187                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3188defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
3189                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3190defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
3191                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3192defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
3193                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3194defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
3195                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3196
3197// match select on i1 variables:
3198def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
3199          (CROR (CRAND        $cond , $tval),
3200                (CRAND (crnot $cond), $fval))>;
3201
3202// match selectcc on i1 variables:
3203//   select (lhs == rhs), tval, fval is:
3204//   ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
3205def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
3206           (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3207                 (CRAND (CRORC  $lhs, $rhs), $fval))>;
3208def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
3209           (CROR (CRAND (CRORC  $rhs, $lhs), $tval),
3210                 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3211def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
3212           (CROR (CRAND (CREQV $lhs, $rhs), $tval),
3213                 (CRAND (CRXOR $lhs, $rhs), $fval))>;
3214def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
3215           (CROR (CRAND (CRORC  $lhs, $rhs), $tval),
3216                 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3217def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
3218           (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3219                 (CRAND (CRORC  $rhs, $lhs), $fval))>;
3220def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
3221           (CROR (CRAND (CREQV $lhs, $rhs), $fval),
3222                 (CRAND (CRXOR $lhs, $rhs), $tval))>;
3223
3224// match selectcc on i1 variables with non-i1 output.
3225def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3226          (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3227def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3228          (SELECT_I4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3229def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3230          (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3231def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3232          (SELECT_I4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3233def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3234          (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3235def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3236          (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3237
3238def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3239          (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3240def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3241          (SELECT_I8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3242def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3243          (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3244def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3245          (SELECT_I8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3246def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3247          (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3248def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3249          (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3250
3251def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3252          (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3253def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3254          (SELECT_F4 (CRORC  $rhs, $lhs), $tval, $fval)>;
3255def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3256          (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3257def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3258          (SELECT_F4 (CRORC  $lhs, $rhs), $tval, $fval)>;
3259def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3260          (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3261def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3262          (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3263
3264def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3265          (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3266def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3267          (SELECT_F8 (CRORC  $rhs, $lhs), $tval, $fval)>;
3268def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3269          (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3270def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3271          (SELECT_F8 (CRORC  $lhs, $rhs), $tval, $fval)>;
3272def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3273          (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3274def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3275          (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3276
3277def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3278          (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3279def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3280          (SELECT_VRRC (CRORC  $rhs, $lhs), $tval, $fval)>;
3281def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3282          (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3283def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3284          (SELECT_VRRC (CRORC  $lhs, $rhs), $tval, $fval)>;
3285def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3286          (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3287def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3288          (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3289
3290let usesCustomInserter = 1 in {
3291def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3292                             "#ANDIo_1_EQ_BIT",
3293                             [(set i1:$dst, (trunc (not i32:$in)))]>;
3294def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3295                             "#ANDIo_1_GT_BIT",
3296                             [(set i1:$dst, (trunc i32:$in))]>;
3297
3298def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3299                              "#ANDIo_1_EQ_BIT8",
3300                              [(set i1:$dst, (trunc (not i64:$in)))]>;
3301def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3302                              "#ANDIo_1_GT_BIT8",
3303                              [(set i1:$dst, (trunc i64:$in))]>;
3304}
3305
3306def : Pat<(i1 (not (trunc i32:$in))),
3307           (ANDIo_1_EQ_BIT $in)>;
3308def : Pat<(i1 (not (trunc i64:$in))),
3309           (ANDIo_1_EQ_BIT8 $in)>;
3310
3311//===----------------------------------------------------------------------===//
3312// PowerPC Instructions used for assembler/disassembler only
3313//
3314
3315// FIXME: For B=0 or B > 8, the registers following RT are used.
3316// WARNING: Do not add patterns for this instruction without fixing this.
3317def LSWI  : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3318                            "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3319
3320// FIXME: For B=0 or B > 8, the registers following RT are used.
3321// WARNING: Do not add patterns for this instruction without fixing this.
3322def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3323                            "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3324
3325def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3326                         "isync", IIC_SprISYNC, []>;
3327
3328def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3329                    "icbi $src", IIC_LdStICBI, []>;
3330
3331// We used to have EIEIO as value but E[0-9A-Z] is a reserved name
3332def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3333                           "eieio", IIC_LdStLoad, []>;
3334
3335def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3336                         "wait $L", IIC_LdStLoad, []>;
3337
3338def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3339                         "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3340
3341def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3342            "mtsr $SR, $RS", IIC_SprMTSR>;
3343
3344def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3345            "mfsr $RS, $SR", IIC_SprMFSR>;
3346
3347def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3348            "mtsrin $RS, $RB", IIC_SprMTSR>;
3349
3350def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3351            "mfsrin $RS, $RB", IIC_SprMFSR>;
3352
3353def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3354                    "mtmsr $RS, $L", IIC_SprMTMSR>;
3355
3356def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3357                    "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3358  let L = 0;
3359}
3360
3361def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3362              Requires<[IsBookE]> {
3363  bits<1> E;
3364
3365  let Inst{16} = E;
3366  let Inst{21-30} = 163;
3367}
3368
3369def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3370               "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3371def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3372               "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3373
3374def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3375def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3376def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3377def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3378
3379def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3380                  "mfmsr $RT", IIC_SprMFMSR, []>;
3381
3382def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3383                    "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3384
3385def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
3386                     "mcrfs $BF, $BFA", IIC_BrMCR>;
3387
3388def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3389                      "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
3390
3391def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3392                       "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
3393
3394def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
3395def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
3396
3397def MTFSF : XFLForm_1<63, 711, (outs),
3398                      (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3399                      "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
3400def MTFSFo : XFLForm_1<63, 711, (outs),
3401                       (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3402                       "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
3403
3404def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3405def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3406
3407def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3408                        "slbie $RB", IIC_SprSLBIE, []>;
3409
3410def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3411                    "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3412
3413def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3414                       "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3415
3416def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3417
3418def TLBIA : XForm_0<31, 370, (outs), (ins),
3419                        "tlbia", IIC_SprTLBIA, []>;
3420
3421def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3422                        "tlbsync", IIC_SprTLBSYNC, []>;
3423
3424def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3425                          "tlbiel $RB", IIC_SprTLBIEL, []>;
3426
3427def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3428                          "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3429def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3430                          "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3431
3432def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3433                          "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3434
3435def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3436                IIC_LdStLoad>, Requires<[IsBookE]>;
3437
3438def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3439                IIC_LdStLoad>, Requires<[IsBookE]>;
3440
3441def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3442                           "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3443
3444def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3445                           "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3446
3447def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3448               "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3449
3450def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3451               "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3452
3453def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3454                             "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3455                             Requires<[IsPPC4xx]>;
3456def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3457                              (ins gprc:$RST, gprc:$A, gprc:$B),
3458                              "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3459                              Requires<[IsPPC4xx]>, isDOT;
3460
3461def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3462
3463def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3464                  Requires<[IsBookE]>;
3465def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3466                   Requires<[IsBookE]>;
3467
3468def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3469                   Requires<[IsE500]>;
3470def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3471                    Requires<[IsE500]>;
3472
3473def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3474                      "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3475def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3476                      "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3477
3478def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
3479
3480def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3481                             "lbzcix $RST, $A, $B", IIC_LdStLoad, []>;
3482def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3483                             "lhzcix $RST, $A, $B", IIC_LdStLoad, []>;
3484def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3485                             "lwzcix $RST, $A, $B", IIC_LdStLoad, []>;
3486def LDCIX :  XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3487                             "ldcix $RST, $A, $B", IIC_LdStLoad, []>;
3488
3489def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3490                             "stbcix $RST, $A, $B", IIC_LdStLoad, []>;
3491def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3492                             "sthcix $RST, $A, $B", IIC_LdStLoad, []>;
3493def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3494                             "stwcix $RST, $A, $B", IIC_LdStLoad, []>;
3495def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3496                             "stdcix $RST, $A, $B", IIC_LdStLoad, []>;
3497
3498//===----------------------------------------------------------------------===//
3499// PowerPC Assembler Instruction Aliases
3500//
3501
3502// Pseudo-instructions for alternate assembly syntax (never used by codegen).
3503// These are aliases that require C++ handling to convert to the target
3504// instruction, while InstAliases can be handled directly by tblgen.
3505class PPCAsmPseudo<string asm, dag iops>
3506  : Instruction {
3507  let Namespace = "PPC";
3508  bit PPC64 = 0;  // Default value, override with isPPC64
3509
3510  let OutOperandList = (outs);
3511  let InOperandList = iops;
3512  let Pattern = [];
3513  let AsmString = asm;
3514  let isAsmParserOnly = 1;
3515  let isPseudo = 1;
3516}
3517
3518def : InstAlias<"sc", (SC 0)>;
3519
3520def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
3521def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>;
3522def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
3523def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
3524
3525def : InstAlias<"wait", (WAIT 0)>;
3526def : InstAlias<"waitrsv", (WAIT 1)>;
3527def : InstAlias<"waitimpl", (WAIT 2)>;
3528
3529def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3530
3531def DCBTx   : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>;
3532def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>;
3533
3534def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3535def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3536def DCBTT  : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>;
3537
3538def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3539def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
3540def DCBTSTT  : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>;
3541
3542def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3543def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3544def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3545def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3546
3547def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3548def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3549
3550def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3551def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3552
3553def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3554def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3555
3556def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3557def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3558
3559def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3560def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3561
3562def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3563def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3564
3565def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3566def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3567
3568def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3569def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3570
3571def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3572def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3573
3574def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3575def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3576
3577def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3578def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3579
3580def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3581def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3582
3583def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3584def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3585
3586def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3587def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3588
3589def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3590def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3591def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3592
3593def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3594def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3595
3596def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3597def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3598def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3599def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3600
3601def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3602
3603def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3604def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3605
3606def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3607def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3608
3609def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3610
3611foreach BATR = 0-3 in {
3612    def : InstAlias<"mtdbatu "#BATR#", $Rx",
3613                    (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3614                    Requires<[IsPPC6xx]>;
3615    def : InstAlias<"mfdbatu $Rx, "#BATR,
3616                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3617                    Requires<[IsPPC6xx]>;
3618    def : InstAlias<"mtdbatl "#BATR#", $Rx",
3619                    (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3620                    Requires<[IsPPC6xx]>;
3621    def : InstAlias<"mfdbatl $Rx, "#BATR,
3622                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3623                    Requires<[IsPPC6xx]>;
3624    def : InstAlias<"mtibatu "#BATR#", $Rx",
3625                    (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3626                    Requires<[IsPPC6xx]>;
3627    def : InstAlias<"mfibatu $Rx, "#BATR,
3628                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3629                    Requires<[IsPPC6xx]>;
3630    def : InstAlias<"mtibatl "#BATR#", $Rx",
3631                    (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3632                    Requires<[IsPPC6xx]>;
3633    def : InstAlias<"mfibatl $Rx, "#BATR,
3634                    (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3635                    Requires<[IsPPC6xx]>;
3636}
3637
3638foreach BR = 0-7 in {
3639    def : InstAlias<"mfbr"#BR#" $Rx",
3640                    (MFDCR gprc:$Rx, !add(BR, 0x80))>,
3641                    Requires<[IsPPC4xx]>;
3642    def : InstAlias<"mtbr"#BR#" $Rx",
3643                    (MTDCR gprc:$Rx, !add(BR, 0x80))>,
3644                    Requires<[IsPPC4xx]>;
3645}
3646
3647def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3648def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
3649
3650def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3651def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
3652
3653def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3654def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
3655
3656def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3657def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
3658
3659def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
3660def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
3661
3662def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3663def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
3664
3665def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3666
3667def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3668                        (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3669def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3670                         (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3671def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3672                         (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3673def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3674                          (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3675
3676def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3677def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3678def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3679def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3680
3681def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3682def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3683
3684def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
3685def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
3686
3687foreach SPRG = 0-3 in {
3688  def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
3689  def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
3690  def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3691  def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3692}
3693foreach SPRG = 4-7 in {
3694  def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
3695                  Requires<[IsBookE]>;
3696  def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
3697                  Requires<[IsBookE]>;
3698  def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3699                  Requires<[IsBookE]>;
3700  def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3701                  Requires<[IsBookE]>;
3702}
3703
3704def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3705
3706def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3707def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3708
3709def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3710
3711def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3712def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3713
3714def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3715def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3716def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3717def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3718
3719def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3720
3721def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
3722                Requires<[IsPPC4xx]>;
3723def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
3724                Requires<[IsPPC4xx]>;
3725def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
3726                Requires<[IsPPC4xx]>;
3727def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
3728                Requires<[IsPPC4xx]>;
3729
3730def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3731                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3732def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3733                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3734def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3735                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3736def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3737                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3738def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3739                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3740def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3741                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3742def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3743                          (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3744def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3745                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3746def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3747                          (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3748def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3749                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3750def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3751                        (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3752def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3753                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3754def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3755                        (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3756def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3757                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3758def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3759                          (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3760def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3761                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3762def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3763                            (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3764def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3765                             (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3766
3767def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3768def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3769def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3770def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3771def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3772def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3773
3774def : InstAlias<"cntlz $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
3775def : InstAlias<"cntlz. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>;
3776
3777def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3778                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3779def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3780                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3781def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3782                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3783def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3784                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3785def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3786                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3787def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3788                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3789def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3790                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3791def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3792                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3793def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3794                        (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3795def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3796                         (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3797def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3798                        (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3799def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3800                         (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3801def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3802                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3803def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3804                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3805def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3806                            (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3807def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3808                             (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3809
3810def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3811def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3812def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3813def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3814def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3815def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3816
3817def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b",
3818                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3819def RLWINMobm : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b",
3820                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3821def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b",
3822                           (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3823def RLWIMIobm : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b",
3824                            (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3825def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b",
3826                          (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3827def RLWNMobm : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b",
3828                           (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3829
3830// These generic branch instruction forms are used for the assembler parser only.
3831// Defs and Uses are conservative, since we don't know the BO value.
3832let PPC970_Unit = 7 in {
3833  let Defs = [CTR], Uses = [CTR, RM] in {
3834    def gBC : BForm_3<16, 0, 0, (outs),
3835                      (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3836                      "bc $bo, $bi, $dst">;
3837    def gBCA : BForm_3<16, 1, 0, (outs),
3838                       (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3839                       "bca $bo, $bi, $dst">;
3840  }
3841  let Defs = [LR, CTR], Uses = [CTR, RM] in {
3842    def gBCL : BForm_3<16, 0, 1, (outs),
3843                       (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3844                       "bcl $bo, $bi, $dst">;
3845    def gBCLA : BForm_3<16, 1, 1, (outs),
3846                        (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3847                        "bcla $bo, $bi, $dst">;
3848  }
3849  let Defs = [CTR], Uses = [CTR, LR, RM] in
3850    def gBCLR : XLForm_2<19, 16, 0, (outs),
3851                         (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3852                         "bclr $bo, $bi, $bh", IIC_BrB, []>;
3853  let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3854    def gBCLRL : XLForm_2<19, 16, 1, (outs),
3855                          (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3856                          "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3857  let Defs = [CTR], Uses = [CTR, LR, RM] in
3858    def gBCCTR : XLForm_2<19, 528, 0, (outs),
3859                          (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3860                          "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3861  let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3862    def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3863                           (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3864                           "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3865}
3866def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3867def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
3868def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
3869def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
3870
3871multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
3872  def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
3873  def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3874  def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
3875  def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
3876  def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3877  def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
3878}
3879multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
3880  : BranchSimpleMnemonic1<name, pm, bo> {
3881  def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
3882  def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
3883}
3884defm : BranchSimpleMnemonic2<"t", "", 12>;
3885defm : BranchSimpleMnemonic2<"f", "", 4>;
3886defm : BranchSimpleMnemonic2<"t", "-", 14>;
3887defm : BranchSimpleMnemonic2<"f", "-", 6>;
3888defm : BranchSimpleMnemonic2<"t", "+", 15>;
3889defm : BranchSimpleMnemonic2<"f", "+", 7>;
3890defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
3891defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
3892defm : BranchSimpleMnemonic1<"dzt", "", 10>;
3893defm : BranchSimpleMnemonic1<"dzf", "", 2>;
3894
3895multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
3896  def : InstAlias<"b"#name#pm#" $cc, $dst",
3897                  (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
3898  def : InstAlias<"b"#name#pm#" $dst",
3899                  (BCC bibo, CR0, condbrtarget:$dst)>;
3900
3901  def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
3902                  (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3903  def : InstAlias<"b"#name#"a"#pm#" $dst",
3904                  (BCCA bibo, CR0, abscondbrtarget:$dst)>;
3905
3906  def : InstAlias<"b"#name#"lr"#pm#" $cc",
3907                  (BCCLR bibo, crrc:$cc)>;
3908  def : InstAlias<"b"#name#"lr"#pm,
3909                  (BCCLR bibo, CR0)>;
3910
3911  def : InstAlias<"b"#name#"ctr"#pm#" $cc",
3912                  (BCCCTR bibo, crrc:$cc)>;
3913  def : InstAlias<"b"#name#"ctr"#pm,
3914                  (BCCCTR bibo, CR0)>;
3915
3916  def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
3917                  (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
3918  def : InstAlias<"b"#name#"l"#pm#" $dst",
3919                  (BCCL bibo, CR0, condbrtarget:$dst)>;
3920
3921  def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
3922                  (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3923  def : InstAlias<"b"#name#"la"#pm#" $dst",
3924                  (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
3925
3926  def : InstAlias<"b"#name#"lrl"#pm#" $cc",
3927                  (BCCLRL bibo, crrc:$cc)>;
3928  def : InstAlias<"b"#name#"lrl"#pm,
3929                  (BCCLRL bibo, CR0)>;
3930
3931  def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
3932                  (BCCCTRL bibo, crrc:$cc)>;
3933  def : InstAlias<"b"#name#"ctrl"#pm,
3934                  (BCCCTRL bibo, CR0)>;
3935}
3936multiclass BranchExtendedMnemonic<string name, int bibo> {
3937  defm : BranchExtendedMnemonicPM<name, "", bibo>;
3938  defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
3939  defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
3940}
3941defm : BranchExtendedMnemonic<"lt", 12>;
3942defm : BranchExtendedMnemonic<"gt", 44>;
3943defm : BranchExtendedMnemonic<"eq", 76>;
3944defm : BranchExtendedMnemonic<"un", 108>;
3945defm : BranchExtendedMnemonic<"so", 108>;
3946defm : BranchExtendedMnemonic<"ge", 4>;
3947defm : BranchExtendedMnemonic<"nl", 4>;
3948defm : BranchExtendedMnemonic<"le", 36>;
3949defm : BranchExtendedMnemonic<"ng", 36>;
3950defm : BranchExtendedMnemonic<"ne", 68>;
3951defm : BranchExtendedMnemonic<"nu", 100>;
3952defm : BranchExtendedMnemonic<"ns", 100>;
3953
3954def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
3955def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
3956def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
3957def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
3958def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
3959def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
3960def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
3961def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
3962
3963def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
3964def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
3965def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
3966def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
3967def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
3968def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3969def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
3970def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3971
3972multiclass TrapExtendedMnemonic<string name, int to> {
3973  def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
3974  def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
3975  def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
3976  def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
3977}
3978defm : TrapExtendedMnemonic<"lt", 16>;
3979defm : TrapExtendedMnemonic<"le", 20>;
3980defm : TrapExtendedMnemonic<"eq", 4>;
3981defm : TrapExtendedMnemonic<"ge", 12>;
3982defm : TrapExtendedMnemonic<"gt", 8>;
3983defm : TrapExtendedMnemonic<"nl", 12>;
3984defm : TrapExtendedMnemonic<"ne", 24>;
3985defm : TrapExtendedMnemonic<"ng", 20>;
3986defm : TrapExtendedMnemonic<"llt", 2>;
3987defm : TrapExtendedMnemonic<"lle", 6>;
3988defm : TrapExtendedMnemonic<"lge", 5>;
3989defm : TrapExtendedMnemonic<"lgt", 1>;
3990defm : TrapExtendedMnemonic<"lnl", 5>;
3991defm : TrapExtendedMnemonic<"lng", 6>;
3992defm : TrapExtendedMnemonic<"u", 31>;
3993
3994// Atomic loads
3995def : Pat<(atomic_load_8  iaddr:$src), (LBZ  memri:$src)>;
3996def : Pat<(atomic_load_16 iaddr:$src), (LHZ  memri:$src)>;
3997def : Pat<(atomic_load_32 iaddr:$src), (LWZ  memri:$src)>;
3998def : Pat<(atomic_load_8  xaddr:$src), (LBZX memrr:$src)>;
3999def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
4000def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
4001
4002// Atomic stores
4003def : Pat<(atomic_store_8  iaddr:$ptr, i32:$val), (STB  gprc:$val, memri:$ptr)>;
4004def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH  gprc:$val, memri:$ptr)>;
4005def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW  gprc:$val, memri:$ptr)>;
4006def : Pat<(atomic_store_8  xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
4007def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
4008def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;
4009