1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 15 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 16 17 #include "PPC.h" 18 #include "PPCRegisterInfo.h" 19 #include "llvm/CodeGen/TargetInstrInfo.h" 20 21 #define GET_INSTRINFO_HEADER 22 #include "PPCGenInstrInfo.inc" 23 24 namespace llvm { 25 26 /// PPCII - This namespace holds all of the PowerPC target-specific 27 /// per-instruction flags. These must match the corresponding definitions in 28 /// PPC.td and PPCInstrFormats.td. 29 namespace PPCII { 30 enum { 31 // PPC970 Instruction Flags. These flags describe the characteristics of the 32 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 33 // raw machine instructions. 34 35 /// PPC970_First - This instruction starts a new dispatch group, so it will 36 /// always be the first one in the group. 37 PPC970_First = 0x1, 38 39 /// PPC970_Single - This instruction starts a new dispatch group and 40 /// terminates it, so it will be the sole instruction in the group. 41 PPC970_Single = 0x2, 42 43 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 44 /// two dispatch pipes to be available to issue. 45 PPC970_Cracked = 0x4, 46 47 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 48 /// an instruction is issued to. 49 PPC970_Shift = 3, 50 PPC970_Mask = 0x07 << PPC970_Shift 51 }; 52 enum PPC970_Unit { 53 /// These are the various PPC970 execution unit pipelines. Each instruction 54 /// is one of these. 55 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 56 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 57 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 58 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 59 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 60 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 61 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 62 PPC970_BRU = 7 << PPC970_Shift // Branch Unit 63 }; 64 65 enum { 66 /// Shift count to bypass PPC970 flags 67 NewDef_Shift = 6, 68 69 /// The VSX instruction that uses VSX register (vs0-vs63), instead of VMX 70 /// register (v0-v31). 71 UseVSXReg = 0x1 << NewDef_Shift 72 }; 73 } // end namespace PPCII 74 75 // Instructions that have an immediate form might be convertible to that 76 // form if the correct input is a result of a load immediate. In order to 77 // know whether the transformation is special, we might need to know some 78 // of the details of the two forms. 79 struct ImmInstrInfo { 80 // Is the immediate field in the immediate form signed or unsigned? 81 uint64_t SignedImm : 1; 82 // Does the immediate need to be a multiple of some value? 83 uint64_t ImmMustBeMultipleOf : 5; 84 // Is R0/X0 treated specially by the original r+r instruction? 85 // If so, in which operand? 86 uint64_t ZeroIsSpecialOrig : 3; 87 // Is R0/X0 treated specially by the new r+i instruction? 88 // If so, in which operand? 89 uint64_t ZeroIsSpecialNew : 3; 90 // Is the operation commutative? 91 uint64_t IsCommutative : 1; 92 // The operand number to check for load immediate. 93 uint64_t ConstantOpNo : 3; 94 // The operand number for the immediate. 95 uint64_t ImmOpNo : 3; 96 // The opcode of the new instruction. 97 uint64_t ImmOpcode : 16; 98 // The size of the immediate. 99 uint64_t ImmWidth : 5; 100 // The immediate should be truncated to N bits. 101 uint64_t TruncateImmTo : 5; 102 }; 103 104 // Information required to convert an instruction to just a materialized 105 // immediate. 106 struct LoadImmediateInfo { 107 unsigned Imm : 16; 108 unsigned Is64Bit : 1; 109 unsigned SetCR : 1; 110 }; 111 112 class PPCSubtarget; 113 class PPCInstrInfo : public PPCGenInstrInfo { 114 PPCSubtarget &Subtarget; 115 const PPCRegisterInfo RI; 116 117 bool StoreRegToStackSlot(MachineFunction &MF, 118 unsigned SrcReg, bool isKill, int FrameIdx, 119 const TargetRegisterClass *RC, 120 SmallVectorImpl<MachineInstr*> &NewMIs, 121 bool &NonRI, bool &SpillsVRS) const; 122 bool LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, 123 unsigned DestReg, int FrameIdx, 124 const TargetRegisterClass *RC, 125 SmallVectorImpl<MachineInstr *> &NewMIs, 126 bool &NonRI, bool &SpillsVRS) const; 127 bool transformToImmForm(MachineInstr &MI, const ImmInstrInfo &III, 128 unsigned ConstantOpNo, int64_t Imm) const; 129 MachineInstr *getConstantDefMI(MachineInstr &MI, unsigned &ConstOp, 130 bool &SeenIntermediateUse) const; 131 virtual void anchor(); 132 133 protected: 134 /// Commutes the operands in the given instruction. 135 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2. 136 /// 137 /// Do not call this method for a non-commutable instruction or for 138 /// non-commutable pair of operand indices OpIdx1 and OpIdx2. 139 /// Even though the instruction is commutable, the method may still 140 /// fail to commute the operands, null pointer is returned in such cases. 141 /// 142 /// For example, we can commute rlwimi instructions, but only if the 143 /// rotate amt is zero. We also have to munge the immediates a bit. 144 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 145 unsigned OpIdx1, 146 unsigned OpIdx2) const override; 147 148 public: 149 explicit PPCInstrInfo(PPCSubtarget &STI); 150 151 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 152 /// such, whenever a client has an instance of instruction info, it should 153 /// always be able to get register info as well (through this method). 154 /// 155 const PPCRegisterInfo &getRegisterInfo() const { return RI; } 156 157 ScheduleHazardRecognizer * 158 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 159 const ScheduleDAG *DAG) const override; 160 ScheduleHazardRecognizer * 161 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 162 const ScheduleDAG *DAG) const override; 163 164 unsigned getInstrLatency(const InstrItineraryData *ItinData, 165 const MachineInstr &MI, 166 unsigned *PredCost = nullptr) const override; 167 168 int getOperandLatency(const InstrItineraryData *ItinData, 169 const MachineInstr &DefMI, unsigned DefIdx, 170 const MachineInstr &UseMI, 171 unsigned UseIdx) const override; 172 int getOperandLatency(const InstrItineraryData *ItinData, 173 SDNode *DefNode, unsigned DefIdx, 174 SDNode *UseNode, unsigned UseIdx) const override { 175 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, 176 UseNode, UseIdx); 177 } 178 179 bool hasLowDefLatency(const TargetSchedModel &SchedModel, 180 const MachineInstr &DefMI, 181 unsigned DefIdx) const override { 182 // Machine LICM should hoist all instructions in low-register-pressure 183 // situations; none are sufficiently free to justify leaving in a loop 184 // body. 185 return false; 186 } 187 188 bool useMachineCombiner() const override { 189 return true; 190 } 191 192 /// Return true when there is potentially a faster code sequence 193 /// for an instruction chain ending in <Root>. All potential patterns are 194 /// output in the <Pattern> array. 195 bool getMachineCombinerPatterns( 196 MachineInstr &Root, 197 SmallVectorImpl<MachineCombinerPattern> &P) const override; 198 199 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override; 200 201 bool isCoalescableExtInstr(const MachineInstr &MI, 202 unsigned &SrcReg, unsigned &DstReg, 203 unsigned &SubIdx) const override; 204 unsigned isLoadFromStackSlot(const MachineInstr &MI, 205 int &FrameIndex) const override; 206 bool isReallyTriviallyReMaterializable(const MachineInstr &MI, 207 AliasAnalysis *AA) const override; 208 unsigned isStoreToStackSlot(const MachineInstr &MI, 209 int &FrameIndex) const override; 210 211 bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, 212 unsigned &SrcOpIdx2) const override; 213 214 void insertNoop(MachineBasicBlock &MBB, 215 MachineBasicBlock::iterator MI) const override; 216 217 218 // Branch analysis. 219 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 220 MachineBasicBlock *&FBB, 221 SmallVectorImpl<MachineOperand> &Cond, 222 bool AllowModify) const override; 223 unsigned removeBranch(MachineBasicBlock &MBB, 224 int *BytesRemoved = nullptr) const override; 225 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 226 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 227 const DebugLoc &DL, 228 int *BytesAdded = nullptr) const override; 229 230 // Select analysis. 231 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 232 unsigned, unsigned, int &, int &, int &) const override; 233 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 234 const DebugLoc &DL, unsigned DstReg, 235 ArrayRef<MachineOperand> Cond, unsigned TrueReg, 236 unsigned FalseReg) const override; 237 238 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 239 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, 240 bool KillSrc) const override; 241 242 void storeRegToStackSlot(MachineBasicBlock &MBB, 243 MachineBasicBlock::iterator MBBI, 244 unsigned SrcReg, bool isKill, int FrameIndex, 245 const TargetRegisterClass *RC, 246 const TargetRegisterInfo *TRI) const override; 247 248 void loadRegFromStackSlot(MachineBasicBlock &MBB, 249 MachineBasicBlock::iterator MBBI, 250 unsigned DestReg, int FrameIndex, 251 const TargetRegisterClass *RC, 252 const TargetRegisterInfo *TRI) const override; 253 254 bool 255 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 256 257 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, 258 MachineRegisterInfo *MRI) const override; 259 260 // If conversion by predication (only supported by some branch instructions). 261 // All of the profitability checks always return true; it is always 262 // profitable to use the predicated branches. 263 bool isProfitableToIfCvt(MachineBasicBlock &MBB, 264 unsigned NumCycles, unsigned ExtraPredCycles, 265 BranchProbability Probability) const override { 266 return true; 267 } 268 269 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 270 unsigned NumT, unsigned ExtraT, 271 MachineBasicBlock &FMBB, 272 unsigned NumF, unsigned ExtraF, 273 BranchProbability Probability) const override; 274 275 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 276 BranchProbability Probability) const override { 277 return true; 278 } 279 280 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 281 MachineBasicBlock &FMBB) const override { 282 return false; 283 } 284 285 // Predication support. 286 bool isPredicated(const MachineInstr &MI) const override; 287 288 bool isUnpredicatedTerminator(const MachineInstr &MI) const override; 289 290 bool PredicateInstruction(MachineInstr &MI, 291 ArrayRef<MachineOperand> Pred) const override; 292 293 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 294 ArrayRef<MachineOperand> Pred2) const override; 295 296 bool DefinesPredicate(MachineInstr &MI, 297 std::vector<MachineOperand> &Pred) const override; 298 299 bool isPredicable(const MachineInstr &MI) const override; 300 301 // Comparison optimization. 302 303 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, 304 unsigned &SrcReg2, int &Mask, int &Value) const override; 305 306 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, 307 unsigned SrcReg2, int Mask, int Value, 308 const MachineRegisterInfo *MRI) const override; 309 310 /// GetInstSize - Return the number of bytes of code the specified 311 /// instruction may be. This returns the maximum number of bytes. 312 /// 313 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 314 315 void getNoop(MCInst &NopInst) const override; 316 317 std::pair<unsigned, unsigned> 318 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 319 320 ArrayRef<std::pair<unsigned, const char *>> 321 getSerializableDirectMachineOperandTargetFlags() const override; 322 323 ArrayRef<std::pair<unsigned, const char *>> 324 getSerializableBitmaskMachineOperandTargetFlags() const override; 325 326 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction. 327 bool expandVSXMemPseudo(MachineInstr &MI) const; 328 329 // Lower pseudo instructions after register allocation. 330 bool expandPostRAPseudo(MachineInstr &MI) const override; 331 332 static bool isVFRegister(unsigned Reg) { 333 return Reg >= PPC::VF0 && Reg <= PPC::VF31; 334 } 335 static bool isVRRegister(unsigned Reg) { 336 return Reg >= PPC::V0 && Reg <= PPC::V31; 337 } 338 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const; 339 static int getRecordFormOpcode(unsigned Opcode); 340 341 bool isTOCSaveMI(const MachineInstr &MI) const; 342 343 bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, 344 const unsigned PhiDepth) const; 345 346 /// Return true if the output of the instruction is always a sign-extended, 347 /// i.e. 0 to 31-th bits are same as 32-th bit. 348 bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const { 349 return isSignOrZeroExtended(MI, true, depth); 350 } 351 352 /// Return true if the output of the instruction is always zero-extended, 353 /// i.e. 0 to 31-th bits are all zeros 354 bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const { 355 return isSignOrZeroExtended(MI, false, depth); 356 } 357 358 bool convertToImmediateForm(MachineInstr &MI, 359 MachineInstr **KilledDef = nullptr) const; 360 void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const; 361 362 // This is used to find the "true" source register for n 363 // Machine instruction. Returns the original SrcReg unless it is the target 364 // of a copy-like operation, in which case we chain backwards through all 365 // such operations to the ultimate source register. If a 366 // physical register is encountered, we stop the search. 367 static unsigned lookThruCopyLike(unsigned SrcReg, 368 const MachineRegisterInfo *MRI); 369 bool instrHasImmForm(const MachineInstr &MI, ImmInstrInfo &III) const; 370 }; 371 372 } 373 374 #endif 375