1//===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Altivec extension to the PowerPC instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Altivec transformation functions and pattern fragments. 16// 17 18// Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be 19// of that type. 20def vnot_ppc : PatFrag<(ops node:$in), 21 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>; 22 23def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 24 (vector_shuffle node:$lhs, node:$rhs), [{ 25 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 26}]>; 27def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 28 (vector_shuffle node:$lhs, node:$rhs), [{ 29 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 30}]>; 31def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 32 (vector_shuffle node:$lhs, node:$rhs), [{ 33 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 34}]>; 35def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 36 (vector_shuffle node:$lhs, node:$rhs), [{ 37 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 38}]>; 39 40// These fragments are provided for little-endian, where the inputs must be 41// swapped for correct semantics. 42def vpkuhum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 43 (vector_shuffle node:$lhs, node:$rhs), [{ 44 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 45}]>; 46def vpkuwum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 47 (vector_shuffle node:$lhs, node:$rhs), [{ 48 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 49}]>; 50 51def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 52 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 53 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG); 54}]>; 55def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 56 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 57 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG); 58}]>; 59def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 60 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 61 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG); 62}]>; 63def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 64 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 65 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG); 66}]>; 67def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 68 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 69 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG); 70}]>; 71def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 72 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 73 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG); 74}]>; 75 76 77def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 78 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 79 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG); 80}]>; 81def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 82 (vector_shuffle node:$lhs, node:$rhs), [{ 83 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG); 84}]>; 85def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 86 (vector_shuffle node:$lhs, node:$rhs), [{ 87 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG); 88}]>; 89def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 90 (vector_shuffle node:$lhs, node:$rhs), [{ 91 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG); 92}]>; 93def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 94 (vector_shuffle node:$lhs, node:$rhs), [{ 95 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG); 96}]>; 97def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 98 (vector_shuffle node:$lhs, node:$rhs), [{ 99 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG); 100}]>; 101 102 103// These fragments are provided for little-endian, where the inputs must be 104// swapped for correct semantics. 105def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 106 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 107 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG); 108}]>; 109def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 110 (vector_shuffle node:$lhs, node:$rhs), [{ 111 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG); 112}]>; 113def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 114 (vector_shuffle node:$lhs, node:$rhs), [{ 115 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG); 116}]>; 117def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 118 (vector_shuffle node:$lhs, node:$rhs), [{ 119 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG); 120}]>; 121def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 122 (vector_shuffle node:$lhs, node:$rhs), [{ 123 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG); 124}]>; 125def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 126 (vector_shuffle node:$lhs, node:$rhs), [{ 127 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG); 128}]>; 129 130 131def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{ 132 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 0, *CurDAG)); 133}]>; 134def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 135 (vector_shuffle node:$lhs, node:$rhs), [{ 136 return PPC::isVSLDOIShuffleMask(N, 0, *CurDAG) != -1; 137}], VSLDOI_get_imm>; 138 139 140/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into 141/// vector_shuffle(X,undef,mask) by the dag combiner. 142def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{ 143 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 1, *CurDAG)); 144}]>; 145def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 146 (vector_shuffle node:$lhs, node:$rhs), [{ 147 return PPC::isVSLDOIShuffleMask(N, 1, *CurDAG) != -1; 148}], VSLDOI_unary_get_imm>; 149 150 151/// VSLDOI_swapped* - These fragments are provided for little-endian, where 152/// the inputs must be swapped for correct semantics. 153def VSLDOI_swapped_get_imm : SDNodeXForm<vector_shuffle, [{ 154 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 2, *CurDAG)); 155}]>; 156def vsldoi_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 157 (vector_shuffle node:$lhs, node:$rhs), [{ 158 return PPC::isVSLDOIShuffleMask(N, 2, *CurDAG) != -1; 159}], VSLDOI_get_imm>; 160 161 162// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. 163def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{ 164 return getI32Imm(PPC::getVSPLTImmediate(N, 1, *CurDAG)); 165}]>; 166def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 167 (vector_shuffle node:$lhs, node:$rhs), [{ 168 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1); 169}], VSPLTB_get_imm>; 170def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{ 171 return getI32Imm(PPC::getVSPLTImmediate(N, 2, *CurDAG)); 172}]>; 173def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 174 (vector_shuffle node:$lhs, node:$rhs), [{ 175 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2); 176}], VSPLTH_get_imm>; 177def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{ 178 return getI32Imm(PPC::getVSPLTImmediate(N, 4, *CurDAG)); 179}]>; 180def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 181 (vector_shuffle node:$lhs, node:$rhs), [{ 182 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4); 183}], VSPLTW_get_imm>; 184 185 186// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. 187def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{ 188 return PPC::get_VSPLTI_elt(N, 1, *CurDAG); 189}]>; 190def vecspltisb : PatLeaf<(build_vector), [{ 191 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0; 192}], VSPLTISB_get_imm>; 193 194// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm. 195def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{ 196 return PPC::get_VSPLTI_elt(N, 2, *CurDAG); 197}]>; 198def vecspltish : PatLeaf<(build_vector), [{ 199 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0; 200}], VSPLTISH_get_imm>; 201 202// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm. 203def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{ 204 return PPC::get_VSPLTI_elt(N, 4, *CurDAG); 205}]>; 206def vecspltisw : PatLeaf<(build_vector), [{ 207 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0; 208}], VSPLTISW_get_imm>; 209 210//===----------------------------------------------------------------------===// 211// Helpers for defining instructions that directly correspond to intrinsics. 212 213// VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type. 214class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty> 215 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 216 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 217 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>; 218 219// VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the 220// inputs doesn't match the type of the output. 221class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 222 ValueType InTy> 223 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 224 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 225 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>; 226 227// VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two 228// input types and an output type. 229class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 230 ValueType In1Ty, ValueType In2Ty> 231 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 232 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 233 [(set OutTy:$vD, 234 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>; 235 236// VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type. 237class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 238 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 239 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 240 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>; 241 242// VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the 243// inputs doesn't match the type of the output. 244class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 245 ValueType InTy> 246 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 247 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 248 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>; 249 250// VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two 251// input types and an output type. 252class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 253 ValueType In1Ty, ValueType In2Ty> 254 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 255 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 256 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>; 257 258// VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type. 259class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID> 260 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 261 !strconcat(opc, " $vD, $vB"), IIC_VecFP, 262 [(set v4f32:$vD, (IntID v4f32:$vB))]>; 263 264// VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the 265// inputs doesn't match the type of the output. 266class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 267 ValueType InTy> 268 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 269 !strconcat(opc, " $vD, $vB"), IIC_VecFP, 270 [(set OutTy:$vD, (IntID InTy:$vB))]>; 271 272//===----------------------------------------------------------------------===// 273// Instruction Definitions. 274 275def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">; 276let Predicates = [HasAltivec] in { 277 278let isCodeGenOnly = 1 in { 279def DSS : DSS_Form<822, (outs), 280 (ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), 281 "dss $STRM", IIC_LdStLoad /*FIXME*/, []>, 282 Deprecated<DeprecatedDST>; 283def DSSALL : DSS_Form<822, (outs), 284 (ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2), 285 "dssall", IIC_LdStLoad /*FIXME*/, []>, 286 Deprecated<DeprecatedDST>; 287def DST : DSS_Form<342, (outs), 288 (ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB), 289 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 290 Deprecated<DeprecatedDST>; 291def DSTT : DSS_Form<342, (outs), 292 (ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB), 293 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 294 Deprecated<DeprecatedDST>; 295def DSTST : DSS_Form<374, (outs), 296 (ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB), 297 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 298 Deprecated<DeprecatedDST>; 299def DSTSTT : DSS_Form<374, (outs), 300 (ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB), 301 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 302 Deprecated<DeprecatedDST>; 303 304def DST64 : DSS_Form<342, (outs), 305 (ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB), 306 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 307 Deprecated<DeprecatedDST>; 308def DSTT64 : DSS_Form<342, (outs), 309 (ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB), 310 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 311 Deprecated<DeprecatedDST>; 312def DSTST64 : DSS_Form<374, (outs), 313 (ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB), 314 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 315 Deprecated<DeprecatedDST>; 316def DSTSTT64 : DSS_Form<374, (outs), 317 (ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB), 318 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>, 319 Deprecated<DeprecatedDST>; 320} 321 322def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins), 323 "mfvscr $vD", IIC_LdStStore, 324 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>; 325def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB), 326 "mtvscr $vB", IIC_LdStLoad, 327 [(int_ppc_altivec_mtvscr v4i32:$vB)]>; 328 329let canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads. 330def LVEBX: XForm_1<31, 7, (outs vrrc:$vD), (ins memrr:$src), 331 "lvebx $vD, $src", IIC_LdStLoad, 332 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; 333def LVEHX: XForm_1<31, 39, (outs vrrc:$vD), (ins memrr:$src), 334 "lvehx $vD, $src", IIC_LdStLoad, 335 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>; 336def LVEWX: XForm_1<31, 71, (outs vrrc:$vD), (ins memrr:$src), 337 "lvewx $vD, $src", IIC_LdStLoad, 338 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; 339def LVX : XForm_1<31, 103, (outs vrrc:$vD), (ins memrr:$src), 340 "lvx $vD, $src", IIC_LdStLoad, 341 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; 342def LVXL : XForm_1<31, 359, (outs vrrc:$vD), (ins memrr:$src), 343 "lvxl $vD, $src", IIC_LdStLoad, 344 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; 345} 346 347def LVSL : XForm_1<31, 6, (outs vrrc:$vD), (ins memrr:$src), 348 "lvsl $vD, $src", IIC_LdStLoad, 349 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, 350 PPC970_Unit_LSU; 351def LVSR : XForm_1<31, 38, (outs vrrc:$vD), (ins memrr:$src), 352 "lvsr $vD, $src", IIC_LdStLoad, 353 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, 354 PPC970_Unit_LSU; 355 356let PPC970_Unit = 2 in { // Stores. 357def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS, memrr:$dst), 358 "stvebx $rS, $dst", IIC_LdStStore, 359 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>; 360def STVEHX: XForm_8<31, 167, (outs), (ins vrrc:$rS, memrr:$dst), 361 "stvehx $rS, $dst", IIC_LdStStore, 362 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>; 363def STVEWX: XForm_8<31, 199, (outs), (ins vrrc:$rS, memrr:$dst), 364 "stvewx $rS, $dst", IIC_LdStStore, 365 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>; 366def STVX : XForm_8<31, 231, (outs), (ins vrrc:$rS, memrr:$dst), 367 "stvx $rS, $dst", IIC_LdStStore, 368 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>; 369def STVXL : XForm_8<31, 487, (outs), (ins vrrc:$rS, memrr:$dst), 370 "stvxl $rS, $dst", IIC_LdStStore, 371 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>; 372} 373 374let PPC970_Unit = 5 in { // VALU Operations. 375// VA-Form instructions. 3-input AltiVec ops. 376let isCommutable = 1 in { 377def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 378 "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP, 379 [(set v4f32:$vD, 380 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>; 381 382// FIXME: The fma+fneg pattern won't match because fneg is not legal. 383def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 384 "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP, 385 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC, 386 (fneg v4f32:$vB))))]>; 387 388def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>; 389def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs, 390 v8i16>; 391def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>; 392} // isCommutable 393 394def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm, 395 v4i32, v4i32, v16i8>; 396def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>; 397 398// Shuffles. 399def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u5imm:$SH), 400 "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP, 401 [(set v16i8:$vD, 402 (vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>; 403 404// VX-Form instructions. AltiVec arithmetic ops. 405let isCommutable = 1 in { 406def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 407 "vaddfp $vD, $vA, $vB", IIC_VecFP, 408 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>; 409 410def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 411 "vaddubm $vD, $vA, $vB", IIC_VecGeneral, 412 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>; 413def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 414 "vadduhm $vD, $vA, $vB", IIC_VecGeneral, 415 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>; 416def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 417 "vadduwm $vD, $vA, $vB", IIC_VecGeneral, 418 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>; 419 420def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>; 421def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>; 422def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>; 423def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>; 424def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>; 425def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>; 426def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>; 427} // isCommutable 428 429let isCommutable = 1 in 430def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 431 "vand $vD, $vA, $vB", IIC_VecFP, 432 [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>; 433def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 434 "vandc $vD, $vA, $vB", IIC_VecFP, 435 [(set v4i32:$vD, (and v4i32:$vA, 436 (vnot_ppc v4i32:$vB)))]>; 437 438def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 439 "vcfsx $vD, $vB, $UIMM", IIC_VecFP, 440 [(set v4f32:$vD, 441 (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>; 442def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 443 "vcfux $vD, $vB, $UIMM", IIC_VecFP, 444 [(set v4f32:$vD, 445 (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>; 446def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 447 "vctsxs $vD, $vB, $UIMM", IIC_VecFP, 448 [(set v4i32:$vD, 449 (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>; 450def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 451 "vctuxs $vD, $vB, $UIMM", IIC_VecFP, 452 [(set v4i32:$vD, 453 (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>; 454 455// Defines with the UIM field set to 0 for floating-point 456// to integer (fp_to_sint/fp_to_uint) conversions and integer 457// to floating-point (sint_to_fp/uint_to_fp) conversions. 458let isCodeGenOnly = 1, VA = 0 in { 459def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB), 460 "vcfsx $vD, $vB, 0", IIC_VecFP, 461 [(set v4f32:$vD, 462 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>; 463def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB), 464 "vctuxs $vD, $vB, 0", IIC_VecFP, 465 [(set v4i32:$vD, 466 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>; 467def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB), 468 "vcfux $vD, $vB, 0", IIC_VecFP, 469 [(set v4f32:$vD, 470 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>; 471def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB), 472 "vctsxs $vD, $vB, 0", IIC_VecFP, 473 [(set v4i32:$vD, 474 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>; 475} 476def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>; 477def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>; 478 479let isCommutable = 1 in { 480def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>; 481def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>; 482def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>; 483def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>; 484def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>; 485def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>; 486 487def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>; 488def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>; 489def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>; 490def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>; 491def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>; 492def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>; 493def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>; 494def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>; 495def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>; 496def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>; 497def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>; 498def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>; 499def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>; 500def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>; 501} // isCommutable 502 503def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 504 "vmrghb $vD, $vA, $vB", IIC_VecFP, 505 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>; 506def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 507 "vmrghh $vD, $vA, $vB", IIC_VecFP, 508 [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>; 509def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 510 "vmrghw $vD, $vA, $vB", IIC_VecFP, 511 [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>; 512def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 513 "vmrglb $vD, $vA, $vB", IIC_VecFP, 514 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>; 515def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 516 "vmrglh $vD, $vA, $vB", IIC_VecFP, 517 [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>; 518def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 519 "vmrglw $vD, $vA, $vB", IIC_VecFP, 520 [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>; 521 522def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm, 523 v4i32, v16i8, v4i32>; 524def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm, 525 v4i32, v8i16, v4i32>; 526def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs, 527 v4i32, v8i16, v4i32>; 528def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm, 529 v4i32, v16i8, v4i32>; 530def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm, 531 v4i32, v8i16, v4i32>; 532def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs, 533 v4i32, v8i16, v4i32>; 534 535let isCommutable = 1 in { 536def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb, 537 v8i16, v16i8>; 538def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh, 539 v4i32, v8i16>; 540def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub, 541 v8i16, v16i8>; 542def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh, 543 v4i32, v8i16>; 544def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb, 545 v8i16, v16i8>; 546def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh, 547 v4i32, v8i16>; 548def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub, 549 v8i16, v16i8>; 550def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh, 551 v4i32, v8i16>; 552} // isCommutable 553 554def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>; 555def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>; 556def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>; 557def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>; 558def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>; 559def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; 560 561def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>; 562 563def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 564 "vsubfp $vD, $vA, $vB", IIC_VecGeneral, 565 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>; 566def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 567 "vsububm $vD, $vA, $vB", IIC_VecGeneral, 568 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>; 569def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 570 "vsubuhm $vD, $vA, $vB", IIC_VecGeneral, 571 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>; 572def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 573 "vsubuwm $vD, $vA, $vB", IIC_VecGeneral, 574 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>; 575 576def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>; 577def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>; 578def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>; 579def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>; 580def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>; 581def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>; 582 583def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>; 584def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>; 585 586def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs, 587 v4i32, v16i8, v4i32>; 588def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs, 589 v4i32, v8i16, v4i32>; 590def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs, 591 v4i32, v16i8, v4i32>; 592 593def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 594 "vnor $vD, $vA, $vB", IIC_VecFP, 595 [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA, 596 v4i32:$vB)))]>; 597let isCommutable = 1 in { 598def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 599 "vor $vD, $vA, $vB", IIC_VecFP, 600 [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>; 601def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 602 "vxor $vD, $vA, $vB", IIC_VecFP, 603 [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>; 604} // isCommutable 605 606def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>; 607def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>; 608def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>; 609 610def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >; 611def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>; 612 613def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>; 614def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>; 615def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>; 616 617def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 618 "vspltb $vD, $vB, $UIMM", IIC_VecPerm, 619 [(set v16i8:$vD, 620 (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>; 621def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 622 "vsplth $vD, $vB, $UIMM", IIC_VecPerm, 623 [(set v16i8:$vD, 624 (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>; 625def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 626 "vspltw $vD, $vB, $UIMM", IIC_VecPerm, 627 [(set v16i8:$vD, 628 (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>; 629 630def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>; 631def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>; 632 633def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>; 634def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>; 635def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>; 636def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>; 637def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>; 638def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>; 639 640 641def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM), 642 "vspltisb $vD, $SIMM", IIC_VecPerm, 643 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>; 644def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM), 645 "vspltish $vD, $SIMM", IIC_VecPerm, 646 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>; 647def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM), 648 "vspltisw $vD, $SIMM", IIC_VecPerm, 649 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>; 650 651// Vector Pack. 652def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx, 653 v8i16, v4i32>; 654def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss, 655 v16i8, v8i16>; 656def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus, 657 v16i8, v8i16>; 658def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss, 659 v16i8, v4i32>; 660def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus, 661 v8i16, v4i32>; 662def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 663 "vpkuhum $vD, $vA, $vB", IIC_VecFP, 664 [(set v16i8:$vD, 665 (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>; 666def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus, 667 v16i8, v8i16>; 668def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 669 "vpkuwum $vD, $vA, $vB", IIC_VecFP, 670 [(set v16i8:$vD, 671 (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>; 672def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus, 673 v8i16, v4i32>; 674 675// Vector Unpack. 676def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx, 677 v4i32, v8i16>; 678def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb, 679 v8i16, v16i8>; 680def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh, 681 v4i32, v8i16>; 682def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx, 683 v4i32, v8i16>; 684def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb, 685 v8i16, v16i8>; 686def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh, 687 v4i32, v8i16>; 688 689 690// Altivec Comparisons. 691 692class VCMP<bits<10> xo, string asmstr, ValueType Ty> 693 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, 694 IIC_VecFPCompare, 695 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>; 696class VCMPo<bits<10> xo, string asmstr, ValueType Ty> 697 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, 698 IIC_VecFPCompare, 699 [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> { 700 let Defs = [CR6]; 701 let RC = 1; 702} 703 704// f32 element comparisons.0 705def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; 706def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>; 707def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>; 708def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>; 709def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>; 710def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>; 711def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>; 712def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>; 713 714// i8 element comparisons. 715def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>; 716def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>; 717def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>; 718def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>; 719def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>; 720def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>; 721 722// i16 element comparisons. 723def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>; 724def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>; 725def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>; 726def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>; 727def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>; 728def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>; 729 730// i32 element comparisons. 731def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>; 732def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>; 733def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>; 734def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; 735def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; 736def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; 737 738let isCodeGenOnly = 1 in { 739def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 740 "vxor $vD, $vD, $vD", IIC_VecFP, 741 [(set v16i8:$vD, (v16i8 immAllZerosV))]>; 742def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 743 "vxor $vD, $vD, $vD", IIC_VecFP, 744 [(set v8i16:$vD, (v8i16 immAllZerosV))]>; 745def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 746 "vxor $vD, $vD, $vD", IIC_VecFP, 747 [(set v4i32:$vD, (v4i32 immAllZerosV))]>; 748 749let IMM=-1 in { 750def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins), 751 "vspltisw $vD, -1", IIC_VecFP, 752 [(set v16i8:$vD, (v16i8 immAllOnesV))]>; 753def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins), 754 "vspltisw $vD, -1", IIC_VecFP, 755 [(set v8i16:$vD, (v8i16 immAllOnesV))]>; 756def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins), 757 "vspltisw $vD, -1", IIC_VecFP, 758 [(set v4i32:$vD, (v4i32 immAllOnesV))]>; 759} 760} 761} // VALU Operations. 762 763//===----------------------------------------------------------------------===// 764// Additional Altivec Patterns 765// 766 767// DS* intrinsics 768def : Pat<(int_ppc_altivec_dssall), (DSSALL 1, 0, 0, 0)>; 769def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>; 770 771// * 32-bit 772def : Pat<(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM), 773 (DST 0, imm:$STRM, $rA, $rB)>; 774def : Pat<(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM), 775 (DSTT 1, imm:$STRM, $rA, $rB)>; 776def : Pat<(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM), 777 (DSTST 0, imm:$STRM, $rA, $rB)>; 778def : Pat<(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM), 779 (DSTSTT 1, imm:$STRM, $rA, $rB)>; 780 781// * 64-bit 782def : Pat<(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM), 783 (DST64 0, imm:$STRM, $rA, $rB)>; 784def : Pat<(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM), 785 (DSTT64 1, imm:$STRM, $rA, $rB)>; 786def : Pat<(int_ppc_altivec_dstst i64:$rA, i32:$rB, imm:$STRM), 787 (DSTST64 0, imm:$STRM, $rA, $rB)>; 788def : Pat<(int_ppc_altivec_dststt i64:$rA, i32:$rB, imm:$STRM), 789 (DSTSTT64 1, imm:$STRM, $rA, $rB)>; 790 791// Loads. 792def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; 793 794// Stores. 795def : Pat<(store v4i32:$rS, xoaddr:$dst), 796 (STVX $rS, xoaddr:$dst)>; 797 798// Bit conversions. 799def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>; 800def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>; 801def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>; 802 803def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>; 804def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>; 805def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>; 806 807def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>; 808def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>; 809def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>; 810 811def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>; 812def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>; 813def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>; 814 815// Shuffles. 816 817// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x) 818def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef), 819 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>; 820def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef), 821 (VPKUWUM $vA, $vA)>; 822def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef), 823 (VPKUHUM $vA, $vA)>; 824 825// Match vsldoi(y,x), vpkuwum(y,x), vpkuhum(y,x), i.e., swapped operands. 826// These fragments are matched for little-endian, where the inputs must 827// be swapped for correct semantics. 828def:Pat<(vsldoi_swapped_shuffle:$in v16i8:$vA, v16i8:$vB), 829 (VSLDOI $vB, $vA, (VSLDOI_swapped_get_imm $in))>; 830def:Pat<(vpkuwum_swapped_shuffle v16i8:$vA, v16i8:$vB), 831 (VPKUWUM $vB, $vA)>; 832def:Pat<(vpkuhum_swapped_shuffle v16i8:$vA, v16i8:$vB), 833 (VPKUHUM $vB, $vA)>; 834 835// Match vmrg*(x,x) 836def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef), 837 (VMRGLB $vA, $vA)>; 838def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef), 839 (VMRGLH $vA, $vA)>; 840def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef), 841 (VMRGLW $vA, $vA)>; 842def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef), 843 (VMRGHB $vA, $vA)>; 844def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef), 845 (VMRGHH $vA, $vA)>; 846def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef), 847 (VMRGHW $vA, $vA)>; 848 849// Match vmrg*(y,x), i.e., swapped operands. These fragments 850// are matched for little-endian, where the inputs must be 851// swapped for correct semantics. 852def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB), 853 (VMRGLB $vB, $vA)>; 854def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB), 855 (VMRGLH $vB, $vA)>; 856def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB), 857 (VMRGLW $vB, $vA)>; 858def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB), 859 (VMRGHB $vB, $vA)>; 860def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB), 861 (VMRGHH $vB, $vA)>; 862def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB), 863 (VMRGHW $vB, $vA)>; 864 865// Logical Operations 866def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>; 867 868def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)), 869 (VNOR $A, $B)>; 870def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)), 871 (VANDC $A, $B)>; 872 873def : Pat<(fmul v4f32:$vA, v4f32:$vB), 874 (VMADDFP $vA, $vB, 875 (v4i32 (VSLW (V_SETALLONES), (V_SETALLONES))))>; 876 877// Fused multiply add and multiply sub for packed float. These are represented 878// separately from the real instructions above, for operations that must have 879// the additional precision, such as Newton-Rhapson (used by divide, sqrt) 880def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 881 (VMADDFP $A, $B, $C)>; 882def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 883 (VNMSUBFP $A, $B, $C)>; 884 885def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 886 (VMADDFP $A, $B, $C)>; 887def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 888 (VNMSUBFP $A, $B, $C)>; 889 890def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC), 891 (VPERM $vA, $vB, $vC)>; 892 893def : Pat<(PPCfre v4f32:$A), (VREFP $A)>; 894def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>; 895 896// Vector shifts 897def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)), 898 (v16i8 (VSLB $vA, $vB))>; 899def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)), 900 (v8i16 (VSLH $vA, $vB))>; 901def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)), 902 (v4i32 (VSLW $vA, $vB))>; 903 904def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)), 905 (v16i8 (VSRB $vA, $vB))>; 906def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)), 907 (v8i16 (VSRH $vA, $vB))>; 908def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)), 909 (v4i32 (VSRW $vA, $vB))>; 910 911def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)), 912 (v16i8 (VSRAB $vA, $vB))>; 913def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)), 914 (v8i16 (VSRAH $vA, $vB))>; 915def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)), 916 (v4i32 (VSRAW $vA, $vB))>; 917 918// Float to integer and integer to float conversions 919def : Pat<(v4i32 (fp_to_sint v4f32:$vA)), 920 (VCTSXS_0 $vA)>; 921def : Pat<(v4i32 (fp_to_uint v4f32:$vA)), 922 (VCTUXS_0 $vA)>; 923def : Pat<(v4f32 (sint_to_fp v4i32:$vA)), 924 (VCFSX_0 $vA)>; 925def : Pat<(v4f32 (uint_to_fp v4i32:$vA)), 926 (VCFUX_0 $vA)>; 927 928// Floating-point rounding 929def : Pat<(v4f32 (ffloor v4f32:$vA)), 930 (VRFIM $vA)>; 931def : Pat<(v4f32 (fceil v4f32:$vA)), 932 (VRFIP $vA)>; 933def : Pat<(v4f32 (ftrunc v4f32:$vA)), 934 (VRFIZ $vA)>; 935def : Pat<(v4f32 (fnearbyint v4f32:$vA)), 936 (VRFIN $vA)>; 937 938} // end HasAltivec 939 940