1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that PPC uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 17 18 #include "PPC.h" 19 #include "PPCInstrInfo.h" 20 #include "PPCRegisterInfo.h" 21 #include "llvm/CodeGen/CallingConvLower.h" 22 #include "llvm/CodeGen/SelectionDAG.h" 23 #include "llvm/Target/TargetLowering.h" 24 25 namespace llvm { 26 namespace PPCISD { 27 enum NodeType { 28 // Start the numbering where the builtin ops and target ops leave off. 29 FIRST_NUMBER = ISD::BUILTIN_OP_END, 30 31 /// FSEL - Traditional three-operand fsel node. 32 /// 33 FSEL, 34 35 /// FCFID - The FCFID instruction, taking an f64 operand and producing 36 /// and f64 value containing the FP representation of the integer that 37 /// was temporarily in the f64 operand. 38 FCFID, 39 40 /// Newer FCFID[US] integer-to-floating-point conversion instructions for 41 /// unsigned integers and single-precision outputs. 42 FCFIDU, FCFIDS, FCFIDUS, 43 44 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 45 /// operand, producing an f64 value containing the integer representation 46 /// of that FP value. 47 FCTIDZ, FCTIWZ, 48 49 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for 50 /// unsigned integers. 51 FCTIDUZ, FCTIWUZ, 52 53 /// Reciprocal estimate instructions (unary FP ops). 54 FRE, FRSQRTE, 55 56 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 57 // three v4f32 operands and producing a v4f32 result. 58 VMADDFP, VNMSUBFP, 59 60 /// VPERM - The PPC VPERM Instruction. 61 /// 62 VPERM, 63 64 /// Hi/Lo - These represent the high and low 16-bit parts of a global 65 /// address respectively. These nodes have two operands, the first of 66 /// which must be a TargetGlobalAddress, and the second of which must be a 67 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 68 /// though these are usually folded into other nodes. 69 Hi, Lo, 70 71 TOC_ENTRY, 72 73 /// The following two target-specific nodes are used for calls through 74 /// function pointers in the 64-bit SVR4 ABI. 75 76 /// Like a regular LOAD but additionally taking/producing a flag. 77 LOAD, 78 79 /// Like LOAD (taking/producing a flag), but using r2 as hard-coded 80 /// destination. 81 LOAD_TOC, 82 83 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 84 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 85 /// compute an allocation on the stack. 86 DYNALLOC, 87 88 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 89 /// at function entry, used for PIC code. 90 GlobalBaseReg, 91 92 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit 93 /// shift amounts. These nodes are generated by the multi-precision shift 94 /// code. 95 SRL, SRA, SHL, 96 97 /// CALL - A direct function call. 98 /// CALL_NOP is a call with the special NOP which follows 64-bit 99 /// SVR4 calls. 100 CALL, CALL_NOP, 101 102 /// CALL_TLS and CALL_NOP_TLS - Versions of CALL and CALL_NOP used 103 /// to access TLS variables. 104 CALL_TLS, CALL_NOP_TLS, 105 106 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 107 /// MTCTR instruction. 108 MTCTR, 109 110 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 111 /// BCTRL instruction. 112 BCTRL, 113 114 /// Return with a flag operand, matched by 'blr' 115 RET_FLAG, 116 117 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction. 118 /// This copies the bits corresponding to the specified CRREG into the 119 /// resultant GPR. Bits corresponding to other CR regs are undefined. 120 MFOCRF, 121 122 // FIXME: Remove these once the ANDI glue bug is fixed: 123 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the 124 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to 125 /// implement truncation of i32 or i64 to i1. 126 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT, 127 128 // EH_SJLJ_SETJMP - SjLj exception handling setjmp. 129 EH_SJLJ_SETJMP, 130 131 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp. 132 EH_SJLJ_LONGJMP, 133 134 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 135 /// instructions. For lack of better number, we use the opcode number 136 /// encoding for the OPC field to identify the compare. For example, 838 137 /// is VCMPGTSH. 138 VCMP, 139 140 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 141 /// altivec VCMP*o instructions. For lack of better number, we use the 142 /// opcode number encoding for the OPC field to identify the compare. For 143 /// example, 838 is VCMPGTSH. 144 VCMPo, 145 146 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 147 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 148 /// condition register to branch on, OPC is the branch opcode to use (e.g. 149 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 150 /// an optional input flag argument. 151 COND_BRANCH, 152 153 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based 154 /// loops. 155 BDNZ, BDZ, 156 157 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding 158 /// towards zero. Used only as part of the long double-to-int 159 /// conversion sequence. 160 FADDRTZ, 161 162 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register. 163 MFFS, 164 165 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and 166 /// reserve indexed. This is used to implement atomic operations. 167 LARX, 168 169 /// STCX = This corresponds to PPC stcx. instrcution: store conditional 170 /// indexed. This is used to implement atomic operations. 171 STCX, 172 173 /// TC_RETURN - A tail call return. 174 /// operand #0 chain 175 /// operand #1 callee (register or absolute) 176 /// operand #2 stack adjustment 177 /// operand #3 optional in flag 178 TC_RETURN, 179 180 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls 181 CR6SET, 182 CR6UNSET, 183 184 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS 185 /// on PPC32. 186 PPC32_GOT, 187 188 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and 189 /// local dynamic TLS on PPC32. 190 PPC32_PICGOT, 191 192 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec 193 /// TLS model, produces an ADDIS8 instruction that adds the GOT 194 /// base to sym\@got\@tprel\@ha. 195 ADDIS_GOT_TPREL_HA, 196 197 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec 198 /// TLS model, produces a LD instruction with base register G8RReg 199 /// and offset sym\@got\@tprel\@l. This completes the addition that 200 /// finds the offset of "sym" relative to the thread pointer. 201 LD_GOT_TPREL_L, 202 203 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS 204 /// model, produces an ADD instruction that adds the contents of 205 /// G8RReg to the thread pointer. Symbol contains a relocation 206 /// sym\@tls which is to be replaced by the thread pointer and 207 /// identifies to the linker that the instruction is part of a 208 /// TLS sequence. 209 ADD_TLS, 210 211 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS 212 /// model, produces an ADDIS8 instruction that adds the GOT base 213 /// register to sym\@got\@tlsgd\@ha. 214 ADDIS_TLSGD_HA, 215 216 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS 217 /// model, produces an ADDI8 instruction that adds G8RReg to 218 /// sym\@got\@tlsgd\@l. 219 ADDI_TLSGD_L, 220 221 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS 222 /// model, produces an ADDIS8 instruction that adds the GOT base 223 /// register to sym\@got\@tlsld\@ha. 224 ADDIS_TLSLD_HA, 225 226 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS 227 /// model, produces an ADDI8 instruction that adds G8RReg to 228 /// sym\@got\@tlsld\@l. 229 ADDI_TLSLD_L, 230 231 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the 232 /// local-dynamic TLS model, produces an ADDIS8 instruction 233 /// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed 234 /// to tie this in place following a copy to %X3 from the result 235 /// of a GET_TLSLD_ADDR. 236 ADDIS_DTPREL_HA, 237 238 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS 239 /// model, produces an ADDI8 instruction that adds G8RReg to 240 /// sym\@got\@dtprel\@l. 241 ADDI_DTPREL_L, 242 243 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded 244 /// during instruction selection to optimize a BUILD_VECTOR into 245 /// operations on splats. This is necessary to avoid losing these 246 /// optimizations due to constant folding. 247 VADD_SPLAT, 248 249 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned 250 /// operand identifies the operating system entry point. 251 SC, 252 253 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 254 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 255 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 256 /// i32. 257 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, 258 259 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 260 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 261 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 262 /// or i32. 263 LBRX, 264 265 /// STFIWX - The STFIWX instruction. The first operand is an input token 266 /// chain, then an f64 value to store, then an address to store it to. 267 STFIWX, 268 269 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point 270 /// load which sign-extends from a 32-bit integer value into the 271 /// destination 64-bit register. 272 LFIWAX, 273 274 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point 275 /// load which zero-extends from a 32-bit integer value into the 276 /// destination 64-bit register. 277 LFIWZX, 278 279 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model, 280 /// produces an ADDIS8 instruction that adds the TOC base register to 281 /// sym\@toc\@ha. 282 ADDIS_TOC_HA, 283 284 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model, 285 /// produces a LD instruction with base register G8RReg and offset 286 /// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset. 287 LD_TOC_L, 288 289 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces 290 /// an ADDI8 instruction that adds G8RReg to sym\@toc\@l. 291 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset. 292 ADDI_TOC_L 293 }; 294 } 295 296 /// Define some predicates that are used for node matching. 297 namespace PPC { 298 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 299 /// VPKUHUM instruction. 300 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 301 SelectionDAG &DAG); 302 303 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 304 /// VPKUWUM instruction. 305 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 306 SelectionDAG &DAG); 307 308 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 309 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 310 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 311 unsigned ShuffleKind, SelectionDAG &DAG); 312 313 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 314 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 315 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 316 unsigned ShuffleKind, SelectionDAG &DAG); 317 318 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the 319 /// shift amount, otherwise return -1. 320 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, 321 SelectionDAG &DAG); 322 323 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 324 /// specifies a splat of a single element that is suitable for input to 325 /// VSPLTB/VSPLTH/VSPLTW. 326 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 327 328 /// isAllNegativeZeroVector - Returns true if all elements of build_vector 329 /// are -0.0. 330 bool isAllNegativeZeroVector(SDNode *N); 331 332 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 333 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 334 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG); 335 336 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 337 /// formed by using a vspltis[bhw] instruction of the specified element 338 /// size, return the constant being splatted. The ByteSize field indicates 339 /// the number of bytes of each element [124] -> [bhw]. 340 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 341 } 342 343 class PPCSubtarget; 344 class PPCTargetLowering : public TargetLowering { 345 const PPCSubtarget &Subtarget; 346 347 public: 348 explicit PPCTargetLowering(PPCTargetMachine &TM); 349 350 /// getTargetNodeName() - This method returns the name of a target specific 351 /// DAG node. 352 const char *getTargetNodeName(unsigned Opcode) const override; 353 354 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; } 355 356 /// getSetCCResultType - Return the ISD::SETCC ValueType 357 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override; 358 359 /// getPreIndexedAddressParts - returns true by value, base pointer and 360 /// offset pointer and addressing mode by reference if the node's address 361 /// can be legally represented as pre-indexed load / store address. 362 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 363 SDValue &Offset, 364 ISD::MemIndexedMode &AM, 365 SelectionDAG &DAG) const override; 366 367 /// SelectAddressRegReg - Given the specified addressed, check to see if it 368 /// can be represented as an indexed [r+r] operation. Returns false if it 369 /// can be more efficiently represented with [r+imm]. 370 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 371 SelectionDAG &DAG) const; 372 373 /// SelectAddressRegImm - Returns true if the address N can be represented 374 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 375 /// is not better represented as reg+reg. If Aligned is true, only accept 376 /// displacements suitable for STD and friends, i.e. multiples of 4. 377 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 378 SelectionDAG &DAG, bool Aligned) const; 379 380 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 381 /// represented as an indexed [r+r] operation. 382 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 383 SelectionDAG &DAG) const; 384 385 Sched::Preference getSchedulingPreference(SDNode *N) const override; 386 387 /// LowerOperation - Provide custom lowering hooks for some operations. 388 /// 389 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 390 391 /// ReplaceNodeResults - Replace the results of node with an illegal result 392 /// type with new values built out of custom code. 393 /// 394 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 395 SelectionDAG &DAG) const override; 396 397 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 398 399 unsigned getRegisterByName(const char* RegName, EVT VT) const override; 400 401 void computeKnownBitsForTargetNode(const SDValue Op, 402 APInt &KnownZero, 403 APInt &KnownOne, 404 const SelectionDAG &DAG, 405 unsigned Depth = 0) const override; 406 407 MachineBasicBlock * 408 EmitInstrWithCustomInserter(MachineInstr *MI, 409 MachineBasicBlock *MBB) const override; 410 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 411 MachineBasicBlock *MBB, bool is64Bit, 412 unsigned BinOpcode) const; 413 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI, 414 MachineBasicBlock *MBB, 415 bool is8bit, unsigned Opcode) const; 416 417 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI, 418 MachineBasicBlock *MBB) const; 419 420 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI, 421 MachineBasicBlock *MBB) const; 422 423 ConstraintType 424 getConstraintType(const std::string &Constraint) const override; 425 426 /// Examine constraint string and operand type and determine a weight value. 427 /// The operand object must already have been set up with the operand type. 428 ConstraintWeight getSingleConstraintMatchWeight( 429 AsmOperandInfo &info, const char *constraint) const override; 430 431 std::pair<unsigned, const TargetRegisterClass*> 432 getRegForInlineAsmConstraint(const std::string &Constraint, 433 MVT VT) const override; 434 435 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 436 /// function arguments in the caller parameter area. This is the actual 437 /// alignment, not its logarithm. 438 unsigned getByValTypeAlignment(Type *Ty) const override; 439 440 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 441 /// vector. If it is invalid, don't add anything to Ops. 442 void LowerAsmOperandForConstraint(SDValue Op, 443 std::string &Constraint, 444 std::vector<SDValue> &Ops, 445 SelectionDAG &DAG) const override; 446 447 /// isLegalAddressingMode - Return true if the addressing mode represented 448 /// by AM is legal for this target, for a load/store of the specified type. 449 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override; 450 451 /// isLegalICmpImmediate - Return true if the specified immediate is legal 452 /// icmp immediate, that is the target has icmp instructions which can 453 /// compare a register against the immediate without having to materialize 454 /// the immediate into a register. 455 bool isLegalICmpImmediate(int64_t Imm) const override; 456 457 /// isLegalAddImmediate - Return true if the specified immediate is legal 458 /// add immediate, that is the target has add instructions which can 459 /// add a register and the immediate without having to materialize 460 /// the immediate into a register. 461 bool isLegalAddImmediate(int64_t Imm) const override; 462 463 /// isTruncateFree - Return true if it's free to truncate a value of 464 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in 465 /// register X1 to i32 by referencing its sub-register R1. 466 bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 467 bool isTruncateFree(EVT VT1, EVT VT2) const override; 468 469 /// \brief Returns true if it is beneficial to convert a load of a constant 470 /// to just the constant itself. 471 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 472 Type *Ty) const override; 473 474 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 475 476 /// getOptimalMemOpType - Returns the target specific optimal type for load 477 /// and store operations as a result of memset, memcpy, and memmove 478 /// lowering. If DstAlign is zero that means it's safe to destination 479 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 480 /// means there isn't a need to check it against alignment requirement, 481 /// probably because the source does not need to be loaded. If 'IsMemset' is 482 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 483 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 484 /// source is constant so it does not need to be loaded. 485 /// It returns EVT::Other if the type should be determined using generic 486 /// target-independent logic. 487 EVT 488 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 489 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, 490 MachineFunction &MF) const override; 491 492 /// Is unaligned memory access allowed for the given type, and is it fast 493 /// relative to software emulation. 494 bool allowsUnalignedMemoryAccesses(EVT VT, 495 unsigned AddrSpace, 496 bool *Fast = nullptr) const override; 497 498 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 499 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 500 /// expanded to FMAs when this method returns true, otherwise fmuladd is 501 /// expanded to fmul + fadd. 502 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 503 504 // Should we expand the build vector with shuffles? 505 bool 506 shouldExpandBuildVectorWithShuffles(EVT VT, 507 unsigned DefinedValues) const override; 508 509 /// createFastISel - This method returns a target-specific FastISel object, 510 /// or null if the target does not support "fast" instruction selection. 511 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 512 const TargetLibraryInfo *LibInfo) const override; 513 514 /// \brief Returns true if an argument of type Ty needs to be passed in a 515 /// contiguous block of registers in calling convention CallConv. 516 bool functionArgumentNeedsConsecutiveRegisters( 517 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override { 518 // We support any array type as "consecutive" block in the parameter 519 // save area. The element type defines the alignment requirement and 520 // whether the argument should go in GPRs, FPRs, or VRs if available. 521 // 522 // Note that clang uses this capability both to implement the ELFv2 523 // homogeneous float/vector aggregate ABI, and to avoid having to use 524 // "byval" when passing aggregates that might fully fit in registers. 525 return Ty->isArrayTy(); 526 } 527 528 private: 529 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 530 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 531 532 bool 533 IsEligibleForTailCallOptimization(SDValue Callee, 534 CallingConv::ID CalleeCC, 535 bool isVarArg, 536 const SmallVectorImpl<ISD::InputArg> &Ins, 537 SelectionDAG& DAG) const; 538 539 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 540 int SPDiff, 541 SDValue Chain, 542 SDValue &LROpOut, 543 SDValue &FPOpOut, 544 bool isDarwinABI, 545 SDLoc dl) const; 546 547 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 548 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 549 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 550 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 551 std::pair<SDValue,SDValue> lowerTLSCall(SDValue Op, SDLoc dl, 552 SelectionDAG &DAG) const; 553 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 554 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 555 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 556 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 557 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 558 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 559 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 560 const PPCSubtarget &Subtarget) const; 561 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, 562 const PPCSubtarget &Subtarget) const; 563 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG, 564 const PPCSubtarget &Subtarget) const; 565 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 566 const PPCSubtarget &Subtarget) const; 567 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, 568 const PPCSubtarget &Subtarget) const; 569 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 570 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 571 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; 572 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 573 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const; 574 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 575 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 576 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const; 577 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; 578 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; 579 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 580 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 581 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 582 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 583 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; 584 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 585 586 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 587 CallingConv::ID CallConv, bool isVarArg, 588 const SmallVectorImpl<ISD::InputArg> &Ins, 589 SDLoc dl, SelectionDAG &DAG, 590 SmallVectorImpl<SDValue> &InVals) const; 591 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall, 592 bool isVarArg, 593 SelectionDAG &DAG, 594 SmallVector<std::pair<unsigned, SDValue>, 8> 595 &RegsToPass, 596 SDValue InFlag, SDValue Chain, 597 SDValue &Callee, 598 int SPDiff, unsigned NumBytes, 599 const SmallVectorImpl<ISD::InputArg> &Ins, 600 SmallVectorImpl<SDValue> &InVals) const; 601 602 SDValue 603 LowerFormalArguments(SDValue Chain, 604 CallingConv::ID CallConv, bool isVarArg, 605 const SmallVectorImpl<ISD::InputArg> &Ins, 606 SDLoc dl, SelectionDAG &DAG, 607 SmallVectorImpl<SDValue> &InVals) const override; 608 609 SDValue 610 LowerCall(TargetLowering::CallLoweringInfo &CLI, 611 SmallVectorImpl<SDValue> &InVals) const override; 612 613 bool 614 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 615 bool isVarArg, 616 const SmallVectorImpl<ISD::OutputArg> &Outs, 617 LLVMContext &Context) const override; 618 619 SDValue 620 LowerReturn(SDValue Chain, 621 CallingConv::ID CallConv, bool isVarArg, 622 const SmallVectorImpl<ISD::OutputArg> &Outs, 623 const SmallVectorImpl<SDValue> &OutVals, 624 SDLoc dl, SelectionDAG &DAG) const override; 625 626 SDValue 627 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG, 628 SDValue ArgVal, SDLoc dl) const; 629 630 SDValue 631 LowerFormalArguments_Darwin(SDValue Chain, 632 CallingConv::ID CallConv, bool isVarArg, 633 const SmallVectorImpl<ISD::InputArg> &Ins, 634 SDLoc dl, SelectionDAG &DAG, 635 SmallVectorImpl<SDValue> &InVals) const; 636 SDValue 637 LowerFormalArguments_64SVR4(SDValue Chain, 638 CallingConv::ID CallConv, bool isVarArg, 639 const SmallVectorImpl<ISD::InputArg> &Ins, 640 SDLoc dl, SelectionDAG &DAG, 641 SmallVectorImpl<SDValue> &InVals) const; 642 SDValue 643 LowerFormalArguments_32SVR4(SDValue Chain, 644 CallingConv::ID CallConv, bool isVarArg, 645 const SmallVectorImpl<ISD::InputArg> &Ins, 646 SDLoc dl, SelectionDAG &DAG, 647 SmallVectorImpl<SDValue> &InVals) const; 648 649 SDValue 650 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 651 SDValue CallSeqStart, ISD::ArgFlagsTy Flags, 652 SelectionDAG &DAG, SDLoc dl) const; 653 654 SDValue 655 LowerCall_Darwin(SDValue Chain, SDValue Callee, 656 CallingConv::ID CallConv, 657 bool isVarArg, bool isTailCall, 658 const SmallVectorImpl<ISD::OutputArg> &Outs, 659 const SmallVectorImpl<SDValue> &OutVals, 660 const SmallVectorImpl<ISD::InputArg> &Ins, 661 SDLoc dl, SelectionDAG &DAG, 662 SmallVectorImpl<SDValue> &InVals) const; 663 SDValue 664 LowerCall_64SVR4(SDValue Chain, SDValue Callee, 665 CallingConv::ID CallConv, 666 bool isVarArg, bool isTailCall, 667 const SmallVectorImpl<ISD::OutputArg> &Outs, 668 const SmallVectorImpl<SDValue> &OutVals, 669 const SmallVectorImpl<ISD::InputArg> &Ins, 670 SDLoc dl, SelectionDAG &DAG, 671 SmallVectorImpl<SDValue> &InVals) const; 672 SDValue 673 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, 674 bool isVarArg, bool isTailCall, 675 const SmallVectorImpl<ISD::OutputArg> &Outs, 676 const SmallVectorImpl<SDValue> &OutVals, 677 const SmallVectorImpl<ISD::InputArg> &Ins, 678 SDLoc dl, SelectionDAG &DAG, 679 SmallVectorImpl<SDValue> &InVals) const; 680 681 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 682 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 683 684 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const; 685 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const; 686 SDValue DAGCombineFastRecip(SDValue Op, DAGCombinerInfo &DCI) const; 687 SDValue DAGCombineFastRecipFSQRT(SDValue Op, DAGCombinerInfo &DCI) const; 688 689 CCAssignFn *useFastISelCCs(unsigned Flag) const; 690 }; 691 692 namespace PPC { 693 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 694 const TargetLibraryInfo *LibInfo); 695 } 696 697 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 698 CCValAssign::LocInfo &LocInfo, 699 ISD::ArgFlagsTy &ArgFlags, 700 CCState &State); 701 702 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 703 MVT &LocVT, 704 CCValAssign::LocInfo &LocInfo, 705 ISD::ArgFlagsTy &ArgFlags, 706 CCState &State); 707 708 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 709 MVT &LocVT, 710 CCValAssign::LocInfo &LocInfo, 711 ISD::ArgFlagsTy &ArgFlags, 712 CCState &State); 713 } 714 715 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 716