1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the PPCMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MCTargetDesc/PPCFixupKinds.h"
15 #include "PPCInstrInfo.h"
16 #include "PPCMCCodeEmitter.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/MC/MCFixup.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/Support/Endian.h"
24 #include "llvm/Support/EndianStream.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/MathExtras.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include <cassert>
29 #include <cstdint>
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "mccodeemitter"
34 
35 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
36 
37 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
38                                             const MCRegisterInfo &MRI,
39                                             MCContext &Ctx) {
40   return new PPCMCCodeEmitter(MCII, Ctx);
41 }
42 
43 unsigned PPCMCCodeEmitter::
44 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
45                     SmallVectorImpl<MCFixup> &Fixups,
46                     const MCSubtargetInfo &STI) const {
47   const MCOperand &MO = MI.getOperand(OpNo);
48   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
49 
50   // Add a fixup for the branch target.
51   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
52                                    (MCFixupKind)PPC::fixup_ppc_br24));
53   return 0;
54 }
55 
56 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
57                                      SmallVectorImpl<MCFixup> &Fixups,
58                                      const MCSubtargetInfo &STI) const {
59   const MCOperand &MO = MI.getOperand(OpNo);
60   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
61 
62   // Add a fixup for the branch target.
63   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
64                                    (MCFixupKind)PPC::fixup_ppc_brcond14));
65   return 0;
66 }
67 
68 unsigned PPCMCCodeEmitter::
69 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
70                        SmallVectorImpl<MCFixup> &Fixups,
71                        const MCSubtargetInfo &STI) const {
72   const MCOperand &MO = MI.getOperand(OpNo);
73   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
74 
75   // Add a fixup for the branch target.
76   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
77                                    (MCFixupKind)PPC::fixup_ppc_br24abs));
78   return 0;
79 }
80 
81 unsigned PPCMCCodeEmitter::
82 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
83                      SmallVectorImpl<MCFixup> &Fixups,
84                      const MCSubtargetInfo &STI) const {
85   const MCOperand &MO = MI.getOperand(OpNo);
86   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
87 
88   // Add a fixup for the branch target.
89   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
90                                    (MCFixupKind)PPC::fixup_ppc_brcond14abs));
91   return 0;
92 }
93 
94 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
95                                        SmallVectorImpl<MCFixup> &Fixups,
96                                        const MCSubtargetInfo &STI) const {
97   const MCOperand &MO = MI.getOperand(OpNo);
98   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
99 
100   // Add a fixup for the immediate field.
101   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
102                                    (MCFixupKind)PPC::fixup_ppc_half16));
103   return 0;
104 }
105 
106 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
107                                             SmallVectorImpl<MCFixup> &Fixups,
108                                             const MCSubtargetInfo &STI) const {
109   // Encode (imm, reg) as a memri, which has the low 16-bits as the
110   // displacement and the next 5 bits as the register #.
111   assert(MI.getOperand(OpNo+1).isReg());
112   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;
113 
114   const MCOperand &MO = MI.getOperand(OpNo);
115   if (MO.isImm())
116     return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;
117 
118   // Add a fixup for the displacement field.
119   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
120                                    (MCFixupKind)PPC::fixup_ppc_half16));
121   return RegBits;
122 }
123 
124 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
125                                        SmallVectorImpl<MCFixup> &Fixups,
126                                        const MCSubtargetInfo &STI) const {
127   // Encode (imm, reg) as a memrix, which has the low 14-bits as the
128   // displacement and the next 5 bits as the register #.
129   assert(MI.getOperand(OpNo+1).isReg());
130   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14;
131 
132   const MCOperand &MO = MI.getOperand(OpNo);
133   if (MO.isImm())
134     return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;
135 
136   // Add a fixup for the displacement field.
137   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
138                                    (MCFixupKind)PPC::fixup_ppc_half16ds));
139   return RegBits;
140 }
141 
142 unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
143                                        SmallVectorImpl<MCFixup> &Fixups,
144                                        const MCSubtargetInfo &STI) const {
145   // Encode (imm, reg) as a memrix16, which has the low 12-bits as the
146   // displacement and the next 5 bits as the register #.
147   assert(MI.getOperand(OpNo+1).isReg());
148   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12;
149 
150   const MCOperand &MO = MI.getOperand(OpNo);
151   if (MO.isImm()) {
152     assert(!(MO.getImm() % 16) &&
153            "Expecting an immediate that is a multiple of 16");
154     return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
155   }
156 
157   // Otherwise add a fixup for the displacement field.
158   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
159                                    (MCFixupKind)PPC::fixup_ppc_half16ds));
160   return RegBits;
161 }
162 
163 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
164                                               SmallVectorImpl<MCFixup> &Fixups,
165                                               const MCSubtargetInfo &STI)
166                                               const {
167   // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8)
168   // as the displacement and the next 5 bits as the register #.
169   assert(MI.getOperand(OpNo+1).isReg());
170   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
171 
172   const MCOperand &MO = MI.getOperand(OpNo);
173   assert(MO.isImm());
174   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3;
175   return reverseBits(Imm | RegBits) >> 22;
176 }
177 
178 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
179                                               SmallVectorImpl<MCFixup> &Fixups,
180                                               const MCSubtargetInfo &STI)
181                                               const {
182   // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4)
183   // as the displacement and the next 5 bits as the register #.
184   assert(MI.getOperand(OpNo+1).isReg());
185   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
186 
187   const MCOperand &MO = MI.getOperand(OpNo);
188   assert(MO.isImm());
189   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2;
190   return reverseBits(Imm | RegBits) >> 22;
191 }
192 
193 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
194                                               SmallVectorImpl<MCFixup> &Fixups,
195                                               const MCSubtargetInfo &STI)
196                                               const {
197   // Encode (imm, reg) as a spe2dis, which has the low 5-bits of (imm / 2)
198   // as the displacement and the next 5 bits as the register #.
199   assert(MI.getOperand(OpNo+1).isReg());
200   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
201 
202   const MCOperand &MO = MI.getOperand(OpNo);
203   assert(MO.isImm());
204   uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1;
205   return reverseBits(Imm | RegBits) >> 22;
206 }
207 
208 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
209                                        SmallVectorImpl<MCFixup> &Fixups,
210                                        const MCSubtargetInfo &STI) const {
211   const MCOperand &MO = MI.getOperand(OpNo);
212   if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
213 
214   // Add a fixup for the TLS register, which simply provides a relocation
215   // hint to the linker that this statement is part of a relocation sequence.
216   // Return the thread-pointer register's encoding.
217   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
218                                    (MCFixupKind)PPC::fixup_ppc_nofixup));
219   const Triple &TT = STI.getTargetTriple();
220   bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le;
221   return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
222 }
223 
224 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
225                                        SmallVectorImpl<MCFixup> &Fixups,
226                                        const MCSubtargetInfo &STI) const {
227   // For special TLS calls, we need two fixups; one for the branch target
228   // (__tls_get_addr), which we create via getDirectBrEncoding as usual,
229   // and one for the TLSGD or TLSLD symbol, which is emitted here.
230   const MCOperand &MO = MI.getOperand(OpNo+1);
231   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
232                                    (MCFixupKind)PPC::fixup_ppc_nofixup));
233   return getDirectBrEncoding(MI, OpNo, Fixups, STI);
234 }
235 
236 unsigned PPCMCCodeEmitter::
237 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
238                     SmallVectorImpl<MCFixup> &Fixups,
239                     const MCSubtargetInfo &STI) const {
240   const MCOperand &MO = MI.getOperand(OpNo);
241   assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
242           MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
243          (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
244   return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
245 }
246 
247 // Get the index for this operand in this instruction. This is needed for
248 // computing the register number in PPCInstrInfo::getRegNumForOperand() for
249 // any instructions that use a different numbering scheme for registers in
250 // different operands.
251 static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO) {
252   for (unsigned i = 0; i < MI.getNumOperands(); i++) {
253     const MCOperand &Op = MI.getOperand(i);
254     if (&Op == &MO)
255       return i;
256   }
257   llvm_unreachable("This operand is not part of this instruction");
258   return ~0U; // Silence any warnings about no return.
259 }
260 
261 unsigned PPCMCCodeEmitter::
262 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
263                   SmallVectorImpl<MCFixup> &Fixups,
264                   const MCSubtargetInfo &STI) const {
265   if (MO.isReg()) {
266     // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
267     // The GPR operand should come through here though.
268     assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
269             MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
270            MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
271     unsigned OpNo = getOpIdxForMO(MI, MO);
272     unsigned Reg =
273       PPCInstrInfo::getRegNumForOperand(MCII.get(MI.getOpcode()),
274                                         MO.getReg(), OpNo);
275     return CTX.getRegisterInfo()->getEncodingValue(Reg);
276   }
277 
278   assert(MO.isImm() &&
279          "Relocation required in an instruction that we cannot encode!");
280   return MO.getImm();
281 }
282 
283 void PPCMCCodeEmitter::encodeInstruction(
284     const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
285     const MCSubtargetInfo &STI) const {
286   verifyInstructionPredicates(MI,
287                               computeAvailableFeatures(STI.getFeatureBits()));
288 
289   uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
290 
291   // Output the constant in big/little endian byte order.
292   unsigned Size = getInstSizeInBytes(MI);
293   support::endianness E = IsLittleEndian ? support::little : support::big;
294   switch (Size) {
295   case 0:
296     break;
297   case 4:
298     support::endian::write<uint32_t>(OS, Bits, E);
299     break;
300   case 8:
301     // If we emit a pair of instructions, the first one is
302     // always in the top 32 bits, even on little-endian.
303     support::endian::write<uint32_t>(OS, Bits >> 32, E);
304     support::endian::write<uint32_t>(OS, Bits, E);
305     break;
306   default:
307     llvm_unreachable("Invalid instruction size");
308   }
309 
310   ++MCNumEmitted; // Keep track of the # of mi's emitted.
311 }
312 
313 // Get the number of bytes used to encode the given MCInst.
314 unsigned PPCMCCodeEmitter::getInstSizeInBytes(const MCInst &MI) const {
315   unsigned Opcode = MI.getOpcode();
316   const MCInstrDesc &Desc = MCII.get(Opcode);
317   return Desc.getSize();
318 }
319 
320 #define ENABLE_INSTR_PREDICATE_VERIFIER
321 #include "PPCGenMCCodeEmitter.inc"
322