1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the PPCMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "MCTargetDesc/PPCFixupKinds.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26 using namespace llvm;
27 
28 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
29 
30 namespace {
31 class PPCMCCodeEmitter : public MCCodeEmitter {
32   PPCMCCodeEmitter(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
33   void operator=(const PPCMCCodeEmitter &) LLVM_DELETED_FUNCTION;
34 
35   const MCSubtargetInfo &STI;
36   const MCContext &CTX;
37   Triple TT;
38 
39 public:
40   PPCMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
41                    MCContext &ctx)
42     : STI(sti), CTX(ctx), TT(STI.getTargetTriple()) {
43   }
44 
45   ~PPCMCCodeEmitter() {}
46 
47   unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
48                                SmallVectorImpl<MCFixup> &Fixups) const;
49   unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
50                              SmallVectorImpl<MCFixup> &Fixups) const;
51   unsigned getHA16Encoding(const MCInst &MI, unsigned OpNo,
52                            SmallVectorImpl<MCFixup> &Fixups) const;
53   unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo,
54                            SmallVectorImpl<MCFixup> &Fixups) const;
55   unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
56                             SmallVectorImpl<MCFixup> &Fixups) const;
57   unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
58                              SmallVectorImpl<MCFixup> &Fixups) const;
59   unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
60                              SmallVectorImpl<MCFixup> &Fixups) const;
61   unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
62                                SmallVectorImpl<MCFixup> &Fixups) const;
63 
64   /// getMachineOpValue - Return binary encoding of operand. If the machine
65   /// operand requires relocation, record the relocation and return zero.
66   unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
67                              SmallVectorImpl<MCFixup> &Fixups) const;
68 
69   // getBinaryCodeForInstr - TableGen'erated function for getting the
70   // binary encoding for an instruction.
71   uint64_t getBinaryCodeForInstr(const MCInst &MI,
72                                  SmallVectorImpl<MCFixup> &Fixups) const;
73   void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
74                          SmallVectorImpl<MCFixup> &Fixups) const {
75     uint64_t Bits = getBinaryCodeForInstr(MI, Fixups);
76 
77     // BL8_NOP etc. all have a size of 8 because of the following 'nop'.
78     unsigned Size = 4; // FIXME: Have Desc.getSize() return the correct value!
79     unsigned Opcode = MI.getOpcode();
80     if (Opcode == PPC::BL8_NOP || Opcode == PPC::BLA8_NOP ||
81         Opcode == PPC::BL8_NOP_TLSGD || Opcode == PPC::BL8_NOP_TLSLD)
82       Size = 8;
83 
84     // Output the constant in big endian byte order.
85     int ShiftValue = (Size * 8) - 8;
86     for (unsigned i = 0; i != Size; ++i) {
87       OS << (char)(Bits >> ShiftValue);
88       Bits <<= 8;
89     }
90 
91     ++MCNumEmitted;  // Keep track of the # of mi's emitted.
92   }
93 
94 };
95 
96 } // end anonymous namespace
97 
98 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
99                                             const MCRegisterInfo &MRI,
100                                             const MCSubtargetInfo &STI,
101                                             MCContext &Ctx) {
102   return new PPCMCCodeEmitter(MCII, STI, Ctx);
103 }
104 
105 unsigned PPCMCCodeEmitter::
106 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
107                     SmallVectorImpl<MCFixup> &Fixups) const {
108   const MCOperand &MO = MI.getOperand(OpNo);
109   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
110 
111   // Add a fixup for the branch target.
112   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
113                                    (MCFixupKind)PPC::fixup_ppc_br24));
114 
115   // For special TLS calls, add another fixup for the symbol.  Apparently
116   // BL8_NOP, BL8_NOP_TLSGD, and BL8_NOP_TLSLD are sufficiently
117   // similar that TblGen will not generate a separate case for the latter
118   // two, so this is the only way to get the extra fixup generated.
119   unsigned Opcode = MI.getOpcode();
120   if (Opcode == PPC::BL8_NOP_TLSGD || Opcode == PPC::BL8_NOP_TLSLD) {
121     const MCOperand &MO2 = MI.getOperand(OpNo+1);
122     Fixups.push_back(MCFixup::Create(0, MO2.getExpr(),
123                                      (MCFixupKind)PPC::fixup_ppc_nofixup));
124   }
125   return 0;
126 }
127 
128 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
129                                      SmallVectorImpl<MCFixup> &Fixups) const {
130   const MCOperand &MO = MI.getOperand(OpNo);
131   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
132 
133   // Add a fixup for the branch target.
134   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
135                                    (MCFixupKind)PPC::fixup_ppc_brcond14));
136   return 0;
137 }
138 
139 unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo,
140                                        SmallVectorImpl<MCFixup> &Fixups) const {
141   const MCOperand &MO = MI.getOperand(OpNo);
142   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
143 
144   // Add a fixup for the branch target.
145   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
146                                    (MCFixupKind)PPC::fixup_ppc_ha16));
147   return 0;
148 }
149 
150 unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo,
151                                        SmallVectorImpl<MCFixup> &Fixups) const {
152   const MCOperand &MO = MI.getOperand(OpNo);
153   if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
154 
155   // Add a fixup for the branch target.
156   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
157                                    (MCFixupKind)PPC::fixup_ppc_lo16));
158   return 0;
159 }
160 
161 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
162                                             SmallVectorImpl<MCFixup> &Fixups) const {
163   // Encode (imm, reg) as a memri, which has the low 16-bits as the
164   // displacement and the next 5 bits as the register #.
165   assert(MI.getOperand(OpNo+1).isReg());
166   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16;
167 
168   const MCOperand &MO = MI.getOperand(OpNo);
169   if (MO.isImm())
170     return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
171 
172   // Add a fixup for the displacement field.
173   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
174                                    (MCFixupKind)PPC::fixup_ppc_lo16));
175   return RegBits;
176 }
177 
178 
179 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
180                                        SmallVectorImpl<MCFixup> &Fixups) const {
181   // Encode (imm, reg) as a memrix, which has the low 14-bits as the
182   // displacement and the next 5 bits as the register #.
183   assert(MI.getOperand(OpNo+1).isReg());
184   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14;
185 
186   const MCOperand &MO = MI.getOperand(OpNo);
187   if (MO.isImm())
188     return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits;
189 
190   // Add a fixup for the displacement field.
191   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
192                                    (MCFixupKind)PPC::fixup_ppc_lo16_ds));
193   return RegBits;
194 }
195 
196 
197 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
198                                        SmallVectorImpl<MCFixup> &Fixups) const {
199   const MCOperand &MO = MI.getOperand(OpNo);
200   if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups);
201 
202   // Add a fixup for the TLS register, which simply provides a relocation
203   // hint to the linker that this statement is part of a relocation sequence.
204   // Return the thread-pointer register's encoding.
205   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
206                                    (MCFixupKind)PPC::fixup_ppc_tlsreg));
207   return CTX.getRegisterInfo().getEncodingValue(PPC::X13);
208 }
209 
210 unsigned PPCMCCodeEmitter::
211 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
212                     SmallVectorImpl<MCFixup> &Fixups) const {
213   const MCOperand &MO = MI.getOperand(OpNo);
214   assert((MI.getOpcode() == PPC::MTCRF ||
215           MI.getOpcode() == PPC::MFOCRF ||
216           MI.getOpcode() == PPC::MTCRF8) &&
217          (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
218   return 0x80 >> CTX.getRegisterInfo().getEncodingValue(MO.getReg());
219 }
220 
221 
222 unsigned PPCMCCodeEmitter::
223 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
224                   SmallVectorImpl<MCFixup> &Fixups) const {
225   if (MO.isReg()) {
226     // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
227     // The GPR operand should come through here though.
228     assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
229            MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
230     return CTX.getRegisterInfo().getEncodingValue(MO.getReg());
231   }
232 
233   assert(MO.isImm() &&
234          "Relocation required in an instruction that we cannot encode!");
235   return MO.getImm();
236 }
237 
238 
239 #include "PPCGenMCCodeEmitter.inc"
240