1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the NVPTX target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "NVPTXTargetMachine.h"
15 #include "MCTargetDesc/NVPTXMCAsmInfo.h"
16 #include "NVPTX.h"
17 #include "NVPTXAllocaHoisting.h"
18 #include "NVPTXLowerAggrCopies.h"
19 #include "NVPTXSplitBBatBar.h"
20 #include "llvm/ADT/OwningPtr.h"
21 #include "llvm/Analysis/Passes.h"
22 #include "llvm/Analysis/Verifier.h"
23 #include "llvm/Assembly/PrintModulePass.h"
24 #include "llvm/CodeGen/AsmPrinter.h"
25 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCInstrInfo.h"
31 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/MC/MCSubtargetInfo.h"
33 #include "llvm/PassManager.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/FormattedStream.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetLowering.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Target/TargetRegisterInfo.h"
45 #include "llvm/Target/TargetSubtargetInfo.h"
46 #include "llvm/Transforms/Scalar.h"
47 
48 using namespace llvm;
49 
50 namespace llvm {
51 void initializeNVVMReflectPass(PassRegistry&);
52 void initializeGenericToNVVMPass(PassRegistry&);
53 }
54 
55 extern "C" void LLVMInitializeNVPTXTarget() {
56   // Register the target.
57   RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
58   RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
59 
60   RegisterMCAsmInfo<NVPTXMCAsmInfo> A(TheNVPTXTarget32);
61   RegisterMCAsmInfo<NVPTXMCAsmInfo> B(TheNVPTXTarget64);
62 
63   // FIXME: This pass is really intended to be invoked during IR optimization,
64   // but it's very NVPTX-specific.
65   initializeNVVMReflectPass(*PassRegistry::getPassRegistry());
66   initializeGenericToNVVMPass(*PassRegistry::getPassRegistry());
67 }
68 
69 NVPTXTargetMachine::NVPTXTargetMachine(
70     const Target &T, StringRef TT, StringRef CPU, StringRef FS,
71     const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
72     CodeGenOpt::Level OL, bool is64bit)
73     : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
74       Subtarget(TT, CPU, FS, is64bit), DL(Subtarget.getDataLayout()),
75       InstrInfo(*this), TLInfo(*this), TSInfo(*this),
76       FrameLowering(
77           *this, is64bit) /*FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0)*/ {}
78 
79 void NVPTXTargetMachine32::anchor() {}
80 
81 NVPTXTargetMachine32::NVPTXTargetMachine32(
82     const Target &T, StringRef TT, StringRef CPU, StringRef FS,
83     const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
84     CodeGenOpt::Level OL)
85     : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
86 
87 void NVPTXTargetMachine64::anchor() {}
88 
89 NVPTXTargetMachine64::NVPTXTargetMachine64(
90     const Target &T, StringRef TT, StringRef CPU, StringRef FS,
91     const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
92     CodeGenOpt::Level OL)
93     : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
94 
95 namespace llvm {
96 class NVPTXPassConfig : public TargetPassConfig {
97 public:
98   NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
99       : TargetPassConfig(TM, PM) {}
100 
101   NVPTXTargetMachine &getNVPTXTargetMachine() const {
102     return getTM<NVPTXTargetMachine>();
103   }
104 
105   virtual void addIRPasses();
106   virtual bool addInstSelector();
107   virtual bool addPreRegAlloc();
108 };
109 }
110 
111 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
112   NVPTXPassConfig *PassConfig = new NVPTXPassConfig(this, PM);
113   return PassConfig;
114 }
115 
116 void NVPTXPassConfig::addIRPasses() {
117   TargetPassConfig::addIRPasses();
118   addPass(createGenericToNVVMPass());
119 }
120 
121 bool NVPTXPassConfig::addInstSelector() {
122   addPass(createLowerAggrCopies());
123   addPass(createSplitBBatBarPass());
124   addPass(createAllocaHoisting());
125   addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
126   return false;
127 }
128 
129 bool NVPTXPassConfig::addPreRegAlloc() { return false; }
130