1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Mips target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Mips.h"
15 #include "MipsTargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/Target/TargetRegistry.h"
18 using namespace llvm;
19 
20 extern "C" void LLVMInitializeMipsTarget() {
21   // Register the target.
22   RegisterTargetMachine<MipsTargetMachine> X(TheMipsTarget);
23   RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
24 }
25 
26 // DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
27 // The stack is always 8 byte aligned
28 // On function prologue, the stack is created by decrementing
29 // its pointer. Once decremented, all references are done with positive
30 // offset from the stack/frame pointer, using StackGrowsUp enables
31 // an easier handling.
32 // Using CodeModel::Large enables different CALL behavior.
33 MipsTargetMachine::
34 MipsTargetMachine(const Target &T, const std::string &TT,
35                   const std::string &CPU, const std::string &FS,
36                   bool isLittle=false):
37   LLVMTargetMachine(T, TT, CPU, FS),
38   Subtarget(TT, CPU, FS, isLittle),
39   DataLayout(isLittle ?
40              std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
41              std::string("E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
42   InstrInfo(*this),
43   FrameLowering(Subtarget),
44   TLInfo(*this), TSInfo(*this) {
45   // Abicall enables PIC by default
46   if (getRelocationModel() == Reloc::Default) {
47     if (Subtarget.isABI_O32())
48       setRelocationModel(Reloc::PIC_);
49     else
50       setRelocationModel(Reloc::Static);
51   }
52 }
53 
54 MipselTargetMachine::
55 MipselTargetMachine(const Target &T, const std::string &TT,
56                     const std::string &CPU, const std::string &FS) :
57   MipsTargetMachine(T, TT, CPU, FS, true) {}
58 
59 // Install an instruction selector pass using
60 // the ISelDag to gen Mips code.
61 bool MipsTargetMachine::
62 addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
63 {
64   PM.add(createMipsISelDag(*this));
65   return false;
66 }
67 
68 // Implemented by targets that want to run passes immediately before
69 // machine code is emitted. return true if -print-machineinstrs should
70 // print out the code after the passes.
71 bool MipsTargetMachine::
72 addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
73 {
74   PM.add(createMipsDelaySlotFillerPass(*this));
75   return true;
76 }
77 
78 bool MipsTargetMachine::
79 addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
80   PM.add(createMipsEmitGPRestorePass(*this));
81   return true;
82 }
83 
84 bool MipsTargetMachine::
85 addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
86   PM.add(createMipsExpandPseudoPass(*this));
87   return true;
88 }
89