1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the Mips specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsMachineFunction.h" 15 #include "Mips.h" 16 #include "MipsRegisterInfo.h" 17 #include "MipsSubtarget.h" 18 #include "MipsTargetMachine.h" 19 #include "llvm/IR/Attributes.h" 20 #include "llvm/IR/Function.h" 21 #include "llvm/Support/CommandLine.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Support/raw_ostream.h" 25 26 using namespace llvm; 27 28 #define DEBUG_TYPE "mips-subtarget" 29 30 #define GET_SUBTARGETINFO_TARGET_DESC 31 #define GET_SUBTARGETINFO_CTOR 32 #include "MipsGenSubtargetInfo.inc" 33 34 // FIXME: Maybe this should be on by default when Mips16 is specified 35 // 36 static cl::opt<bool> Mixed16_32( 37 "mips-mixed-16-32", 38 cl::init(false), 39 cl::desc("Allow for a mixture of Mips16 " 40 "and Mips32 code in a single source file"), 41 cl::Hidden); 42 43 static cl::opt<bool> Mips_Os16( 44 "mips-os16", 45 cl::init(false), 46 cl::desc("Compile all functions that don' use " 47 "floating point as Mips 16"), 48 cl::Hidden); 49 50 static cl::opt<bool> 51 Mips16HardFloat("mips16-hard-float", cl::NotHidden, 52 cl::desc("MIPS: mips16 hard float enable."), 53 cl::init(false)); 54 55 static cl::opt<bool> 56 Mips16ConstantIslands( 57 "mips16-constant-islands", cl::NotHidden, 58 cl::desc("MIPS: mips16 constant islands enable."), 59 cl::init(true)); 60 61 static cl::opt<bool> 62 GPOpt("mgpopt", cl::Hidden, 63 cl::desc("MIPS: Enable gp-relative addressing of small data items")); 64 65 /// Select the Mips CPU for the given triple and cpu name. 66 /// FIXME: Merge with the copy in MipsMCTargetDesc.cpp 67 static StringRef selectMipsCPU(Triple TT, StringRef CPU) { 68 if (CPU.empty() || CPU == "generic") { 69 if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel) 70 CPU = "mips32"; 71 else 72 CPU = "mips64"; 73 } 74 return CPU; 75 } 76 77 void MipsSubtarget::anchor() { } 78 79 static std::string computeDataLayout(const MipsSubtarget &ST) { 80 std::string Ret = ""; 81 82 // There are both little and big endian mips. 83 if (ST.isLittle()) 84 Ret += "e"; 85 else 86 Ret += "E"; 87 88 Ret += "-m:m"; 89 90 // Pointers are 32 bit on some ABIs. 91 if (!ST.isABI_N64()) 92 Ret += "-p:32:32"; 93 94 // 8 and 16 bit integers only need no have natural alignment, but try to 95 // align them to 32 bits. 64 bit integers have natural alignment. 96 Ret += "-i8:8:32-i16:16:32-i64:64"; 97 98 // 32 bit registers are always available and the stack is at least 64 bit 99 // aligned. On N64 64 bit registers are also available and the stack is 100 // 128 bit aligned. 101 if (ST.isABI_N64() || ST.isABI_N32()) 102 Ret += "-n32:64-S128"; 103 else 104 Ret += "-n32-S64"; 105 106 return Ret; 107 } 108 109 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, 110 const std::string &FS, bool little, 111 const MipsTargetMachine &TM) 112 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault), 113 ABI(MipsABIInfo::Unknown()), IsLittle(little), IsSingleFloat(false), 114 IsFPXX(false), NoABICalls(false), IsFP64bit(false), UseOddSPReg(true), 115 IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false), 116 HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false), 117 HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false), 118 InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), 119 HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), 120 HasMSA(false), TM(TM), TargetTriple(TT), 121 DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))), 122 TSInfo(DL), InstrInfo(MipsInstrInfo::create(*this)), 123 FrameLowering(MipsFrameLowering::create(*this)), 124 TLInfo(MipsTargetLowering::create(TM, *this)) { 125 126 PreviousInMips16Mode = InMips16Mode; 127 128 if (MipsArchVersion == MipsDefault) 129 MipsArchVersion = Mips32; 130 131 // Don't even attempt to generate code for MIPS-I and MIPS-V. They have not 132 // been tested and currently exist for the integrated assembler only. 133 if (MipsArchVersion == Mips1) 134 report_fatal_error("Code generation for MIPS-I is not implemented", false); 135 if (MipsArchVersion == Mips5) 136 report_fatal_error("Code generation for MIPS-V is not implemented", false); 137 138 // Assert exactly one ABI was chosen. 139 assert(ABI.IsKnown()); 140 assert((((getFeatureBits() & Mips::FeatureO32) != 0) + 141 ((getFeatureBits() & Mips::FeatureEABI) != 0) + 142 ((getFeatureBits() & Mips::FeatureN32) != 0) + 143 ((getFeatureBits() & Mips::FeatureN64) != 0)) == 1); 144 145 // Check if Architecture and ABI are compatible. 146 assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) || 147 (isGP64bit() && (isABI_N32() || isABI_N64()))) && 148 "Invalid Arch & ABI pair."); 149 150 if (hasMSA() && !isFP64bit()) 151 report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). " 152 "See -mattr=+fp64.", 153 false); 154 155 if (!isABI_O32() && !useOddSPReg()) 156 report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false); 157 158 if (IsFPXX && (isABI_N32() || isABI_N64())) 159 report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false); 160 161 if (hasMips32r6()) { 162 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6"; 163 164 assert(isFP64bit()); 165 assert(isNaN2008()); 166 if (hasDSP()) 167 report_fatal_error(ISA + " is not compatible with the DSP ASE", false); 168 } 169 170 if (NoABICalls && TM.getRelocationModel() == Reloc::PIC_) 171 report_fatal_error("position-independent code requires '-mabicalls'"); 172 173 // Set UseSmallSection. 174 UseSmallSection = GPOpt; 175 if (!NoABICalls && GPOpt) { 176 errs() << "warning: cannot use small-data accesses for '-mabicalls'" 177 << "\n"; 178 UseSmallSection = false; 179 } 180 } 181 182 /// This overrides the PostRAScheduler bit in the SchedModel for any CPU. 183 bool MipsSubtarget::enablePostMachineScheduler() const { return true; } 184 185 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 186 CriticalPathRCs.clear(); 187 CriticalPathRCs.push_back(isGP64bit() ? 188 &Mips::GPR64RegClass : &Mips::GPR32RegClass); 189 } 190 191 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const { 192 return CodeGenOpt::Aggressive; 193 } 194 195 MipsSubtarget & 196 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, 197 const TargetMachine &TM) { 198 std::string CPUName = selectMipsCPU(TargetTriple, CPU); 199 200 // Parse features string. 201 ParseSubtargetFeatures(CPUName, FS); 202 // Initialize scheduling itinerary for the specified CPU. 203 InstrItins = getInstrItineraryForCPU(CPUName); 204 205 if (InMips16Mode && !TM.Options.UseSoftFloat) 206 InMips16HardFloat = true; 207 208 return *this; 209 } 210 211 bool MipsSubtarget::abiUsesSoftFloat() const { 212 return TM.Options.UseSoftFloat && !InMips16HardFloat; 213 } 214 215 bool MipsSubtarget::useConstantIslands() { 216 DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n"); 217 return Mips16ConstantIslands; 218 } 219 220 Reloc::Model MipsSubtarget::getRelocationModel() const { 221 return TM.getRelocationModel(); 222 } 223