1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsSubtarget.h"
15 #include "Mips.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsRegisterInfo.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Support/raw_ostream.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "mips-subtarget"
29 
30 #define GET_SUBTARGETINFO_TARGET_DESC
31 #define GET_SUBTARGETINFO_CTOR
32 #include "MipsGenSubtargetInfo.inc"
33 
34 // FIXME: Maybe this should be on by default when Mips16 is specified
35 //
36 static cl::opt<bool>
37     Mixed16_32("mips-mixed-16-32", cl::init(false),
38                cl::desc("Allow for a mixture of Mips16 "
39                         "and Mips32 code in a single output file"),
40                cl::Hidden);
41 
42 static cl::opt<bool> Mips_Os16("mips-os16", cl::init(false),
43                                cl::desc("Compile all functions that don't use "
44                                         "floating point as Mips 16"),
45                                cl::Hidden);
46 
47 static cl::opt<bool> Mips16HardFloat("mips16-hard-float", cl::NotHidden,
48                                      cl::desc("Enable mips16 hard float."),
49                                      cl::init(false));
50 
51 static cl::opt<bool>
52     Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden,
53                           cl::desc("Enable mips16 constant islands."),
54                           cl::init(true));
55 
56 static cl::opt<bool>
57     GPOpt("mgpopt", cl::Hidden,
58           cl::desc("Enable gp-relative addressing of mips small data items"));
59 
60 void MipsSubtarget::anchor() {}
61 
62 MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
63                              bool little, const MipsTargetMachine &TM,
64                              unsigned StackAlignOverride)
65     : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
66       IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
67       NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
68       IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
69       HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
70       HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
71       InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
72       HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
73       Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
74       HasEVA(false), DisableMadd4(false), HasMT(false),
75       UseIndirectJumpsHazard(false), StackAlignOverride(StackAlignOverride),
76       TM(TM), TargetTriple(TT), TSInfo(),
77       InstrInfo(
78           MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
79       FrameLowering(MipsFrameLowering::create(*this)),
80       TLInfo(MipsTargetLowering::create(TM, *this)) {
81 
82   if (MipsArchVersion == MipsDefault)
83     MipsArchVersion = Mips32;
84 
85   // Don't even attempt to generate code for MIPS-I and MIPS-V. They have not
86   // been tested and currently exist for the integrated assembler only.
87   if (MipsArchVersion == Mips1)
88     report_fatal_error("Code generation for MIPS-I is not implemented", false);
89   if (MipsArchVersion == Mips5)
90     report_fatal_error("Code generation for MIPS-V is not implemented", false);
91 
92   // Check if Architecture and ABI are compatible.
93   assert(((!isGP64bit() && isABI_O32()) ||
94           (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
95          "Invalid  Arch & ABI pair.");
96 
97   if (hasMSA() && !isFP64bit())
98     report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
99                        "See -mattr=+fp64.",
100                        false);
101 
102   if (!isABI_O32() && !useOddSPReg())
103     report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
104 
105   if (IsFPXX && (isABI_N32() || isABI_N64()))
106     report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
107 
108   if (hasMips64r6() && InMicroMipsMode)
109     report_fatal_error("microMIPS64R6 is not supported", false);
110 
111 
112   if (UseIndirectJumpsHazard) {
113     if (InMicroMipsMode)
114       report_fatal_error(
115           "cannot combine indirect jumps with hazard barriers and microMIPS");
116     if (!hasMips32r2())
117       report_fatal_error(
118           "indirect jumps with hazard barriers requires MIPS32R2 or later");
119   }
120   if (hasMips32r6()) {
121     StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
122 
123     assert(isFP64bit());
124     assert(isNaN2008());
125     if (hasDSP())
126       report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
127   }
128 
129   if (NoABICalls && TM.isPositionIndependent())
130     report_fatal_error("position-independent code requires '-mabicalls'");
131 
132   if (isABI_N64() && !TM.isPositionIndependent() && !hasSym32())
133     NoABICalls = true;
134 
135   // Set UseSmallSection.
136   UseSmallSection = GPOpt;
137   if (!NoABICalls && GPOpt) {
138     errs() << "warning: cannot use small-data accesses for '-mabicalls'"
139            << "\n";
140     UseSmallSection = false;
141   }
142 }
143 
144 bool MipsSubtarget::isPositionIndependent() const {
145   return TM.isPositionIndependent();
146 }
147 
148 /// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
149 bool MipsSubtarget::enablePostRAScheduler() const { return true; }
150 
151 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
152   CriticalPathRCs.clear();
153   CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass
154                                         : &Mips::GPR32RegClass);
155 }
156 
157 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
158   return CodeGenOpt::Aggressive;
159 }
160 
161 MipsSubtarget &
162 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
163                                                const TargetMachine &TM) {
164   std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
165 
166   // Parse features string.
167   ParseSubtargetFeatures(CPUName, FS);
168   // Initialize scheduling itinerary for the specified CPU.
169   InstrItins = getInstrItineraryForCPU(CPUName);
170 
171   if (InMips16Mode && !IsSoftFloat)
172     InMips16HardFloat = true;
173 
174   if (StackAlignOverride)
175     stackAlignment = StackAlignOverride;
176   else if (isABI_N32() || isABI_N64())
177     stackAlignment = 16;
178   else {
179     assert(isABI_O32() && "Unknown ABI for stack alignment!");
180     stackAlignment = 8;
181   }
182 
183   return *this;
184 }
185 
186 bool MipsSubtarget::useConstantIslands() {
187   DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
188   return Mips16ConstantIslands;
189 }
190 
191 Reloc::Model MipsSubtarget::getRelocationModel() const {
192   return TM.getRelocationModel();
193 }
194 
195 bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); }
196 bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
197 bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
198 const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }
199