1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the Mips specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsMachineFunction.h" 15 #include "Mips.h" 16 #include "MipsRegisterInfo.h" 17 #include "MipsSubtarget.h" 18 #include "MipsTargetMachine.h" 19 #include "llvm/IR/Attributes.h" 20 #include "llvm/IR/Function.h" 21 #include "llvm/Support/CommandLine.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Support/raw_ostream.h" 25 26 using namespace llvm; 27 28 #define DEBUG_TYPE "mips-subtarget" 29 30 #define GET_SUBTARGETINFO_TARGET_DESC 31 #define GET_SUBTARGETINFO_CTOR 32 #include "MipsGenSubtargetInfo.inc" 33 34 // FIXME: Maybe this should be on by default when Mips16 is specified 35 // 36 static cl::opt<bool> Mixed16_32( 37 "mips-mixed-16-32", 38 cl::init(false), 39 cl::desc("Allow for a mixture of Mips16 " 40 "and Mips32 code in a single source file"), 41 cl::Hidden); 42 43 static cl::opt<bool> Mips_Os16( 44 "mips-os16", 45 cl::init(false), 46 cl::desc("Compile all functions that don' use " 47 "floating point as Mips 16"), 48 cl::Hidden); 49 50 static cl::opt<bool> 51 Mips16HardFloat("mips16-hard-float", cl::NotHidden, 52 cl::desc("MIPS: mips16 hard float enable."), 53 cl::init(false)); 54 55 static cl::opt<bool> 56 Mips16ConstantIslands( 57 "mips16-constant-islands", cl::NotHidden, 58 cl::desc("MIPS: mips16 constant islands enable."), 59 cl::init(true)); 60 61 /// Select the Mips CPU for the given triple and cpu name. 62 /// FIXME: Merge with the copy in MipsMCTargetDesc.cpp 63 static StringRef selectMipsCPU(Triple TT, StringRef CPU) { 64 if (CPU.empty() || CPU == "generic") { 65 if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel) 66 CPU = "mips32"; 67 else 68 CPU = "mips64"; 69 } 70 return CPU; 71 } 72 73 void MipsSubtarget::anchor() { } 74 75 static std::string computeDataLayout(const MipsSubtarget &ST) { 76 std::string Ret = ""; 77 78 // There are both little and big endian mips. 79 if (ST.isLittle()) 80 Ret += "e"; 81 else 82 Ret += "E"; 83 84 Ret += "-m:m"; 85 86 // Pointers are 32 bit on some ABIs. 87 if (!ST.isABI_N64()) 88 Ret += "-p:32:32"; 89 90 // 8 and 16 bit integers only need no have natural alignment, but try to 91 // align them to 32 bits. 64 bit integers have natural alignment. 92 Ret += "-i8:8:32-i16:16:32-i64:64"; 93 94 // 32 bit registers are always available and the stack is at least 64 bit 95 // aligned. On N64 64 bit registers are also available and the stack is 96 // 128 bit aligned. 97 if (ST.isABI_N64() || ST.isABI_N32()) 98 Ret += "-n32:64-S128"; 99 else 100 Ret += "-n32-S64"; 101 102 return Ret; 103 } 104 105 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, 106 const std::string &FS, bool little, 107 MipsTargetMachine *_TM) 108 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32), 109 MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false), 110 IsFPXX(false), IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false), 111 IsGP64bit(false), HasVFPU(false), HasCnMips(false), IsLinux(true), 112 HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false), 113 HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false), 114 InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), 115 HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), 116 HasMSA(false), TM(_TM), TargetTriple(TT), 117 DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))), 118 TSInfo(DL), JITInfo(), InstrInfo(MipsInstrInfo::create(*this)), 119 FrameLowering(MipsFrameLowering::create(*this)), 120 TLInfo(MipsTargetLowering::create(*TM, *this)) { 121 122 PreviousInMips16Mode = InMips16Mode; 123 124 // Don't even attempt to generate code for MIPS-I, MIPS-II, MIPS-III, and 125 // MIPS-V. They have not been tested and currently exist for the integrated 126 // assembler only. 127 if (MipsArchVersion == Mips1) 128 report_fatal_error("Code generation for MIPS-I is not implemented", false); 129 if (MipsArchVersion == Mips2) 130 report_fatal_error("Code generation for MIPS-II is not implemented", false); 131 if (MipsArchVersion == Mips3) 132 report_fatal_error("Code generation for MIPS-III is not implemented", 133 false); 134 if (MipsArchVersion == Mips5) 135 report_fatal_error("Code generation for MIPS-V is not implemented", false); 136 137 // Assert exactly one ABI was chosen. 138 assert(MipsABI != UnknownABI); 139 assert((((getFeatureBits() & Mips::FeatureO32) != 0) + 140 ((getFeatureBits() & Mips::FeatureEABI) != 0) + 141 ((getFeatureBits() & Mips::FeatureN32) != 0) + 142 ((getFeatureBits() & Mips::FeatureN64) != 0)) == 1); 143 144 // Check if Architecture and ABI are compatible. 145 assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) || 146 (isGP64bit() && (isABI_N32() || isABI_N64()))) && 147 "Invalid Arch & ABI pair."); 148 149 if (hasMSA() && !isFP64bit()) 150 report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). " 151 "See -mattr=+fp64.", 152 false); 153 154 if (!isABI_O32() && !useOddSPReg()) 155 report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false); 156 157 if (IsFPXX && (isABI_N32() || isABI_N64())) 158 report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false); 159 160 if (hasMips32r6()) { 161 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6"; 162 163 assert(isFP64bit()); 164 assert(isNaN2008()); 165 if (hasDSP()) 166 report_fatal_error(ISA + " is not compatible with the DSP ASE", false); 167 } 168 169 // Is the target system Linux ? 170 if (TT.find("linux") == std::string::npos) 171 IsLinux = false; 172 173 // Set UseSmallSection. 174 // TODO: Investigate the IsLinux check. I suspect it's really checking for 175 // bare-metal. 176 UseSmallSection = !IsLinux && (TM->getRelocationModel() == Reloc::Static); 177 } 178 179 /// This overrides the PostRAScheduler bit in the SchedModel for any CPU. 180 bool MipsSubtarget::enablePostMachineScheduler() const { return true; } 181 182 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 183 CriticalPathRCs.clear(); 184 CriticalPathRCs.push_back(isGP64bit() ? 185 &Mips::GPR64RegClass : &Mips::GPR32RegClass); 186 } 187 188 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const { 189 return CodeGenOpt::Aggressive; 190 } 191 192 MipsSubtarget & 193 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, 194 const TargetMachine *TM) { 195 std::string CPUName = selectMipsCPU(TargetTriple, CPU); 196 197 // Parse features string. 198 ParseSubtargetFeatures(CPUName, FS); 199 // Initialize scheduling itinerary for the specified CPU. 200 InstrItins = getInstrItineraryForCPU(CPUName); 201 202 if (InMips16Mode && !TM->Options.UseSoftFloat) 203 InMips16HardFloat = true; 204 205 return *this; 206 } 207 208 bool MipsSubtarget::abiUsesSoftFloat() const { 209 return TM->Options.UseSoftFloat && !InMips16HardFloat; 210 } 211 212 bool MipsSubtarget::useConstantIslands() { 213 DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n"); 214 return Mips16ConstantIslands; 215 } 216 217 Reloc::Model MipsSubtarget::getRelocationModel() const { 218 return TM->getRelocationModel(); 219 } 220