1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "mips-reg-info"
15 
16 #include "Mips.h"
17 #include "MipsSubtarget.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsMachineFunction.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Type.h"
22 #include "llvm/Function.h"
23 #include "llvm/CodeGen/ValueTypes.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineLocation.h"
28 #include "llvm/Target/TargetFrameInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/ADT/BitVector.h"
37 #include "llvm/ADT/STLExtras.h"
38 
39 using namespace llvm;
40 
41 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
42                                    const TargetInstrInfo &tii)
43   : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
44     Subtarget(ST), TII(tii) {}
45 
46 /// getRegisterNumbering - Given the enum value for some register, e.g.
47 /// Mips::RA, return the number that it corresponds to (e.g. 31).
48 unsigned MipsRegisterInfo::
49 getRegisterNumbering(unsigned RegEnum)
50 {
51   switch (RegEnum) {
52     case Mips::ZERO : case Mips::F0 : case Mips::D0 : return 0;
53     case Mips::AT   : case Mips::F1 : return 1;
54     case Mips::V0   : case Mips::F2 : case Mips::D1 : return 2;
55     case Mips::V1   : case Mips::F3 : return 3;
56     case Mips::A0   : case Mips::F4 : case Mips::D2 : return 4;
57     case Mips::A1   : case Mips::F5 : return 5;
58     case Mips::A2   : case Mips::F6 : case Mips::D3 : return 6;
59     case Mips::A3   : case Mips::F7 : return 7;
60     case Mips::T0   : case Mips::F8 : case Mips::D4 : return 8;
61     case Mips::T1   : case Mips::F9 : return 9;
62     case Mips::T2   : case Mips::F10: case Mips::D5: return 10;
63     case Mips::T3   : case Mips::F11: return 11;
64     case Mips::T4   : case Mips::F12: case Mips::D6: return 12;
65     case Mips::T5   : case Mips::F13: return 13;
66     case Mips::T6   : case Mips::F14: case Mips::D7: return 14;
67     case Mips::T7   : case Mips::F15: return 15;
68     case Mips::T8   : case Mips::F16: case Mips::D8: return 16;
69     case Mips::T9   : case Mips::F17: return 17;
70     case Mips::S0   : case Mips::F18: case Mips::D9: return 18;
71     case Mips::S1   : case Mips::F19: return 19;
72     case Mips::S2   : case Mips::F20: case Mips::D10: return 20;
73     case Mips::S3   : case Mips::F21: return 21;
74     case Mips::S4   : case Mips::F22: case Mips::D11: return 22;
75     case Mips::S5   : case Mips::F23: return 23;
76     case Mips::S6   : case Mips::F24: case Mips::D12: return 24;
77     case Mips::S7   : case Mips::F25: return 25;
78     case Mips::K0   : case Mips::F26: case Mips::D13: return 26;
79     case Mips::K1   : case Mips::F27: return 27;
80     case Mips::GP   : case Mips::F28: case Mips::D14: return 28;
81     case Mips::SP   : case Mips::F29: return 29;
82     case Mips::FP   : case Mips::F30: case Mips::D15: return 30;
83     case Mips::RA   : case Mips::F31: return 31;
84     default: llvm_unreachable("Unknown register number!");
85   }
86   return 0; // Not reached
87 }
88 
89 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
90 
91 //===----------------------------------------------------------------------===//
92 // Callee Saved Registers methods
93 //===----------------------------------------------------------------------===//
94 
95 /// Mips Callee Saved Registers
96 const unsigned* MipsRegisterInfo::
97 getCalleeSavedRegs(const MachineFunction *MF) const
98 {
99   // Mips callee-save register range is $16-$23, $f20-$f30
100   static const unsigned SingleFloatOnlyCalleeSavedRegs[] = {
101     Mips::S0, Mips::S1, Mips::S2, Mips::S3,
102     Mips::S4, Mips::S5, Mips::S6, Mips::S7,
103     Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25,
104     Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, 0
105   };
106 
107   static const unsigned BitMode32CalleeSavedRegs[] = {
108     Mips::S0, Mips::S1, Mips::S2, Mips::S3,
109     Mips::S4, Mips::S5, Mips::S6, Mips::S7,
110     Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30, 0
111   };
112 
113   if (Subtarget.isSingleFloat())
114     return SingleFloatOnlyCalleeSavedRegs;
115   else
116     return BitMode32CalleeSavedRegs;
117 }
118 
119 BitVector MipsRegisterInfo::
120 getReservedRegs(const MachineFunction &MF) const
121 {
122   BitVector Reserved(getNumRegs());
123   Reserved.set(Mips::ZERO);
124   Reserved.set(Mips::AT);
125   Reserved.set(Mips::K0);
126   Reserved.set(Mips::K1);
127   Reserved.set(Mips::GP);
128   Reserved.set(Mips::SP);
129   Reserved.set(Mips::FP);
130   Reserved.set(Mips::RA);
131 
132   // SRV4 requires that odd register can't be used.
133   if (!Subtarget.isSingleFloat())
134     for (unsigned FReg=(Mips::F0)+1; FReg < Mips::F30; FReg+=2)
135       Reserved.set(FReg);
136 
137   return Reserved;
138 }
139 
140 //===----------------------------------------------------------------------===//
141 //
142 // Stack Frame Processing methods
143 // +----------------------------+
144 //
145 // The stack is allocated decrementing the stack pointer on
146 // the first instruction of a function prologue. Once decremented,
147 // all stack references are done thought a positive offset
148 // from the stack/frame pointer, so the stack is considering
149 // to grow up! Otherwise terrible hacks would have to be made
150 // to get this stack ABI compliant :)
151 //
152 //  The stack frame required by the ABI (after call):
153 //  Offset
154 //
155 //  0                 ----------
156 //  4                 Args to pass
157 //  .                 saved $GP  (used in PIC)
158 //  .                 Alloca allocations
159 //  .                 Local Area
160 //  .                 CPU "Callee Saved" Registers
161 //  .                 saved FP
162 //  .                 saved RA
163 //  .                 FPU "Callee Saved" Registers
164 //  StackSize         -----------
165 //
166 // Offset - offset from sp after stack allocation on function prologue
167 //
168 // The sp is the stack pointer subtracted/added from the stack size
169 // at the Prologue/Epilogue
170 //
171 // References to the previous stack (to obtain arguments) are done
172 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
173 //
174 // Examples:
175 // - reference to the actual stack frame
176 //   for any local area var there is smt like : FI >= 0, StackOffset: 4
177 //     sw REGX, 4(SP)
178 //
179 // - reference to previous stack frame
180 //   suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
181 //   The emitted instruction will be something like:
182 //     lw REGX, 16+StackSize(SP)
183 //
184 // Since the total stack size is unknown on LowerFormalArguments, all
185 // stack references (ObjectOffset) created to reference the function
186 // arguments, are negative numbers. This way, on eliminateFrameIndex it's
187 // possible to detect those references and the offsets are adjusted to
188 // their real location.
189 //
190 //===----------------------------------------------------------------------===//
191 
192 void MipsRegisterInfo::adjustMipsStackFrame(MachineFunction &MF) const
193 {
194   MachineFrameInfo *MFI = MF.getFrameInfo();
195   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
196   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
197   unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
198   unsigned RegSize = Subtarget.isGP32bit() ? 4 : 8;
199   bool HasGP = MipsFI->needGPSaveRestore();
200 
201   // Min and Max CSI FrameIndex.
202   int MinCSFI = -1, MaxCSFI = -1;
203 
204   // See the description at MipsMachineFunction.h
205   int TopCPUSavedRegOff = -1, TopFPUSavedRegOff = -1;
206 
207   // Replace the dummy '0' SPOffset by the negative offsets, as explained on
208   // LowerFormalArguments. Leaving '0' for while is necessary to avoid
209   // the approach done by calculateFrameObjectOffsets to the stack frame.
210   MipsFI->adjustLoadArgsFI(MFI);
211   MipsFI->adjustStoreVarArgsFI(MFI);
212 
213   // It happens that the default stack frame allocation order does not directly
214   // map to the convention used for mips. So we must fix it. We move the callee
215   // save register slots after the local variables area, as described in the
216   // stack frame above.
217   unsigned CalleeSavedAreaSize = 0;
218   if (!CSI.empty()) {
219     MinCSFI = CSI[0].getFrameIdx();
220     MaxCSFI = CSI[CSI.size()-1].getFrameIdx();
221   }
222   for (unsigned i = 0, e = CSI.size(); i != e; ++i)
223     CalleeSavedAreaSize += MFI->getObjectAlignment(CSI[i].getFrameIdx());
224 
225   unsigned StackOffset = HasGP ? (MipsFI->getGPStackOffset()+RegSize)
226                 : (Subtarget.isABI_O32() ? 16 : 0);
227 
228   // Adjust local variables. They should come on the stack right
229   // after the arguments.
230   int LastOffsetFI = -1;
231   for (int i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) {
232     if (i >= MinCSFI && i <= MaxCSFI)
233       continue;
234     if (MFI->isDeadObjectIndex(i))
235       continue;
236     unsigned Offset =
237       StackOffset + MFI->getObjectOffset(i) - CalleeSavedAreaSize;
238     if (LastOffsetFI == -1)
239       LastOffsetFI = i;
240     if (Offset > MFI->getObjectOffset(LastOffsetFI))
241       LastOffsetFI = i;
242     MFI->setObjectOffset(i, Offset);
243   }
244 
245   // Adjust CPU Callee Saved Registers Area. Registers RA and FP must
246   // be saved in this CPU Area. This whole area must be aligned to the
247   // default Stack Alignment requirements.
248   if (LastOffsetFI >= 0)
249     StackOffset = MFI->getObjectOffset(LastOffsetFI)+
250                   MFI->getObjectSize(LastOffsetFI);
251   StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
252 
253   for (unsigned i = 0, e = CSI.size(); i != e ; ++i) {
254     unsigned Reg = CSI[i].getReg();
255     if (!Mips::CPURegsRegisterClass->contains(Reg))
256       break;
257     MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
258     TopCPUSavedRegOff = StackOffset;
259     StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
260   }
261 
262   // Stack locations for FP and RA. If only one of them is used,
263   // the space must be allocated for both, otherwise no space at all.
264   if (hasFP(MF) || MFI->adjustsStack()) {
265     // FP stack location
266     MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
267                          StackOffset);
268     MipsFI->setFPStackOffset(StackOffset);
269     TopCPUSavedRegOff = StackOffset;
270     StackOffset += RegSize;
271 
272     // SP stack location
273     MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
274                          StackOffset);
275     MipsFI->setRAStackOffset(StackOffset);
276     StackOffset += RegSize;
277 
278     if (MFI->adjustsStack())
279       TopCPUSavedRegOff += RegSize;
280   }
281 
282   StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
283 
284   // Adjust FPU Callee Saved Registers Area. This Area must be
285   // aligned to the default Stack Alignment requirements.
286   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
287     unsigned Reg = CSI[i].getReg();
288     if (Mips::CPURegsRegisterClass->contains(Reg))
289       continue;
290     MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
291     TopFPUSavedRegOff = StackOffset;
292     StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
293   }
294   StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
295 
296   // Update frame info
297   MFI->setStackSize(StackOffset);
298 
299   // Recalculate the final tops offset. The final values must be '0'
300   // if there isn't a callee saved register for CPU or FPU, otherwise
301   // a negative offset is needed.
302   if (TopCPUSavedRegOff >= 0)
303     MipsFI->setCPUTopSavedRegOff(TopCPUSavedRegOff-StackOffset);
304 
305   if (TopFPUSavedRegOff >= 0)
306     MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset);
307 }
308 
309 // hasFP - Return true if the specified function should have a dedicated frame
310 // pointer register.  This is true if the function has variable sized allocas or
311 // if frame pointer elimination is disabled.
312 bool MipsRegisterInfo::
313 hasFP(const MachineFunction &MF) const {
314   const MachineFrameInfo *MFI = MF.getFrameInfo();
315   return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
316 }
317 
318 // This function eliminate ADJCALLSTACKDOWN,
319 // ADJCALLSTACKUP pseudo instructions
320 void MipsRegisterInfo::
321 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
322                               MachineBasicBlock::iterator I) const {
323   // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
324   MBB.erase(I);
325 }
326 
327 // FrameIndex represent objects inside a abstract stack.
328 // We must replace FrameIndex with an stack/frame pointer
329 // direct reference.
330 void MipsRegisterInfo::
331 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
332                     RegScavenger *RS) const {
333   MachineInstr &MI = *II;
334   MachineFunction &MF = *MI.getParent()->getParent();
335 
336   unsigned i = 0;
337   while (!MI.getOperand(i).isFI()) {
338     ++i;
339     assert(i < MI.getNumOperands() &&
340            "Instr doesn't have FrameIndex operand!");
341   }
342 
343   DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
344         errs() << "<--------->\n" << MI);
345 
346   int FrameIndex = MI.getOperand(i).getIndex();
347   int stackSize  = MF.getFrameInfo()->getStackSize();
348   int spOffset   = MF.getFrameInfo()->getObjectOffset(FrameIndex);
349 
350   DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
351                << "spOffset   : " << spOffset << "\n"
352                << "stackSize  : " << stackSize << "\n");
353 
354   // as explained on LowerFormalArguments, detect negative offsets
355   // and adjust SPOffsets considering the final stack size.
356   int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
357   Offset    += MI.getOperand(i-1).getImm();
358 
359   DEBUG(errs() << "Offset     : " << Offset << "\n" << "<--------->\n");
360 
361   MI.getOperand(i-1).ChangeToImmediate(Offset);
362   MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
363 }
364 
365 void MipsRegisterInfo::
366 emitPrologue(MachineFunction &MF) const
367 {
368   MachineBasicBlock &MBB   = MF.front();
369   MachineFrameInfo *MFI    = MF.getFrameInfo();
370   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
371   MachineBasicBlock::iterator MBBI = MBB.begin();
372   DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
373   bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
374 
375   // Get the right frame order for Mips.
376   adjustMipsStackFrame(MF);
377 
378   // Get the number of bytes to allocate from the FrameInfo.
379   unsigned StackSize = MFI->getStackSize();
380 
381   // No need to allocate space on the stack.
382   if (StackSize == 0 && !MFI->adjustsStack()) return;
383 
384   int FPOffset = MipsFI->getFPStackOffset();
385   int RAOffset = MipsFI->getRAStackOffset();
386 
387   BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
388 
389   // TODO: check need from GP here.
390   if (isPIC && Subtarget.isABI_O32())
391     BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD)).addReg(getPICCallReg());
392   BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
393 
394   // Adjust stack : addi sp, sp, (-imm)
395   BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
396       .addReg(Mips::SP).addImm(-StackSize);
397 
398   // Save the return address only if the function isnt a leaf one.
399   // sw  $ra, stack_loc($sp)
400   if (MFI->adjustsStack()) {
401     BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
402         .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
403   }
404 
405   // if framepointer enabled, save it and set it
406   // to point to the stack pointer
407   if (hasFP(MF)) {
408     // sw  $fp,stack_loc($sp)
409     BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
410       .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
411 
412     // move $fp, $sp
413     BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP)
414       .addReg(Mips::SP).addReg(Mips::ZERO);
415   }
416 
417   // Restore GP from the saved stack location
418   if (MipsFI->needGPSaveRestore())
419     BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE))
420       .addImm(MipsFI->getGPStackOffset());
421 }
422 
423 void MipsRegisterInfo::
424 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
425 {
426   MachineBasicBlock::iterator MBBI = prior(MBB.end());
427   MachineFrameInfo *MFI            = MF.getFrameInfo();
428   MipsFunctionInfo *MipsFI         = MF.getInfo<MipsFunctionInfo>();
429   DebugLoc dl = MBBI->getDebugLoc();
430 
431   // Get the number of bytes from FrameInfo
432   int NumBytes = (int) MFI->getStackSize();
433 
434   // Get the FI's where RA and FP are saved.
435   int FPOffset = MipsFI->getFPStackOffset();
436   int RAOffset = MipsFI->getRAStackOffset();
437 
438   // if framepointer enabled, restore it and restore the
439   // stack pointer
440   if (hasFP(MF)) {
441     // move $sp, $fp
442     BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::SP)
443       .addReg(Mips::FP).addReg(Mips::ZERO);
444 
445     // lw  $fp,stack_loc($sp)
446     BuildMI(MBB, MBBI, dl, TII.get(Mips::LW), Mips::FP)
447       .addImm(FPOffset).addReg(Mips::SP);
448   }
449 
450   // Restore the return address only if the function isnt a leaf one.
451   // lw  $ra, stack_loc($sp)
452   if (MFI->adjustsStack()) {
453     BuildMI(MBB, MBBI, dl, TII.get(Mips::LW), Mips::RA)
454       .addImm(RAOffset).addReg(Mips::SP);
455   }
456 
457   // adjust stack  : insert addi sp, sp, (imm)
458   if (NumBytes) {
459     BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
460       .addReg(Mips::SP).addImm(NumBytes);
461   }
462 }
463 
464 
465 void MipsRegisterInfo::
466 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
467   // Set the stack offset where GP must be saved/loaded from.
468   MachineFrameInfo *MFI = MF.getFrameInfo();
469   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
470   if (MipsFI->needGPSaveRestore())
471     MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
472 }
473 
474 unsigned MipsRegisterInfo::
475 getRARegister() const {
476   return Mips::RA;
477 }
478 
479 unsigned MipsRegisterInfo::
480 getFrameRegister(const MachineFunction &MF) const {
481   return hasFP(MF) ? Mips::FP : Mips::SP;
482 }
483 
484 unsigned MipsRegisterInfo::
485 getEHExceptionRegister() const {
486   llvm_unreachable("What is the exception register");
487   return 0;
488 }
489 
490 unsigned MipsRegisterInfo::
491 getEHHandlerRegister() const {
492   llvm_unreachable("What is the exception handler register");
493   return 0;
494 }
495 
496 int MipsRegisterInfo::
497 getDwarfRegNum(unsigned RegNum, bool isEH) const {
498   llvm_unreachable("What is the dwarf register number");
499   return -1;
500 }
501 
502 #include "MipsGenRegisterInfo.inc"
503