1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "mips-reg-info"
15 
16 #include "MipsRegisterInfo.h"
17 #include "Mips.h"
18 #include "MipsAnalyzeImmediate.h"
19 #include "MipsInstrInfo.h"
20 #include "MipsMachineFunction.h"
21 #include "MipsSubtarget.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/DebugInfo.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameLowering.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
39 
40 #define GET_REGINFO_TARGET_DESC
41 #include "MipsGenRegisterInfo.inc"
42 
43 using namespace llvm;
44 
45 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST)
46   : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {}
47 
48 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
49 
50 
51 unsigned
52 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
53                                       MachineFunction &MF) const {
54   switch (RC->getID()) {
55   default:
56     return 0;
57   case Mips::CPURegsRegClassID:
58   case Mips::CPU64RegsRegClassID:
59   case Mips::DSPRegsRegClassID: {
60     const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
61     return 28 - TFI->hasFP(MF);
62   }
63   case Mips::FGR32RegClassID:
64     return 32;
65   case Mips::AFGR64RegClassID:
66     return 16;
67   case Mips::FGR64RegClassID:
68     return 32;
69   }
70 }
71 
72 //===----------------------------------------------------------------------===//
73 // Callee Saved Registers methods
74 //===----------------------------------------------------------------------===//
75 
76 /// Mips Callee Saved Registers
77 const uint16_t* MipsRegisterInfo::
78 getCalleeSavedRegs(const MachineFunction *MF) const {
79   if (Subtarget.isSingleFloat())
80     return CSR_SingleFloatOnly_SaveList;
81   else if (!Subtarget.hasMips64())
82     return CSR_O32_SaveList;
83   else if (Subtarget.isABI_N32())
84     return CSR_N32_SaveList;
85 
86   assert(Subtarget.isABI_N64());
87   return CSR_N64_SaveList;
88 }
89 
90 const uint32_t*
91 MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
92   if (Subtarget.isSingleFloat())
93     return CSR_SingleFloatOnly_RegMask;
94   else if (!Subtarget.hasMips64())
95     return CSR_O32_RegMask;
96   else if (Subtarget.isABI_N32())
97     return CSR_N32_RegMask;
98 
99   assert(Subtarget.isABI_N64());
100   return CSR_N64_RegMask;
101 }
102 
103 BitVector MipsRegisterInfo::
104 getReservedRegs(const MachineFunction &MF) const {
105   static const uint16_t ReservedCPURegs[] = {
106     Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
107   };
108 
109   static const uint16_t ReservedCPU64Regs[] = {
110     Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
111   };
112 
113   BitVector Reserved(getNumRegs());
114   typedef TargetRegisterClass::const_iterator RegIter;
115 
116   for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I)
117     Reserved.set(ReservedCPURegs[I]);
118 
119   for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I)
120     Reserved.set(ReservedCPU64Regs[I]);
121 
122   if (Subtarget.hasMips64()) {
123     // Reserve all registers in AFGR64.
124     for (RegIter Reg = Mips::AFGR64RegClass.begin(),
125          EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
126       Reserved.set(*Reg);
127   } else {
128     // Reserve all registers in FGR64.
129     for (RegIter Reg = Mips::FGR64RegClass.begin(),
130          EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
131       Reserved.set(*Reg);
132   }
133   // Reserve FP if this function should have a dedicated frame pointer register.
134   if (MF.getTarget().getFrameLowering()->hasFP(MF)) {
135     if (Subtarget.inMips16Mode())
136       Reserved.set(Mips::S0);
137     else {
138       Reserved.set(Mips::FP);
139       Reserved.set(Mips::FP_64);
140     }
141   }
142 
143   // Reserve hardware registers.
144   Reserved.set(Mips::HWR29);
145   Reserved.set(Mips::HWR29_64);
146 
147   // Reserve DSP control register.
148   Reserved.set(Mips::DSPPos);
149   Reserved.set(Mips::DSPSCount);
150   Reserved.set(Mips::DSPCarry);
151   Reserved.set(Mips::DSPEFI);
152   Reserved.set(Mips::DSPOutFlag);
153 
154   // Reserve RA if in mips16 mode.
155   if (Subtarget.inMips16Mode()) {
156     Reserved.set(Mips::RA);
157     Reserved.set(Mips::RA_64);
158   }
159 
160   // Reserve GP if small section is used.
161   if (Subtarget.useSmallSection()) {
162     Reserved.set(Mips::GP);
163     Reserved.set(Mips::GP_64);
164   }
165 
166   return Reserved;
167 }
168 
169 bool
170 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
171   return true;
172 }
173 
174 bool
175 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
176   return true;
177 }
178 
179 // FrameIndex represent objects inside a abstract stack.
180 // We must replace FrameIndex with an stack/frame pointer
181 // direct reference.
182 void MipsRegisterInfo::
183 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
184                     unsigned FIOperandNum, RegScavenger *RS) const {
185   MachineInstr &MI = *II;
186   MachineFunction &MF = *MI.getParent()->getParent();
187 
188   DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
189         errs() << "<--------->\n" << MI);
190 
191   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
192   uint64_t stackSize = MF.getFrameInfo()->getStackSize();
193   int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
194 
195   DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
196                << "spOffset   : " << spOffset << "\n"
197                << "stackSize  : " << stackSize << "\n");
198 
199   eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
200 }
201 
202 unsigned MipsRegisterInfo::
203 getFrameRegister(const MachineFunction &MF) const {
204   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
205   bool IsN64 = Subtarget.isABI_N64();
206 
207   if (Subtarget.inMips16Mode())
208     return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
209   else
210     return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
211                             (IsN64 ? Mips::SP_64 : Mips::SP);
212 
213 }
214 
215 unsigned MipsRegisterInfo::
216 getEHExceptionRegister() const {
217   llvm_unreachable("What is the exception register");
218 }
219 
220 unsigned MipsRegisterInfo::
221 getEHHandlerRegister() const {
222   llvm_unreachable("What is the exception handler register");
223 }
224