1 //===- MipsRegisterBankInfo.cpp ---------------------------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the targeting of the RegisterBankInfo class for Mips.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsInstrInfo.h"
15 #include "MipsRegisterBankInfo.h"
16 #include "llvm/CodeGen/MachineRegisterInfo.h"
17 
18 #define GET_TARGET_REGBANK_IMPL
19 
20 #define DEBUG_TYPE "registerbankinfo"
21 
22 #include "MipsGenRegisterBank.inc"
23 
24 namespace llvm {
25 namespace Mips {
26 enum PartialMappingIdx {
27   PMI_GPR,
28   PMI_Min = PMI_GPR,
29 };
30 
31 RegisterBankInfo::PartialMapping PartMappings[]{
32     {0, 32, GPRBRegBank}
33 };
34 
35 enum ValueMappingIdx { InvalidIdx = 0, GPRIdx = 1 };
36 
37 RegisterBankInfo::ValueMapping ValueMappings[] = {
38     // invalid
39     {nullptr, 0},
40     // 3 operands in GPRs
41     {&PartMappings[PMI_GPR - PMI_Min], 1},
42     {&PartMappings[PMI_GPR - PMI_Min], 1},
43     {&PartMappings[PMI_GPR - PMI_Min], 1}};
44 
45 } // end namespace Mips
46 } // end namespace llvm
47 
48 using namespace llvm;
49 
50 MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI)
51     : MipsGenRegisterBankInfo() {}
52 
53 const RegisterBank &MipsRegisterBankInfo::getRegBankFromRegClass(
54     const TargetRegisterClass &RC) const {
55   using namespace Mips;
56 
57   switch (RC.getID()) {
58   case Mips::GPR32RegClassID:
59   case Mips::CPU16Regs_and_GPRMM16ZeroRegClassID:
60   case Mips::GPRMM16MovePPairFirstRegClassID:
61   case Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID:
62   case Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID:
63   case Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID:
64   case Mips::SP32RegClassID:
65     return getRegBank(Mips::GPRBRegBankID);
66   default:
67     llvm_unreachable("Register class not supported");
68   }
69 }
70 
71 const RegisterBankInfo::InstructionMapping &
72 MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
73 
74   unsigned Opc = MI.getOpcode();
75 
76   const RegisterBankInfo::InstructionMapping &Mapping = getInstrMappingImpl(MI);
77   if (Mapping.isValid())
78     return Mapping;
79 
80   using namespace TargetOpcode;
81 
82   unsigned NumOperands = MI.getNumOperands();
83   const ValueMapping *OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
84 
85   switch (Opc) {
86   case G_ADD:
87   case G_LOAD:
88   case G_STORE:
89   case G_GEP:
90   case G_AND:
91   case G_OR:
92   case G_XOR:
93   case G_SHL:
94   case G_ASHR:
95   case G_LSHR:
96   case G_SDIV:
97   case G_UDIV:
98   case G_SREM:
99   case G_UREM:
100     OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
101     break;
102   case G_CONSTANT:
103   case G_FRAME_INDEX:
104   case G_GLOBAL_VALUE:
105     OperandsMapping =
106         getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr});
107     break;
108   case G_ICMP:
109     OperandsMapping =
110         getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr,
111                             &Mips::ValueMappings[Mips::GPRIdx],
112                             &Mips::ValueMappings[Mips::GPRIdx]});
113     break;
114   case G_SELECT:
115     OperandsMapping =
116         getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx],
117                             &Mips::ValueMappings[Mips::GPRIdx],
118                             &Mips::ValueMappings[Mips::GPRIdx],
119                             &Mips::ValueMappings[Mips::GPRIdx]});
120     break;
121   default:
122     return getInvalidInstructionMapping();
123   }
124 
125   return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping,
126                                NumOperands);
127 }
128