1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 #include "MipsISelLowering.h" 15 #include "InstPrinter/MipsInstPrinter.h" 16 #include "MCTargetDesc/MipsBaseInfo.h" 17 #include "MipsCCState.h" 18 #include "MipsMachineFunction.h" 19 #include "MipsSubtarget.h" 20 #include "MipsTargetMachine.h" 21 #include "MipsTargetObjectFile.h" 22 #include "llvm/ADT/Statistic.h" 23 #include "llvm/ADT/StringSwitch.h" 24 #include "llvm/CodeGen/CallingConvLower.h" 25 #include "llvm/CodeGen/FunctionLoweringInfo.h" 26 #include "llvm/CodeGen/MachineFrameInfo.h" 27 #include "llvm/CodeGen/MachineFunction.h" 28 #include "llvm/CodeGen/MachineInstrBuilder.h" 29 #include "llvm/CodeGen/MachineJumpTableInfo.h" 30 #include "llvm/CodeGen/MachineRegisterInfo.h" 31 #include "llvm/CodeGen/SelectionDAGISel.h" 32 #include "llvm/CodeGen/ValueTypes.h" 33 #include "llvm/IR/CallingConv.h" 34 #include "llvm/IR/DerivedTypes.h" 35 #include "llvm/IR/GlobalVariable.h" 36 #include "llvm/Support/CommandLine.h" 37 #include "llvm/Support/Debug.h" 38 #include "llvm/Support/ErrorHandling.h" 39 #include "llvm/Support/raw_ostream.h" 40 #include <cctype> 41 42 using namespace llvm; 43 44 #define DEBUG_TYPE "mips-lower" 45 46 STATISTIC(NumTailCalls, "Number of tail calls"); 47 48 static cl::opt<bool> 49 LargeGOT("mxgot", cl::Hidden, 50 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 51 52 static cl::opt<bool> 53 NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 54 cl::desc("MIPS: Don't trap on integer division by zero."), 55 cl::init(false)); 56 57 static const MCPhysReg Mips64DPRegs[8] = { 58 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 59 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 60 }; 61 62 // If I is a shifted mask, set the size (Size) and the first bit of the 63 // mask (Pos), and return true. 64 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 65 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 66 if (!isShiftedMask_64(I)) 67 return false; 68 69 Size = countPopulation(I); 70 Pos = countTrailingZeros(I); 71 return true; 72 } 73 74 // The MIPS MSA ABI passes vector arguments in the integer register set. 75 // The number of integer registers used is dependant on the ABI used. 76 MVT MipsTargetLowering::getRegisterTypeForCallingConv(MVT VT) const { 77 if (VT.isVector() && Subtarget.hasMSA()) 78 return Subtarget.isABI_O32() ? MVT::i32 : MVT::i64; 79 return MipsTargetLowering::getRegisterType(VT); 80 } 81 82 MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, 83 EVT VT) const { 84 if (VT.isVector()) { 85 if (Subtarget.isABI_O32()) { 86 return MVT::i32; 87 } else { 88 return (VT.getSizeInBits() == 32) ? MVT::i32 : MVT::i64; 89 } 90 } 91 return MipsTargetLowering::getRegisterType(Context, VT); 92 } 93 94 unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context, 95 EVT VT) const { 96 if (VT.isVector()) 97 return std::max((VT.getSizeInBits() / (Subtarget.isABI_O32() ? 32 : 64)), 98 1U); 99 return MipsTargetLowering::getNumRegisters(Context, VT); 100 } 101 102 unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv( 103 LLVMContext &Context, EVT VT, EVT &IntermediateVT, 104 unsigned &NumIntermediates, MVT &RegisterVT) const { 105 106 // Break down vector types to either 2 i64s or 4 i32s. 107 RegisterVT = getRegisterTypeForCallingConv(Context, VT) ; 108 IntermediateVT = RegisterVT; 109 NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits() 110 ? VT.getVectorNumElements() 111 : VT.getSizeInBits() / RegisterVT.getSizeInBits(); 112 113 return NumIntermediates; 114 } 115 116 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 117 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 118 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 119 } 120 121 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 122 SelectionDAG &DAG, 123 unsigned Flag) const { 124 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 125 } 126 127 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 128 SelectionDAG &DAG, 129 unsigned Flag) const { 130 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 131 } 132 133 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 134 SelectionDAG &DAG, 135 unsigned Flag) const { 136 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 137 } 138 139 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 140 SelectionDAG &DAG, 141 unsigned Flag) const { 142 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 143 } 144 145 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 146 SelectionDAG &DAG, 147 unsigned Flag) const { 148 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 149 N->getOffset(), Flag); 150 } 151 152 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 153 switch ((MipsISD::NodeType)Opcode) { 154 case MipsISD::FIRST_NUMBER: break; 155 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 156 case MipsISD::TailCall: return "MipsISD::TailCall"; 157 case MipsISD::Highest: return "MipsISD::Highest"; 158 case MipsISD::Higher: return "MipsISD::Higher"; 159 case MipsISD::Hi: return "MipsISD::Hi"; 160 case MipsISD::Lo: return "MipsISD::Lo"; 161 case MipsISD::GotHi: return "MipsISD::GotHi"; 162 case MipsISD::GPRel: return "MipsISD::GPRel"; 163 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 164 case MipsISD::Ret: return "MipsISD::Ret"; 165 case MipsISD::ERet: return "MipsISD::ERet"; 166 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 167 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 168 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 169 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 170 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 171 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 172 case MipsISD::MFHI: return "MipsISD::MFHI"; 173 case MipsISD::MFLO: return "MipsISD::MFLO"; 174 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 175 case MipsISD::Mult: return "MipsISD::Mult"; 176 case MipsISD::Multu: return "MipsISD::Multu"; 177 case MipsISD::MAdd: return "MipsISD::MAdd"; 178 case MipsISD::MAddu: return "MipsISD::MAddu"; 179 case MipsISD::MSub: return "MipsISD::MSub"; 180 case MipsISD::MSubu: return "MipsISD::MSubu"; 181 case MipsISD::DivRem: return "MipsISD::DivRem"; 182 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 183 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 184 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 185 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 186 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 187 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 188 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 189 case MipsISD::Sync: return "MipsISD::Sync"; 190 case MipsISD::Ext: return "MipsISD::Ext"; 191 case MipsISD::Ins: return "MipsISD::Ins"; 192 case MipsISD::CIns: return "MipsISD::CIns"; 193 case MipsISD::LWL: return "MipsISD::LWL"; 194 case MipsISD::LWR: return "MipsISD::LWR"; 195 case MipsISD::SWL: return "MipsISD::SWL"; 196 case MipsISD::SWR: return "MipsISD::SWR"; 197 case MipsISD::LDL: return "MipsISD::LDL"; 198 case MipsISD::LDR: return "MipsISD::LDR"; 199 case MipsISD::SDL: return "MipsISD::SDL"; 200 case MipsISD::SDR: return "MipsISD::SDR"; 201 case MipsISD::EXTP: return "MipsISD::EXTP"; 202 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 203 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 204 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 205 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 206 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 207 case MipsISD::SHILO: return "MipsISD::SHILO"; 208 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 209 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; 210 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; 211 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; 212 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; 213 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; 214 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; 215 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; 216 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; 217 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; 218 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; 219 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; 220 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; 221 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; 222 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; 223 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; 224 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; 225 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; 226 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; 227 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; 228 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; 229 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; 230 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; 231 case MipsISD::MULT: return "MipsISD::MULT"; 232 case MipsISD::MULTU: return "MipsISD::MULTU"; 233 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 234 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 235 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 236 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 237 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 238 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 239 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 240 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 241 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 242 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 243 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 244 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 245 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 246 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 247 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 248 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 249 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 250 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 251 case MipsISD::VSMAX: return "MipsISD::VSMAX"; 252 case MipsISD::VSMIN: return "MipsISD::VSMIN"; 253 case MipsISD::VUMAX: return "MipsISD::VUMAX"; 254 case MipsISD::VUMIN: return "MipsISD::VUMIN"; 255 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 256 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 257 case MipsISD::VNOR: return "MipsISD::VNOR"; 258 case MipsISD::VSHF: return "MipsISD::VSHF"; 259 case MipsISD::SHF: return "MipsISD::SHF"; 260 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 261 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 262 case MipsISD::ILVL: return "MipsISD::ILVL"; 263 case MipsISD::ILVR: return "MipsISD::ILVR"; 264 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 265 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 266 case MipsISD::INSVE: return "MipsISD::INSVE"; 267 } 268 return nullptr; 269 } 270 271 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, 272 const MipsSubtarget &STI) 273 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { 274 // Mips does not have i1 type, so use i32 for 275 // setcc operations results (slt, sgt, ...). 276 setBooleanContents(ZeroOrOneBooleanContent); 277 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 278 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA 279 // does. Integer booleans still use 0 and 1. 280 if (Subtarget.hasMips32r6()) 281 setBooleanContents(ZeroOrOneBooleanContent, 282 ZeroOrNegativeOneBooleanContent); 283 284 // Load extented operations for i1 types must be promoted 285 for (MVT VT : MVT::integer_valuetypes()) { 286 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 287 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 288 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 289 } 290 291 // MIPS doesn't have extending float->double load/store. Set LoadExtAction 292 // for f32, f16 293 for (MVT VT : MVT::fp_valuetypes()) { 294 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 295 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 296 } 297 298 // Set LoadExtAction for f16 vectors to Expand 299 for (MVT VT : MVT::fp_vector_valuetypes()) { 300 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); 301 if (F16VT.isValid()) 302 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); 303 } 304 305 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 306 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 307 308 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 309 310 // Used by legalize types to correctly generate the setcc result. 311 // Without this, every float setcc comes with a AND/OR with the result, 312 // we don't want this, since the fpcmp result goes to a flag register, 313 // which is used implicitly by brcond and select operations. 314 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 315 316 // Mips Custom Operations 317 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 318 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 319 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 320 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 321 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 322 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 323 setOperationAction(ISD::SELECT, MVT::f32, Custom); 324 setOperationAction(ISD::SELECT, MVT::f64, Custom); 325 setOperationAction(ISD::SELECT, MVT::i32, Custom); 326 setOperationAction(ISD::SETCC, MVT::f32, Custom); 327 setOperationAction(ISD::SETCC, MVT::f64, Custom); 328 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 329 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 330 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 331 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 332 333 if (Subtarget.isGP64bit()) { 334 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 335 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 336 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 337 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 338 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 339 setOperationAction(ISD::SELECT, MVT::i64, Custom); 340 setOperationAction(ISD::LOAD, MVT::i64, Custom); 341 setOperationAction(ISD::STORE, MVT::i64, Custom); 342 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 343 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 344 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 345 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 346 } 347 348 if (!Subtarget.isGP64bit()) { 349 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 350 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 351 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 352 } 353 354 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); 355 if (Subtarget.isGP64bit()) 356 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); 357 358 setOperationAction(ISD::SDIV, MVT::i32, Expand); 359 setOperationAction(ISD::SREM, MVT::i32, Expand); 360 setOperationAction(ISD::UDIV, MVT::i32, Expand); 361 setOperationAction(ISD::UREM, MVT::i32, Expand); 362 setOperationAction(ISD::SDIV, MVT::i64, Expand); 363 setOperationAction(ISD::SREM, MVT::i64, Expand); 364 setOperationAction(ISD::UDIV, MVT::i64, Expand); 365 setOperationAction(ISD::UREM, MVT::i64, Expand); 366 367 if (!(Subtarget.hasDSP() && Subtarget.hasMips32r2())) { 368 setOperationAction(ISD::ADDC, MVT::i32, Expand); 369 setOperationAction(ISD::ADDE, MVT::i32, Expand); 370 } 371 372 setOperationAction(ISD::ADDC, MVT::i64, Expand); 373 setOperationAction(ISD::ADDE, MVT::i64, Expand); 374 setOperationAction(ISD::SUBC, MVT::i32, Expand); 375 setOperationAction(ISD::SUBE, MVT::i32, Expand); 376 setOperationAction(ISD::SUBC, MVT::i64, Expand); 377 setOperationAction(ISD::SUBE, MVT::i64, Expand); 378 379 // Operations not directly supported by Mips. 380 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 381 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 382 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 383 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 384 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 385 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 386 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 387 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 388 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 389 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 390 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 391 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 392 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 393 if (Subtarget.hasCnMips()) { 394 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 395 setOperationAction(ISD::CTPOP, MVT::i64, Legal); 396 } else { 397 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 398 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 399 } 400 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 401 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 402 setOperationAction(ISD::ROTL, MVT::i32, Expand); 403 setOperationAction(ISD::ROTL, MVT::i64, Expand); 404 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 405 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 406 407 if (!Subtarget.hasMips32r2()) 408 setOperationAction(ISD::ROTR, MVT::i32, Expand); 409 410 if (!Subtarget.hasMips64r2()) 411 setOperationAction(ISD::ROTR, MVT::i64, Expand); 412 413 setOperationAction(ISD::FSIN, MVT::f32, Expand); 414 setOperationAction(ISD::FSIN, MVT::f64, Expand); 415 setOperationAction(ISD::FCOS, MVT::f32, Expand); 416 setOperationAction(ISD::FCOS, MVT::f64, Expand); 417 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 418 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 419 setOperationAction(ISD::FPOW, MVT::f32, Expand); 420 setOperationAction(ISD::FPOW, MVT::f64, Expand); 421 setOperationAction(ISD::FLOG, MVT::f32, Expand); 422 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 423 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 424 setOperationAction(ISD::FEXP, MVT::f32, Expand); 425 setOperationAction(ISD::FMA, MVT::f32, Expand); 426 setOperationAction(ISD::FMA, MVT::f64, Expand); 427 setOperationAction(ISD::FREM, MVT::f32, Expand); 428 setOperationAction(ISD::FREM, MVT::f64, Expand); 429 430 // Lower f16 conversion operations into library calls 431 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); 432 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); 433 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); 434 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); 435 436 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 437 438 setOperationAction(ISD::VASTART, MVT::Other, Custom); 439 setOperationAction(ISD::VAARG, MVT::Other, Custom); 440 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 441 setOperationAction(ISD::VAEND, MVT::Other, Expand); 442 443 // Use the default for now 444 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 445 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 446 447 if (!Subtarget.isGP64bit()) { 448 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 449 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 450 } 451 452 453 if (!Subtarget.hasMips32r2()) { 454 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 455 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 456 } 457 458 // MIPS16 lacks MIPS32's clz and clo instructions. 459 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 460 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 461 if (!Subtarget.hasMips64()) 462 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 463 464 if (!Subtarget.hasMips32r2()) 465 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 466 if (!Subtarget.hasMips64r2()) 467 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 468 469 if (Subtarget.isGP64bit()) { 470 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); 471 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); 472 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); 473 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 474 } 475 476 setOperationAction(ISD::TRAP, MVT::Other, Legal); 477 478 setTargetDAGCombine(ISD::SDIVREM); 479 setTargetDAGCombine(ISD::UDIVREM); 480 setTargetDAGCombine(ISD::SELECT); 481 setTargetDAGCombine(ISD::AND); 482 setTargetDAGCombine(ISD::OR); 483 setTargetDAGCombine(ISD::ADD); 484 setTargetDAGCombine(ISD::SUB); 485 setTargetDAGCombine(ISD::AssertZext); 486 setTargetDAGCombine(ISD::SHL); 487 488 if (ABI.IsO32()) { 489 // These libcalls are not available in 32-bit. 490 setLibcallName(RTLIB::SHL_I128, nullptr); 491 setLibcallName(RTLIB::SRL_I128, nullptr); 492 setLibcallName(RTLIB::SRA_I128, nullptr); 493 } 494 495 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2); 496 497 // The arguments on the stack are defined in terms of 4-byte slots on O32 498 // and 8-byte slots on N32/N64. 499 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4); 500 501 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); 502 503 MaxStoresPerMemcpy = 16; 504 505 isMicroMips = Subtarget.inMicroMipsMode(); 506 } 507 508 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM, 509 const MipsSubtarget &STI) { 510 if (STI.inMips16Mode()) 511 return llvm::createMips16TargetLowering(TM, STI); 512 513 return llvm::createMipsSETargetLowering(TM, STI); 514 } 515 516 // Create a fast isel object. 517 FastISel * 518 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 519 const TargetLibraryInfo *libInfo) const { 520 const MipsTargetMachine &TM = 521 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget()); 522 523 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs. 524 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() && 525 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() && 526 !Subtarget.inMicroMipsMode(); 527 528 // Disable if either of the following is true: 529 // We do not generate PIC, the ABI is not O32, LargeGOT is being used. 530 if (!TM.isPositionIndependent() || !TM.getABI().IsO32() || LargeGOT) 531 UseFastISel = false; 532 533 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr; 534 } 535 536 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, 537 EVT VT) const { 538 if (!VT.isVector()) 539 return MVT::i32; 540 return VT.changeVectorElementTypeToInteger(); 541 } 542 543 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 544 TargetLowering::DAGCombinerInfo &DCI, 545 const MipsSubtarget &Subtarget) { 546 if (DCI.isBeforeLegalizeOps()) 547 return SDValue(); 548 549 EVT Ty = N->getValueType(0); 550 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 551 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 552 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 553 MipsISD::DivRemU16; 554 SDLoc DL(N); 555 556 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 557 N->getOperand(0), N->getOperand(1)); 558 SDValue InChain = DAG.getEntryNode(); 559 SDValue InGlue = DivRem; 560 561 // insert MFLO 562 if (N->hasAnyUseOfValue(0)) { 563 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 564 InGlue); 565 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 566 InChain = CopyFromLo.getValue(1); 567 InGlue = CopyFromLo.getValue(2); 568 } 569 570 // insert MFHI 571 if (N->hasAnyUseOfValue(1)) { 572 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 573 HI, Ty, InGlue); 574 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 575 } 576 577 return SDValue(); 578 } 579 580 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 581 switch (CC) { 582 default: llvm_unreachable("Unknown fp condition code!"); 583 case ISD::SETEQ: 584 case ISD::SETOEQ: return Mips::FCOND_OEQ; 585 case ISD::SETUNE: return Mips::FCOND_UNE; 586 case ISD::SETLT: 587 case ISD::SETOLT: return Mips::FCOND_OLT; 588 case ISD::SETGT: 589 case ISD::SETOGT: return Mips::FCOND_OGT; 590 case ISD::SETLE: 591 case ISD::SETOLE: return Mips::FCOND_OLE; 592 case ISD::SETGE: 593 case ISD::SETOGE: return Mips::FCOND_OGE; 594 case ISD::SETULT: return Mips::FCOND_ULT; 595 case ISD::SETULE: return Mips::FCOND_ULE; 596 case ISD::SETUGT: return Mips::FCOND_UGT; 597 case ISD::SETUGE: return Mips::FCOND_UGE; 598 case ISD::SETUO: return Mips::FCOND_UN; 599 case ISD::SETO: return Mips::FCOND_OR; 600 case ISD::SETNE: 601 case ISD::SETONE: return Mips::FCOND_ONE; 602 case ISD::SETUEQ: return Mips::FCOND_UEQ; 603 } 604 } 605 606 607 /// This function returns true if the floating point conditional branches and 608 /// conditional moves which use condition code CC should be inverted. 609 static bool invertFPCondCodeUser(Mips::CondCode CC) { 610 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 611 return false; 612 613 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 614 "Illegal Condition Code"); 615 616 return true; 617 } 618 619 // Creates and returns an FPCmp node from a setcc node. 620 // Returns Op if setcc is not a floating point comparison. 621 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 622 // must be a SETCC node 623 if (Op.getOpcode() != ISD::SETCC) 624 return Op; 625 626 SDValue LHS = Op.getOperand(0); 627 628 if (!LHS.getValueType().isFloatingPoint()) 629 return Op; 630 631 SDValue RHS = Op.getOperand(1); 632 SDLoc DL(Op); 633 634 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 635 // node if necessary. 636 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 637 638 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 639 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); 640 } 641 642 // Creates and returns a CMovFPT/F node. 643 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 644 SDValue False, const SDLoc &DL) { 645 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 646 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 647 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 648 649 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 650 True.getValueType(), True, FCC0, False, Cond); 651 } 652 653 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 654 TargetLowering::DAGCombinerInfo &DCI, 655 const MipsSubtarget &Subtarget) { 656 if (DCI.isBeforeLegalizeOps()) 657 return SDValue(); 658 659 SDValue SetCC = N->getOperand(0); 660 661 if ((SetCC.getOpcode() != ISD::SETCC) || 662 !SetCC.getOperand(0).getValueType().isInteger()) 663 return SDValue(); 664 665 SDValue False = N->getOperand(2); 666 EVT FalseTy = False.getValueType(); 667 668 if (!FalseTy.isInteger()) 669 return SDValue(); 670 671 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); 672 673 // If the RHS (False) is 0, we swap the order of the operands 674 // of ISD::SELECT (obviously also inverting the condition) so that we can 675 // take advantage of conditional moves using the $0 register. 676 // Example: 677 // return (a != 0) ? x : 0; 678 // load $reg, x 679 // movz $reg, $0, a 680 if (!FalseC) 681 return SDValue(); 682 683 const SDLoc DL(N); 684 685 if (!FalseC->getZExtValue()) { 686 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 687 SDValue True = N->getOperand(1); 688 689 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 690 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 691 692 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 693 } 694 695 // If both operands are integer constants there's a possibility that we 696 // can do some interesting optimizations. 697 SDValue True = N->getOperand(1); 698 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); 699 700 if (!TrueC || !True.getValueType().isInteger()) 701 return SDValue(); 702 703 // We'll also ignore MVT::i64 operands as this optimizations proves 704 // to be ineffective because of the required sign extensions as the result 705 // of a SETCC operator is always MVT::i32 for non-vector types. 706 if (True.getValueType() == MVT::i64) 707 return SDValue(); 708 709 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); 710 711 // 1) (a < x) ? y : y-1 712 // slti $reg1, a, x 713 // addiu $reg2, $reg1, y-1 714 if (Diff == 1) 715 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); 716 717 // 2) (a < x) ? y-1 : y 718 // slti $reg1, a, x 719 // xor $reg1, $reg1, 1 720 // addiu $reg2, $reg1, y-1 721 if (Diff == -1) { 722 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 723 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 724 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 725 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); 726 } 727 728 // Couldn't optimize. 729 return SDValue(); 730 } 731 732 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, 733 TargetLowering::DAGCombinerInfo &DCI, 734 const MipsSubtarget &Subtarget) { 735 if (DCI.isBeforeLegalizeOps()) 736 return SDValue(); 737 738 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); 739 740 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse); 741 if (!FalseC || FalseC->getZExtValue()) 742 return SDValue(); 743 744 // Since RHS (False) is 0, we swap the order of the True/False operands 745 // (obviously also inverting the condition) so that we can 746 // take advantage of conditional moves using the $0 register. 747 // Example: 748 // return (a != 0) ? x : 0; 749 // load $reg, x 750 // movz $reg, $0, a 751 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : 752 MipsISD::CMovFP_T; 753 754 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); 755 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(), 756 ValueIfFalse, FCC, ValueIfTrue, Glue); 757 } 758 759 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 760 TargetLowering::DAGCombinerInfo &DCI, 761 const MipsSubtarget &Subtarget) { 762 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 763 return SDValue(); 764 765 SDValue FirstOperand = N->getOperand(0); 766 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 767 SDValue Mask = N->getOperand(1); 768 EVT ValTy = N->getValueType(0); 769 SDLoc DL(N); 770 771 uint64_t Pos = 0, SMPos, SMSize; 772 ConstantSDNode *CN; 773 SDValue NewOperand; 774 unsigned Opc; 775 776 // Op's second operand must be a shifted mask. 777 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 778 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 779 return SDValue(); 780 781 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { 782 // Pattern match EXT. 783 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 784 // => ext $dst, $src, pos, size 785 786 // The second operand of the shift must be an immediate. 787 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 788 return SDValue(); 789 790 Pos = CN->getZExtValue(); 791 792 // Return if the shifted mask does not start at bit 0 or the sum of its size 793 // and Pos exceeds the word's size. 794 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 795 return SDValue(); 796 797 Opc = MipsISD::Ext; 798 NewOperand = FirstOperand.getOperand(0); 799 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) { 800 // Pattern match CINS. 801 // $dst = and (shl $src , pos), mask 802 // => cins $dst, $src, pos, size 803 // mask is a shifted mask with consecutive 1's, pos = shift amount, 804 // size = population count. 805 806 // The second operand of the shift must be an immediate. 807 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 808 return SDValue(); 809 810 Pos = CN->getZExtValue(); 811 812 if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 || 813 Pos + SMSize > ValTy.getSizeInBits()) 814 return SDValue(); 815 816 NewOperand = FirstOperand.getOperand(0); 817 // SMSize is 'location' (position) in this case, not size. 818 SMSize--; 819 Opc = MipsISD::CIns; 820 } else { 821 // Pattern match EXT. 822 // $dst = and $src, (2**size - 1) , if size > 16 823 // => ext $dst, $src, pos, size , pos = 0 824 825 // If the mask is <= 0xffff, andi can be used instead. 826 if (CN->getZExtValue() <= 0xffff) 827 return SDValue(); 828 829 // Return if the mask doesn't start at position 0. 830 if (SMPos) 831 return SDValue(); 832 833 Opc = MipsISD::Ext; 834 NewOperand = FirstOperand; 835 } 836 return DAG.getNode(Opc, DL, ValTy, NewOperand, 837 DAG.getConstant(Pos, DL, MVT::i32), 838 DAG.getConstant(SMSize, DL, MVT::i32)); 839 } 840 841 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 842 TargetLowering::DAGCombinerInfo &DCI, 843 const MipsSubtarget &Subtarget) { 844 // Pattern match INS. 845 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 846 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 847 // => ins $dst, $src, size, pos, $src1 848 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 849 return SDValue(); 850 851 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 852 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 853 ConstantSDNode *CN, *CN1; 854 855 // See if Op's first operand matches (and $src1 , mask0). 856 if (And0.getOpcode() != ISD::AND) 857 return SDValue(); 858 859 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 860 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 861 return SDValue(); 862 863 // See if Op's second operand matches (and (shl $src, pos), mask1). 864 if (And1.getOpcode() == ISD::AND && 865 And1.getOperand(0).getOpcode() == ISD::SHL) { 866 867 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 868 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 869 return SDValue(); 870 871 // The shift masks must have the same position and size. 872 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 873 return SDValue(); 874 875 SDValue Shl = And1.getOperand(0); 876 877 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 878 return SDValue(); 879 880 unsigned Shamt = CN->getZExtValue(); 881 882 // Return if the shift amount and the first bit position of mask are not the 883 // same. 884 EVT ValTy = N->getValueType(0); 885 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 886 return SDValue(); 887 888 SDLoc DL(N); 889 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0), 890 DAG.getConstant(SMPos0, DL, MVT::i32), 891 DAG.getConstant(SMSize0, DL, MVT::i32), 892 And0.getOperand(0)); 893 } else { 894 // Pattern match DINS. 895 // $dst = or (and $src, mask0), mask1 896 // where mask0 = ((1 << SMSize0) -1) << SMPos0 897 // => dins $dst, $src, pos, size 898 if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) && 899 ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) || 900 (SMSize0 + SMPos0 <= 32))) { 901 // Check if AND instruction has constant as argument 902 bool isConstCase = And1.getOpcode() != ISD::AND; 903 if (And1.getOpcode() == ISD::AND) { 904 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1)))) 905 return SDValue(); 906 } else { 907 if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1)))) 908 return SDValue(); 909 } 910 // Don't generate INS if constant OR operand doesn't fit into bits 911 // cleared by constant AND operand. 912 if (CN->getSExtValue() & CN1->getSExtValue()) 913 return SDValue(); 914 915 SDLoc DL(N); 916 EVT ValTy = N->getOperand(0)->getValueType(0); 917 SDValue Const1; 918 SDValue SrlX; 919 if (!isConstCase) { 920 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32); 921 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); 922 } 923 return DAG.getNode( 924 MipsISD::Ins, DL, N->getValueType(0), 925 isConstCase 926 ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy) 927 : SrlX, 928 DAG.getConstant(SMPos0, DL, MVT::i32), 929 DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31 930 : SMSize0, 931 DL, MVT::i32), 932 And0->getOperand(0)); 933 934 } 935 return SDValue(); 936 } 937 } 938 939 static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, 940 const MipsSubtarget &Subtarget) { 941 // ROOTNode must have a multiplication as an operand for the match to be 942 // successful. 943 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL && 944 ROOTNode->getOperand(1).getOpcode() != ISD::MUL) 945 return SDValue(); 946 947 // We don't handle vector types here. 948 if (ROOTNode->getValueType(0).isVector()) 949 return SDValue(); 950 951 // For MIPS64, madd / msub instructions are inefficent to use with 64 bit 952 // arithmetic. E.g. 953 // (add (mul a b) c) => 954 // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in 955 // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32) 956 // or 957 // MIPS64R2: (dins (mflo res) (mfhi res) 32 32) 958 // 959 // The overhead of setting up the Hi/Lo registers and reassembling the 960 // result makes this a dubious optimzation for MIPS64. The core of the 961 // problem is that Hi/Lo contain the upper and lower 32 bits of the 962 // operand and result. 963 // 964 // It requires a chain of 4 add/mul for MIPS64R2 to get better code 965 // density than doing it naively, 5 for MIPS64. Additionally, using 966 // madd/msub on MIPS64 requires the operands actually be 32 bit sign 967 // extended operands, not true 64 bit values. 968 // 969 // FIXME: For the moment, disable this completely for MIPS64. 970 if (Subtarget.hasMips64()) 971 return SDValue(); 972 973 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 974 ? ROOTNode->getOperand(0) 975 : ROOTNode->getOperand(1); 976 977 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 978 ? ROOTNode->getOperand(1) 979 : ROOTNode->getOperand(0); 980 981 // Transform this to a MADD only if the user of this node is the add. 982 // If there are other users of the mul, this function returns here. 983 if (!Mult.hasOneUse()) 984 return SDValue(); 985 986 // maddu and madd are unusual instructions in that on MIPS64 bits 63..31 987 // must be in canonical form, i.e. sign extended. For MIPS32, the operands 988 // of the multiply must have 32 or more sign bits, otherwise we cannot 989 // perform this optimization. We have to check this here as we're performing 990 // this optimization pre-legalization. 991 SDValue MultLHS = Mult->getOperand(0); 992 SDValue MultRHS = Mult->getOperand(1); 993 994 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND && 995 MultRHS->getOpcode() == ISD::SIGN_EXTEND; 996 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND && 997 MultRHS->getOpcode() == ISD::ZERO_EXTEND; 998 999 if (!IsSigned && !IsUnsigned) 1000 return SDValue(); 1001 1002 // Initialize accumulator. 1003 SDLoc DL(ROOTNode); 1004 SDValue TopHalf; 1005 SDValue BottomHalf; 1006 BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, 1007 CurDAG.getIntPtrConstant(0, DL)); 1008 1009 TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, 1010 CurDAG.getIntPtrConstant(1, DL)); 1011 SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, 1012 BottomHalf, 1013 TopHalf); 1014 1015 // Create MipsMAdd(u) / MipsMSub(u) node. 1016 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD; 1017 unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd) 1018 : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub); 1019 SDValue MAddOps[3] = { 1020 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)), 1021 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn}; 1022 EVT VTs[2] = {MVT::i32, MVT::i32}; 1023 SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps); 1024 1025 SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); 1026 SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); 1027 SDValue Combined = 1028 CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi); 1029 return Combined; 1030 } 1031 1032 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, 1033 TargetLowering::DAGCombinerInfo &DCI, 1034 const MipsSubtarget &Subtarget) { 1035 // (sub v0 (mul v1, v2)) => (msub v1, v2, v0) 1036 if (DCI.isBeforeLegalizeOps()) { 1037 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1038 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1039 return performMADD_MSUBCombine(N, DAG, Subtarget); 1040 1041 return SDValue(); 1042 } 1043 1044 return SDValue(); 1045 } 1046 1047 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 1048 TargetLowering::DAGCombinerInfo &DCI, 1049 const MipsSubtarget &Subtarget) { 1050 // (add v0 (mul v1, v2)) => (madd v1, v2, v0) 1051 if (DCI.isBeforeLegalizeOps()) { 1052 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1053 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1054 return performMADD_MSUBCombine(N, DAG, Subtarget); 1055 1056 return SDValue(); 1057 } 1058 1059 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 1060 SDValue Add = N->getOperand(1); 1061 1062 if (Add.getOpcode() != ISD::ADD) 1063 return SDValue(); 1064 1065 SDValue Lo = Add.getOperand(1); 1066 1067 if ((Lo.getOpcode() != MipsISD::Lo) || 1068 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 1069 return SDValue(); 1070 1071 EVT ValTy = N->getValueType(0); 1072 SDLoc DL(N); 1073 1074 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 1075 Add.getOperand(0)); 1076 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 1077 } 1078 1079 static SDValue performAssertZextCombine(SDNode *N, SelectionDAG &DAG, 1080 TargetLowering::DAGCombinerInfo &DCI, 1081 const MipsSubtarget &Subtarget) { 1082 SDValue N0 = N->getOperand(0); 1083 EVT NarrowerVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1084 1085 if (N0.getOpcode() != ISD::TRUNCATE) 1086 return SDValue(); 1087 1088 if (N0.getOperand(0).getOpcode() != ISD::AssertZext) 1089 return SDValue(); 1090 1091 // fold (AssertZext (trunc (AssertZext x))) -> (trunc (AssertZext x)) 1092 // if the type of the extension of the innermost AssertZext node is 1093 // smaller from that of the outermost node, eg: 1094 // (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8) 1095 // -> (trunc:i32 (AssertZext X, i8)) 1096 SDValue WiderAssertZext = N0.getOperand(0); 1097 EVT WiderVT = cast<VTSDNode>(WiderAssertZext->getOperand(1))->getVT(); 1098 1099 if (NarrowerVT.bitsLT(WiderVT)) { 1100 SDValue NewAssertZext = DAG.getNode( 1101 ISD::AssertZext, SDLoc(N), WiderAssertZext.getValueType(), 1102 WiderAssertZext.getOperand(0), DAG.getValueType(NarrowerVT)); 1103 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), 1104 NewAssertZext); 1105 } 1106 1107 return SDValue(); 1108 } 1109 1110 1111 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, 1112 TargetLowering::DAGCombinerInfo &DCI, 1113 const MipsSubtarget &Subtarget) { 1114 // Pattern match CINS. 1115 // $dst = shl (and $src , imm), pos 1116 // => cins $dst, $src, pos, size 1117 1118 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips()) 1119 return SDValue(); 1120 1121 SDValue FirstOperand = N->getOperand(0); 1122 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 1123 SDValue SecondOperand = N->getOperand(1); 1124 EVT ValTy = N->getValueType(0); 1125 SDLoc DL(N); 1126 1127 uint64_t Pos = 0, SMPos, SMSize; 1128 ConstantSDNode *CN; 1129 SDValue NewOperand; 1130 1131 // The second operand of the shift must be an immediate. 1132 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand))) 1133 return SDValue(); 1134 1135 Pos = CN->getZExtValue(); 1136 1137 if (Pos >= ValTy.getSizeInBits()) 1138 return SDValue(); 1139 1140 if (FirstOperandOpc != ISD::AND) 1141 return SDValue(); 1142 1143 // AND's second operand must be a shifted mask. 1144 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) || 1145 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 1146 return SDValue(); 1147 1148 // Return if the shifted mask does not start at bit 0 or the sum of its size 1149 // and Pos exceeds the word's size. 1150 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits()) 1151 return SDValue(); 1152 1153 NewOperand = FirstOperand.getOperand(0); 1154 // SMSize is 'location' (position) in this case, not size. 1155 SMSize--; 1156 1157 return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand, 1158 DAG.getConstant(Pos, DL, MVT::i32), 1159 DAG.getConstant(SMSize, DL, MVT::i32)); 1160 } 1161 1162 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 1163 const { 1164 SelectionDAG &DAG = DCI.DAG; 1165 unsigned Opc = N->getOpcode(); 1166 1167 switch (Opc) { 1168 default: break; 1169 case ISD::SDIVREM: 1170 case ISD::UDIVREM: 1171 return performDivRemCombine(N, DAG, DCI, Subtarget); 1172 case ISD::SELECT: 1173 return performSELECTCombine(N, DAG, DCI, Subtarget); 1174 case MipsISD::CMovFP_F: 1175 case MipsISD::CMovFP_T: 1176 return performCMovFPCombine(N, DAG, DCI, Subtarget); 1177 case ISD::AND: 1178 return performANDCombine(N, DAG, DCI, Subtarget); 1179 case ISD::OR: 1180 return performORCombine(N, DAG, DCI, Subtarget); 1181 case ISD::ADD: 1182 return performADDCombine(N, DAG, DCI, Subtarget); 1183 case ISD::AssertZext: 1184 return performAssertZextCombine(N, DAG, DCI, Subtarget); 1185 case ISD::SHL: 1186 return performSHLCombine(N, DAG, DCI, Subtarget); 1187 case ISD::SUB: 1188 return performSUBCombine(N, DAG, DCI, Subtarget); 1189 } 1190 1191 return SDValue(); 1192 } 1193 1194 bool MipsTargetLowering::isCheapToSpeculateCttz() const { 1195 return Subtarget.hasMips32(); 1196 } 1197 1198 bool MipsTargetLowering::isCheapToSpeculateCtlz() const { 1199 return Subtarget.hasMips32(); 1200 } 1201 1202 void 1203 MipsTargetLowering::LowerOperationWrapper(SDNode *N, 1204 SmallVectorImpl<SDValue> &Results, 1205 SelectionDAG &DAG) const { 1206 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 1207 1208 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 1209 Results.push_back(Res.getValue(I)); 1210 } 1211 1212 void 1213 MipsTargetLowering::ReplaceNodeResults(SDNode *N, 1214 SmallVectorImpl<SDValue> &Results, 1215 SelectionDAG &DAG) const { 1216 return LowerOperationWrapper(N, Results, DAG); 1217 } 1218 1219 SDValue MipsTargetLowering:: 1220 LowerOperation(SDValue Op, SelectionDAG &DAG) const 1221 { 1222 switch (Op.getOpcode()) 1223 { 1224 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 1225 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 1226 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 1227 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 1228 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 1229 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 1230 case ISD::SELECT: return lowerSELECT(Op, DAG); 1231 case ISD::SETCC: return lowerSETCC(Op, DAG); 1232 case ISD::VASTART: return lowerVASTART(Op, DAG); 1233 case ISD::VAARG: return lowerVAARG(Op, DAG); 1234 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 1235 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 1236 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 1237 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 1238 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 1239 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 1240 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 1241 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 1242 case ISD::LOAD: return lowerLOAD(Op, DAG); 1243 case ISD::STORE: return lowerSTORE(Op, DAG); 1244 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG); 1245 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 1246 } 1247 return SDValue(); 1248 } 1249 1250 //===----------------------------------------------------------------------===// 1251 // Lower helper functions 1252 //===----------------------------------------------------------------------===// 1253 1254 // addLiveIn - This helper function adds the specified physical register to the 1255 // MachineFunction as a live in value. It also creates a corresponding 1256 // virtual register for it. 1257 static unsigned 1258 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 1259 { 1260 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 1261 MF.getRegInfo().addLiveIn(PReg, VReg); 1262 return VReg; 1263 } 1264 1265 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI, 1266 MachineBasicBlock &MBB, 1267 const TargetInstrInfo &TII, 1268 bool Is64Bit, bool IsMicroMips) { 1269 if (NoZeroDivCheck) 1270 return &MBB; 1271 1272 // Insert instruction "teq $divisor_reg, $zero, 7". 1273 MachineBasicBlock::iterator I(MI); 1274 MachineInstrBuilder MIB; 1275 MachineOperand &Divisor = MI.getOperand(2); 1276 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(), 1277 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ)) 1278 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 1279 .addReg(Mips::ZERO) 1280 .addImm(7); 1281 1282 // Use the 32-bit sub-register if this is a 64-bit division. 1283 if (Is64Bit) 1284 MIB->getOperand(0).setSubReg(Mips::sub_32); 1285 1286 // Clear Divisor's kill flag. 1287 Divisor.setIsKill(false); 1288 1289 // We would normally delete the original instruction here but in this case 1290 // we only needed to inject an additional instruction rather than replace it. 1291 1292 return &MBB; 1293 } 1294 1295 MachineBasicBlock * 1296 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 1297 MachineBasicBlock *BB) const { 1298 switch (MI.getOpcode()) { 1299 default: 1300 llvm_unreachable("Unexpected instr type to insert"); 1301 case Mips::ATOMIC_LOAD_ADD_I8: 1302 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 1303 case Mips::ATOMIC_LOAD_ADD_I16: 1304 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 1305 case Mips::ATOMIC_LOAD_ADD_I32: 1306 return emitAtomicBinary(MI, BB, 4, Mips::ADDu); 1307 case Mips::ATOMIC_LOAD_ADD_I64: 1308 return emitAtomicBinary(MI, BB, 8, Mips::DADDu); 1309 1310 case Mips::ATOMIC_LOAD_AND_I8: 1311 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 1312 case Mips::ATOMIC_LOAD_AND_I16: 1313 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 1314 case Mips::ATOMIC_LOAD_AND_I32: 1315 return emitAtomicBinary(MI, BB, 4, Mips::AND); 1316 case Mips::ATOMIC_LOAD_AND_I64: 1317 return emitAtomicBinary(MI, BB, 8, Mips::AND64); 1318 1319 case Mips::ATOMIC_LOAD_OR_I8: 1320 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 1321 case Mips::ATOMIC_LOAD_OR_I16: 1322 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 1323 case Mips::ATOMIC_LOAD_OR_I32: 1324 return emitAtomicBinary(MI, BB, 4, Mips::OR); 1325 case Mips::ATOMIC_LOAD_OR_I64: 1326 return emitAtomicBinary(MI, BB, 8, Mips::OR64); 1327 1328 case Mips::ATOMIC_LOAD_XOR_I8: 1329 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 1330 case Mips::ATOMIC_LOAD_XOR_I16: 1331 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 1332 case Mips::ATOMIC_LOAD_XOR_I32: 1333 return emitAtomicBinary(MI, BB, 4, Mips::XOR); 1334 case Mips::ATOMIC_LOAD_XOR_I64: 1335 return emitAtomicBinary(MI, BB, 8, Mips::XOR64); 1336 1337 case Mips::ATOMIC_LOAD_NAND_I8: 1338 return emitAtomicBinaryPartword(MI, BB, 1, 0, true); 1339 case Mips::ATOMIC_LOAD_NAND_I16: 1340 return emitAtomicBinaryPartword(MI, BB, 2, 0, true); 1341 case Mips::ATOMIC_LOAD_NAND_I32: 1342 return emitAtomicBinary(MI, BB, 4, 0, true); 1343 case Mips::ATOMIC_LOAD_NAND_I64: 1344 return emitAtomicBinary(MI, BB, 8, 0, true); 1345 1346 case Mips::ATOMIC_LOAD_SUB_I8: 1347 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 1348 case Mips::ATOMIC_LOAD_SUB_I16: 1349 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 1350 case Mips::ATOMIC_LOAD_SUB_I32: 1351 return emitAtomicBinary(MI, BB, 4, Mips::SUBu); 1352 case Mips::ATOMIC_LOAD_SUB_I64: 1353 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu); 1354 1355 case Mips::ATOMIC_SWAP_I8: 1356 return emitAtomicBinaryPartword(MI, BB, 1, 0); 1357 case Mips::ATOMIC_SWAP_I16: 1358 return emitAtomicBinaryPartword(MI, BB, 2, 0); 1359 case Mips::ATOMIC_SWAP_I32: 1360 return emitAtomicBinary(MI, BB, 4, 0); 1361 case Mips::ATOMIC_SWAP_I64: 1362 return emitAtomicBinary(MI, BB, 8, 0); 1363 1364 case Mips::ATOMIC_CMP_SWAP_I8: 1365 return emitAtomicCmpSwapPartword(MI, BB, 1); 1366 case Mips::ATOMIC_CMP_SWAP_I16: 1367 return emitAtomicCmpSwapPartword(MI, BB, 2); 1368 case Mips::ATOMIC_CMP_SWAP_I32: 1369 return emitAtomicCmpSwap(MI, BB, 4); 1370 case Mips::ATOMIC_CMP_SWAP_I64: 1371 return emitAtomicCmpSwap(MI, BB, 8); 1372 case Mips::PseudoSDIV: 1373 case Mips::PseudoUDIV: 1374 case Mips::DIV: 1375 case Mips::DIVU: 1376 case Mips::MOD: 1377 case Mips::MODU: 1378 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, 1379 false); 1380 case Mips::SDIV_MM_Pseudo: 1381 case Mips::UDIV_MM_Pseudo: 1382 case Mips::SDIV_MM: 1383 case Mips::UDIV_MM: 1384 case Mips::DIV_MMR6: 1385 case Mips::DIVU_MMR6: 1386 case Mips::MOD_MMR6: 1387 case Mips::MODU_MMR6: 1388 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); 1389 case Mips::PseudoDSDIV: 1390 case Mips::PseudoDUDIV: 1391 case Mips::DDIV: 1392 case Mips::DDIVU: 1393 case Mips::DMOD: 1394 case Mips::DMODU: 1395 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); 1396 case Mips::DDIV_MM64R6: 1397 case Mips::DDIVU_MM64R6: 1398 case Mips::DMOD_MM64R6: 1399 case Mips::DMODU_MM64R6: 1400 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true); 1401 case Mips::SEL_D: 1402 case Mips::SEL_D_MMR6: 1403 return emitSEL_D(MI, BB); 1404 1405 case Mips::PseudoSELECT_I: 1406 case Mips::PseudoSELECT_I64: 1407 case Mips::PseudoSELECT_S: 1408 case Mips::PseudoSELECT_D32: 1409 case Mips::PseudoSELECT_D64: 1410 return emitPseudoSELECT(MI, BB, false, Mips::BNE); 1411 case Mips::PseudoSELECTFP_F_I: 1412 case Mips::PseudoSELECTFP_F_I64: 1413 case Mips::PseudoSELECTFP_F_S: 1414 case Mips::PseudoSELECTFP_F_D32: 1415 case Mips::PseudoSELECTFP_F_D64: 1416 return emitPseudoSELECT(MI, BB, true, Mips::BC1F); 1417 case Mips::PseudoSELECTFP_T_I: 1418 case Mips::PseudoSELECTFP_T_I64: 1419 case Mips::PseudoSELECTFP_T_S: 1420 case Mips::PseudoSELECTFP_T_D32: 1421 case Mips::PseudoSELECTFP_T_D64: 1422 return emitPseudoSELECT(MI, BB, true, Mips::BC1T); 1423 } 1424 } 1425 1426 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1427 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1428 MachineBasicBlock *MipsTargetLowering::emitAtomicBinary(MachineInstr &MI, 1429 MachineBasicBlock *BB, 1430 unsigned Size, 1431 unsigned BinOpcode, 1432 bool Nand) const { 1433 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 1434 1435 MachineFunction *MF = BB->getParent(); 1436 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1437 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1438 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1439 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1440 DebugLoc DL = MI.getDebugLoc(); 1441 unsigned LL, SC, AND, NOR, ZERO, BEQ; 1442 1443 if (Size == 4) { 1444 if (isMicroMips) { 1445 LL = Mips::LL_MM; 1446 SC = Mips::SC_MM; 1447 } else { 1448 LL = Subtarget.hasMips32r6() 1449 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1450 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1451 SC = Subtarget.hasMips32r6() 1452 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1453 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1454 } 1455 1456 AND = Mips::AND; 1457 NOR = Mips::NOR; 1458 ZERO = Mips::ZERO; 1459 BEQ = Mips::BEQ; 1460 } else { 1461 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1462 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1463 AND = Mips::AND64; 1464 NOR = Mips::NOR64; 1465 ZERO = Mips::ZERO_64; 1466 BEQ = Mips::BEQ64; 1467 } 1468 1469 unsigned OldVal = MI.getOperand(0).getReg(); 1470 unsigned Ptr = MI.getOperand(1).getReg(); 1471 unsigned Incr = MI.getOperand(2).getReg(); 1472 1473 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1474 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1475 unsigned Success = RegInfo.createVirtualRegister(RC); 1476 1477 // insert new blocks after the current block 1478 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1479 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1480 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1481 MachineFunction::iterator It = ++BB->getIterator(); 1482 MF->insert(It, loopMBB); 1483 MF->insert(It, exitMBB); 1484 1485 // Transfer the remainder of BB and its successor edges to exitMBB. 1486 exitMBB->splice(exitMBB->begin(), BB, 1487 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1488 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1489 1490 // thisMBB: 1491 // ... 1492 // fallthrough --> loopMBB 1493 BB->addSuccessor(loopMBB); 1494 loopMBB->addSuccessor(loopMBB); 1495 loopMBB->addSuccessor(exitMBB); 1496 1497 // loopMBB: 1498 // ll oldval, 0(ptr) 1499 // <binop> storeval, oldval, incr 1500 // sc success, storeval, 0(ptr) 1501 // beq success, $0, loopMBB 1502 BB = loopMBB; 1503 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1504 if (Nand) { 1505 // and andres, oldval, incr 1506 // nor storeval, $0, andres 1507 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1508 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1509 } else if (BinOpcode) { 1510 // <binop> storeval, oldval, incr 1511 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1512 } else { 1513 StoreVal = Incr; 1514 } 1515 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1516 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1517 1518 MI.eraseFromParent(); // The instruction is gone now. 1519 1520 return exitMBB; 1521 } 1522 1523 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( 1524 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, 1525 unsigned SrcReg) const { 1526 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1527 const DebugLoc &DL = MI.getDebugLoc(); 1528 1529 if (Subtarget.hasMips32r2() && Size == 1) { 1530 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); 1531 return BB; 1532 } 1533 1534 if (Subtarget.hasMips32r2() && Size == 2) { 1535 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); 1536 return BB; 1537 } 1538 1539 MachineFunction *MF = BB->getParent(); 1540 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1541 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1542 unsigned ScrReg = RegInfo.createVirtualRegister(RC); 1543 1544 assert(Size < 32); 1545 int64_t ShiftImm = 32 - (Size * 8); 1546 1547 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); 1548 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); 1549 1550 return BB; 1551 } 1552 1553 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( 1554 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 1555 bool Nand) const { 1556 assert((Size == 1 || Size == 2) && 1557 "Unsupported size for EmitAtomicBinaryPartial."); 1558 1559 MachineFunction *MF = BB->getParent(); 1560 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1561 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1562 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1563 const TargetRegisterClass *RCp = 1564 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1565 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1566 DebugLoc DL = MI.getDebugLoc(); 1567 1568 unsigned Dest = MI.getOperand(0).getReg(); 1569 unsigned Ptr = MI.getOperand(1).getReg(); 1570 unsigned Incr = MI.getOperand(2).getReg(); 1571 1572 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1573 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1574 unsigned Mask = RegInfo.createVirtualRegister(RC); 1575 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1576 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1577 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1578 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1579 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1580 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1581 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1582 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1583 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1584 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1585 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1586 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1587 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1588 unsigned Success = RegInfo.createVirtualRegister(RC); 1589 1590 unsigned LL, SC; 1591 if (isMicroMips) { 1592 LL = Mips::LL_MM; 1593 SC = Mips::SC_MM; 1594 } else { 1595 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1596 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1597 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1598 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1599 } 1600 1601 // insert new blocks after the current block 1602 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1603 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1604 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1605 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1606 MachineFunction::iterator It = ++BB->getIterator(); 1607 MF->insert(It, loopMBB); 1608 MF->insert(It, sinkMBB); 1609 MF->insert(It, exitMBB); 1610 1611 // Transfer the remainder of BB and its successor edges to exitMBB. 1612 exitMBB->splice(exitMBB->begin(), BB, 1613 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1614 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1615 1616 BB->addSuccessor(loopMBB); 1617 loopMBB->addSuccessor(loopMBB); 1618 loopMBB->addSuccessor(sinkMBB); 1619 sinkMBB->addSuccessor(exitMBB); 1620 1621 // thisMBB: 1622 // addiu masklsb2,$0,-4 # 0xfffffffc 1623 // and alignedaddr,ptr,masklsb2 1624 // andi ptrlsb2,ptr,3 1625 // sll shiftamt,ptrlsb2,3 1626 // ori maskupper,$0,255 # 0xff 1627 // sll mask,maskupper,shiftamt 1628 // nor mask2,$0,mask 1629 // sll incr2,incr,shiftamt 1630 1631 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1632 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2) 1633 .addReg(ABI.GetNullPtr()).addImm(-4); 1634 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) 1635 .addReg(Ptr).addReg(MaskLSB2); 1636 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1637 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1638 if (Subtarget.isLittle()) { 1639 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1640 } else { 1641 unsigned Off = RegInfo.createVirtualRegister(RC); 1642 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1643 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1644 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1645 } 1646 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1647 .addReg(Mips::ZERO).addImm(MaskImm); 1648 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1649 .addReg(MaskUpper).addReg(ShiftAmt); 1650 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1651 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1652 1653 // atomic.load.binop 1654 // loopMBB: 1655 // ll oldval,0(alignedaddr) 1656 // binop binopres,oldval,incr2 1657 // and newval,binopres,mask 1658 // and maskedoldval0,oldval,mask2 1659 // or storeval,maskedoldval0,newval 1660 // sc success,storeval,0(alignedaddr) 1661 // beq success,$0,loopMBB 1662 1663 // atomic.swap 1664 // loopMBB: 1665 // ll oldval,0(alignedaddr) 1666 // and newval,incr2,mask 1667 // and maskedoldval0,oldval,mask2 1668 // or storeval,maskedoldval0,newval 1669 // sc success,storeval,0(alignedaddr) 1670 // beq success,$0,loopMBB 1671 1672 BB = loopMBB; 1673 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1674 if (Nand) { 1675 // and andres, oldval, incr2 1676 // nor binopres, $0, andres 1677 // and newval, binopres, mask 1678 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1679 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes) 1680 .addReg(Mips::ZERO).addReg(AndRes); 1681 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1682 } else if (BinOpcode) { 1683 // <binop> binopres, oldval, incr2 1684 // and newval, binopres, mask 1685 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1686 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1687 } else { // atomic.swap 1688 // and newval, incr2, mask 1689 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1690 } 1691 1692 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1693 .addReg(OldVal).addReg(Mask2); 1694 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1695 .addReg(MaskedOldVal0).addReg(NewVal); 1696 BuildMI(BB, DL, TII->get(SC), Success) 1697 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1698 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1699 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1700 1701 // sinkMBB: 1702 // and maskedoldval1,oldval,mask 1703 // srl srlres,maskedoldval1,shiftamt 1704 // sign_extend dest,srlres 1705 BB = sinkMBB; 1706 1707 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1708 .addReg(OldVal).addReg(Mask); 1709 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1710 .addReg(MaskedOldVal1).addReg(ShiftAmt); 1711 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1712 1713 MI.eraseFromParent(); // The instruction is gone now. 1714 1715 return exitMBB; 1716 } 1717 1718 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, 1719 MachineBasicBlock *BB, 1720 unsigned Size) const { 1721 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1722 1723 MachineFunction *MF = BB->getParent(); 1724 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1725 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1726 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1727 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1728 DebugLoc DL = MI.getDebugLoc(); 1729 unsigned LL, SC, ZERO, BNE, BEQ; 1730 1731 if (Size == 4) { 1732 if (isMicroMips) { 1733 LL = Mips::LL_MM; 1734 SC = Mips::SC_MM; 1735 } else { 1736 LL = Subtarget.hasMips32r6() 1737 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1738 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1739 SC = Subtarget.hasMips32r6() 1740 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1741 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1742 } 1743 1744 ZERO = Mips::ZERO; 1745 BNE = Mips::BNE; 1746 BEQ = Mips::BEQ; 1747 } else { 1748 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1749 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1750 ZERO = Mips::ZERO_64; 1751 BNE = Mips::BNE64; 1752 BEQ = Mips::BEQ64; 1753 } 1754 1755 unsigned Dest = MI.getOperand(0).getReg(); 1756 unsigned Ptr = MI.getOperand(1).getReg(); 1757 unsigned OldVal = MI.getOperand(2).getReg(); 1758 unsigned NewVal = MI.getOperand(3).getReg(); 1759 1760 unsigned Success = RegInfo.createVirtualRegister(RC); 1761 1762 // insert new blocks after the current block 1763 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1764 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1765 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1766 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1767 MachineFunction::iterator It = ++BB->getIterator(); 1768 MF->insert(It, loop1MBB); 1769 MF->insert(It, loop2MBB); 1770 MF->insert(It, exitMBB); 1771 1772 // Transfer the remainder of BB and its successor edges to exitMBB. 1773 exitMBB->splice(exitMBB->begin(), BB, 1774 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1775 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1776 1777 // thisMBB: 1778 // ... 1779 // fallthrough --> loop1MBB 1780 BB->addSuccessor(loop1MBB); 1781 loop1MBB->addSuccessor(exitMBB); 1782 loop1MBB->addSuccessor(loop2MBB); 1783 loop2MBB->addSuccessor(loop1MBB); 1784 loop2MBB->addSuccessor(exitMBB); 1785 1786 // loop1MBB: 1787 // ll dest, 0(ptr) 1788 // bne dest, oldval, exitMBB 1789 BB = loop1MBB; 1790 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1791 BuildMI(BB, DL, TII->get(BNE)) 1792 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1793 1794 // loop2MBB: 1795 // sc success, newval, 0(ptr) 1796 // beq success, $0, loop1MBB 1797 BB = loop2MBB; 1798 BuildMI(BB, DL, TII->get(SC), Success) 1799 .addReg(NewVal).addReg(Ptr).addImm(0); 1800 BuildMI(BB, DL, TII->get(BEQ)) 1801 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1802 1803 MI.eraseFromParent(); // The instruction is gone now. 1804 1805 return exitMBB; 1806 } 1807 1808 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword( 1809 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1810 assert((Size == 1 || Size == 2) && 1811 "Unsupported size for EmitAtomicCmpSwapPartial."); 1812 1813 MachineFunction *MF = BB->getParent(); 1814 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1815 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1816 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1817 const TargetRegisterClass *RCp = 1818 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1819 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1820 DebugLoc DL = MI.getDebugLoc(); 1821 1822 unsigned Dest = MI.getOperand(0).getReg(); 1823 unsigned Ptr = MI.getOperand(1).getReg(); 1824 unsigned CmpVal = MI.getOperand(2).getReg(); 1825 unsigned NewVal = MI.getOperand(3).getReg(); 1826 1827 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1828 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1829 unsigned Mask = RegInfo.createVirtualRegister(RC); 1830 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1831 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1832 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1833 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1834 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1835 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1836 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1837 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1838 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1839 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1840 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1841 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1842 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1843 unsigned Success = RegInfo.createVirtualRegister(RC); 1844 unsigned LL, SC; 1845 1846 if (isMicroMips) { 1847 LL = Mips::LL_MM; 1848 SC = Mips::SC_MM; 1849 } else { 1850 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1851 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1852 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1853 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1854 } 1855 1856 // insert new blocks after the current block 1857 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1858 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1859 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1860 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1861 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1862 MachineFunction::iterator It = ++BB->getIterator(); 1863 MF->insert(It, loop1MBB); 1864 MF->insert(It, loop2MBB); 1865 MF->insert(It, sinkMBB); 1866 MF->insert(It, exitMBB); 1867 1868 // Transfer the remainder of BB and its successor edges to exitMBB. 1869 exitMBB->splice(exitMBB->begin(), BB, 1870 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1871 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1872 1873 BB->addSuccessor(loop1MBB); 1874 loop1MBB->addSuccessor(sinkMBB); 1875 loop1MBB->addSuccessor(loop2MBB); 1876 loop2MBB->addSuccessor(loop1MBB); 1877 loop2MBB->addSuccessor(sinkMBB); 1878 sinkMBB->addSuccessor(exitMBB); 1879 1880 // FIXME: computation of newval2 can be moved to loop2MBB. 1881 // thisMBB: 1882 // addiu masklsb2,$0,-4 # 0xfffffffc 1883 // and alignedaddr,ptr,masklsb2 1884 // andi ptrlsb2,ptr,3 1885 // xori ptrlsb2,ptrlsb2,3 # Only for BE 1886 // sll shiftamt,ptrlsb2,3 1887 // ori maskupper,$0,255 # 0xff 1888 // sll mask,maskupper,shiftamt 1889 // nor mask2,$0,mask 1890 // andi maskedcmpval,cmpval,255 1891 // sll shiftedcmpval,maskedcmpval,shiftamt 1892 // andi maskednewval,newval,255 1893 // sll shiftednewval,maskednewval,shiftamt 1894 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1895 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) 1896 .addReg(ABI.GetNullPtr()).addImm(-4); 1897 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) 1898 .addReg(Ptr).addReg(MaskLSB2); 1899 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1900 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1901 if (Subtarget.isLittle()) { 1902 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1903 } else { 1904 unsigned Off = RegInfo.createVirtualRegister(RC); 1905 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1906 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1907 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1908 } 1909 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1910 .addReg(Mips::ZERO).addImm(MaskImm); 1911 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1912 .addReg(MaskUpper).addReg(ShiftAmt); 1913 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1914 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1915 .addReg(CmpVal).addImm(MaskImm); 1916 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1917 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1918 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1919 .addReg(NewVal).addImm(MaskImm); 1920 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1921 .addReg(MaskedNewVal).addReg(ShiftAmt); 1922 1923 // loop1MBB: 1924 // ll oldval,0(alginedaddr) 1925 // and maskedoldval0,oldval,mask 1926 // bne maskedoldval0,shiftedcmpval,sinkMBB 1927 BB = loop1MBB; 1928 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1929 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1930 .addReg(OldVal).addReg(Mask); 1931 BuildMI(BB, DL, TII->get(Mips::BNE)) 1932 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1933 1934 // loop2MBB: 1935 // and maskedoldval1,oldval,mask2 1936 // or storeval,maskedoldval1,shiftednewval 1937 // sc success,storeval,0(alignedaddr) 1938 // beq success,$0,loop1MBB 1939 BB = loop2MBB; 1940 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1941 .addReg(OldVal).addReg(Mask2); 1942 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1943 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1944 BuildMI(BB, DL, TII->get(SC), Success) 1945 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1946 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1947 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1948 1949 // sinkMBB: 1950 // srl srlres,maskedoldval0,shiftamt 1951 // sign_extend dest,srlres 1952 BB = sinkMBB; 1953 1954 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1955 .addReg(MaskedOldVal0).addReg(ShiftAmt); 1956 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1957 1958 MI.eraseFromParent(); // The instruction is gone now. 1959 1960 return exitMBB; 1961 } 1962 1963 MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr &MI, 1964 MachineBasicBlock *BB) const { 1965 MachineFunction *MF = BB->getParent(); 1966 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 1967 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1968 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1969 DebugLoc DL = MI.getDebugLoc(); 1970 MachineBasicBlock::iterator II(MI); 1971 1972 unsigned Fc = MI.getOperand(1).getReg(); 1973 const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID); 1974 1975 unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass); 1976 1977 BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2) 1978 .addImm(0) 1979 .addReg(Fc) 1980 .addImm(Mips::sub_lo); 1981 1982 // We don't erase the original instruction, we just replace the condition 1983 // register with the 64-bit super-register. 1984 MI.getOperand(1).setReg(Fc2); 1985 1986 return BB; 1987 } 1988 1989 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 1990 // The first operand is the chain, the second is the condition, the third is 1991 // the block to branch to if the condition is true. 1992 SDValue Chain = Op.getOperand(0); 1993 SDValue Dest = Op.getOperand(2); 1994 SDLoc DL(Op); 1995 1996 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1997 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1998 1999 // Return if flag is not set by a floating point comparison. 2000 if (CondRes.getOpcode() != MipsISD::FPCmp) 2001 return Op; 2002 2003 SDValue CCNode = CondRes.getOperand(2); 2004 Mips::CondCode CC = 2005 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 2006 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 2007 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); 2008 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 2009 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 2010 FCC0, Dest, CondRes); 2011 } 2012 2013 SDValue MipsTargetLowering:: 2014 lowerSELECT(SDValue Op, SelectionDAG &DAG) const 2015 { 2016 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 2017 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 2018 2019 // Return if flag is not set by a floating point comparison. 2020 if (Cond.getOpcode() != MipsISD::FPCmp) 2021 return Op; 2022 2023 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 2024 SDLoc(Op)); 2025 } 2026 2027 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 2028 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 2029 SDValue Cond = createFPCmp(DAG, Op); 2030 2031 assert(Cond.getOpcode() == MipsISD::FPCmp && 2032 "Floating point operand expected."); 2033 2034 SDLoc DL(Op); 2035 SDValue True = DAG.getConstant(1, DL, MVT::i32); 2036 SDValue False = DAG.getConstant(0, DL, MVT::i32); 2037 2038 return createCMovFP(DAG, Cond, True, False, DL); 2039 } 2040 2041 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 2042 SelectionDAG &DAG) const { 2043 EVT Ty = Op.getValueType(); 2044 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 2045 const GlobalValue *GV = N->getGlobal(); 2046 2047 if (!isPositionIndependent()) { 2048 const MipsTargetObjectFile *TLOF = 2049 static_cast<const MipsTargetObjectFile *>( 2050 getTargetMachine().getObjFileLowering()); 2051 const GlobalObject *GO = GV->getBaseObject(); 2052 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) 2053 // %gp_rel relocation 2054 return getAddrGPRel(N, SDLoc(N), Ty, DAG); 2055 2056 // %hi/%lo relocation 2057 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2058 // %highest/%higher/%hi/%lo relocation 2059 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2060 } 2061 2062 // Every other architecture would use shouldAssumeDSOLocal in here, but 2063 // mips is special. 2064 // * In PIC code mips requires got loads even for local statics! 2065 // * To save on got entries, for local statics the got entry contains the 2066 // page and an additional add instruction takes care of the low bits. 2067 // * It is legal to access a hidden symbol with a non hidden undefined, 2068 // so one cannot guarantee that all access to a hidden symbol will know 2069 // it is hidden. 2070 // * Mips linkers don't support creating a page and a full got entry for 2071 // the same symbol. 2072 // * Given all that, we have to use a full got entry for hidden symbols :-( 2073 if (GV->hasLocalLinkage()) 2074 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2075 2076 if (LargeGOT) 2077 return getAddrGlobalLargeGOT( 2078 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, 2079 DAG.getEntryNode(), 2080 MachinePointerInfo::getGOT(DAG.getMachineFunction())); 2081 2082 return getAddrGlobal( 2083 N, SDLoc(N), Ty, DAG, 2084 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT, 2085 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); 2086 } 2087 2088 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 2089 SelectionDAG &DAG) const { 2090 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 2091 EVT Ty = Op.getValueType(); 2092 2093 if (!isPositionIndependent()) 2094 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2095 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2096 2097 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2098 } 2099 2100 SDValue MipsTargetLowering:: 2101 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 2102 { 2103 // If the relocation model is PIC, use the General Dynamic TLS Model or 2104 // Local Dynamic TLS model, otherwise use the Initial Exec or 2105 // Local Exec TLS Model. 2106 2107 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2108 if (DAG.getTarget().Options.EmulatedTLS) 2109 return LowerToTLSEmulatedModel(GA, DAG); 2110 2111 SDLoc DL(GA); 2112 const GlobalValue *GV = GA->getGlobal(); 2113 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 2114 2115 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 2116 2117 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 2118 // General Dynamic and Local Dynamic TLS Model. 2119 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 2120 : MipsII::MO_TLSGD; 2121 2122 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 2123 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 2124 getGlobalReg(DAG, PtrVT), TGA); 2125 unsigned PtrSize = PtrVT.getSizeInBits(); 2126 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 2127 2128 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 2129 2130 ArgListTy Args; 2131 ArgListEntry Entry; 2132 Entry.Node = Argument; 2133 Entry.Ty = PtrTy; 2134 Args.push_back(Entry); 2135 2136 TargetLowering::CallLoweringInfo CLI(DAG); 2137 CLI.setDebugLoc(DL) 2138 .setChain(DAG.getEntryNode()) 2139 .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); 2140 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 2141 2142 SDValue Ret = CallResult.first; 2143 2144 if (model != TLSModel::LocalDynamic) 2145 return Ret; 2146 2147 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2148 MipsII::MO_DTPREL_HI); 2149 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 2150 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2151 MipsII::MO_DTPREL_LO); 2152 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2153 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 2154 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 2155 } 2156 2157 SDValue Offset; 2158 if (model == TLSModel::InitialExec) { 2159 // Initial Exec TLS Model 2160 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2161 MipsII::MO_GOTTPREL); 2162 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 2163 TGA); 2164 Offset = 2165 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo()); 2166 } else { 2167 // Local Exec TLS Model 2168 assert(model == TLSModel::LocalExec); 2169 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2170 MipsII::MO_TPREL_HI); 2171 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2172 MipsII::MO_TPREL_LO); 2173 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 2174 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2175 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 2176 } 2177 2178 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 2179 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 2180 } 2181 2182 SDValue MipsTargetLowering:: 2183 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 2184 { 2185 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 2186 EVT Ty = Op.getValueType(); 2187 2188 if (!isPositionIndependent()) 2189 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2190 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2191 2192 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2193 } 2194 2195 SDValue MipsTargetLowering:: 2196 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 2197 { 2198 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 2199 EVT Ty = Op.getValueType(); 2200 2201 if (!isPositionIndependent()) { 2202 const MipsTargetObjectFile *TLOF = 2203 static_cast<const MipsTargetObjectFile *>( 2204 getTargetMachine().getObjFileLowering()); 2205 2206 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), 2207 getTargetMachine())) 2208 // %gp_rel relocation 2209 return getAddrGPRel(N, SDLoc(N), Ty, DAG); 2210 2211 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2212 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2213 } 2214 2215 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2216 } 2217 2218 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 2219 MachineFunction &MF = DAG.getMachineFunction(); 2220 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2221 2222 SDLoc DL(Op); 2223 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 2224 getPointerTy(MF.getDataLayout())); 2225 2226 // vastart just stores the address of the VarArgsFrameIndex slot into the 2227 // memory location argument. 2228 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2229 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 2230 MachinePointerInfo(SV)); 2231 } 2232 2233 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { 2234 SDNode *Node = Op.getNode(); 2235 EVT VT = Node->getValueType(0); 2236 SDValue Chain = Node->getOperand(0); 2237 SDValue VAListPtr = Node->getOperand(1); 2238 unsigned Align = Node->getConstantOperandVal(3); 2239 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2240 SDLoc DL(Node); 2241 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4; 2242 2243 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, 2244 VAListPtr, MachinePointerInfo(SV)); 2245 SDValue VAList = VAListLoad; 2246 2247 // Re-align the pointer if necessary. 2248 // It should only ever be necessary for 64-bit types on O32 since the minimum 2249 // argument alignment is the same as the maximum type alignment for N32/N64. 2250 // 2251 // FIXME: We currently align too often. The code generator doesn't notice 2252 // when the pointer is still aligned from the last va_arg (or pair of 2253 // va_args for the i64 on O32 case). 2254 if (Align > getMinStackArgumentAlignment()) { 2255 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 2256 2257 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 2258 DAG.getConstant(Align - 1, DL, VAList.getValueType())); 2259 2260 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList, 2261 DAG.getConstant(-(int64_t)Align, DL, 2262 VAList.getValueType())); 2263 } 2264 2265 // Increment the pointer, VAList, to the next vaarg. 2266 auto &TD = DAG.getDataLayout(); 2267 unsigned ArgSizeInBytes = 2268 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); 2269 SDValue Tmp3 = 2270 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 2271 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes), 2272 DL, VAList.getValueType())); 2273 // Store the incremented VAList to the legalized pointer 2274 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, 2275 MachinePointerInfo(SV)); 2276 2277 // In big-endian mode we must adjust the pointer when the load size is smaller 2278 // than the argument slot size. We must also reduce the known alignment to 2279 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get 2280 // the correct half of the slot, and reduce the alignment from 8 (slot 2281 // alignment) down to 4 (type alignment). 2282 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { 2283 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; 2284 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, 2285 DAG.getIntPtrConstant(Adjustment, DL)); 2286 } 2287 // Load the actual argument out of the pointer VAList 2288 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo()); 2289 } 2290 2291 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 2292 bool HasExtractInsert) { 2293 EVT TyX = Op.getOperand(0).getValueType(); 2294 EVT TyY = Op.getOperand(1).getValueType(); 2295 SDLoc DL(Op); 2296 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2297 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32); 2298 SDValue Res; 2299 2300 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2301 // to i32. 2302 SDValue X = (TyX == MVT::f32) ? 2303 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2304 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2305 Const1); 2306 SDValue Y = (TyY == MVT::f32) ? 2307 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 2308 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 2309 Const1); 2310 2311 if (HasExtractInsert) { 2312 // ext E, Y, 31, 1 ; extract bit31 of Y 2313 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 2314 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 2315 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 2316 } else { 2317 // sll SllX, X, 1 2318 // srl SrlX, SllX, 1 2319 // srl SrlY, Y, 31 2320 // sll SllY, SrlX, 31 2321 // or Or, SrlX, SllY 2322 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2323 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2324 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2325 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 2326 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2327 } 2328 2329 if (TyX == MVT::f32) 2330 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2331 2332 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2333 Op.getOperand(0), 2334 DAG.getConstant(0, DL, MVT::i32)); 2335 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2336 } 2337 2338 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 2339 bool HasExtractInsert) { 2340 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2341 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2342 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2343 SDLoc DL(Op); 2344 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2345 2346 // Bitcast to integer nodes. 2347 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2348 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2349 2350 if (HasExtractInsert) { 2351 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2352 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2353 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2354 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); 2355 2356 if (WidthX > WidthY) 2357 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2358 else if (WidthY > WidthX) 2359 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2360 2361 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2362 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, 2363 X); 2364 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2365 } 2366 2367 // (d)sll SllX, X, 1 2368 // (d)srl SrlX, SllX, 1 2369 // (d)srl SrlY, Y, width(Y)-1 2370 // (d)sll SllY, SrlX, width(Y)-1 2371 // or Or, SrlX, SllY 2372 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2373 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2374 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2375 DAG.getConstant(WidthY - 1, DL, MVT::i32)); 2376 2377 if (WidthX > WidthY) 2378 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2379 else if (WidthY > WidthX) 2380 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2381 2382 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2383 DAG.getConstant(WidthX - 1, DL, MVT::i32)); 2384 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2385 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2386 } 2387 2388 SDValue 2389 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2390 if (Subtarget.isGP64bit()) 2391 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); 2392 2393 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); 2394 } 2395 2396 SDValue MipsTargetLowering:: 2397 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2398 // check the depth 2399 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2400 "Frame address can only be determined for current frame."); 2401 2402 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2403 MFI.setFrameAddressIsTaken(true); 2404 EVT VT = Op.getValueType(); 2405 SDLoc DL(Op); 2406 SDValue FrameAddr = DAG.getCopyFromReg( 2407 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); 2408 return FrameAddr; 2409 } 2410 2411 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 2412 SelectionDAG &DAG) const { 2413 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 2414 return SDValue(); 2415 2416 // check the depth 2417 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2418 "Return address can be determined only for current frame."); 2419 2420 MachineFunction &MF = DAG.getMachineFunction(); 2421 MachineFrameInfo &MFI = MF.getFrameInfo(); 2422 MVT VT = Op.getSimpleValueType(); 2423 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; 2424 MFI.setReturnAddressIsTaken(true); 2425 2426 // Return RA, which contains the return address. Mark it an implicit live-in. 2427 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2428 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 2429 } 2430 2431 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is 2432 // generated from __builtin_eh_return (offset, handler) 2433 // The effect of this is to adjust the stack pointer by "offset" 2434 // and then branch to "handler". 2435 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 2436 const { 2437 MachineFunction &MF = DAG.getMachineFunction(); 2438 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2439 2440 MipsFI->setCallsEhReturn(); 2441 SDValue Chain = Op.getOperand(0); 2442 SDValue Offset = Op.getOperand(1); 2443 SDValue Handler = Op.getOperand(2); 2444 SDLoc DL(Op); 2445 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2446 2447 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2448 // EH_RETURN nodes, so that instructions are emitted back-to-back. 2449 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; 2450 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 2451 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 2452 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 2453 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 2454 DAG.getRegister(OffsetReg, Ty), 2455 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), 2456 Chain.getValue(1)); 2457 } 2458 2459 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 2460 SelectionDAG &DAG) const { 2461 // FIXME: Need pseudo-fence for 'singlethread' fences 2462 // FIXME: Set SType for weaker fences where supported/appropriate. 2463 unsigned SType = 0; 2464 SDLoc DL(Op); 2465 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 2466 DAG.getConstant(SType, DL, MVT::i32)); 2467 } 2468 2469 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 2470 SelectionDAG &DAG) const { 2471 SDLoc DL(Op); 2472 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2473 2474 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2475 SDValue Shamt = Op.getOperand(2); 2476 // if shamt < (VT.bits): 2477 // lo = (shl lo, shamt) 2478 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2479 // else: 2480 // lo = 0 2481 // hi = (shl lo, shamt[4:0]) 2482 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2483 DAG.getConstant(-1, DL, MVT::i32)); 2484 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, 2485 DAG.getConstant(1, DL, VT)); 2486 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); 2487 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); 2488 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2489 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); 2490 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2491 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2492 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2493 DAG.getConstant(0, DL, VT), ShiftLeftLo); 2494 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); 2495 2496 SDValue Ops[2] = {Lo, Hi}; 2497 return DAG.getMergeValues(Ops, DL); 2498 } 2499 2500 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2501 bool IsSRA) const { 2502 SDLoc DL(Op); 2503 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2504 SDValue Shamt = Op.getOperand(2); 2505 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2506 2507 // if shamt < (VT.bits): 2508 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2509 // if isSRA: 2510 // hi = (sra hi, shamt) 2511 // else: 2512 // hi = (srl hi, shamt) 2513 // else: 2514 // if isSRA: 2515 // lo = (sra hi, shamt[4:0]) 2516 // hi = (sra hi, 31) 2517 // else: 2518 // lo = (srl hi, shamt[4:0]) 2519 // hi = 0 2520 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2521 DAG.getConstant(-1, DL, MVT::i32)); 2522 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, 2523 DAG.getConstant(1, DL, VT)); 2524 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); 2525 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); 2526 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2527 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, 2528 DL, VT, Hi, Shamt); 2529 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2530 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2531 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, 2532 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); 2533 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); 2534 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2535 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); 2536 2537 SDValue Ops[2] = {Lo, Hi}; 2538 return DAG.getMergeValues(Ops, DL); 2539 } 2540 2541 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2542 SDValue Chain, SDValue Src, unsigned Offset) { 2543 SDValue Ptr = LD->getBasePtr(); 2544 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2545 EVT BasePtrVT = Ptr.getValueType(); 2546 SDLoc DL(LD); 2547 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2548 2549 if (Offset) 2550 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2551 DAG.getConstant(Offset, DL, BasePtrVT)); 2552 2553 SDValue Ops[] = { Chain, Ptr, Src }; 2554 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2555 LD->getMemOperand()); 2556 } 2557 2558 // Expand an unaligned 32 or 64-bit integer load node. 2559 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2560 LoadSDNode *LD = cast<LoadSDNode>(Op); 2561 EVT MemVT = LD->getMemoryVT(); 2562 2563 if (Subtarget.systemSupportsUnalignedAccess()) 2564 return Op; 2565 2566 // Return if load is aligned or if MemVT is neither i32 nor i64. 2567 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2568 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2569 return SDValue(); 2570 2571 bool IsLittle = Subtarget.isLittle(); 2572 EVT VT = Op.getValueType(); 2573 ISD::LoadExtType ExtType = LD->getExtensionType(); 2574 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2575 2576 assert((VT == MVT::i32) || (VT == MVT::i64)); 2577 2578 // Expand 2579 // (set dst, (i64 (load baseptr))) 2580 // to 2581 // (set tmp, (ldl (add baseptr, 7), undef)) 2582 // (set dst, (ldr baseptr, tmp)) 2583 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2584 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2585 IsLittle ? 7 : 0); 2586 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2587 IsLittle ? 0 : 7); 2588 } 2589 2590 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2591 IsLittle ? 3 : 0); 2592 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2593 IsLittle ? 0 : 3); 2594 2595 // Expand 2596 // (set dst, (i32 (load baseptr))) or 2597 // (set dst, (i64 (sextload baseptr))) or 2598 // (set dst, (i64 (extload baseptr))) 2599 // to 2600 // (set tmp, (lwl (add baseptr, 3), undef)) 2601 // (set dst, (lwr baseptr, tmp)) 2602 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2603 (ExtType == ISD::EXTLOAD)) 2604 return LWR; 2605 2606 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2607 2608 // Expand 2609 // (set dst, (i64 (zextload baseptr))) 2610 // to 2611 // (set tmp0, (lwl (add baseptr, 3), undef)) 2612 // (set tmp1, (lwr baseptr, tmp0)) 2613 // (set tmp2, (shl tmp1, 32)) 2614 // (set dst, (srl tmp2, 32)) 2615 SDLoc DL(LD); 2616 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32); 2617 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2618 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2619 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2620 return DAG.getMergeValues(Ops, DL); 2621 } 2622 2623 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2624 SDValue Chain, unsigned Offset) { 2625 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2626 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2627 SDLoc DL(SD); 2628 SDVTList VTList = DAG.getVTList(MVT::Other); 2629 2630 if (Offset) 2631 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2632 DAG.getConstant(Offset, DL, BasePtrVT)); 2633 2634 SDValue Ops[] = { Chain, Value, Ptr }; 2635 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2636 SD->getMemOperand()); 2637 } 2638 2639 // Expand an unaligned 32 or 64-bit integer store node. 2640 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2641 bool IsLittle) { 2642 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2643 EVT VT = Value.getValueType(); 2644 2645 // Expand 2646 // (store val, baseptr) or 2647 // (truncstore val, baseptr) 2648 // to 2649 // (swl val, (add baseptr, 3)) 2650 // (swr val, baseptr) 2651 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2652 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2653 IsLittle ? 3 : 0); 2654 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2655 } 2656 2657 assert(VT == MVT::i64); 2658 2659 // Expand 2660 // (store val, baseptr) 2661 // to 2662 // (sdl val, (add baseptr, 7)) 2663 // (sdr val, baseptr) 2664 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2665 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2666 } 2667 2668 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2669 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) { 2670 SDValue Val = SD->getValue(); 2671 2672 if (Val.getOpcode() != ISD::FP_TO_SINT) 2673 return SDValue(); 2674 2675 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2676 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2677 Val.getOperand(0)); 2678 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2679 SD->getPointerInfo(), SD->getAlignment(), 2680 SD->getMemOperand()->getFlags()); 2681 } 2682 2683 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2684 StoreSDNode *SD = cast<StoreSDNode>(Op); 2685 EVT MemVT = SD->getMemoryVT(); 2686 2687 // Lower unaligned integer stores. 2688 if (!Subtarget.systemSupportsUnalignedAccess() && 2689 (SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2690 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2691 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); 2692 2693 return lowerFP_TO_SINT_STORE(SD, DAG); 2694 } 2695 2696 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op, 2697 SelectionDAG &DAG) const { 2698 2699 // Return a fixed StackObject with offset 0 which points to the old stack 2700 // pointer. 2701 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2702 EVT ValTy = Op->getValueType(0); 2703 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2704 return DAG.getFrameIndex(FI, ValTy); 2705 } 2706 2707 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2708 SelectionDAG &DAG) const { 2709 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2710 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2711 Op.getOperand(0)); 2712 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2713 } 2714 2715 //===----------------------------------------------------------------------===// 2716 // Calling Convention Implementation 2717 //===----------------------------------------------------------------------===// 2718 2719 //===----------------------------------------------------------------------===// 2720 // TODO: Implement a generic logic using tblgen that can support this. 2721 // Mips O32 ABI rules: 2722 // --- 2723 // i32 - Passed in A0, A1, A2, A3 and stack 2724 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 2725 // an argument. Otherwise, passed in A1, A2, A3 and stack. 2726 // f64 - Only passed in two aliased f32 registers if no int reg has been used 2727 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2728 // not used, it must be shadowed. If only A3 is available, shadow it and 2729 // go to stack. 2730 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack. 2731 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3} 2732 // with the remainder spilled to the stack. 2733 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases 2734 // spilling the remainder to the stack. 2735 // 2736 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2737 //===----------------------------------------------------------------------===// 2738 2739 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2740 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2741 CCState &State, ArrayRef<MCPhysReg> F64Regs) { 2742 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( 2743 State.getMachineFunction().getSubtarget()); 2744 2745 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2746 2747 const MipsCCState * MipsState = static_cast<MipsCCState *>(&State); 2748 2749 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 }; 2750 2751 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 }; 2752 2753 // Do not process byval args here. 2754 if (ArgFlags.isByVal()) 2755 return true; 2756 2757 // Promote i8 and i16 2758 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { 2759 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) { 2760 LocVT = MVT::i32; 2761 if (ArgFlags.isSExt()) 2762 LocInfo = CCValAssign::SExtUpper; 2763 else if (ArgFlags.isZExt()) 2764 LocInfo = CCValAssign::ZExtUpper; 2765 else 2766 LocInfo = CCValAssign::AExtUpper; 2767 } 2768 } 2769 2770 // Promote i8 and i16 2771 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2772 LocVT = MVT::i32; 2773 if (ArgFlags.isSExt()) 2774 LocInfo = CCValAssign::SExt; 2775 else if (ArgFlags.isZExt()) 2776 LocInfo = CCValAssign::ZExt; 2777 else 2778 LocInfo = CCValAssign::AExt; 2779 } 2780 2781 unsigned Reg; 2782 2783 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2784 // is true: function is vararg, argument is 3rd or higher, there is previous 2785 // argument which is not f32 or f64. 2786 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 || 2787 State.getFirstUnallocated(F32Regs) != ValNo; 2788 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2789 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2790 bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo); 2791 2792 // The MIPS vector ABI for floats passes them in a pair of registers 2793 if (ValVT == MVT::i32 && isVectorFloat) { 2794 // This is the start of an vector that was scalarized into an unknown number 2795 // of components. It doesn't matter how many there are. Allocate one of the 2796 // notional 8 byte aligned registers which map onto the argument stack, and 2797 // shadow the register lost to alignment requirements. 2798 if (ArgFlags.isSplit()) { 2799 Reg = State.AllocateReg(FloatVectorIntRegs); 2800 if (Reg == Mips::A2) 2801 State.AllocateReg(Mips::A1); 2802 else if (Reg == 0) 2803 State.AllocateReg(Mips::A3); 2804 } else { 2805 // If we're an intermediate component of the split, we can just attempt to 2806 // allocate a register directly. 2807 Reg = State.AllocateReg(IntRegs); 2808 } 2809 } else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2810 Reg = State.AllocateReg(IntRegs); 2811 // If this is the first part of an i64 arg, 2812 // the allocated register must be either A0 or A2. 2813 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2814 Reg = State.AllocateReg(IntRegs); 2815 LocVT = MVT::i32; 2816 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2817 // Allocate int register and shadow next int register. If first 2818 // available register is Mips::A1 or Mips::A3, shadow it too. 2819 Reg = State.AllocateReg(IntRegs); 2820 if (Reg == Mips::A1 || Reg == Mips::A3) 2821 Reg = State.AllocateReg(IntRegs); 2822 State.AllocateReg(IntRegs); 2823 LocVT = MVT::i32; 2824 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2825 // we are guaranteed to find an available float register 2826 if (ValVT == MVT::f32) { 2827 Reg = State.AllocateReg(F32Regs); 2828 // Shadow int register 2829 State.AllocateReg(IntRegs); 2830 } else { 2831 Reg = State.AllocateReg(F64Regs); 2832 // Shadow int registers 2833 unsigned Reg2 = State.AllocateReg(IntRegs); 2834 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2835 State.AllocateReg(IntRegs); 2836 State.AllocateReg(IntRegs); 2837 } 2838 } else 2839 llvm_unreachable("Cannot handle this ValVT."); 2840 2841 if (!Reg) { 2842 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 2843 OrigAlign); 2844 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2845 } else 2846 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2847 2848 return false; 2849 } 2850 2851 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2852 MVT LocVT, CCValAssign::LocInfo LocInfo, 2853 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2854 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 }; 2855 2856 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2857 } 2858 2859 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2860 MVT LocVT, CCValAssign::LocInfo LocInfo, 2861 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2862 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 2863 2864 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2865 } 2866 2867 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2868 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2869 CCState &State) LLVM_ATTRIBUTE_UNUSED; 2870 2871 #include "MipsGenCallingConv.inc" 2872 2873 //===----------------------------------------------------------------------===// 2874 // Call Calling Convention Implementation 2875 //===----------------------------------------------------------------------===// 2876 2877 // Return next O32 integer argument register. 2878 static unsigned getNextIntArgReg(unsigned Reg) { 2879 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2880 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2881 } 2882 2883 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2884 SDValue Chain, SDValue Arg, 2885 const SDLoc &DL, bool IsTailCall, 2886 SelectionDAG &DAG) const { 2887 if (!IsTailCall) { 2888 SDValue PtrOff = 2889 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr, 2890 DAG.getIntPtrConstant(Offset, DL)); 2891 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()); 2892 } 2893 2894 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2895 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2896 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 2897 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2898 /* Alignment = */ 0, MachineMemOperand::MOVolatile); 2899 } 2900 2901 void MipsTargetLowering:: 2902 getOpndList(SmallVectorImpl<SDValue> &Ops, 2903 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 2904 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2905 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 2906 SDValue Chain) const { 2907 // Insert node "GP copy globalreg" before call to function. 2908 // 2909 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2910 // in PIC mode) allow symbols to be resolved via lazy binding. 2911 // The lazy binding stub requires GP to point to the GOT. 2912 // Note that we don't need GP to point to the GOT for indirect calls 2913 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates 2914 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs 2915 // used for the function (that is, Mips linker doesn't generate lazy binding 2916 // stub for a function whose address is taken in the program). 2917 if (IsPICCall && !InternalLinkage && IsCallReloc) { 2918 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP; 2919 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2920 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2921 } 2922 2923 // Build a sequence of copy-to-reg nodes chained together with token 2924 // chain and flag operands which copy the outgoing args into registers. 2925 // The InFlag in necessary since all emitted instructions must be 2926 // stuck together. 2927 SDValue InFlag; 2928 2929 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2930 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2931 RegsToPass[i].second, InFlag); 2932 InFlag = Chain.getValue(1); 2933 } 2934 2935 // Add argument registers to the end of the list so that they are 2936 // known live into the call. 2937 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2938 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2939 RegsToPass[i].second.getValueType())); 2940 2941 // Add a register mask operand representing the call-preserved registers. 2942 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 2943 const uint32_t *Mask = 2944 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv); 2945 assert(Mask && "Missing call preserved mask for calling convention"); 2946 if (Subtarget.inMips16HardFloat()) { 2947 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2948 llvm::StringRef Sym = G->getGlobal()->getName(); 2949 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2950 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 2951 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2952 } 2953 } 2954 } 2955 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2956 2957 if (InFlag.getNode()) 2958 Ops.push_back(InFlag); 2959 } 2960 2961 /// LowerCall - functions arguments are copied from virtual regs to 2962 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2963 SDValue 2964 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2965 SmallVectorImpl<SDValue> &InVals) const { 2966 SelectionDAG &DAG = CLI.DAG; 2967 SDLoc DL = CLI.DL; 2968 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2969 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2970 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2971 SDValue Chain = CLI.Chain; 2972 SDValue Callee = CLI.Callee; 2973 bool &IsTailCall = CLI.IsTailCall; 2974 CallingConv::ID CallConv = CLI.CallConv; 2975 bool IsVarArg = CLI.IsVarArg; 2976 2977 MachineFunction &MF = DAG.getMachineFunction(); 2978 MachineFrameInfo &MFI = MF.getFrameInfo(); 2979 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 2980 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2981 bool IsPIC = isPositionIndependent(); 2982 2983 // Analyze operands of the call, assigning locations to each operand. 2984 SmallVector<CCValAssign, 16> ArgLocs; 2985 MipsCCState CCInfo( 2986 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), 2987 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); 2988 2989 // Allocate the reserved argument area. It seems strange to do this from the 2990 // caller side but removing it breaks the frame size calculation. 2991 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 2992 2993 const ExternalSymbolSDNode *ES = 2994 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode()); 2995 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), 2996 ES ? ES->getSymbol() : nullptr); 2997 2998 // Get a count of how many bytes are to be pushed on the stack. 2999 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 3000 3001 // Check if it's really possible to do a tail call. Restrict it to functions 3002 // that are part of this compilation unit. 3003 bool InternalLinkage = false; 3004 if (IsTailCall) { 3005 IsTailCall = isEligibleForTailCallOptimization( 3006 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>()); 3007 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3008 InternalLinkage = G->getGlobal()->hasInternalLinkage(); 3009 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() || 3010 G->getGlobal()->hasPrivateLinkage() || 3011 G->getGlobal()->hasHiddenVisibility() || 3012 G->getGlobal()->hasProtectedVisibility()); 3013 } 3014 } 3015 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall()) 3016 report_fatal_error("failed to perform tail call elimination on a call " 3017 "site marked musttail"); 3018 3019 if (IsTailCall) 3020 ++NumTailCalls; 3021 3022 // Chain is the output chain of the last Load/Store or CopyToReg node. 3023 // ByValChain is the output chain of the last Memcpy node created for copying 3024 // byval arguments to the stack. 3025 unsigned StackAlignment = TFL->getStackAlignment(); 3026 NextStackOffset = alignTo(NextStackOffset, StackAlignment); 3027 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); 3028 3029 if (!IsTailCall) 3030 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL); 3031 3032 SDValue StackPtr = 3033 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, 3034 getPointerTy(DAG.getDataLayout())); 3035 3036 std::deque< std::pair<unsigned, SDValue> > RegsToPass; 3037 SmallVector<SDValue, 8> MemOpChains; 3038 3039 CCInfo.rewindByValRegsInfo(); 3040 3041 // Walk the register/memloc assignments, inserting copies/loads. 3042 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3043 SDValue Arg = OutVals[i]; 3044 CCValAssign &VA = ArgLocs[i]; 3045 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 3046 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3047 bool UseUpperBits = false; 3048 3049 // ByVal Arg. 3050 if (Flags.isByVal()) { 3051 unsigned FirstByValReg, LastByValReg; 3052 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3053 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3054 3055 assert(Flags.getByValSize() && 3056 "ByVal args of size 0 should have been ignored by front-end."); 3057 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3058 assert(!IsTailCall && 3059 "Do not tail-call optimize if there is a byval argument."); 3060 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 3061 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), 3062 VA); 3063 CCInfo.nextInRegsParam(); 3064 continue; 3065 } 3066 3067 // Promote the value if needed. 3068 switch (VA.getLocInfo()) { 3069 default: 3070 llvm_unreachable("Unknown loc info!"); 3071 case CCValAssign::Full: 3072 if (VA.isRegLoc()) { 3073 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 3074 (ValVT == MVT::f64 && LocVT == MVT::i64) || 3075 (ValVT == MVT::i64 && LocVT == MVT::f64)) 3076 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3077 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 3078 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3079 Arg, DAG.getConstant(0, DL, MVT::i32)); 3080 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3081 Arg, DAG.getConstant(1, DL, MVT::i32)); 3082 if (!Subtarget.isLittle()) 3083 std::swap(Lo, Hi); 3084 unsigned LocRegLo = VA.getLocReg(); 3085 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 3086 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 3087 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 3088 continue; 3089 } 3090 } 3091 break; 3092 case CCValAssign::BCvt: 3093 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3094 break; 3095 case CCValAssign::SExtUpper: 3096 UseUpperBits = true; 3097 LLVM_FALLTHROUGH; 3098 case CCValAssign::SExt: 3099 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 3100 break; 3101 case CCValAssign::ZExtUpper: 3102 UseUpperBits = true; 3103 LLVM_FALLTHROUGH; 3104 case CCValAssign::ZExt: 3105 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 3106 break; 3107 case CCValAssign::AExtUpper: 3108 UseUpperBits = true; 3109 LLVM_FALLTHROUGH; 3110 case CCValAssign::AExt: 3111 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 3112 break; 3113 } 3114 3115 if (UseUpperBits) { 3116 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3117 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3118 Arg = DAG.getNode( 3119 ISD::SHL, DL, VA.getLocVT(), Arg, 3120 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3121 } 3122 3123 // Arguments that can be passed on register must be kept at 3124 // RegsToPass vector 3125 if (VA.isRegLoc()) { 3126 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 3127 continue; 3128 } 3129 3130 // Register can't get to this point... 3131 assert(VA.isMemLoc()); 3132 3133 // emit ISD::STORE whichs stores the 3134 // parameter value to a stack Location 3135 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 3136 Chain, Arg, DL, IsTailCall, DAG)); 3137 } 3138 3139 // Transform all store nodes into one single node because all store 3140 // nodes are independent of each other. 3141 if (!MemOpChains.empty()) 3142 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 3143 3144 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 3145 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 3146 // node so that legalize doesn't hack it. 3147 3148 SDValue CalleeLo; 3149 EVT Ty = Callee.getValueType(); 3150 bool GlobalOrExternal = false, IsCallReloc = false; 3151 3152 // The long-calls feature is ignored in case of PIC. 3153 // While we do not support -mshared / -mno-shared properly, 3154 // ignore long-calls in case of -mabicalls too. 3155 if (Subtarget.useLongCalls() && !Subtarget.isABICalls() && !IsPIC) { 3156 // Get the address of the callee into a register to prevent 3157 // using of the `jal` instruction for the direct call. 3158 if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) 3159 Callee = Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3160 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3161 else if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) 3162 Callee = Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3163 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3164 } 3165 3166 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3167 if (IsPIC) { 3168 const GlobalValue *Val = G->getGlobal(); 3169 InternalLinkage = Val->hasInternalLinkage(); 3170 3171 if (InternalLinkage) 3172 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); 3173 else if (LargeGOT) { 3174 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3175 MipsII::MO_CALL_LO16, Chain, 3176 FuncInfo->callPtrInfo(Val)); 3177 IsCallReloc = true; 3178 } else { 3179 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3180 FuncInfo->callPtrInfo(Val)); 3181 IsCallReloc = true; 3182 } 3183 } else 3184 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, 3185 getPointerTy(DAG.getDataLayout()), 0, 3186 MipsII::MO_NO_FLAG); 3187 GlobalOrExternal = true; 3188 } 3189 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3190 const char *Sym = S->getSymbol(); 3191 3192 if (!IsPIC) // static 3193 Callee = DAG.getTargetExternalSymbol( 3194 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); 3195 else if (LargeGOT) { 3196 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3197 MipsII::MO_CALL_LO16, Chain, 3198 FuncInfo->callPtrInfo(Sym)); 3199 IsCallReloc = true; 3200 } else { // PIC 3201 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3202 FuncInfo->callPtrInfo(Sym)); 3203 IsCallReloc = true; 3204 } 3205 3206 GlobalOrExternal = true; 3207 } 3208 3209 SmallVector<SDValue, 8> Ops(1, Chain); 3210 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 3211 3212 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage, 3213 IsCallReloc, CLI, Callee, Chain); 3214 3215 if (IsTailCall) { 3216 MF.getFrameInfo().setHasTailCall(); 3217 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); 3218 } 3219 3220 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); 3221 SDValue InFlag = Chain.getValue(1); 3222 3223 // Create the CALLSEQ_END node. 3224 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 3225 DAG.getIntPtrConstant(0, DL, true), InFlag, DL); 3226 InFlag = Chain.getValue(1); 3227 3228 // Handle result values, copying them out of physregs into vregs that we 3229 // return. 3230 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, 3231 InVals, CLI); 3232 } 3233 3234 /// LowerCallResult - Lower the result values of a call into the 3235 /// appropriate copies out of appropriate physical registers. 3236 SDValue MipsTargetLowering::LowerCallResult( 3237 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 3238 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3239 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 3240 TargetLowering::CallLoweringInfo &CLI) const { 3241 // Assign locations to each value returned by this call. 3242 SmallVector<CCValAssign, 16> RVLocs; 3243 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 3244 *DAG.getContext()); 3245 3246 const ExternalSymbolSDNode *ES = 3247 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode()); 3248 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy, 3249 ES ? ES->getSymbol() : nullptr); 3250 3251 // Copy all of the result registers out of their specified physreg. 3252 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3253 CCValAssign &VA = RVLocs[i]; 3254 assert(VA.isRegLoc() && "Can only return in registers!"); 3255 3256 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 3257 RVLocs[i].getLocVT(), InFlag); 3258 Chain = Val.getValue(1); 3259 InFlag = Val.getValue(2); 3260 3261 if (VA.isUpperBitsInLoc()) { 3262 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); 3263 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3264 unsigned Shift = 3265 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3266 Val = DAG.getNode( 3267 Shift, DL, VA.getLocVT(), Val, 3268 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3269 } 3270 3271 switch (VA.getLocInfo()) { 3272 default: 3273 llvm_unreachable("Unknown loc info!"); 3274 case CCValAssign::Full: 3275 break; 3276 case CCValAssign::BCvt: 3277 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 3278 break; 3279 case CCValAssign::AExt: 3280 case CCValAssign::AExtUpper: 3281 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3282 break; 3283 case CCValAssign::ZExt: 3284 case CCValAssign::ZExtUpper: 3285 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, 3286 DAG.getValueType(VA.getValVT())); 3287 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3288 break; 3289 case CCValAssign::SExt: 3290 case CCValAssign::SExtUpper: 3291 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, 3292 DAG.getValueType(VA.getValVT())); 3293 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3294 break; 3295 } 3296 3297 InVals.push_back(Val); 3298 } 3299 3300 return Chain; 3301 } 3302 3303 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, 3304 EVT ArgVT, const SDLoc &DL, 3305 SelectionDAG &DAG) { 3306 MVT LocVT = VA.getLocVT(); 3307 EVT ValVT = VA.getValVT(); 3308 3309 // Shift into the upper bits if necessary. 3310 switch (VA.getLocInfo()) { 3311 default: 3312 break; 3313 case CCValAssign::AExtUpper: 3314 case CCValAssign::SExtUpper: 3315 case CCValAssign::ZExtUpper: { 3316 unsigned ValSizeInBits = ArgVT.getSizeInBits(); 3317 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3318 unsigned Opcode = 3319 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3320 Val = DAG.getNode( 3321 Opcode, DL, VA.getLocVT(), Val, 3322 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3323 break; 3324 } 3325 } 3326 3327 // If this is an value smaller than the argument slot size (32-bit for O32, 3328 // 64-bit for N32/N64), it has been promoted in some way to the argument slot 3329 // size. Extract the value and insert any appropriate assertions regarding 3330 // sign/zero extension. 3331 switch (VA.getLocInfo()) { 3332 default: 3333 llvm_unreachable("Unknown loc info!"); 3334 case CCValAssign::Full: 3335 break; 3336 case CCValAssign::AExtUpper: 3337 case CCValAssign::AExt: 3338 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3339 break; 3340 case CCValAssign::SExtUpper: 3341 case CCValAssign::SExt: 3342 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3343 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3344 break; 3345 case CCValAssign::ZExtUpper: 3346 case CCValAssign::ZExt: 3347 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3348 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3349 break; 3350 case CCValAssign::BCvt: 3351 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); 3352 break; 3353 } 3354 3355 return Val; 3356 } 3357 3358 //===----------------------------------------------------------------------===// 3359 // Formal Arguments Calling Convention Implementation 3360 //===----------------------------------------------------------------------===// 3361 /// LowerFormalArguments - transform physical registers into virtual registers 3362 /// and generate load operations for arguments places on the stack. 3363 SDValue MipsTargetLowering::LowerFormalArguments( 3364 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 3365 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3366 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 3367 MachineFunction &MF = DAG.getMachineFunction(); 3368 MachineFrameInfo &MFI = MF.getFrameInfo(); 3369 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3370 3371 MipsFI->setVarArgsFrameIndex(0); 3372 3373 // Used with vargs to acumulate store chains. 3374 std::vector<SDValue> OutChains; 3375 3376 // Assign locations to all of the incoming arguments. 3377 SmallVector<CCValAssign, 16> ArgLocs; 3378 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 3379 *DAG.getContext()); 3380 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 3381 const Function *Func = DAG.getMachineFunction().getFunction(); 3382 Function::const_arg_iterator FuncArg = Func->arg_begin(); 3383 3384 if (Func->hasFnAttribute("interrupt") && !Func->arg_empty()) 3385 report_fatal_error( 3386 "Functions with the interrupt attribute cannot have arguments!"); 3387 3388 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); 3389 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 3390 CCInfo.getInRegsParamsCount() > 0); 3391 3392 unsigned CurArgIdx = 0; 3393 CCInfo.rewindByValRegsInfo(); 3394 3395 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3396 CCValAssign &VA = ArgLocs[i]; 3397 if (Ins[i].isOrigArg()) { 3398 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx); 3399 CurArgIdx = Ins[i].getOrigArgIndex(); 3400 } 3401 EVT ValVT = VA.getValVT(); 3402 ISD::ArgFlagsTy Flags = Ins[i].Flags; 3403 bool IsRegLoc = VA.isRegLoc(); 3404 3405 if (Flags.isByVal()) { 3406 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit"); 3407 unsigned FirstByValReg, LastByValReg; 3408 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3409 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3410 3411 assert(Flags.getByValSize() && 3412 "ByVal args of size 0 should have been ignored by front-end."); 3413 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3414 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 3415 FirstByValReg, LastByValReg, VA, CCInfo); 3416 CCInfo.nextInRegsParam(); 3417 continue; 3418 } 3419 3420 // Arguments stored on registers 3421 if (IsRegLoc) { 3422 MVT RegVT = VA.getLocVT(); 3423 unsigned ArgReg = VA.getLocReg(); 3424 const TargetRegisterClass *RC = getRegClassFor(RegVT); 3425 3426 // Transform the arguments stored on 3427 // physical registers into virtual ones 3428 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3429 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 3430 3431 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3432 3433 // Handle floating point arguments passed in integer registers and 3434 // long double arguments passed in floating point registers. 3435 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3436 (RegVT == MVT::i64 && ValVT == MVT::f64) || 3437 (RegVT == MVT::f64 && ValVT == MVT::i64)) 3438 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 3439 else if (ABI.IsO32() && RegVT == MVT::i32 && 3440 ValVT == MVT::f64) { 3441 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 3442 getNextIntArgReg(ArgReg), RC); 3443 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 3444 if (!Subtarget.isLittle()) 3445 std::swap(ArgValue, ArgValue2); 3446 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 3447 ArgValue, ArgValue2); 3448 } 3449 3450 InVals.push_back(ArgValue); 3451 } else { // VA.isRegLoc() 3452 MVT LocVT = VA.getLocVT(); 3453 3454 if (ABI.IsO32()) { 3455 // We ought to be able to use LocVT directly but O32 sets it to i32 3456 // when allocating floating point values to integer registers. 3457 // This shouldn't influence how we load the value into registers unless 3458 // we are targeting softfloat. 3459 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) 3460 LocVT = VA.getValVT(); 3461 } 3462 3463 // sanity check 3464 assert(VA.isMemLoc()); 3465 3466 // The stack pointer offset is relative to the caller stack frame. 3467 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, 3468 VA.getLocMemOffset(), true); 3469 3470 // Create load nodes to retrieve arguments from the stack 3471 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3472 SDValue ArgValue = DAG.getLoad( 3473 LocVT, DL, Chain, FIN, 3474 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); 3475 OutChains.push_back(ArgValue.getValue(1)); 3476 3477 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3478 3479 InVals.push_back(ArgValue); 3480 } 3481 } 3482 3483 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3484 // The mips ABIs for returning structs by value requires that we copy 3485 // the sret argument into $v0 for the return. Save the argument into 3486 // a virtual register so that we can access it from the return points. 3487 if (Ins[i].Flags.isSRet()) { 3488 unsigned Reg = MipsFI->getSRetReturnReg(); 3489 if (!Reg) { 3490 Reg = MF.getRegInfo().createVirtualRegister( 3491 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); 3492 MipsFI->setSRetReturnReg(Reg); 3493 } 3494 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); 3495 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 3496 break; 3497 } 3498 } 3499 3500 if (IsVarArg) 3501 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); 3502 3503 // All stores are grouped in one node to allow the matching between 3504 // the size of Ins and InVals. This only happens when on varg functions 3505 if (!OutChains.empty()) { 3506 OutChains.push_back(Chain); 3507 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 3508 } 3509 3510 return Chain; 3511 } 3512 3513 //===----------------------------------------------------------------------===// 3514 // Return Value Calling Convention Implementation 3515 //===----------------------------------------------------------------------===// 3516 3517 bool 3518 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3519 MachineFunction &MF, bool IsVarArg, 3520 const SmallVectorImpl<ISD::OutputArg> &Outs, 3521 LLVMContext &Context) const { 3522 SmallVector<CCValAssign, 16> RVLocs; 3523 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 3524 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3525 } 3526 3527 bool 3528 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { 3529 if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) { 3530 if (Type == MVT::i32) 3531 return true; 3532 } 3533 return IsSigned; 3534 } 3535 3536 SDValue 3537 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, 3538 const SDLoc &DL, 3539 SelectionDAG &DAG) const { 3540 3541 MachineFunction &MF = DAG.getMachineFunction(); 3542 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3543 3544 MipsFI->setISR(); 3545 3546 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps); 3547 } 3548 3549 SDValue 3550 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 3551 bool IsVarArg, 3552 const SmallVectorImpl<ISD::OutputArg> &Outs, 3553 const SmallVectorImpl<SDValue> &OutVals, 3554 const SDLoc &DL, SelectionDAG &DAG) const { 3555 // CCValAssign - represent the assignment of 3556 // the return value to a location 3557 SmallVector<CCValAssign, 16> RVLocs; 3558 MachineFunction &MF = DAG.getMachineFunction(); 3559 3560 // CCState - Info about the registers and stack slot. 3561 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 3562 3563 // Analyze return values. 3564 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3565 3566 SDValue Flag; 3567 SmallVector<SDValue, 4> RetOps(1, Chain); 3568 3569 // Copy the result values into the output registers. 3570 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3571 SDValue Val = OutVals[i]; 3572 CCValAssign &VA = RVLocs[i]; 3573 assert(VA.isRegLoc() && "Can only return in registers!"); 3574 bool UseUpperBits = false; 3575 3576 switch (VA.getLocInfo()) { 3577 default: 3578 llvm_unreachable("Unknown loc info!"); 3579 case CCValAssign::Full: 3580 break; 3581 case CCValAssign::BCvt: 3582 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); 3583 break; 3584 case CCValAssign::AExtUpper: 3585 UseUpperBits = true; 3586 LLVM_FALLTHROUGH; 3587 case CCValAssign::AExt: 3588 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); 3589 break; 3590 case CCValAssign::ZExtUpper: 3591 UseUpperBits = true; 3592 LLVM_FALLTHROUGH; 3593 case CCValAssign::ZExt: 3594 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); 3595 break; 3596 case CCValAssign::SExtUpper: 3597 UseUpperBits = true; 3598 LLVM_FALLTHROUGH; 3599 case CCValAssign::SExt: 3600 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); 3601 break; 3602 } 3603 3604 if (UseUpperBits) { 3605 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3606 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3607 Val = DAG.getNode( 3608 ISD::SHL, DL, VA.getLocVT(), Val, 3609 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3610 } 3611 3612 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 3613 3614 // Guarantee that all emitted copies are stuck together with flags. 3615 Flag = Chain.getValue(1); 3616 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3617 } 3618 3619 // The mips ABIs for returning structs by value requires that we copy 3620 // the sret argument into $v0 for the return. We saved the argument into 3621 // a virtual register in the entry block, so now we copy the value out 3622 // and into $v0. 3623 if (MF.getFunction()->hasStructRetAttr()) { 3624 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3625 unsigned Reg = MipsFI->getSRetReturnReg(); 3626 3627 if (!Reg) 3628 llvm_unreachable("sret virtual register not created in the entry block"); 3629 SDValue Val = 3630 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); 3631 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 3632 3633 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 3634 Flag = Chain.getValue(1); 3635 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); 3636 } 3637 3638 RetOps[0] = Chain; // Update chain. 3639 3640 // Add the flag if we have it. 3641 if (Flag.getNode()) 3642 RetOps.push_back(Flag); 3643 3644 // ISRs must use "eret". 3645 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt")) 3646 return LowerInterruptReturn(RetOps, DL, DAG); 3647 3648 // Standard return on Mips is a "jr $ra" 3649 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); 3650 } 3651 3652 //===----------------------------------------------------------------------===// 3653 // Mips Inline Assembly Support 3654 //===----------------------------------------------------------------------===// 3655 3656 /// getConstraintType - Given a constraint letter, return the type of 3657 /// constraint it is for this target. 3658 MipsTargetLowering::ConstraintType 3659 MipsTargetLowering::getConstraintType(StringRef Constraint) const { 3660 // Mips specific constraints 3661 // GCC config/mips/constraints.md 3662 // 3663 // 'd' : An address register. Equivalent to r 3664 // unless generating MIPS16 code. 3665 // 'y' : Equivalent to r; retained for 3666 // backwards compatibility. 3667 // 'c' : A register suitable for use in an indirect 3668 // jump. This will always be $25 for -mabicalls. 3669 // 'l' : The lo register. 1 word storage. 3670 // 'x' : The hilo register pair. Double word storage. 3671 if (Constraint.size() == 1) { 3672 switch (Constraint[0]) { 3673 default : break; 3674 case 'd': 3675 case 'y': 3676 case 'f': 3677 case 'c': 3678 case 'l': 3679 case 'x': 3680 return C_RegisterClass; 3681 case 'R': 3682 return C_Memory; 3683 } 3684 } 3685 3686 if (Constraint == "ZC") 3687 return C_Memory; 3688 3689 return TargetLowering::getConstraintType(Constraint); 3690 } 3691 3692 /// Examine constraint type and operand type and determine a weight value. 3693 /// This object must already have been set up with the operand type 3694 /// and the current alternative constraint selected. 3695 TargetLowering::ConstraintWeight 3696 MipsTargetLowering::getSingleConstraintMatchWeight( 3697 AsmOperandInfo &info, const char *constraint) const { 3698 ConstraintWeight weight = CW_Invalid; 3699 Value *CallOperandVal = info.CallOperandVal; 3700 // If we don't have a value, we can't do a match, 3701 // but allow it at the lowest weight. 3702 if (!CallOperandVal) 3703 return CW_Default; 3704 Type *type = CallOperandVal->getType(); 3705 // Look at the constraint type. 3706 switch (*constraint) { 3707 default: 3708 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3709 break; 3710 case 'd': 3711 case 'y': 3712 if (type->isIntegerTy()) 3713 weight = CW_Register; 3714 break; 3715 case 'f': // FPU or MSA register 3716 if (Subtarget.hasMSA() && type->isVectorTy() && 3717 cast<VectorType>(type)->getBitWidth() == 128) 3718 weight = CW_Register; 3719 else if (type->isFloatTy()) 3720 weight = CW_Register; 3721 break; 3722 case 'c': // $25 for indirect jumps 3723 case 'l': // lo register 3724 case 'x': // hilo register pair 3725 if (type->isIntegerTy()) 3726 weight = CW_SpecificReg; 3727 break; 3728 case 'I': // signed 16 bit immediate 3729 case 'J': // integer zero 3730 case 'K': // unsigned 16 bit immediate 3731 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3732 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3733 case 'O': // signed 15 bit immediate (+- 16383) 3734 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3735 if (isa<ConstantInt>(CallOperandVal)) 3736 weight = CW_Constant; 3737 break; 3738 case 'R': 3739 weight = CW_Memory; 3740 break; 3741 } 3742 return weight; 3743 } 3744 3745 /// This is a helper function to parse a physical register string and split it 3746 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 3747 /// that is returned indicates whether parsing was successful. The second flag 3748 /// is true if the numeric part exists. 3749 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix, 3750 unsigned long long &Reg) { 3751 if (C.front() != '{' || C.back() != '}') 3752 return std::make_pair(false, false); 3753 3754 // Search for the first numeric character. 3755 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 3756 I = std::find_if(B, E, isdigit); 3757 3758 Prefix = StringRef(B, I - B); 3759 3760 // The second flag is set to false if no numeric characters were found. 3761 if (I == E) 3762 return std::make_pair(true, false); 3763 3764 // Parse the numeric characters. 3765 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 3766 true); 3767 } 3768 3769 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 3770 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const { 3771 const TargetRegisterInfo *TRI = 3772 Subtarget.getRegisterInfo(); 3773 const TargetRegisterClass *RC; 3774 StringRef Prefix; 3775 unsigned long long Reg; 3776 3777 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 3778 3779 if (!R.first) 3780 return std::make_pair(0U, nullptr); 3781 3782 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 3783 // No numeric characters follow "hi" or "lo". 3784 if (R.second) 3785 return std::make_pair(0U, nullptr); 3786 3787 RC = TRI->getRegClass(Prefix == "hi" ? 3788 Mips::HI32RegClassID : Mips::LO32RegClassID); 3789 return std::make_pair(*(RC->begin()), RC); 3790 } else if (Prefix.startswith("$msa")) { 3791 // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 3792 3793 // No numeric characters follow the name. 3794 if (R.second) 3795 return std::make_pair(0U, nullptr); 3796 3797 Reg = StringSwitch<unsigned long long>(Prefix) 3798 .Case("$msair", Mips::MSAIR) 3799 .Case("$msacsr", Mips::MSACSR) 3800 .Case("$msaaccess", Mips::MSAAccess) 3801 .Case("$msasave", Mips::MSASave) 3802 .Case("$msamodify", Mips::MSAModify) 3803 .Case("$msarequest", Mips::MSARequest) 3804 .Case("$msamap", Mips::MSAMap) 3805 .Case("$msaunmap", Mips::MSAUnmap) 3806 .Default(0); 3807 3808 if (!Reg) 3809 return std::make_pair(0U, nullptr); 3810 3811 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 3812 return std::make_pair(Reg, RC); 3813 } 3814 3815 if (!R.second) 3816 return std::make_pair(0U, nullptr); 3817 3818 if (Prefix == "$f") { // Parse $f0-$f31. 3819 // If the size of FP registers is 64-bit or Reg is an even number, select 3820 // the 64-bit register class. Otherwise, select the 32-bit register class. 3821 if (VT == MVT::Other) 3822 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 3823 3824 RC = getRegClassFor(VT); 3825 3826 if (RC == &Mips::AFGR64RegClass) { 3827 assert(Reg % 2 == 0); 3828 Reg >>= 1; 3829 } 3830 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 3831 RC = TRI->getRegClass(Mips::FCCRegClassID); 3832 else if (Prefix == "$w") { // Parse $w0-$w31. 3833 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 3834 } else { // Parse $0-$31. 3835 assert(Prefix == "$"); 3836 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 3837 } 3838 3839 assert(Reg < RC->getNumRegs()); 3840 return std::make_pair(*(RC->begin() + Reg), RC); 3841 } 3842 3843 /// Given a register class constraint, like 'r', if this corresponds directly 3844 /// to an LLVM register class, return a register of 0 and the register class 3845 /// pointer. 3846 std::pair<unsigned, const TargetRegisterClass *> 3847 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 3848 StringRef Constraint, 3849 MVT VT) const { 3850 if (Constraint.size() == 1) { 3851 switch (Constraint[0]) { 3852 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3853 case 'y': // Same as 'r'. Exists for compatibility. 3854 case 'r': 3855 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3856 if (Subtarget.inMips16Mode()) 3857 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3858 return std::make_pair(0U, &Mips::GPR32RegClass); 3859 } 3860 if (VT == MVT::i64 && !Subtarget.isGP64bit()) 3861 return std::make_pair(0U, &Mips::GPR32RegClass); 3862 if (VT == MVT::i64 && Subtarget.isGP64bit()) 3863 return std::make_pair(0U, &Mips::GPR64RegClass); 3864 // This will generate an error message 3865 return std::make_pair(0U, nullptr); 3866 case 'f': // FPU or MSA register 3867 if (VT == MVT::v16i8) 3868 return std::make_pair(0U, &Mips::MSA128BRegClass); 3869 else if (VT == MVT::v8i16 || VT == MVT::v8f16) 3870 return std::make_pair(0U, &Mips::MSA128HRegClass); 3871 else if (VT == MVT::v4i32 || VT == MVT::v4f32) 3872 return std::make_pair(0U, &Mips::MSA128WRegClass); 3873 else if (VT == MVT::v2i64 || VT == MVT::v2f64) 3874 return std::make_pair(0U, &Mips::MSA128DRegClass); 3875 else if (VT == MVT::f32) 3876 return std::make_pair(0U, &Mips::FGR32RegClass); 3877 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { 3878 if (Subtarget.isFP64bit()) 3879 return std::make_pair(0U, &Mips::FGR64RegClass); 3880 return std::make_pair(0U, &Mips::AFGR64RegClass); 3881 } 3882 break; 3883 case 'c': // register suitable for indirect jump 3884 if (VT == MVT::i32) 3885 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 3886 assert(VT == MVT::i64 && "Unexpected type."); 3887 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 3888 case 'l': // register suitable for indirect jump 3889 if (VT == MVT::i32) 3890 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 3891 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 3892 case 'x': // register suitable for indirect jump 3893 // Fixme: Not triggering the use of both hi and low 3894 // This will generate an error message 3895 return std::make_pair(0U, nullptr); 3896 } 3897 } 3898 3899 std::pair<unsigned, const TargetRegisterClass *> R; 3900 R = parseRegForInlineAsmConstraint(Constraint, VT); 3901 3902 if (R.second) 3903 return R; 3904 3905 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 3906 } 3907 3908 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3909 /// vector. If it is invalid, don't add anything to Ops. 3910 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3911 std::string &Constraint, 3912 std::vector<SDValue>&Ops, 3913 SelectionDAG &DAG) const { 3914 SDLoc DL(Op); 3915 SDValue Result; 3916 3917 // Only support length 1 constraints for now. 3918 if (Constraint.length() > 1) return; 3919 3920 char ConstraintLetter = Constraint[0]; 3921 switch (ConstraintLetter) { 3922 default: break; // This will fall through to the generic implementation 3923 case 'I': // Signed 16 bit constant 3924 // If this fails, the parent routine will give an error 3925 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3926 EVT Type = Op.getValueType(); 3927 int64_t Val = C->getSExtValue(); 3928 if (isInt<16>(Val)) { 3929 Result = DAG.getTargetConstant(Val, DL, Type); 3930 break; 3931 } 3932 } 3933 return; 3934 case 'J': // integer zero 3935 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3936 EVT Type = Op.getValueType(); 3937 int64_t Val = C->getZExtValue(); 3938 if (Val == 0) { 3939 Result = DAG.getTargetConstant(0, DL, Type); 3940 break; 3941 } 3942 } 3943 return; 3944 case 'K': // unsigned 16 bit immediate 3945 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3946 EVT Type = Op.getValueType(); 3947 uint64_t Val = (uint64_t)C->getZExtValue(); 3948 if (isUInt<16>(Val)) { 3949 Result = DAG.getTargetConstant(Val, DL, Type); 3950 break; 3951 } 3952 } 3953 return; 3954 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3955 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3956 EVT Type = Op.getValueType(); 3957 int64_t Val = C->getSExtValue(); 3958 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3959 Result = DAG.getTargetConstant(Val, DL, Type); 3960 break; 3961 } 3962 } 3963 return; 3964 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3965 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3966 EVT Type = Op.getValueType(); 3967 int64_t Val = C->getSExtValue(); 3968 if ((Val >= -65535) && (Val <= -1)) { 3969 Result = DAG.getTargetConstant(Val, DL, Type); 3970 break; 3971 } 3972 } 3973 return; 3974 case 'O': // signed 15 bit immediate 3975 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3976 EVT Type = Op.getValueType(); 3977 int64_t Val = C->getSExtValue(); 3978 if ((isInt<15>(Val))) { 3979 Result = DAG.getTargetConstant(Val, DL, Type); 3980 break; 3981 } 3982 } 3983 return; 3984 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3985 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3986 EVT Type = Op.getValueType(); 3987 int64_t Val = C->getSExtValue(); 3988 if ((Val <= 65535) && (Val >= 1)) { 3989 Result = DAG.getTargetConstant(Val, DL, Type); 3990 break; 3991 } 3992 } 3993 return; 3994 } 3995 3996 if (Result.getNode()) { 3997 Ops.push_back(Result); 3998 return; 3999 } 4000 4001 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 4002 } 4003 4004 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, 4005 const AddrMode &AM, Type *Ty, 4006 unsigned AS) const { 4007 // No global is ever allowed as a base. 4008 if (AM.BaseGV) 4009 return false; 4010 4011 switch (AM.Scale) { 4012 case 0: // "r+i" or just "i", depending on HasBaseReg. 4013 break; 4014 case 1: 4015 if (!AM.HasBaseReg) // allow "r+i". 4016 break; 4017 return false; // disallow "r+r" or "r+r+i". 4018 default: 4019 return false; 4020 } 4021 4022 return true; 4023 } 4024 4025 bool 4026 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 4027 // The Mips target isn't yet aware of offsets. 4028 return false; 4029 } 4030 4031 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 4032 unsigned SrcAlign, 4033 bool IsMemset, bool ZeroMemset, 4034 bool MemcpyStrSrc, 4035 MachineFunction &MF) const { 4036 if (Subtarget.hasMips64()) 4037 return MVT::i64; 4038 4039 return MVT::i32; 4040 } 4041 4042 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 4043 if (VT != MVT::f32 && VT != MVT::f64) 4044 return false; 4045 if (Imm.isNegZero()) 4046 return false; 4047 return Imm.isZero(); 4048 } 4049 4050 unsigned MipsTargetLowering::getJumpTableEncoding() const { 4051 4052 // FIXME: For space reasons this should be: EK_GPRel32BlockAddress. 4053 if (ABI.IsN64() && isPositionIndependent()) 4054 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 4055 4056 return TargetLowering::getJumpTableEncoding(); 4057 } 4058 4059 bool MipsTargetLowering::useSoftFloat() const { 4060 return Subtarget.useSoftFloat(); 4061 } 4062 4063 void MipsTargetLowering::copyByValRegs( 4064 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains, 4065 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 4066 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 4067 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, 4068 MipsCCState &State) const { 4069 MachineFunction &MF = DAG.getMachineFunction(); 4070 MachineFrameInfo &MFI = MF.getFrameInfo(); 4071 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); 4072 unsigned NumRegs = LastReg - FirstReg; 4073 unsigned RegAreaSize = NumRegs * GPRSizeInBytes; 4074 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 4075 int FrameObjOffset; 4076 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs(); 4077 4078 if (RegAreaSize) 4079 FrameObjOffset = 4080 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4081 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); 4082 else 4083 FrameObjOffset = VA.getLocMemOffset(); 4084 4085 // Create frame object. 4086 EVT PtrTy = getPointerTy(DAG.getDataLayout()); 4087 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, true); 4088 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4089 InVals.push_back(FIN); 4090 4091 if (!NumRegs) 4092 return; 4093 4094 // Copy arg registers. 4095 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); 4096 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4097 4098 for (unsigned I = 0; I < NumRegs; ++I) { 4099 unsigned ArgReg = ByValArgRegs[FirstReg + I]; 4100 unsigned VReg = addLiveIn(MF, ArgReg, RC); 4101 unsigned Offset = I * GPRSizeInBytes; 4102 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 4103 DAG.getConstant(Offset, DL, PtrTy)); 4104 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 4105 StorePtr, MachinePointerInfo(FuncArg, Offset)); 4106 OutChains.push_back(Store); 4107 } 4108 } 4109 4110 // Copy byVal arg to registers and stack. 4111 void MipsTargetLowering::passByValArg( 4112 SDValue Chain, const SDLoc &DL, 4113 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 4114 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 4115 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, 4116 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, 4117 const CCValAssign &VA) const { 4118 unsigned ByValSizeInBytes = Flags.getByValSize(); 4119 unsigned OffsetInBytes = 0; // From beginning of struct 4120 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4121 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes); 4122 EVT PtrTy = getPointerTy(DAG.getDataLayout()), 4123 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4124 unsigned NumRegs = LastReg - FirstReg; 4125 4126 if (NumRegs) { 4127 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); 4128 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); 4129 unsigned I = 0; 4130 4131 // Copy words to registers. 4132 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { 4133 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4134 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4135 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 4136 MachinePointerInfo(), Alignment); 4137 MemOpChains.push_back(LoadVal.getValue(1)); 4138 unsigned ArgReg = ArgRegs[FirstReg + I]; 4139 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 4140 } 4141 4142 // Return if the struct has been fully copied. 4143 if (ByValSizeInBytes == OffsetInBytes) 4144 return; 4145 4146 // Copy the remainder of the byval argument with sub-word loads and shifts. 4147 if (LeftoverBytes) { 4148 SDValue Val; 4149 4150 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0; 4151 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) { 4152 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes; 4153 4154 if (RemainingSizeInBytes < LoadSizeInBytes) 4155 continue; 4156 4157 // Load subword. 4158 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4159 DAG.getConstant(OffsetInBytes, DL, 4160 PtrTy)); 4161 SDValue LoadVal = DAG.getExtLoad( 4162 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), 4163 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment); 4164 MemOpChains.push_back(LoadVal.getValue(1)); 4165 4166 // Shift the loaded value. 4167 unsigned Shamt; 4168 4169 if (isLittle) 4170 Shamt = TotalBytesLoaded * 8; 4171 else 4172 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; 4173 4174 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 4175 DAG.getConstant(Shamt, DL, MVT::i32)); 4176 4177 if (Val.getNode()) 4178 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 4179 else 4180 Val = Shift; 4181 4182 OffsetInBytes += LoadSizeInBytes; 4183 TotalBytesLoaded += LoadSizeInBytes; 4184 Alignment = std::min(Alignment, LoadSizeInBytes); 4185 } 4186 4187 unsigned ArgReg = ArgRegs[FirstReg + I]; 4188 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 4189 return; 4190 } 4191 } 4192 4193 // Copy remainder of byval arg to it with memcpy. 4194 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; 4195 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4196 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4197 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 4198 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); 4199 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 4200 DAG.getConstant(MemCpySize, DL, PtrTy), 4201 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, 4202 /*isTailCall=*/false, 4203 MachinePointerInfo(), MachinePointerInfo()); 4204 MemOpChains.push_back(Chain); 4205 } 4206 4207 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 4208 SDValue Chain, const SDLoc &DL, 4209 SelectionDAG &DAG, 4210 CCState &State) const { 4211 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); 4212 unsigned Idx = State.getFirstUnallocated(ArgRegs); 4213 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4214 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4215 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4216 MachineFunction &MF = DAG.getMachineFunction(); 4217 MachineFrameInfo &MFI = MF.getFrameInfo(); 4218 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 4219 4220 // Offset of the first variable argument from stack pointer. 4221 int VaArgOffset; 4222 4223 if (ArgRegs.size() == Idx) 4224 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes); 4225 else { 4226 VaArgOffset = 4227 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4228 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); 4229 } 4230 4231 // Record the frame index of the first variable argument 4232 // which is a value necessary to VASTART. 4233 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4234 MipsFI->setVarArgsFrameIndex(FI); 4235 4236 // Copy the integer registers that have not been used for argument passing 4237 // to the argument register save area. For O32, the save area is allocated 4238 // in the caller's stack frame, while for N32/64, it is allocated in the 4239 // callee's stack frame. 4240 for (unsigned I = Idx; I < ArgRegs.size(); 4241 ++I, VaArgOffset += RegSizeInBytes) { 4242 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 4243 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 4244 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4245 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 4246 SDValue Store = 4247 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo()); 4248 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( 4249 (Value *)nullptr); 4250 OutChains.push_back(Store); 4251 } 4252 } 4253 4254 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, 4255 unsigned Align) const { 4256 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 4257 4258 assert(Size && "Byval argument's size shouldn't be 0."); 4259 4260 Align = std::min(Align, TFL->getStackAlignment()); 4261 4262 unsigned FirstReg = 0; 4263 unsigned NumRegs = 0; 4264 4265 if (State->getCallingConv() != CallingConv::Fast) { 4266 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4267 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs(); 4268 // FIXME: The O32 case actually describes no shadow registers. 4269 const MCPhysReg *ShadowRegs = 4270 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs; 4271 4272 // We used to check the size as well but we can't do that anymore since 4273 // CCState::HandleByVal() rounds up the size after calling this function. 4274 assert(!(Align % RegSizeInBytes) && 4275 "Byval argument's alignment should be a multiple of" 4276 "RegSizeInBytes."); 4277 4278 FirstReg = State->getFirstUnallocated(IntArgRegs); 4279 4280 // If Align > RegSizeInBytes, the first arg register must be even. 4281 // FIXME: This condition happens to do the right thing but it's not the 4282 // right way to test it. We want to check that the stack frame offset 4283 // of the register is aligned. 4284 if ((Align > RegSizeInBytes) && (FirstReg % 2)) { 4285 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); 4286 ++FirstReg; 4287 } 4288 4289 // Mark the registers allocated. 4290 Size = alignTo(Size, RegSizeInBytes); 4291 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size()); 4292 Size -= RegSizeInBytes, ++I, ++NumRegs) 4293 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); 4294 } 4295 4296 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); 4297 } 4298 4299 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI, 4300 MachineBasicBlock *BB, 4301 bool isFPCmp, 4302 unsigned Opc) const { 4303 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4304 "Subtarget already supports SELECT nodes with the use of" 4305 "conditional-move instructions."); 4306 4307 const TargetInstrInfo *TII = 4308 Subtarget.getInstrInfo(); 4309 DebugLoc DL = MI.getDebugLoc(); 4310 4311 // To "insert" a SELECT instruction, we actually have to insert the 4312 // diamond control-flow pattern. The incoming instruction knows the 4313 // destination vreg to set, the condition code register to branch on, the 4314 // true/false values to select between, and a branch opcode to use. 4315 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4316 MachineFunction::iterator It = ++BB->getIterator(); 4317 4318 // thisMBB: 4319 // ... 4320 // TrueVal = ... 4321 // setcc r1, r2, r3 4322 // bNE r1, r0, copy1MBB 4323 // fallthrough --> copy0MBB 4324 MachineBasicBlock *thisMBB = BB; 4325 MachineFunction *F = BB->getParent(); 4326 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4327 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4328 F->insert(It, copy0MBB); 4329 F->insert(It, sinkMBB); 4330 4331 // Transfer the remainder of BB and its successor edges to sinkMBB. 4332 sinkMBB->splice(sinkMBB->begin(), BB, 4333 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 4334 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4335 4336 // Next, add the true and fallthrough blocks as its successors. 4337 BB->addSuccessor(copy0MBB); 4338 BB->addSuccessor(sinkMBB); 4339 4340 if (isFPCmp) { 4341 // bc1[tf] cc, sinkMBB 4342 BuildMI(BB, DL, TII->get(Opc)) 4343 .addReg(MI.getOperand(1).getReg()) 4344 .addMBB(sinkMBB); 4345 } else { 4346 // bne rs, $0, sinkMBB 4347 BuildMI(BB, DL, TII->get(Opc)) 4348 .addReg(MI.getOperand(1).getReg()) 4349 .addReg(Mips::ZERO) 4350 .addMBB(sinkMBB); 4351 } 4352 4353 // copy0MBB: 4354 // %FalseValue = ... 4355 // # fallthrough to sinkMBB 4356 BB = copy0MBB; 4357 4358 // Update machine-CFG edges 4359 BB->addSuccessor(sinkMBB); 4360 4361 // sinkMBB: 4362 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4363 // ... 4364 BB = sinkMBB; 4365 4366 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4367 .addReg(MI.getOperand(2).getReg()) 4368 .addMBB(thisMBB) 4369 .addReg(MI.getOperand(3).getReg()) 4370 .addMBB(copy0MBB); 4371 4372 MI.eraseFromParent(); // The pseudo instruction is gone now. 4373 4374 return BB; 4375 } 4376 4377 // FIXME? Maybe this could be a TableGen attribute on some registers and 4378 // this table could be generated automatically from RegInfo. 4379 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT, 4380 SelectionDAG &DAG) const { 4381 // Named registers is expected to be fairly rare. For now, just support $28 4382 // since the linux kernel uses it. 4383 if (Subtarget.isGP64bit()) { 4384 unsigned Reg = StringSwitch<unsigned>(RegName) 4385 .Case("$28", Mips::GP_64) 4386 .Default(0); 4387 if (Reg) 4388 return Reg; 4389 } else { 4390 unsigned Reg = StringSwitch<unsigned>(RegName) 4391 .Case("$28", Mips::GP) 4392 .Default(0); 4393 if (Reg) 4394 return Reg; 4395 } 4396 report_fatal_error("Invalid register name global variable"); 4397 } 4398