1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "MipsISelLowering.h" 16 #include "InstPrinter/MipsInstPrinter.h" 17 #include "MCTargetDesc/MipsBaseInfo.h" 18 #include "MCTargetDesc/MipsMCTargetDesc.h" 19 #include "MipsCCState.h" 20 #include "MipsInstrInfo.h" 21 #include "MipsMachineFunction.h" 22 #include "MipsRegisterInfo.h" 23 #include "MipsSubtarget.h" 24 #include "MipsTargetMachine.h" 25 #include "MipsTargetObjectFile.h" 26 #include "llvm/ADT/APFloat.h" 27 #include "llvm/ADT/ArrayRef.h" 28 #include "llvm/ADT/SmallVector.h" 29 #include "llvm/ADT/Statistic.h" 30 #include "llvm/ADT/StringRef.h" 31 #include "llvm/ADT/StringSwitch.h" 32 #include "llvm/CodeGen/CallingConvLower.h" 33 #include "llvm/CodeGen/FunctionLoweringInfo.h" 34 #include "llvm/CodeGen/ISDOpcodes.h" 35 #include "llvm/CodeGen/MachineBasicBlock.h" 36 #include "llvm/CodeGen/MachineFrameInfo.h" 37 #include "llvm/CodeGen/MachineFunction.h" 38 #include "llvm/CodeGen/MachineInstr.h" 39 #include "llvm/CodeGen/MachineInstrBuilder.h" 40 #include "llvm/CodeGen/MachineJumpTableInfo.h" 41 #include "llvm/CodeGen/MachineMemOperand.h" 42 #include "llvm/CodeGen/MachineOperand.h" 43 #include "llvm/CodeGen/MachineRegisterInfo.h" 44 #include "llvm/CodeGen/RuntimeLibcalls.h" 45 #include "llvm/CodeGen/SelectionDAG.h" 46 #include "llvm/CodeGen/SelectionDAGNodes.h" 47 #include "llvm/CodeGen/TargetFrameLowering.h" 48 #include "llvm/CodeGen/TargetInstrInfo.h" 49 #include "llvm/CodeGen/TargetRegisterInfo.h" 50 #include "llvm/CodeGen/ValueTypes.h" 51 #include "llvm/IR/CallingConv.h" 52 #include "llvm/IR/Constants.h" 53 #include "llvm/IR/DataLayout.h" 54 #include "llvm/IR/DebugLoc.h" 55 #include "llvm/IR/DerivedTypes.h" 56 #include "llvm/IR/Function.h" 57 #include "llvm/IR/GlobalValue.h" 58 #include "llvm/IR/Type.h" 59 #include "llvm/IR/Value.h" 60 #include "llvm/MC/MCContext.h" 61 #include "llvm/MC/MCRegisterInfo.h" 62 #include "llvm/Support/Casting.h" 63 #include "llvm/Support/CodeGen.h" 64 #include "llvm/Support/CommandLine.h" 65 #include "llvm/Support/Compiler.h" 66 #include "llvm/Support/ErrorHandling.h" 67 #include "llvm/Support/MachineValueType.h" 68 #include "llvm/Support/MathExtras.h" 69 #include "llvm/Target/TargetMachine.h" 70 #include "llvm/Target/TargetOptions.h" 71 #include <algorithm> 72 #include <cassert> 73 #include <cctype> 74 #include <cstdint> 75 #include <deque> 76 #include <iterator> 77 #include <utility> 78 #include <vector> 79 80 using namespace llvm; 81 82 #define DEBUG_TYPE "mips-lower" 83 84 STATISTIC(NumTailCalls, "Number of tail calls"); 85 86 static cl::opt<bool> 87 LargeGOT("mxgot", cl::Hidden, 88 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 89 90 static cl::opt<bool> 91 NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 92 cl::desc("MIPS: Don't trap on integer division by zero."), 93 cl::init(false)); 94 95 extern cl::opt<bool> EmitJalrReloc; 96 97 static const MCPhysReg Mips64DPRegs[8] = { 98 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 99 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 100 }; 101 102 // If I is a shifted mask, set the size (Size) and the first bit of the 103 // mask (Pos), and return true. 104 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 105 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 106 if (!isShiftedMask_64(I)) 107 return false; 108 109 Size = countPopulation(I); 110 Pos = countTrailingZeros(I); 111 return true; 112 } 113 114 // The MIPS MSA ABI passes vector arguments in the integer register set. 115 // The number of integer registers used is dependant on the ABI used. 116 MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, 117 CallingConv::ID CC, 118 EVT VT) const { 119 if (VT.isVector()) { 120 if (Subtarget.isABI_O32()) { 121 return MVT::i32; 122 } else { 123 return (VT.getSizeInBits() == 32) ? MVT::i32 : MVT::i64; 124 } 125 } 126 return MipsTargetLowering::getRegisterType(Context, VT); 127 } 128 129 unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context, 130 CallingConv::ID CC, 131 EVT VT) const { 132 if (VT.isVector()) 133 return std::max((VT.getSizeInBits() / (Subtarget.isABI_O32() ? 32 : 64)), 134 1U); 135 return MipsTargetLowering::getNumRegisters(Context, VT); 136 } 137 138 unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv( 139 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 140 unsigned &NumIntermediates, MVT &RegisterVT) const { 141 // Break down vector types to either 2 i64s or 4 i32s. 142 RegisterVT = getRegisterTypeForCallingConv(Context, CC, VT); 143 IntermediateVT = RegisterVT; 144 NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits() 145 ? VT.getVectorNumElements() 146 : VT.getSizeInBits() / RegisterVT.getSizeInBits(); 147 148 return NumIntermediates; 149 } 150 151 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 152 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 153 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 154 } 155 156 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 157 SelectionDAG &DAG, 158 unsigned Flag) const { 159 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 160 } 161 162 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 163 SelectionDAG &DAG, 164 unsigned Flag) const { 165 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 166 } 167 168 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 169 SelectionDAG &DAG, 170 unsigned Flag) const { 171 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 172 } 173 174 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 175 SelectionDAG &DAG, 176 unsigned Flag) const { 177 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 178 } 179 180 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 181 SelectionDAG &DAG, 182 unsigned Flag) const { 183 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 184 N->getOffset(), Flag); 185 } 186 187 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 188 switch ((MipsISD::NodeType)Opcode) { 189 case MipsISD::FIRST_NUMBER: break; 190 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 191 case MipsISD::TailCall: return "MipsISD::TailCall"; 192 case MipsISD::Highest: return "MipsISD::Highest"; 193 case MipsISD::Higher: return "MipsISD::Higher"; 194 case MipsISD::Hi: return "MipsISD::Hi"; 195 case MipsISD::Lo: return "MipsISD::Lo"; 196 case MipsISD::GotHi: return "MipsISD::GotHi"; 197 case MipsISD::TlsHi: return "MipsISD::TlsHi"; 198 case MipsISD::GPRel: return "MipsISD::GPRel"; 199 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 200 case MipsISD::Ret: return "MipsISD::Ret"; 201 case MipsISD::ERet: return "MipsISD::ERet"; 202 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 203 case MipsISD::FMS: return "MipsISD::FMS"; 204 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 205 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 206 case MipsISD::FSELECT: return "MipsISD::FSELECT"; 207 case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64"; 208 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 209 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 210 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 211 case MipsISD::MFHI: return "MipsISD::MFHI"; 212 case MipsISD::MFLO: return "MipsISD::MFLO"; 213 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 214 case MipsISD::Mult: return "MipsISD::Mult"; 215 case MipsISD::Multu: return "MipsISD::Multu"; 216 case MipsISD::MAdd: return "MipsISD::MAdd"; 217 case MipsISD::MAddu: return "MipsISD::MAddu"; 218 case MipsISD::MSub: return "MipsISD::MSub"; 219 case MipsISD::MSubu: return "MipsISD::MSubu"; 220 case MipsISD::DivRem: return "MipsISD::DivRem"; 221 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 222 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 223 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 224 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 225 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 226 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 227 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 228 case MipsISD::Sync: return "MipsISD::Sync"; 229 case MipsISD::Ext: return "MipsISD::Ext"; 230 case MipsISD::Ins: return "MipsISD::Ins"; 231 case MipsISD::CIns: return "MipsISD::CIns"; 232 case MipsISD::LWL: return "MipsISD::LWL"; 233 case MipsISD::LWR: return "MipsISD::LWR"; 234 case MipsISD::SWL: return "MipsISD::SWL"; 235 case MipsISD::SWR: return "MipsISD::SWR"; 236 case MipsISD::LDL: return "MipsISD::LDL"; 237 case MipsISD::LDR: return "MipsISD::LDR"; 238 case MipsISD::SDL: return "MipsISD::SDL"; 239 case MipsISD::SDR: return "MipsISD::SDR"; 240 case MipsISD::EXTP: return "MipsISD::EXTP"; 241 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 242 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 243 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 244 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 245 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 246 case MipsISD::SHILO: return "MipsISD::SHILO"; 247 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 248 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; 249 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; 250 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; 251 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; 252 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; 253 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; 254 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; 255 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; 256 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; 257 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; 258 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; 259 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; 260 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; 261 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; 262 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; 263 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; 264 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; 265 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; 266 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; 267 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; 268 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; 269 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; 270 case MipsISD::MULT: return "MipsISD::MULT"; 271 case MipsISD::MULTU: return "MipsISD::MULTU"; 272 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 273 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 274 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 275 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 276 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 277 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 278 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 279 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 280 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 281 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 282 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 283 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 284 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 285 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 286 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 287 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 288 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 289 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 290 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 291 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 292 case MipsISD::VNOR: return "MipsISD::VNOR"; 293 case MipsISD::VSHF: return "MipsISD::VSHF"; 294 case MipsISD::SHF: return "MipsISD::SHF"; 295 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 296 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 297 case MipsISD::ILVL: return "MipsISD::ILVL"; 298 case MipsISD::ILVR: return "MipsISD::ILVR"; 299 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 300 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 301 case MipsISD::INSVE: return "MipsISD::INSVE"; 302 } 303 return nullptr; 304 } 305 306 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, 307 const MipsSubtarget &STI) 308 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { 309 // Mips does not have i1 type, so use i32 for 310 // setcc operations results (slt, sgt, ...). 311 setBooleanContents(ZeroOrOneBooleanContent); 312 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 313 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA 314 // does. Integer booleans still use 0 and 1. 315 if (Subtarget.hasMips32r6()) 316 setBooleanContents(ZeroOrOneBooleanContent, 317 ZeroOrNegativeOneBooleanContent); 318 319 // Load extented operations for i1 types must be promoted 320 for (MVT VT : MVT::integer_valuetypes()) { 321 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 322 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 323 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 324 } 325 326 // MIPS doesn't have extending float->double load/store. Set LoadExtAction 327 // for f32, f16 328 for (MVT VT : MVT::fp_valuetypes()) { 329 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 330 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 331 } 332 333 // Set LoadExtAction for f16 vectors to Expand 334 for (MVT VT : MVT::fp_vector_valuetypes()) { 335 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); 336 if (F16VT.isValid()) 337 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); 338 } 339 340 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 341 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 342 343 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 344 345 // Used by legalize types to correctly generate the setcc result. 346 // Without this, every float setcc comes with a AND/OR with the result, 347 // we don't want this, since the fpcmp result goes to a flag register, 348 // which is used implicitly by brcond and select operations. 349 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 350 351 // Mips Custom Operations 352 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 353 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 354 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 355 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 356 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 357 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 358 setOperationAction(ISD::SELECT, MVT::f32, Custom); 359 setOperationAction(ISD::SELECT, MVT::f64, Custom); 360 setOperationAction(ISD::SELECT, MVT::i32, Custom); 361 setOperationAction(ISD::SETCC, MVT::f32, Custom); 362 setOperationAction(ISD::SETCC, MVT::f64, Custom); 363 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 364 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 365 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 366 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 367 368 if (Subtarget.isGP64bit()) { 369 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 370 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 371 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 372 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 373 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 374 setOperationAction(ISD::SELECT, MVT::i64, Custom); 375 setOperationAction(ISD::LOAD, MVT::i64, Custom); 376 setOperationAction(ISD::STORE, MVT::i64, Custom); 377 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 378 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 379 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 380 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 381 } 382 383 if (!Subtarget.isGP64bit()) { 384 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 385 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 386 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 387 } 388 389 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); 390 if (Subtarget.isGP64bit()) 391 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); 392 393 setOperationAction(ISD::SDIV, MVT::i32, Expand); 394 setOperationAction(ISD::SREM, MVT::i32, Expand); 395 setOperationAction(ISD::UDIV, MVT::i32, Expand); 396 setOperationAction(ISD::UREM, MVT::i32, Expand); 397 setOperationAction(ISD::SDIV, MVT::i64, Expand); 398 setOperationAction(ISD::SREM, MVT::i64, Expand); 399 setOperationAction(ISD::UDIV, MVT::i64, Expand); 400 setOperationAction(ISD::UREM, MVT::i64, Expand); 401 402 // Operations not directly supported by Mips. 403 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 404 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 405 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 406 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 407 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 408 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 409 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 410 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 411 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 412 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 413 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 414 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 415 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 416 if (Subtarget.hasCnMips()) { 417 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 418 setOperationAction(ISD::CTPOP, MVT::i64, Legal); 419 } else { 420 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 421 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 422 } 423 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 424 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 425 setOperationAction(ISD::ROTL, MVT::i32, Expand); 426 setOperationAction(ISD::ROTL, MVT::i64, Expand); 427 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 428 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 429 430 if (!Subtarget.hasMips32r2()) 431 setOperationAction(ISD::ROTR, MVT::i32, Expand); 432 433 if (!Subtarget.hasMips64r2()) 434 setOperationAction(ISD::ROTR, MVT::i64, Expand); 435 436 setOperationAction(ISD::FSIN, MVT::f32, Expand); 437 setOperationAction(ISD::FSIN, MVT::f64, Expand); 438 setOperationAction(ISD::FCOS, MVT::f32, Expand); 439 setOperationAction(ISD::FCOS, MVT::f64, Expand); 440 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 441 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 442 setOperationAction(ISD::FPOW, MVT::f32, Expand); 443 setOperationAction(ISD::FPOW, MVT::f64, Expand); 444 setOperationAction(ISD::FLOG, MVT::f32, Expand); 445 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 446 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 447 setOperationAction(ISD::FEXP, MVT::f32, Expand); 448 setOperationAction(ISD::FMA, MVT::f32, Expand); 449 setOperationAction(ISD::FMA, MVT::f64, Expand); 450 setOperationAction(ISD::FREM, MVT::f32, Expand); 451 setOperationAction(ISD::FREM, MVT::f64, Expand); 452 453 // Lower f16 conversion operations into library calls 454 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); 455 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); 456 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); 457 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); 458 459 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 460 461 setOperationAction(ISD::VASTART, MVT::Other, Custom); 462 setOperationAction(ISD::VAARG, MVT::Other, Custom); 463 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 464 setOperationAction(ISD::VAEND, MVT::Other, Expand); 465 466 // Use the default for now 467 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 468 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 469 470 if (!Subtarget.isGP64bit()) { 471 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 472 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 473 } 474 475 if (!Subtarget.hasMips32r2()) { 476 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 477 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 478 } 479 480 // MIPS16 lacks MIPS32's clz and clo instructions. 481 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 482 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 483 if (!Subtarget.hasMips64()) 484 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 485 486 if (!Subtarget.hasMips32r2()) 487 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 488 if (!Subtarget.hasMips64r2()) 489 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 490 491 if (Subtarget.isGP64bit()) { 492 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); 493 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); 494 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); 495 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 496 } 497 498 setOperationAction(ISD::TRAP, MVT::Other, Legal); 499 500 setTargetDAGCombine(ISD::SDIVREM); 501 setTargetDAGCombine(ISD::UDIVREM); 502 setTargetDAGCombine(ISD::SELECT); 503 setTargetDAGCombine(ISD::AND); 504 setTargetDAGCombine(ISD::OR); 505 setTargetDAGCombine(ISD::ADD); 506 setTargetDAGCombine(ISD::SUB); 507 setTargetDAGCombine(ISD::AssertZext); 508 setTargetDAGCombine(ISD::SHL); 509 510 if (ABI.IsO32()) { 511 // These libcalls are not available in 32-bit. 512 setLibcallName(RTLIB::SHL_I128, nullptr); 513 setLibcallName(RTLIB::SRL_I128, nullptr); 514 setLibcallName(RTLIB::SRA_I128, nullptr); 515 } 516 517 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2); 518 519 // The arguments on the stack are defined in terms of 4-byte slots on O32 520 // and 8-byte slots on N32/N64. 521 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4); 522 523 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); 524 525 MaxStoresPerMemcpy = 16; 526 527 isMicroMips = Subtarget.inMicroMipsMode(); 528 } 529 530 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM, 531 const MipsSubtarget &STI) { 532 if (STI.inMips16Mode()) 533 return createMips16TargetLowering(TM, STI); 534 535 return createMipsSETargetLowering(TM, STI); 536 } 537 538 // Create a fast isel object. 539 FastISel * 540 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 541 const TargetLibraryInfo *libInfo) const { 542 const MipsTargetMachine &TM = 543 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget()); 544 545 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs. 546 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() && 547 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() && 548 !Subtarget.inMicroMipsMode(); 549 550 // Disable if either of the following is true: 551 // We do not generate PIC, the ABI is not O32, LargeGOT is being used. 552 if (!TM.isPositionIndependent() || !TM.getABI().IsO32() || LargeGOT) 553 UseFastISel = false; 554 555 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr; 556 } 557 558 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, 559 EVT VT) const { 560 if (!VT.isVector()) 561 return MVT::i32; 562 return VT.changeVectorElementTypeToInteger(); 563 } 564 565 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 566 TargetLowering::DAGCombinerInfo &DCI, 567 const MipsSubtarget &Subtarget) { 568 if (DCI.isBeforeLegalizeOps()) 569 return SDValue(); 570 571 EVT Ty = N->getValueType(0); 572 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 573 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 574 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 575 MipsISD::DivRemU16; 576 SDLoc DL(N); 577 578 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 579 N->getOperand(0), N->getOperand(1)); 580 SDValue InChain = DAG.getEntryNode(); 581 SDValue InGlue = DivRem; 582 583 // insert MFLO 584 if (N->hasAnyUseOfValue(0)) { 585 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 586 InGlue); 587 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 588 InChain = CopyFromLo.getValue(1); 589 InGlue = CopyFromLo.getValue(2); 590 } 591 592 // insert MFHI 593 if (N->hasAnyUseOfValue(1)) { 594 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 595 HI, Ty, InGlue); 596 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 597 } 598 599 return SDValue(); 600 } 601 602 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 603 switch (CC) { 604 default: llvm_unreachable("Unknown fp condition code!"); 605 case ISD::SETEQ: 606 case ISD::SETOEQ: return Mips::FCOND_OEQ; 607 case ISD::SETUNE: return Mips::FCOND_UNE; 608 case ISD::SETLT: 609 case ISD::SETOLT: return Mips::FCOND_OLT; 610 case ISD::SETGT: 611 case ISD::SETOGT: return Mips::FCOND_OGT; 612 case ISD::SETLE: 613 case ISD::SETOLE: return Mips::FCOND_OLE; 614 case ISD::SETGE: 615 case ISD::SETOGE: return Mips::FCOND_OGE; 616 case ISD::SETULT: return Mips::FCOND_ULT; 617 case ISD::SETULE: return Mips::FCOND_ULE; 618 case ISD::SETUGT: return Mips::FCOND_UGT; 619 case ISD::SETUGE: return Mips::FCOND_UGE; 620 case ISD::SETUO: return Mips::FCOND_UN; 621 case ISD::SETO: return Mips::FCOND_OR; 622 case ISD::SETNE: 623 case ISD::SETONE: return Mips::FCOND_ONE; 624 case ISD::SETUEQ: return Mips::FCOND_UEQ; 625 } 626 } 627 628 /// This function returns true if the floating point conditional branches and 629 /// conditional moves which use condition code CC should be inverted. 630 static bool invertFPCondCodeUser(Mips::CondCode CC) { 631 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 632 return false; 633 634 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 635 "Illegal Condition Code"); 636 637 return true; 638 } 639 640 // Creates and returns an FPCmp node from a setcc node. 641 // Returns Op if setcc is not a floating point comparison. 642 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 643 // must be a SETCC node 644 if (Op.getOpcode() != ISD::SETCC) 645 return Op; 646 647 SDValue LHS = Op.getOperand(0); 648 649 if (!LHS.getValueType().isFloatingPoint()) 650 return Op; 651 652 SDValue RHS = Op.getOperand(1); 653 SDLoc DL(Op); 654 655 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 656 // node if necessary. 657 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 658 659 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 660 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); 661 } 662 663 // Creates and returns a CMovFPT/F node. 664 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 665 SDValue False, const SDLoc &DL) { 666 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 667 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 668 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 669 670 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 671 True.getValueType(), True, FCC0, False, Cond); 672 } 673 674 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 675 TargetLowering::DAGCombinerInfo &DCI, 676 const MipsSubtarget &Subtarget) { 677 if (DCI.isBeforeLegalizeOps()) 678 return SDValue(); 679 680 SDValue SetCC = N->getOperand(0); 681 682 if ((SetCC.getOpcode() != ISD::SETCC) || 683 !SetCC.getOperand(0).getValueType().isInteger()) 684 return SDValue(); 685 686 SDValue False = N->getOperand(2); 687 EVT FalseTy = False.getValueType(); 688 689 if (!FalseTy.isInteger()) 690 return SDValue(); 691 692 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); 693 694 // If the RHS (False) is 0, we swap the order of the operands 695 // of ISD::SELECT (obviously also inverting the condition) so that we can 696 // take advantage of conditional moves using the $0 register. 697 // Example: 698 // return (a != 0) ? x : 0; 699 // load $reg, x 700 // movz $reg, $0, a 701 if (!FalseC) 702 return SDValue(); 703 704 const SDLoc DL(N); 705 706 if (!FalseC->getZExtValue()) { 707 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 708 SDValue True = N->getOperand(1); 709 710 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 711 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 712 713 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 714 } 715 716 // If both operands are integer constants there's a possibility that we 717 // can do some interesting optimizations. 718 SDValue True = N->getOperand(1); 719 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); 720 721 if (!TrueC || !True.getValueType().isInteger()) 722 return SDValue(); 723 724 // We'll also ignore MVT::i64 operands as this optimizations proves 725 // to be ineffective because of the required sign extensions as the result 726 // of a SETCC operator is always MVT::i32 for non-vector types. 727 if (True.getValueType() == MVT::i64) 728 return SDValue(); 729 730 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); 731 732 // 1) (a < x) ? y : y-1 733 // slti $reg1, a, x 734 // addiu $reg2, $reg1, y-1 735 if (Diff == 1) 736 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); 737 738 // 2) (a < x) ? y-1 : y 739 // slti $reg1, a, x 740 // xor $reg1, $reg1, 1 741 // addiu $reg2, $reg1, y-1 742 if (Diff == -1) { 743 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 744 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 745 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 746 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); 747 } 748 749 // Could not optimize. 750 return SDValue(); 751 } 752 753 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, 754 TargetLowering::DAGCombinerInfo &DCI, 755 const MipsSubtarget &Subtarget) { 756 if (DCI.isBeforeLegalizeOps()) 757 return SDValue(); 758 759 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); 760 761 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse); 762 if (!FalseC || FalseC->getZExtValue()) 763 return SDValue(); 764 765 // Since RHS (False) is 0, we swap the order of the True/False operands 766 // (obviously also inverting the condition) so that we can 767 // take advantage of conditional moves using the $0 register. 768 // Example: 769 // return (a != 0) ? x : 0; 770 // load $reg, x 771 // movz $reg, $0, a 772 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : 773 MipsISD::CMovFP_T; 774 775 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); 776 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(), 777 ValueIfFalse, FCC, ValueIfTrue, Glue); 778 } 779 780 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 781 TargetLowering::DAGCombinerInfo &DCI, 782 const MipsSubtarget &Subtarget) { 783 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 784 return SDValue(); 785 786 SDValue FirstOperand = N->getOperand(0); 787 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 788 SDValue Mask = N->getOperand(1); 789 EVT ValTy = N->getValueType(0); 790 SDLoc DL(N); 791 792 uint64_t Pos = 0, SMPos, SMSize; 793 ConstantSDNode *CN; 794 SDValue NewOperand; 795 unsigned Opc; 796 797 // Op's second operand must be a shifted mask. 798 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 799 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 800 return SDValue(); 801 802 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { 803 // Pattern match EXT. 804 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 805 // => ext $dst, $src, pos, size 806 807 // The second operand of the shift must be an immediate. 808 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 809 return SDValue(); 810 811 Pos = CN->getZExtValue(); 812 813 // Return if the shifted mask does not start at bit 0 or the sum of its size 814 // and Pos exceeds the word's size. 815 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 816 return SDValue(); 817 818 Opc = MipsISD::Ext; 819 NewOperand = FirstOperand.getOperand(0); 820 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) { 821 // Pattern match CINS. 822 // $dst = and (shl $src , pos), mask 823 // => cins $dst, $src, pos, size 824 // mask is a shifted mask with consecutive 1's, pos = shift amount, 825 // size = population count. 826 827 // The second operand of the shift must be an immediate. 828 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 829 return SDValue(); 830 831 Pos = CN->getZExtValue(); 832 833 if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 || 834 Pos + SMSize > ValTy.getSizeInBits()) 835 return SDValue(); 836 837 NewOperand = FirstOperand.getOperand(0); 838 // SMSize is 'location' (position) in this case, not size. 839 SMSize--; 840 Opc = MipsISD::CIns; 841 } else { 842 // Pattern match EXT. 843 // $dst = and $src, (2**size - 1) , if size > 16 844 // => ext $dst, $src, pos, size , pos = 0 845 846 // If the mask is <= 0xffff, andi can be used instead. 847 if (CN->getZExtValue() <= 0xffff) 848 return SDValue(); 849 850 // Return if the mask doesn't start at position 0. 851 if (SMPos) 852 return SDValue(); 853 854 Opc = MipsISD::Ext; 855 NewOperand = FirstOperand; 856 } 857 return DAG.getNode(Opc, DL, ValTy, NewOperand, 858 DAG.getConstant(Pos, DL, MVT::i32), 859 DAG.getConstant(SMSize, DL, MVT::i32)); 860 } 861 862 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 863 TargetLowering::DAGCombinerInfo &DCI, 864 const MipsSubtarget &Subtarget) { 865 // Pattern match INS. 866 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 867 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 868 // => ins $dst, $src, size, pos, $src1 869 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 870 return SDValue(); 871 872 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 873 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 874 ConstantSDNode *CN, *CN1; 875 876 // See if Op's first operand matches (and $src1 , mask0). 877 if (And0.getOpcode() != ISD::AND) 878 return SDValue(); 879 880 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 881 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 882 return SDValue(); 883 884 // See if Op's second operand matches (and (shl $src, pos), mask1). 885 if (And1.getOpcode() == ISD::AND && 886 And1.getOperand(0).getOpcode() == ISD::SHL) { 887 888 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 889 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 890 return SDValue(); 891 892 // The shift masks must have the same position and size. 893 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 894 return SDValue(); 895 896 SDValue Shl = And1.getOperand(0); 897 898 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 899 return SDValue(); 900 901 unsigned Shamt = CN->getZExtValue(); 902 903 // Return if the shift amount and the first bit position of mask are not the 904 // same. 905 EVT ValTy = N->getValueType(0); 906 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 907 return SDValue(); 908 909 SDLoc DL(N); 910 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0), 911 DAG.getConstant(SMPos0, DL, MVT::i32), 912 DAG.getConstant(SMSize0, DL, MVT::i32), 913 And0.getOperand(0)); 914 } else { 915 // Pattern match DINS. 916 // $dst = or (and $src, mask0), mask1 917 // where mask0 = ((1 << SMSize0) -1) << SMPos0 918 // => dins $dst, $src, pos, size 919 if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) && 920 ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) || 921 (SMSize0 + SMPos0 <= 32))) { 922 // Check if AND instruction has constant as argument 923 bool isConstCase = And1.getOpcode() != ISD::AND; 924 if (And1.getOpcode() == ISD::AND) { 925 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1)))) 926 return SDValue(); 927 } else { 928 if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1)))) 929 return SDValue(); 930 } 931 // Don't generate INS if constant OR operand doesn't fit into bits 932 // cleared by constant AND operand. 933 if (CN->getSExtValue() & CN1->getSExtValue()) 934 return SDValue(); 935 936 SDLoc DL(N); 937 EVT ValTy = N->getOperand(0)->getValueType(0); 938 SDValue Const1; 939 SDValue SrlX; 940 if (!isConstCase) { 941 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32); 942 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); 943 } 944 return DAG.getNode( 945 MipsISD::Ins, DL, N->getValueType(0), 946 isConstCase 947 ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy) 948 : SrlX, 949 DAG.getConstant(SMPos0, DL, MVT::i32), 950 DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31 951 : SMSize0, 952 DL, MVT::i32), 953 And0->getOperand(0)); 954 955 } 956 return SDValue(); 957 } 958 } 959 960 static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, 961 const MipsSubtarget &Subtarget) { 962 // ROOTNode must have a multiplication as an operand for the match to be 963 // successful. 964 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL && 965 ROOTNode->getOperand(1).getOpcode() != ISD::MUL) 966 return SDValue(); 967 968 // We don't handle vector types here. 969 if (ROOTNode->getValueType(0).isVector()) 970 return SDValue(); 971 972 // For MIPS64, madd / msub instructions are inefficent to use with 64 bit 973 // arithmetic. E.g. 974 // (add (mul a b) c) => 975 // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in 976 // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32) 977 // or 978 // MIPS64R2: (dins (mflo res) (mfhi res) 32 32) 979 // 980 // The overhead of setting up the Hi/Lo registers and reassembling the 981 // result makes this a dubious optimzation for MIPS64. The core of the 982 // problem is that Hi/Lo contain the upper and lower 32 bits of the 983 // operand and result. 984 // 985 // It requires a chain of 4 add/mul for MIPS64R2 to get better code 986 // density than doing it naively, 5 for MIPS64. Additionally, using 987 // madd/msub on MIPS64 requires the operands actually be 32 bit sign 988 // extended operands, not true 64 bit values. 989 // 990 // FIXME: For the moment, disable this completely for MIPS64. 991 if (Subtarget.hasMips64()) 992 return SDValue(); 993 994 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 995 ? ROOTNode->getOperand(0) 996 : ROOTNode->getOperand(1); 997 998 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 999 ? ROOTNode->getOperand(1) 1000 : ROOTNode->getOperand(0); 1001 1002 // Transform this to a MADD only if the user of this node is the add. 1003 // If there are other users of the mul, this function returns here. 1004 if (!Mult.hasOneUse()) 1005 return SDValue(); 1006 1007 // maddu and madd are unusual instructions in that on MIPS64 bits 63..31 1008 // must be in canonical form, i.e. sign extended. For MIPS32, the operands 1009 // of the multiply must have 32 or more sign bits, otherwise we cannot 1010 // perform this optimization. We have to check this here as we're performing 1011 // this optimization pre-legalization. 1012 SDValue MultLHS = Mult->getOperand(0); 1013 SDValue MultRHS = Mult->getOperand(1); 1014 1015 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND && 1016 MultRHS->getOpcode() == ISD::SIGN_EXTEND; 1017 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND && 1018 MultRHS->getOpcode() == ISD::ZERO_EXTEND; 1019 1020 if (!IsSigned && !IsUnsigned) 1021 return SDValue(); 1022 1023 // Initialize accumulator. 1024 SDLoc DL(ROOTNode); 1025 SDValue TopHalf; 1026 SDValue BottomHalf; 1027 BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, 1028 CurDAG.getIntPtrConstant(0, DL)); 1029 1030 TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, 1031 CurDAG.getIntPtrConstant(1, DL)); 1032 SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, 1033 BottomHalf, 1034 TopHalf); 1035 1036 // Create MipsMAdd(u) / MipsMSub(u) node. 1037 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD; 1038 unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd) 1039 : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub); 1040 SDValue MAddOps[3] = { 1041 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)), 1042 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn}; 1043 EVT VTs[2] = {MVT::i32, MVT::i32}; 1044 SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps); 1045 1046 SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); 1047 SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); 1048 SDValue Combined = 1049 CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi); 1050 return Combined; 1051 } 1052 1053 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, 1054 TargetLowering::DAGCombinerInfo &DCI, 1055 const MipsSubtarget &Subtarget) { 1056 // (sub v0 (mul v1, v2)) => (msub v1, v2, v0) 1057 if (DCI.isBeforeLegalizeOps()) { 1058 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1059 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1060 return performMADD_MSUBCombine(N, DAG, Subtarget); 1061 1062 return SDValue(); 1063 } 1064 1065 return SDValue(); 1066 } 1067 1068 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 1069 TargetLowering::DAGCombinerInfo &DCI, 1070 const MipsSubtarget &Subtarget) { 1071 // (add v0 (mul v1, v2)) => (madd v1, v2, v0) 1072 if (DCI.isBeforeLegalizeOps()) { 1073 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1074 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1075 return performMADD_MSUBCombine(N, DAG, Subtarget); 1076 1077 return SDValue(); 1078 } 1079 1080 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 1081 SDValue Add = N->getOperand(1); 1082 1083 if (Add.getOpcode() != ISD::ADD) 1084 return SDValue(); 1085 1086 SDValue Lo = Add.getOperand(1); 1087 1088 if ((Lo.getOpcode() != MipsISD::Lo) || 1089 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 1090 return SDValue(); 1091 1092 EVT ValTy = N->getValueType(0); 1093 SDLoc DL(N); 1094 1095 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 1096 Add.getOperand(0)); 1097 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 1098 } 1099 1100 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, 1101 TargetLowering::DAGCombinerInfo &DCI, 1102 const MipsSubtarget &Subtarget) { 1103 // Pattern match CINS. 1104 // $dst = shl (and $src , imm), pos 1105 // => cins $dst, $src, pos, size 1106 1107 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips()) 1108 return SDValue(); 1109 1110 SDValue FirstOperand = N->getOperand(0); 1111 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 1112 SDValue SecondOperand = N->getOperand(1); 1113 EVT ValTy = N->getValueType(0); 1114 SDLoc DL(N); 1115 1116 uint64_t Pos = 0, SMPos, SMSize; 1117 ConstantSDNode *CN; 1118 SDValue NewOperand; 1119 1120 // The second operand of the shift must be an immediate. 1121 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand))) 1122 return SDValue(); 1123 1124 Pos = CN->getZExtValue(); 1125 1126 if (Pos >= ValTy.getSizeInBits()) 1127 return SDValue(); 1128 1129 if (FirstOperandOpc != ISD::AND) 1130 return SDValue(); 1131 1132 // AND's second operand must be a shifted mask. 1133 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) || 1134 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 1135 return SDValue(); 1136 1137 // Return if the shifted mask does not start at bit 0 or the sum of its size 1138 // and Pos exceeds the word's size. 1139 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits()) 1140 return SDValue(); 1141 1142 NewOperand = FirstOperand.getOperand(0); 1143 // SMSize is 'location' (position) in this case, not size. 1144 SMSize--; 1145 1146 return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand, 1147 DAG.getConstant(Pos, DL, MVT::i32), 1148 DAG.getConstant(SMSize, DL, MVT::i32)); 1149 } 1150 1151 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 1152 const { 1153 SelectionDAG &DAG = DCI.DAG; 1154 unsigned Opc = N->getOpcode(); 1155 1156 switch (Opc) { 1157 default: break; 1158 case ISD::SDIVREM: 1159 case ISD::UDIVREM: 1160 return performDivRemCombine(N, DAG, DCI, Subtarget); 1161 case ISD::SELECT: 1162 return performSELECTCombine(N, DAG, DCI, Subtarget); 1163 case MipsISD::CMovFP_F: 1164 case MipsISD::CMovFP_T: 1165 return performCMovFPCombine(N, DAG, DCI, Subtarget); 1166 case ISD::AND: 1167 return performANDCombine(N, DAG, DCI, Subtarget); 1168 case ISD::OR: 1169 return performORCombine(N, DAG, DCI, Subtarget); 1170 case ISD::ADD: 1171 return performADDCombine(N, DAG, DCI, Subtarget); 1172 case ISD::SHL: 1173 return performSHLCombine(N, DAG, DCI, Subtarget); 1174 case ISD::SUB: 1175 return performSUBCombine(N, DAG, DCI, Subtarget); 1176 } 1177 1178 return SDValue(); 1179 } 1180 1181 bool MipsTargetLowering::isCheapToSpeculateCttz() const { 1182 return Subtarget.hasMips32(); 1183 } 1184 1185 bool MipsTargetLowering::isCheapToSpeculateCtlz() const { 1186 return Subtarget.hasMips32(); 1187 } 1188 1189 void 1190 MipsTargetLowering::LowerOperationWrapper(SDNode *N, 1191 SmallVectorImpl<SDValue> &Results, 1192 SelectionDAG &DAG) const { 1193 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 1194 1195 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 1196 Results.push_back(Res.getValue(I)); 1197 } 1198 1199 void 1200 MipsTargetLowering::ReplaceNodeResults(SDNode *N, 1201 SmallVectorImpl<SDValue> &Results, 1202 SelectionDAG &DAG) const { 1203 return LowerOperationWrapper(N, Results, DAG); 1204 } 1205 1206 SDValue MipsTargetLowering:: 1207 LowerOperation(SDValue Op, SelectionDAG &DAG) const 1208 { 1209 switch (Op.getOpcode()) 1210 { 1211 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 1212 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 1213 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 1214 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 1215 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 1216 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 1217 case ISD::SELECT: return lowerSELECT(Op, DAG); 1218 case ISD::SETCC: return lowerSETCC(Op, DAG); 1219 case ISD::VASTART: return lowerVASTART(Op, DAG); 1220 case ISD::VAARG: return lowerVAARG(Op, DAG); 1221 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 1222 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 1223 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 1224 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 1225 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 1226 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 1227 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 1228 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 1229 case ISD::LOAD: return lowerLOAD(Op, DAG); 1230 case ISD::STORE: return lowerSTORE(Op, DAG); 1231 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG); 1232 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 1233 } 1234 return SDValue(); 1235 } 1236 1237 //===----------------------------------------------------------------------===// 1238 // Lower helper functions 1239 //===----------------------------------------------------------------------===// 1240 1241 // addLiveIn - This helper function adds the specified physical register to the 1242 // MachineFunction as a live in value. It also creates a corresponding 1243 // virtual register for it. 1244 static unsigned 1245 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 1246 { 1247 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 1248 MF.getRegInfo().addLiveIn(PReg, VReg); 1249 return VReg; 1250 } 1251 1252 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI, 1253 MachineBasicBlock &MBB, 1254 const TargetInstrInfo &TII, 1255 bool Is64Bit, bool IsMicroMips) { 1256 if (NoZeroDivCheck) 1257 return &MBB; 1258 1259 // Insert instruction "teq $divisor_reg, $zero, 7". 1260 MachineBasicBlock::iterator I(MI); 1261 MachineInstrBuilder MIB; 1262 MachineOperand &Divisor = MI.getOperand(2); 1263 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(), 1264 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ)) 1265 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 1266 .addReg(Mips::ZERO) 1267 .addImm(7); 1268 1269 // Use the 32-bit sub-register if this is a 64-bit division. 1270 if (Is64Bit) 1271 MIB->getOperand(0).setSubReg(Mips::sub_32); 1272 1273 // Clear Divisor's kill flag. 1274 Divisor.setIsKill(false); 1275 1276 // We would normally delete the original instruction here but in this case 1277 // we only needed to inject an additional instruction rather than replace it. 1278 1279 return &MBB; 1280 } 1281 1282 MachineBasicBlock * 1283 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 1284 MachineBasicBlock *BB) const { 1285 switch (MI.getOpcode()) { 1286 default: 1287 llvm_unreachable("Unexpected instr type to insert"); 1288 case Mips::ATOMIC_LOAD_ADD_I8: 1289 return emitAtomicBinaryPartword(MI, BB, 1); 1290 case Mips::ATOMIC_LOAD_ADD_I16: 1291 return emitAtomicBinaryPartword(MI, BB, 2); 1292 case Mips::ATOMIC_LOAD_ADD_I32: 1293 return emitAtomicBinary(MI, BB); 1294 case Mips::ATOMIC_LOAD_ADD_I64: 1295 return emitAtomicBinary(MI, BB); 1296 1297 case Mips::ATOMIC_LOAD_AND_I8: 1298 return emitAtomicBinaryPartword(MI, BB, 1); 1299 case Mips::ATOMIC_LOAD_AND_I16: 1300 return emitAtomicBinaryPartword(MI, BB, 2); 1301 case Mips::ATOMIC_LOAD_AND_I32: 1302 return emitAtomicBinary(MI, BB); 1303 case Mips::ATOMIC_LOAD_AND_I64: 1304 return emitAtomicBinary(MI, BB); 1305 1306 case Mips::ATOMIC_LOAD_OR_I8: 1307 return emitAtomicBinaryPartword(MI, BB, 1); 1308 case Mips::ATOMIC_LOAD_OR_I16: 1309 return emitAtomicBinaryPartword(MI, BB, 2); 1310 case Mips::ATOMIC_LOAD_OR_I32: 1311 return emitAtomicBinary(MI, BB); 1312 case Mips::ATOMIC_LOAD_OR_I64: 1313 return emitAtomicBinary(MI, BB); 1314 1315 case Mips::ATOMIC_LOAD_XOR_I8: 1316 return emitAtomicBinaryPartword(MI, BB, 1); 1317 case Mips::ATOMIC_LOAD_XOR_I16: 1318 return emitAtomicBinaryPartword(MI, BB, 2); 1319 case Mips::ATOMIC_LOAD_XOR_I32: 1320 return emitAtomicBinary(MI, BB); 1321 case Mips::ATOMIC_LOAD_XOR_I64: 1322 return emitAtomicBinary(MI, BB); 1323 1324 case Mips::ATOMIC_LOAD_NAND_I8: 1325 return emitAtomicBinaryPartword(MI, BB, 1); 1326 case Mips::ATOMIC_LOAD_NAND_I16: 1327 return emitAtomicBinaryPartword(MI, BB, 2); 1328 case Mips::ATOMIC_LOAD_NAND_I32: 1329 return emitAtomicBinary(MI, BB); 1330 case Mips::ATOMIC_LOAD_NAND_I64: 1331 return emitAtomicBinary(MI, BB); 1332 1333 case Mips::ATOMIC_LOAD_SUB_I8: 1334 return emitAtomicBinaryPartword(MI, BB, 1); 1335 case Mips::ATOMIC_LOAD_SUB_I16: 1336 return emitAtomicBinaryPartword(MI, BB, 2); 1337 case Mips::ATOMIC_LOAD_SUB_I32: 1338 return emitAtomicBinary(MI, BB); 1339 case Mips::ATOMIC_LOAD_SUB_I64: 1340 return emitAtomicBinary(MI, BB); 1341 1342 case Mips::ATOMIC_SWAP_I8: 1343 return emitAtomicBinaryPartword(MI, BB, 1); 1344 case Mips::ATOMIC_SWAP_I16: 1345 return emitAtomicBinaryPartword(MI, BB, 2); 1346 case Mips::ATOMIC_SWAP_I32: 1347 return emitAtomicBinary(MI, BB); 1348 case Mips::ATOMIC_SWAP_I64: 1349 return emitAtomicBinary(MI, BB); 1350 1351 case Mips::ATOMIC_CMP_SWAP_I8: 1352 return emitAtomicCmpSwapPartword(MI, BB, 1); 1353 case Mips::ATOMIC_CMP_SWAP_I16: 1354 return emitAtomicCmpSwapPartword(MI, BB, 2); 1355 case Mips::ATOMIC_CMP_SWAP_I32: 1356 return emitAtomicCmpSwap(MI, BB); 1357 case Mips::ATOMIC_CMP_SWAP_I64: 1358 return emitAtomicCmpSwap(MI, BB); 1359 case Mips::PseudoSDIV: 1360 case Mips::PseudoUDIV: 1361 case Mips::DIV: 1362 case Mips::DIVU: 1363 case Mips::MOD: 1364 case Mips::MODU: 1365 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, 1366 false); 1367 case Mips::SDIV_MM_Pseudo: 1368 case Mips::UDIV_MM_Pseudo: 1369 case Mips::SDIV_MM: 1370 case Mips::UDIV_MM: 1371 case Mips::DIV_MMR6: 1372 case Mips::DIVU_MMR6: 1373 case Mips::MOD_MMR6: 1374 case Mips::MODU_MMR6: 1375 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); 1376 case Mips::PseudoDSDIV: 1377 case Mips::PseudoDUDIV: 1378 case Mips::DDIV: 1379 case Mips::DDIVU: 1380 case Mips::DMOD: 1381 case Mips::DMODU: 1382 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); 1383 1384 case Mips::PseudoSELECT_I: 1385 case Mips::PseudoSELECT_I64: 1386 case Mips::PseudoSELECT_S: 1387 case Mips::PseudoSELECT_D32: 1388 case Mips::PseudoSELECT_D64: 1389 return emitPseudoSELECT(MI, BB, false, Mips::BNE); 1390 case Mips::PseudoSELECTFP_F_I: 1391 case Mips::PseudoSELECTFP_F_I64: 1392 case Mips::PseudoSELECTFP_F_S: 1393 case Mips::PseudoSELECTFP_F_D32: 1394 case Mips::PseudoSELECTFP_F_D64: 1395 return emitPseudoSELECT(MI, BB, true, Mips::BC1F); 1396 case Mips::PseudoSELECTFP_T_I: 1397 case Mips::PseudoSELECTFP_T_I64: 1398 case Mips::PseudoSELECTFP_T_S: 1399 case Mips::PseudoSELECTFP_T_D32: 1400 case Mips::PseudoSELECTFP_T_D64: 1401 return emitPseudoSELECT(MI, BB, true, Mips::BC1T); 1402 case Mips::PseudoD_SELECT_I: 1403 case Mips::PseudoD_SELECT_I64: 1404 return emitPseudoD_SELECT(MI, BB); 1405 } 1406 } 1407 1408 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1409 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1410 MachineBasicBlock * 1411 MipsTargetLowering::emitAtomicBinary(MachineInstr &MI, 1412 MachineBasicBlock *BB) const { 1413 1414 MachineFunction *MF = BB->getParent(); 1415 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1416 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1417 DebugLoc DL = MI.getDebugLoc(); 1418 1419 unsigned AtomicOp; 1420 switch (MI.getOpcode()) { 1421 case Mips::ATOMIC_LOAD_ADD_I32: 1422 AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA; 1423 break; 1424 case Mips::ATOMIC_LOAD_SUB_I32: 1425 AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA; 1426 break; 1427 case Mips::ATOMIC_LOAD_AND_I32: 1428 AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA; 1429 break; 1430 case Mips::ATOMIC_LOAD_OR_I32: 1431 AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA; 1432 break; 1433 case Mips::ATOMIC_LOAD_XOR_I32: 1434 AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA; 1435 break; 1436 case Mips::ATOMIC_LOAD_NAND_I32: 1437 AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA; 1438 break; 1439 case Mips::ATOMIC_SWAP_I32: 1440 AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA; 1441 break; 1442 case Mips::ATOMIC_LOAD_ADD_I64: 1443 AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA; 1444 break; 1445 case Mips::ATOMIC_LOAD_SUB_I64: 1446 AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA; 1447 break; 1448 case Mips::ATOMIC_LOAD_AND_I64: 1449 AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA; 1450 break; 1451 case Mips::ATOMIC_LOAD_OR_I64: 1452 AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA; 1453 break; 1454 case Mips::ATOMIC_LOAD_XOR_I64: 1455 AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA; 1456 break; 1457 case Mips::ATOMIC_LOAD_NAND_I64: 1458 AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA; 1459 break; 1460 case Mips::ATOMIC_SWAP_I64: 1461 AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA; 1462 break; 1463 default: 1464 llvm_unreachable("Unknown pseudo atomic for replacement!"); 1465 } 1466 1467 unsigned OldVal = MI.getOperand(0).getReg(); 1468 unsigned Ptr = MI.getOperand(1).getReg(); 1469 unsigned Incr = MI.getOperand(2).getReg(); 1470 unsigned Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal)); 1471 1472 MachineBasicBlock::iterator II(MI); 1473 1474 // The scratch registers here with the EarlyClobber | Define | Implicit 1475 // flags is used to persuade the register allocator and the machine 1476 // verifier to accept the usage of this register. This has to be a real 1477 // register which has an UNDEF value but is dead after the instruction which 1478 // is unique among the registers chosen for the instruction. 1479 1480 // The EarlyClobber flag has the semantic properties that the operand it is 1481 // attached to is clobbered before the rest of the inputs are read. Hence it 1482 // must be unique among the operands to the instruction. 1483 // The Define flag is needed to coerce the machine verifier that an Undef 1484 // value isn't a problem. 1485 // The Dead flag is needed as the value in scratch isn't used by any other 1486 // instruction. Kill isn't used as Dead is more precise. 1487 // The implicit flag is here due to the interaction between the other flags 1488 // and the machine verifier. 1489 1490 // For correctness purpose, a new pseudo is introduced here. We need this 1491 // new pseudo, so that FastRegisterAllocator does not see an ll/sc sequence 1492 // that is spread over >1 basic blocks. A register allocator which 1493 // introduces (or any codegen infact) a store, can violate the expectations 1494 // of the hardware. 1495 // 1496 // An atomic read-modify-write sequence starts with a linked load 1497 // instruction and ends with a store conditional instruction. The atomic 1498 // read-modify-write sequence fails if any of the following conditions 1499 // occur between the execution of ll and sc: 1500 // * A coherent store is completed by another process or coherent I/O 1501 // module into the block of synchronizable physical memory containing 1502 // the word. The size and alignment of the block is 1503 // implementation-dependent. 1504 // * A coherent store is executed between an LL and SC sequence on the 1505 // same processor to the block of synchornizable physical memory 1506 // containing the word. 1507 // 1508 1509 unsigned PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr)); 1510 unsigned IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr)); 1511 1512 BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr); 1513 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr); 1514 1515 BuildMI(*BB, II, DL, TII->get(AtomicOp)) 1516 .addReg(OldVal, RegState::Define | RegState::EarlyClobber) 1517 .addReg(PtrCopy) 1518 .addReg(IncrCopy) 1519 .addReg(Scratch, RegState::Define | RegState::EarlyClobber | 1520 RegState::Implicit | RegState::Dead); 1521 1522 MI.eraseFromParent(); 1523 1524 return BB; 1525 } 1526 1527 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( 1528 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, 1529 unsigned SrcReg) const { 1530 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1531 const DebugLoc &DL = MI.getDebugLoc(); 1532 1533 if (Subtarget.hasMips32r2() && Size == 1) { 1534 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); 1535 return BB; 1536 } 1537 1538 if (Subtarget.hasMips32r2() && Size == 2) { 1539 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); 1540 return BB; 1541 } 1542 1543 MachineFunction *MF = BB->getParent(); 1544 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1545 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1546 unsigned ScrReg = RegInfo.createVirtualRegister(RC); 1547 1548 assert(Size < 32); 1549 int64_t ShiftImm = 32 - (Size * 8); 1550 1551 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); 1552 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); 1553 1554 return BB; 1555 } 1556 1557 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( 1558 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1559 assert((Size == 1 || Size == 2) && 1560 "Unsupported size for EmitAtomicBinaryPartial."); 1561 1562 MachineFunction *MF = BB->getParent(); 1563 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1564 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1565 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1566 const TargetRegisterClass *RCp = 1567 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1568 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1569 DebugLoc DL = MI.getDebugLoc(); 1570 1571 unsigned Dest = MI.getOperand(0).getReg(); 1572 unsigned Ptr = MI.getOperand(1).getReg(); 1573 unsigned Incr = MI.getOperand(2).getReg(); 1574 1575 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1576 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1577 unsigned Mask = RegInfo.createVirtualRegister(RC); 1578 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1579 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1580 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1581 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1582 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1583 unsigned Scratch = RegInfo.createVirtualRegister(RC); 1584 unsigned Scratch2 = RegInfo.createVirtualRegister(RC); 1585 unsigned Scratch3 = RegInfo.createVirtualRegister(RC); 1586 1587 unsigned AtomicOp = 0; 1588 switch (MI.getOpcode()) { 1589 case Mips::ATOMIC_LOAD_NAND_I8: 1590 AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA; 1591 break; 1592 case Mips::ATOMIC_LOAD_NAND_I16: 1593 AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA; 1594 break; 1595 case Mips::ATOMIC_SWAP_I8: 1596 AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA; 1597 break; 1598 case Mips::ATOMIC_SWAP_I16: 1599 AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA; 1600 break; 1601 case Mips::ATOMIC_LOAD_ADD_I8: 1602 AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA; 1603 break; 1604 case Mips::ATOMIC_LOAD_ADD_I16: 1605 AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA; 1606 break; 1607 case Mips::ATOMIC_LOAD_SUB_I8: 1608 AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA; 1609 break; 1610 case Mips::ATOMIC_LOAD_SUB_I16: 1611 AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA; 1612 break; 1613 case Mips::ATOMIC_LOAD_AND_I8: 1614 AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA; 1615 break; 1616 case Mips::ATOMIC_LOAD_AND_I16: 1617 AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA; 1618 break; 1619 case Mips::ATOMIC_LOAD_OR_I8: 1620 AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA; 1621 break; 1622 case Mips::ATOMIC_LOAD_OR_I16: 1623 AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA; 1624 break; 1625 case Mips::ATOMIC_LOAD_XOR_I8: 1626 AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA; 1627 break; 1628 case Mips::ATOMIC_LOAD_XOR_I16: 1629 AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA; 1630 break; 1631 default: 1632 llvm_unreachable("Unknown subword atomic pseudo for expansion!"); 1633 } 1634 1635 // insert new blocks after the current block 1636 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1637 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1638 MachineFunction::iterator It = ++BB->getIterator(); 1639 MF->insert(It, exitMBB); 1640 1641 // Transfer the remainder of BB and its successor edges to exitMBB. 1642 exitMBB->splice(exitMBB->begin(), BB, 1643 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1644 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1645 1646 BB->addSuccessor(exitMBB, BranchProbability::getOne()); 1647 1648 // thisMBB: 1649 // addiu masklsb2,$0,-4 # 0xfffffffc 1650 // and alignedaddr,ptr,masklsb2 1651 // andi ptrlsb2,ptr,3 1652 // sll shiftamt,ptrlsb2,3 1653 // ori maskupper,$0,255 # 0xff 1654 // sll mask,maskupper,shiftamt 1655 // nor mask2,$0,mask 1656 // sll incr2,incr,shiftamt 1657 1658 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1659 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2) 1660 .addReg(ABI.GetNullPtr()).addImm(-4); 1661 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) 1662 .addReg(Ptr).addReg(MaskLSB2); 1663 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1664 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1665 if (Subtarget.isLittle()) { 1666 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1667 } else { 1668 unsigned Off = RegInfo.createVirtualRegister(RC); 1669 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1670 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1671 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1672 } 1673 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1674 .addReg(Mips::ZERO).addImm(MaskImm); 1675 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1676 .addReg(MaskUpper).addReg(ShiftAmt); 1677 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1678 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1679 1680 1681 // The purposes of the flags on the scratch registers is explained in 1682 // emitAtomicBinary. In summary, we need a scratch register which is going to 1683 // be undef, that is unique among registers chosen for the instruction. 1684 1685 BuildMI(BB, DL, TII->get(AtomicOp)) 1686 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 1687 .addReg(AlignedAddr) 1688 .addReg(Incr2) 1689 .addReg(Mask) 1690 .addReg(Mask2) 1691 .addReg(ShiftAmt) 1692 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 1693 RegState::Dead | RegState::Implicit) 1694 .addReg(Scratch2, RegState::EarlyClobber | RegState::Define | 1695 RegState::Dead | RegState::Implicit) 1696 .addReg(Scratch3, RegState::EarlyClobber | RegState::Define | 1697 RegState::Dead | RegState::Implicit); 1698 1699 MI.eraseFromParent(); // The instruction is gone now. 1700 1701 return exitMBB; 1702 } 1703 1704 // Lower atomic compare and swap to a pseudo instruction, taking care to 1705 // define a scratch register for the pseudo instruction's expansion. The 1706 // instruction is expanded after the register allocator as to prevent 1707 // the insertion of stores between the linked load and the store conditional. 1708 1709 MachineBasicBlock * 1710 MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, 1711 MachineBasicBlock *BB) const { 1712 1713 assert((MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 || 1714 MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) && 1715 "Unsupported atomic psseudo for EmitAtomicCmpSwap."); 1716 1717 const unsigned Size = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8; 1718 1719 MachineFunction *MF = BB->getParent(); 1720 MachineRegisterInfo &MRI = MF->getRegInfo(); 1721 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1722 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1723 DebugLoc DL = MI.getDebugLoc(); 1724 1725 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 1726 ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA 1727 : Mips::ATOMIC_CMP_SWAP_I64_POSTRA; 1728 unsigned Dest = MI.getOperand(0).getReg(); 1729 unsigned Ptr = MI.getOperand(1).getReg(); 1730 unsigned OldVal = MI.getOperand(2).getReg(); 1731 unsigned NewVal = MI.getOperand(3).getReg(); 1732 1733 unsigned Scratch = MRI.createVirtualRegister(RC); 1734 MachineBasicBlock::iterator II(MI); 1735 1736 // We need to create copies of the various registers and kill them at the 1737 // atomic pseudo. If the copies are not made, when the atomic is expanded 1738 // after fast register allocation, the spills will end up outside of the 1739 // blocks that their values are defined in, causing livein errors. 1740 1741 unsigned DestCopy = MRI.createVirtualRegister(MRI.getRegClass(Dest)); 1742 unsigned PtrCopy = MRI.createVirtualRegister(MRI.getRegClass(Ptr)); 1743 unsigned OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal)); 1744 unsigned NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal)); 1745 1746 BuildMI(*BB, II, DL, TII->get(Mips::COPY), DestCopy).addReg(Dest); 1747 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr); 1748 BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal); 1749 BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal); 1750 1751 // The purposes of the flags on the scratch registers is explained in 1752 // emitAtomicBinary. In summary, we need a scratch register which is going to 1753 // be undef, that is unique among registers chosen for the instruction. 1754 1755 BuildMI(*BB, II, DL, TII->get(AtomicOp)) 1756 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 1757 .addReg(PtrCopy, RegState::Kill) 1758 .addReg(OldValCopy, RegState::Kill) 1759 .addReg(NewValCopy, RegState::Kill) 1760 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 1761 RegState::Dead | RegState::Implicit); 1762 1763 MI.eraseFromParent(); // The instruction is gone now. 1764 1765 return BB; 1766 } 1767 1768 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword( 1769 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1770 assert((Size == 1 || Size == 2) && 1771 "Unsupported size for EmitAtomicCmpSwapPartial."); 1772 1773 MachineFunction *MF = BB->getParent(); 1774 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1775 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1776 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1777 const TargetRegisterClass *RCp = 1778 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1779 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1780 DebugLoc DL = MI.getDebugLoc(); 1781 1782 unsigned Dest = MI.getOperand(0).getReg(); 1783 unsigned Ptr = MI.getOperand(1).getReg(); 1784 unsigned CmpVal = MI.getOperand(2).getReg(); 1785 unsigned NewVal = MI.getOperand(3).getReg(); 1786 1787 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1788 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1789 unsigned Mask = RegInfo.createVirtualRegister(RC); 1790 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1791 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1792 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1793 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1794 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1795 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1796 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1797 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1798 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8 1799 ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA 1800 : Mips::ATOMIC_CMP_SWAP_I16_POSTRA; 1801 1802 // The scratch registers here with the EarlyClobber | Define | Dead | Implicit 1803 // flags are used to coerce the register allocator and the machine verifier to 1804 // accept the usage of these registers. 1805 // The EarlyClobber flag has the semantic properties that the operand it is 1806 // attached to is clobbered before the rest of the inputs are read. Hence it 1807 // must be unique among the operands to the instruction. 1808 // The Define flag is needed to coerce the machine verifier that an Undef 1809 // value isn't a problem. 1810 // The Dead flag is needed as the value in scratch isn't used by any other 1811 // instruction. Kill isn't used as Dead is more precise. 1812 unsigned Scratch = RegInfo.createVirtualRegister(RC); 1813 unsigned Scratch2 = RegInfo.createVirtualRegister(RC); 1814 1815 // insert new blocks after the current block 1816 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1817 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1818 MachineFunction::iterator It = ++BB->getIterator(); 1819 MF->insert(It, exitMBB); 1820 1821 // Transfer the remainder of BB and its successor edges to exitMBB. 1822 exitMBB->splice(exitMBB->begin(), BB, 1823 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1824 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1825 1826 BB->addSuccessor(exitMBB, BranchProbability::getOne()); 1827 1828 // thisMBB: 1829 // addiu masklsb2,$0,-4 # 0xfffffffc 1830 // and alignedaddr,ptr,masklsb2 1831 // andi ptrlsb2,ptr,3 1832 // xori ptrlsb2,ptrlsb2,3 # Only for BE 1833 // sll shiftamt,ptrlsb2,3 1834 // ori maskupper,$0,255 # 0xff 1835 // sll mask,maskupper,shiftamt 1836 // nor mask2,$0,mask 1837 // andi maskedcmpval,cmpval,255 1838 // sll shiftedcmpval,maskedcmpval,shiftamt 1839 // andi maskednewval,newval,255 1840 // sll shiftednewval,maskednewval,shiftamt 1841 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1842 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) 1843 .addReg(ABI.GetNullPtr()).addImm(-4); 1844 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) 1845 .addReg(Ptr).addReg(MaskLSB2); 1846 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1847 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1848 if (Subtarget.isLittle()) { 1849 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1850 } else { 1851 unsigned Off = RegInfo.createVirtualRegister(RC); 1852 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1853 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1854 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1855 } 1856 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1857 .addReg(Mips::ZERO).addImm(MaskImm); 1858 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1859 .addReg(MaskUpper).addReg(ShiftAmt); 1860 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1861 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1862 .addReg(CmpVal).addImm(MaskImm); 1863 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1864 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1865 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1866 .addReg(NewVal).addImm(MaskImm); 1867 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1868 .addReg(MaskedNewVal).addReg(ShiftAmt); 1869 1870 // The purposes of the flags on the scratch registers are explained in 1871 // emitAtomicBinary. In summary, we need a scratch register which is going to 1872 // be undef, that is unique among the register chosen for the instruction. 1873 1874 BuildMI(BB, DL, TII->get(AtomicOp)) 1875 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 1876 .addReg(AlignedAddr) 1877 .addReg(Mask) 1878 .addReg(ShiftedCmpVal) 1879 .addReg(Mask2) 1880 .addReg(ShiftedNewVal) 1881 .addReg(ShiftAmt) 1882 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 1883 RegState::Dead | RegState::Implicit) 1884 .addReg(Scratch2, RegState::EarlyClobber | RegState::Define | 1885 RegState::Dead | RegState::Implicit); 1886 1887 MI.eraseFromParent(); // The instruction is gone now. 1888 1889 return exitMBB; 1890 } 1891 1892 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 1893 // The first operand is the chain, the second is the condition, the third is 1894 // the block to branch to if the condition is true. 1895 SDValue Chain = Op.getOperand(0); 1896 SDValue Dest = Op.getOperand(2); 1897 SDLoc DL(Op); 1898 1899 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1900 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1901 1902 // Return if flag is not set by a floating point comparison. 1903 if (CondRes.getOpcode() != MipsISD::FPCmp) 1904 return Op; 1905 1906 SDValue CCNode = CondRes.getOperand(2); 1907 Mips::CondCode CC = 1908 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1909 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1910 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); 1911 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1912 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1913 FCC0, Dest, CondRes); 1914 } 1915 1916 SDValue MipsTargetLowering:: 1917 lowerSELECT(SDValue Op, SelectionDAG &DAG) const 1918 { 1919 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1920 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1921 1922 // Return if flag is not set by a floating point comparison. 1923 if (Cond.getOpcode() != MipsISD::FPCmp) 1924 return Op; 1925 1926 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1927 SDLoc(Op)); 1928 } 1929 1930 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1931 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1932 SDValue Cond = createFPCmp(DAG, Op); 1933 1934 assert(Cond.getOpcode() == MipsISD::FPCmp && 1935 "Floating point operand expected."); 1936 1937 SDLoc DL(Op); 1938 SDValue True = DAG.getConstant(1, DL, MVT::i32); 1939 SDValue False = DAG.getConstant(0, DL, MVT::i32); 1940 1941 return createCMovFP(DAG, Cond, True, False, DL); 1942 } 1943 1944 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 1945 SelectionDAG &DAG) const { 1946 EVT Ty = Op.getValueType(); 1947 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 1948 const GlobalValue *GV = N->getGlobal(); 1949 1950 if (!isPositionIndependent()) { 1951 const MipsTargetObjectFile *TLOF = 1952 static_cast<const MipsTargetObjectFile *>( 1953 getTargetMachine().getObjFileLowering()); 1954 const GlobalObject *GO = GV->getBaseObject(); 1955 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) 1956 // %gp_rel relocation 1957 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); 1958 1959 // %hi/%lo relocation 1960 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 1961 // %highest/%higher/%hi/%lo relocation 1962 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 1963 } 1964 1965 // Every other architecture would use shouldAssumeDSOLocal in here, but 1966 // mips is special. 1967 // * In PIC code mips requires got loads even for local statics! 1968 // * To save on got entries, for local statics the got entry contains the 1969 // page and an additional add instruction takes care of the low bits. 1970 // * It is legal to access a hidden symbol with a non hidden undefined, 1971 // so one cannot guarantee that all access to a hidden symbol will know 1972 // it is hidden. 1973 // * Mips linkers don't support creating a page and a full got entry for 1974 // the same symbol. 1975 // * Given all that, we have to use a full got entry for hidden symbols :-( 1976 if (GV->hasLocalLinkage()) 1977 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1978 1979 if (LargeGOT) 1980 return getAddrGlobalLargeGOT( 1981 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, 1982 DAG.getEntryNode(), 1983 MachinePointerInfo::getGOT(DAG.getMachineFunction())); 1984 1985 return getAddrGlobal( 1986 N, SDLoc(N), Ty, DAG, 1987 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT, 1988 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); 1989 } 1990 1991 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 1992 SelectionDAG &DAG) const { 1993 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 1994 EVT Ty = Op.getValueType(); 1995 1996 if (!isPositionIndependent()) 1997 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 1998 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 1999 2000 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2001 } 2002 2003 SDValue MipsTargetLowering:: 2004 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 2005 { 2006 // If the relocation model is PIC, use the General Dynamic TLS Model or 2007 // Local Dynamic TLS model, otherwise use the Initial Exec or 2008 // Local Exec TLS Model. 2009 2010 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2011 if (DAG.getTarget().useEmulatedTLS()) 2012 return LowerToTLSEmulatedModel(GA, DAG); 2013 2014 SDLoc DL(GA); 2015 const GlobalValue *GV = GA->getGlobal(); 2016 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 2017 2018 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 2019 2020 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 2021 // General Dynamic and Local Dynamic TLS Model. 2022 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 2023 : MipsII::MO_TLSGD; 2024 2025 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 2026 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 2027 getGlobalReg(DAG, PtrVT), TGA); 2028 unsigned PtrSize = PtrVT.getSizeInBits(); 2029 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 2030 2031 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 2032 2033 ArgListTy Args; 2034 ArgListEntry Entry; 2035 Entry.Node = Argument; 2036 Entry.Ty = PtrTy; 2037 Args.push_back(Entry); 2038 2039 TargetLowering::CallLoweringInfo CLI(DAG); 2040 CLI.setDebugLoc(DL) 2041 .setChain(DAG.getEntryNode()) 2042 .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); 2043 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 2044 2045 SDValue Ret = CallResult.first; 2046 2047 if (model != TLSModel::LocalDynamic) 2048 return Ret; 2049 2050 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2051 MipsII::MO_DTPREL_HI); 2052 SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); 2053 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2054 MipsII::MO_DTPREL_LO); 2055 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2056 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 2057 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 2058 } 2059 2060 SDValue Offset; 2061 if (model == TLSModel::InitialExec) { 2062 // Initial Exec TLS Model 2063 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2064 MipsII::MO_GOTTPREL); 2065 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 2066 TGA); 2067 Offset = 2068 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo()); 2069 } else { 2070 // Local Exec TLS Model 2071 assert(model == TLSModel::LocalExec); 2072 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2073 MipsII::MO_TPREL_HI); 2074 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2075 MipsII::MO_TPREL_LO); 2076 SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); 2077 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2078 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 2079 } 2080 2081 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 2082 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 2083 } 2084 2085 SDValue MipsTargetLowering:: 2086 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 2087 { 2088 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 2089 EVT Ty = Op.getValueType(); 2090 2091 if (!isPositionIndependent()) 2092 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2093 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2094 2095 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2096 } 2097 2098 SDValue MipsTargetLowering:: 2099 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 2100 { 2101 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 2102 EVT Ty = Op.getValueType(); 2103 2104 if (!isPositionIndependent()) { 2105 const MipsTargetObjectFile *TLOF = 2106 static_cast<const MipsTargetObjectFile *>( 2107 getTargetMachine().getObjFileLowering()); 2108 2109 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), 2110 getTargetMachine())) 2111 // %gp_rel relocation 2112 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); 2113 2114 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2115 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2116 } 2117 2118 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2119 } 2120 2121 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 2122 MachineFunction &MF = DAG.getMachineFunction(); 2123 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2124 2125 SDLoc DL(Op); 2126 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 2127 getPointerTy(MF.getDataLayout())); 2128 2129 // vastart just stores the address of the VarArgsFrameIndex slot into the 2130 // memory location argument. 2131 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2132 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 2133 MachinePointerInfo(SV)); 2134 } 2135 2136 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { 2137 SDNode *Node = Op.getNode(); 2138 EVT VT = Node->getValueType(0); 2139 SDValue Chain = Node->getOperand(0); 2140 SDValue VAListPtr = Node->getOperand(1); 2141 unsigned Align = Node->getConstantOperandVal(3); 2142 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2143 SDLoc DL(Node); 2144 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4; 2145 2146 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, 2147 VAListPtr, MachinePointerInfo(SV)); 2148 SDValue VAList = VAListLoad; 2149 2150 // Re-align the pointer if necessary. 2151 // It should only ever be necessary for 64-bit types on O32 since the minimum 2152 // argument alignment is the same as the maximum type alignment for N32/N64. 2153 // 2154 // FIXME: We currently align too often. The code generator doesn't notice 2155 // when the pointer is still aligned from the last va_arg (or pair of 2156 // va_args for the i64 on O32 case). 2157 if (Align > getMinStackArgumentAlignment()) { 2158 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 2159 2160 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 2161 DAG.getConstant(Align - 1, DL, VAList.getValueType())); 2162 2163 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList, 2164 DAG.getConstant(-(int64_t)Align, DL, 2165 VAList.getValueType())); 2166 } 2167 2168 // Increment the pointer, VAList, to the next vaarg. 2169 auto &TD = DAG.getDataLayout(); 2170 unsigned ArgSizeInBytes = 2171 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); 2172 SDValue Tmp3 = 2173 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 2174 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes), 2175 DL, VAList.getValueType())); 2176 // Store the incremented VAList to the legalized pointer 2177 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, 2178 MachinePointerInfo(SV)); 2179 2180 // In big-endian mode we must adjust the pointer when the load size is smaller 2181 // than the argument slot size. We must also reduce the known alignment to 2182 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get 2183 // the correct half of the slot, and reduce the alignment from 8 (slot 2184 // alignment) down to 4 (type alignment). 2185 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { 2186 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; 2187 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, 2188 DAG.getIntPtrConstant(Adjustment, DL)); 2189 } 2190 // Load the actual argument out of the pointer VAList 2191 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo()); 2192 } 2193 2194 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 2195 bool HasExtractInsert) { 2196 EVT TyX = Op.getOperand(0).getValueType(); 2197 EVT TyY = Op.getOperand(1).getValueType(); 2198 SDLoc DL(Op); 2199 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2200 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32); 2201 SDValue Res; 2202 2203 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2204 // to i32. 2205 SDValue X = (TyX == MVT::f32) ? 2206 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2207 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2208 Const1); 2209 SDValue Y = (TyY == MVT::f32) ? 2210 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 2211 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 2212 Const1); 2213 2214 if (HasExtractInsert) { 2215 // ext E, Y, 31, 1 ; extract bit31 of Y 2216 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 2217 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 2218 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 2219 } else { 2220 // sll SllX, X, 1 2221 // srl SrlX, SllX, 1 2222 // srl SrlY, Y, 31 2223 // sll SllY, SrlX, 31 2224 // or Or, SrlX, SllY 2225 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2226 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2227 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2228 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 2229 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2230 } 2231 2232 if (TyX == MVT::f32) 2233 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2234 2235 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2236 Op.getOperand(0), 2237 DAG.getConstant(0, DL, MVT::i32)); 2238 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2239 } 2240 2241 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 2242 bool HasExtractInsert) { 2243 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2244 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2245 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2246 SDLoc DL(Op); 2247 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2248 2249 // Bitcast to integer nodes. 2250 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2251 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2252 2253 if (HasExtractInsert) { 2254 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2255 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2256 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2257 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); 2258 2259 if (WidthX > WidthY) 2260 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2261 else if (WidthY > WidthX) 2262 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2263 2264 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2265 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, 2266 X); 2267 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2268 } 2269 2270 // (d)sll SllX, X, 1 2271 // (d)srl SrlX, SllX, 1 2272 // (d)srl SrlY, Y, width(Y)-1 2273 // (d)sll SllY, SrlX, width(Y)-1 2274 // or Or, SrlX, SllY 2275 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2276 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2277 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2278 DAG.getConstant(WidthY - 1, DL, MVT::i32)); 2279 2280 if (WidthX > WidthY) 2281 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2282 else if (WidthY > WidthX) 2283 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2284 2285 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2286 DAG.getConstant(WidthX - 1, DL, MVT::i32)); 2287 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2288 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2289 } 2290 2291 SDValue 2292 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2293 if (Subtarget.isGP64bit()) 2294 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); 2295 2296 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); 2297 } 2298 2299 SDValue MipsTargetLowering:: 2300 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2301 // check the depth 2302 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2303 "Frame address can only be determined for current frame."); 2304 2305 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2306 MFI.setFrameAddressIsTaken(true); 2307 EVT VT = Op.getValueType(); 2308 SDLoc DL(Op); 2309 SDValue FrameAddr = DAG.getCopyFromReg( 2310 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); 2311 return FrameAddr; 2312 } 2313 2314 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 2315 SelectionDAG &DAG) const { 2316 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 2317 return SDValue(); 2318 2319 // check the depth 2320 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2321 "Return address can be determined only for current frame."); 2322 2323 MachineFunction &MF = DAG.getMachineFunction(); 2324 MachineFrameInfo &MFI = MF.getFrameInfo(); 2325 MVT VT = Op.getSimpleValueType(); 2326 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; 2327 MFI.setReturnAddressIsTaken(true); 2328 2329 // Return RA, which contains the return address. Mark it an implicit live-in. 2330 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2331 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 2332 } 2333 2334 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is 2335 // generated from __builtin_eh_return (offset, handler) 2336 // The effect of this is to adjust the stack pointer by "offset" 2337 // and then branch to "handler". 2338 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 2339 const { 2340 MachineFunction &MF = DAG.getMachineFunction(); 2341 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2342 2343 MipsFI->setCallsEhReturn(); 2344 SDValue Chain = Op.getOperand(0); 2345 SDValue Offset = Op.getOperand(1); 2346 SDValue Handler = Op.getOperand(2); 2347 SDLoc DL(Op); 2348 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2349 2350 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2351 // EH_RETURN nodes, so that instructions are emitted back-to-back. 2352 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; 2353 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 2354 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 2355 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 2356 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 2357 DAG.getRegister(OffsetReg, Ty), 2358 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), 2359 Chain.getValue(1)); 2360 } 2361 2362 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 2363 SelectionDAG &DAG) const { 2364 // FIXME: Need pseudo-fence for 'singlethread' fences 2365 // FIXME: Set SType for weaker fences where supported/appropriate. 2366 unsigned SType = 0; 2367 SDLoc DL(Op); 2368 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 2369 DAG.getConstant(SType, DL, MVT::i32)); 2370 } 2371 2372 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 2373 SelectionDAG &DAG) const { 2374 SDLoc DL(Op); 2375 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2376 2377 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2378 SDValue Shamt = Op.getOperand(2); 2379 // if shamt < (VT.bits): 2380 // lo = (shl lo, shamt) 2381 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2382 // else: 2383 // lo = 0 2384 // hi = (shl lo, shamt[4:0]) 2385 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2386 DAG.getConstant(-1, DL, MVT::i32)); 2387 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, 2388 DAG.getConstant(1, DL, VT)); 2389 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); 2390 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); 2391 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2392 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); 2393 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2394 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2395 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2396 DAG.getConstant(0, DL, VT), ShiftLeftLo); 2397 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); 2398 2399 SDValue Ops[2] = {Lo, Hi}; 2400 return DAG.getMergeValues(Ops, DL); 2401 } 2402 2403 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2404 bool IsSRA) const { 2405 SDLoc DL(Op); 2406 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2407 SDValue Shamt = Op.getOperand(2); 2408 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2409 2410 // if shamt < (VT.bits): 2411 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2412 // if isSRA: 2413 // hi = (sra hi, shamt) 2414 // else: 2415 // hi = (srl hi, shamt) 2416 // else: 2417 // if isSRA: 2418 // lo = (sra hi, shamt[4:0]) 2419 // hi = (sra hi, 31) 2420 // else: 2421 // lo = (srl hi, shamt[4:0]) 2422 // hi = 0 2423 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2424 DAG.getConstant(-1, DL, MVT::i32)); 2425 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, 2426 DAG.getConstant(1, DL, VT)); 2427 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); 2428 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); 2429 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2430 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, 2431 DL, VT, Hi, Shamt); 2432 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2433 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2434 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, 2435 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); 2436 2437 if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) { 2438 SDVTList VTList = DAG.getVTList(VT, VT); 2439 return DAG.getNode(Subtarget.isGP64bit() ? Mips::PseudoD_SELECT_I64 2440 : Mips::PseudoD_SELECT_I, 2441 DL, VTList, Cond, ShiftRightHi, 2442 IsSRA ? Ext : DAG.getConstant(0, DL, VT), Or, 2443 ShiftRightHi); 2444 } 2445 2446 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); 2447 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2448 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); 2449 2450 SDValue Ops[2] = {Lo, Hi}; 2451 return DAG.getMergeValues(Ops, DL); 2452 } 2453 2454 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2455 SDValue Chain, SDValue Src, unsigned Offset) { 2456 SDValue Ptr = LD->getBasePtr(); 2457 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2458 EVT BasePtrVT = Ptr.getValueType(); 2459 SDLoc DL(LD); 2460 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2461 2462 if (Offset) 2463 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2464 DAG.getConstant(Offset, DL, BasePtrVT)); 2465 2466 SDValue Ops[] = { Chain, Ptr, Src }; 2467 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2468 LD->getMemOperand()); 2469 } 2470 2471 // Expand an unaligned 32 or 64-bit integer load node. 2472 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2473 LoadSDNode *LD = cast<LoadSDNode>(Op); 2474 EVT MemVT = LD->getMemoryVT(); 2475 2476 if (Subtarget.systemSupportsUnalignedAccess()) 2477 return Op; 2478 2479 // Return if load is aligned or if MemVT is neither i32 nor i64. 2480 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2481 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2482 return SDValue(); 2483 2484 bool IsLittle = Subtarget.isLittle(); 2485 EVT VT = Op.getValueType(); 2486 ISD::LoadExtType ExtType = LD->getExtensionType(); 2487 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2488 2489 assert((VT == MVT::i32) || (VT == MVT::i64)); 2490 2491 // Expand 2492 // (set dst, (i64 (load baseptr))) 2493 // to 2494 // (set tmp, (ldl (add baseptr, 7), undef)) 2495 // (set dst, (ldr baseptr, tmp)) 2496 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2497 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2498 IsLittle ? 7 : 0); 2499 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2500 IsLittle ? 0 : 7); 2501 } 2502 2503 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2504 IsLittle ? 3 : 0); 2505 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2506 IsLittle ? 0 : 3); 2507 2508 // Expand 2509 // (set dst, (i32 (load baseptr))) or 2510 // (set dst, (i64 (sextload baseptr))) or 2511 // (set dst, (i64 (extload baseptr))) 2512 // to 2513 // (set tmp, (lwl (add baseptr, 3), undef)) 2514 // (set dst, (lwr baseptr, tmp)) 2515 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2516 (ExtType == ISD::EXTLOAD)) 2517 return LWR; 2518 2519 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2520 2521 // Expand 2522 // (set dst, (i64 (zextload baseptr))) 2523 // to 2524 // (set tmp0, (lwl (add baseptr, 3), undef)) 2525 // (set tmp1, (lwr baseptr, tmp0)) 2526 // (set tmp2, (shl tmp1, 32)) 2527 // (set dst, (srl tmp2, 32)) 2528 SDLoc DL(LD); 2529 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32); 2530 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2531 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2532 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2533 return DAG.getMergeValues(Ops, DL); 2534 } 2535 2536 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2537 SDValue Chain, unsigned Offset) { 2538 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2539 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2540 SDLoc DL(SD); 2541 SDVTList VTList = DAG.getVTList(MVT::Other); 2542 2543 if (Offset) 2544 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2545 DAG.getConstant(Offset, DL, BasePtrVT)); 2546 2547 SDValue Ops[] = { Chain, Value, Ptr }; 2548 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2549 SD->getMemOperand()); 2550 } 2551 2552 // Expand an unaligned 32 or 64-bit integer store node. 2553 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2554 bool IsLittle) { 2555 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2556 EVT VT = Value.getValueType(); 2557 2558 // Expand 2559 // (store val, baseptr) or 2560 // (truncstore val, baseptr) 2561 // to 2562 // (swl val, (add baseptr, 3)) 2563 // (swr val, baseptr) 2564 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2565 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2566 IsLittle ? 3 : 0); 2567 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2568 } 2569 2570 assert(VT == MVT::i64); 2571 2572 // Expand 2573 // (store val, baseptr) 2574 // to 2575 // (sdl val, (add baseptr, 7)) 2576 // (sdr val, baseptr) 2577 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2578 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2579 } 2580 2581 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2582 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG, 2583 bool SingleFloat) { 2584 SDValue Val = SD->getValue(); 2585 2586 if (Val.getOpcode() != ISD::FP_TO_SINT || 2587 (Val.getValueSizeInBits() > 32 && SingleFloat)) 2588 return SDValue(); 2589 2590 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2591 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2592 Val.getOperand(0)); 2593 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2594 SD->getPointerInfo(), SD->getAlignment(), 2595 SD->getMemOperand()->getFlags()); 2596 } 2597 2598 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2599 StoreSDNode *SD = cast<StoreSDNode>(Op); 2600 EVT MemVT = SD->getMemoryVT(); 2601 2602 // Lower unaligned integer stores. 2603 if (!Subtarget.systemSupportsUnalignedAccess() && 2604 (SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2605 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2606 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); 2607 2608 return lowerFP_TO_SINT_STORE(SD, DAG, Subtarget.isSingleFloat()); 2609 } 2610 2611 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op, 2612 SelectionDAG &DAG) const { 2613 2614 // Return a fixed StackObject with offset 0 which points to the old stack 2615 // pointer. 2616 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2617 EVT ValTy = Op->getValueType(0); 2618 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2619 return DAG.getFrameIndex(FI, ValTy); 2620 } 2621 2622 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2623 SelectionDAG &DAG) const { 2624 if (Op.getValueSizeInBits() > 32 && Subtarget.isSingleFloat()) 2625 return SDValue(); 2626 2627 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2628 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2629 Op.getOperand(0)); 2630 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2631 } 2632 2633 //===----------------------------------------------------------------------===// 2634 // Calling Convention Implementation 2635 //===----------------------------------------------------------------------===// 2636 2637 //===----------------------------------------------------------------------===// 2638 // TODO: Implement a generic logic using tblgen that can support this. 2639 // Mips O32 ABI rules: 2640 // --- 2641 // i32 - Passed in A0, A1, A2, A3 and stack 2642 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 2643 // an argument. Otherwise, passed in A1, A2, A3 and stack. 2644 // f64 - Only passed in two aliased f32 registers if no int reg has been used 2645 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2646 // not used, it must be shadowed. If only A3 is available, shadow it and 2647 // go to stack. 2648 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack. 2649 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3} 2650 // with the remainder spilled to the stack. 2651 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases 2652 // spilling the remainder to the stack. 2653 // 2654 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2655 //===----------------------------------------------------------------------===// 2656 2657 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2658 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2659 CCState &State, ArrayRef<MCPhysReg> F64Regs) { 2660 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( 2661 State.getMachineFunction().getSubtarget()); 2662 2663 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2664 2665 const MipsCCState * MipsState = static_cast<MipsCCState *>(&State); 2666 2667 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 }; 2668 2669 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 }; 2670 2671 // Do not process byval args here. 2672 if (ArgFlags.isByVal()) 2673 return true; 2674 2675 // Promote i8 and i16 2676 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { 2677 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) { 2678 LocVT = MVT::i32; 2679 if (ArgFlags.isSExt()) 2680 LocInfo = CCValAssign::SExtUpper; 2681 else if (ArgFlags.isZExt()) 2682 LocInfo = CCValAssign::ZExtUpper; 2683 else 2684 LocInfo = CCValAssign::AExtUpper; 2685 } 2686 } 2687 2688 // Promote i8 and i16 2689 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2690 LocVT = MVT::i32; 2691 if (ArgFlags.isSExt()) 2692 LocInfo = CCValAssign::SExt; 2693 else if (ArgFlags.isZExt()) 2694 LocInfo = CCValAssign::ZExt; 2695 else 2696 LocInfo = CCValAssign::AExt; 2697 } 2698 2699 unsigned Reg; 2700 2701 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2702 // is true: function is vararg, argument is 3rd or higher, there is previous 2703 // argument which is not f32 or f64. 2704 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 || 2705 State.getFirstUnallocated(F32Regs) != ValNo; 2706 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2707 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2708 bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo); 2709 2710 // The MIPS vector ABI for floats passes them in a pair of registers 2711 if (ValVT == MVT::i32 && isVectorFloat) { 2712 // This is the start of an vector that was scalarized into an unknown number 2713 // of components. It doesn't matter how many there are. Allocate one of the 2714 // notional 8 byte aligned registers which map onto the argument stack, and 2715 // shadow the register lost to alignment requirements. 2716 if (ArgFlags.isSplit()) { 2717 Reg = State.AllocateReg(FloatVectorIntRegs); 2718 if (Reg == Mips::A2) 2719 State.AllocateReg(Mips::A1); 2720 else if (Reg == 0) 2721 State.AllocateReg(Mips::A3); 2722 } else { 2723 // If we're an intermediate component of the split, we can just attempt to 2724 // allocate a register directly. 2725 Reg = State.AllocateReg(IntRegs); 2726 } 2727 } else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2728 Reg = State.AllocateReg(IntRegs); 2729 // If this is the first part of an i64 arg, 2730 // the allocated register must be either A0 or A2. 2731 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2732 Reg = State.AllocateReg(IntRegs); 2733 LocVT = MVT::i32; 2734 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2735 // Allocate int register and shadow next int register. If first 2736 // available register is Mips::A1 or Mips::A3, shadow it too. 2737 Reg = State.AllocateReg(IntRegs); 2738 if (Reg == Mips::A1 || Reg == Mips::A3) 2739 Reg = State.AllocateReg(IntRegs); 2740 State.AllocateReg(IntRegs); 2741 LocVT = MVT::i32; 2742 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2743 // we are guaranteed to find an available float register 2744 if (ValVT == MVT::f32) { 2745 Reg = State.AllocateReg(F32Regs); 2746 // Shadow int register 2747 State.AllocateReg(IntRegs); 2748 } else { 2749 Reg = State.AllocateReg(F64Regs); 2750 // Shadow int registers 2751 unsigned Reg2 = State.AllocateReg(IntRegs); 2752 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2753 State.AllocateReg(IntRegs); 2754 State.AllocateReg(IntRegs); 2755 } 2756 } else 2757 llvm_unreachable("Cannot handle this ValVT."); 2758 2759 if (!Reg) { 2760 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign); 2761 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2762 } else 2763 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2764 2765 return false; 2766 } 2767 2768 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2769 MVT LocVT, CCValAssign::LocInfo LocInfo, 2770 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2771 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 }; 2772 2773 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2774 } 2775 2776 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2777 MVT LocVT, CCValAssign::LocInfo LocInfo, 2778 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2779 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 2780 2781 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2782 } 2783 2784 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2785 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2786 CCState &State) LLVM_ATTRIBUTE_UNUSED; 2787 2788 #include "MipsGenCallingConv.inc" 2789 2790 CCAssignFn *MipsTargetLowering::CCAssignFnForCall() const{ 2791 return CC_Mips; 2792 } 2793 2794 CCAssignFn *MipsTargetLowering::CCAssignFnForReturn() const{ 2795 return RetCC_Mips; 2796 } 2797 //===----------------------------------------------------------------------===// 2798 // Call Calling Convention Implementation 2799 //===----------------------------------------------------------------------===// 2800 2801 // Return next O32 integer argument register. 2802 static unsigned getNextIntArgReg(unsigned Reg) { 2803 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2804 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2805 } 2806 2807 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2808 SDValue Chain, SDValue Arg, 2809 const SDLoc &DL, bool IsTailCall, 2810 SelectionDAG &DAG) const { 2811 if (!IsTailCall) { 2812 SDValue PtrOff = 2813 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr, 2814 DAG.getIntPtrConstant(Offset, DL)); 2815 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()); 2816 } 2817 2818 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2819 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2820 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 2821 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2822 /* Alignment = */ 0, MachineMemOperand::MOVolatile); 2823 } 2824 2825 void MipsTargetLowering:: 2826 getOpndList(SmallVectorImpl<SDValue> &Ops, 2827 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 2828 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2829 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 2830 SDValue Chain) const { 2831 // Insert node "GP copy globalreg" before call to function. 2832 // 2833 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2834 // in PIC mode) allow symbols to be resolved via lazy binding. 2835 // The lazy binding stub requires GP to point to the GOT. 2836 // Note that we don't need GP to point to the GOT for indirect calls 2837 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates 2838 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs 2839 // used for the function (that is, Mips linker doesn't generate lazy binding 2840 // stub for a function whose address is taken in the program). 2841 if (IsPICCall && !InternalLinkage && IsCallReloc) { 2842 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP; 2843 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2844 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2845 } 2846 2847 // Build a sequence of copy-to-reg nodes chained together with token 2848 // chain and flag operands which copy the outgoing args into registers. 2849 // The InFlag in necessary since all emitted instructions must be 2850 // stuck together. 2851 SDValue InFlag; 2852 2853 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2854 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2855 RegsToPass[i].second, InFlag); 2856 InFlag = Chain.getValue(1); 2857 } 2858 2859 // Add argument registers to the end of the list so that they are 2860 // known live into the call. 2861 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2862 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2863 RegsToPass[i].second.getValueType())); 2864 2865 // Add a register mask operand representing the call-preserved registers. 2866 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 2867 const uint32_t *Mask = 2868 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv); 2869 assert(Mask && "Missing call preserved mask for calling convention"); 2870 if (Subtarget.inMips16HardFloat()) { 2871 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2872 StringRef Sym = G->getGlobal()->getName(); 2873 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2874 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 2875 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2876 } 2877 } 2878 } 2879 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2880 2881 if (InFlag.getNode()) 2882 Ops.push_back(InFlag); 2883 } 2884 2885 void MipsTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI, 2886 SDNode *Node) const { 2887 switch (MI.getOpcode()) { 2888 default: 2889 return; 2890 case Mips::JALR: 2891 case Mips::JALRPseudo: 2892 case Mips::JALR64: 2893 case Mips::JALR64Pseudo: 2894 case Mips::JALR16_MM: 2895 case Mips::JALRC16_MMR6: 2896 case Mips::TAILCALLREG: 2897 case Mips::TAILCALLREG64: 2898 case Mips::TAILCALLR6REG: 2899 case Mips::TAILCALL64R6REG: 2900 case Mips::TAILCALLREG_MM: 2901 case Mips::TAILCALLREG_MMR6: { 2902 if (!EmitJalrReloc || 2903 Subtarget.inMips16Mode() || 2904 !isPositionIndependent() || 2905 Node->getNumOperands() < 1 || 2906 Node->getOperand(0).getNumOperands() < 2) { 2907 return; 2908 } 2909 // We are after the callee address, set by LowerCall(). 2910 // If added to MI, asm printer will emit .reloc R_MIPS_JALR for the 2911 // symbol. 2912 const SDValue TargetAddr = Node->getOperand(0).getOperand(1); 2913 StringRef Sym; 2914 if (const GlobalAddressSDNode *G = 2915 dyn_cast_or_null<const GlobalAddressSDNode>(TargetAddr)) { 2916 Sym = G->getGlobal()->getName(); 2917 } 2918 else if (const ExternalSymbolSDNode *ES = 2919 dyn_cast_or_null<const ExternalSymbolSDNode>(TargetAddr)) { 2920 Sym = ES->getSymbol(); 2921 } 2922 2923 if (Sym.empty()) 2924 return; 2925 2926 MachineFunction *MF = MI.getParent()->getParent(); 2927 MCSymbol *S = MF->getContext().getOrCreateSymbol(Sym); 2928 MI.addOperand(MachineOperand::CreateMCSymbol(S, MipsII::MO_JALR)); 2929 } 2930 } 2931 } 2932 2933 /// LowerCall - functions arguments are copied from virtual regs to 2934 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2935 SDValue 2936 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2937 SmallVectorImpl<SDValue> &InVals) const { 2938 SelectionDAG &DAG = CLI.DAG; 2939 SDLoc DL = CLI.DL; 2940 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2941 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2942 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2943 SDValue Chain = CLI.Chain; 2944 SDValue Callee = CLI.Callee; 2945 bool &IsTailCall = CLI.IsTailCall; 2946 CallingConv::ID CallConv = CLI.CallConv; 2947 bool IsVarArg = CLI.IsVarArg; 2948 2949 MachineFunction &MF = DAG.getMachineFunction(); 2950 MachineFrameInfo &MFI = MF.getFrameInfo(); 2951 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 2952 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2953 bool IsPIC = isPositionIndependent(); 2954 2955 // Analyze operands of the call, assigning locations to each operand. 2956 SmallVector<CCValAssign, 16> ArgLocs; 2957 MipsCCState CCInfo( 2958 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), 2959 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); 2960 2961 const ExternalSymbolSDNode *ES = 2962 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode()); 2963 2964 // There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which 2965 // is during the lowering of a call with a byval argument which produces 2966 // a call to memcpy. For the O32 case, this causes the caller to allocate 2967 // stack space for the reserved argument area for the callee, then recursively 2968 // again for the memcpy call. In the NEWABI case, this doesn't occur as those 2969 // ABIs mandate that the callee allocates the reserved argument area. We do 2970 // still produce nested CALLSEQ_START..CALLSEQ_END with zero space though. 2971 // 2972 // If the callee has a byval argument and memcpy is used, we are mandated 2973 // to already have produced a reserved argument area for the callee for O32. 2974 // Therefore, the reserved argument area can be reused for both calls. 2975 // 2976 // Other cases of calling memcpy cannot have a chain with a CALLSEQ_START 2977 // present, as we have yet to hook that node onto the chain. 2978 // 2979 // Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this 2980 // case. GCC does a similar trick, in that wherever possible, it calculates 2981 // the maximum out going argument area (including the reserved area), and 2982 // preallocates the stack space on entrance to the caller. 2983 // 2984 // FIXME: We should do the same for efficiency and space. 2985 2986 // Note: The check on the calling convention below must match 2987 // MipsABIInfo::GetCalleeAllocdArgSizeInBytes(). 2988 bool MemcpyInByVal = ES && 2989 StringRef(ES->getSymbol()) == StringRef("memcpy") && 2990 CallConv != CallingConv::Fast && 2991 Chain.getOpcode() == ISD::CALLSEQ_START; 2992 2993 // Allocate the reserved argument area. It seems strange to do this from the 2994 // caller side but removing it breaks the frame size calculation. 2995 unsigned ReservedArgArea = 2996 MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv); 2997 CCInfo.AllocateStack(ReservedArgArea, 1); 2998 2999 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), 3000 ES ? ES->getSymbol() : nullptr); 3001 3002 // Get a count of how many bytes are to be pushed on the stack. 3003 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 3004 3005 // Check if it's really possible to do a tail call. Restrict it to functions 3006 // that are part of this compilation unit. 3007 bool InternalLinkage = false; 3008 if (IsTailCall) { 3009 IsTailCall = isEligibleForTailCallOptimization( 3010 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>()); 3011 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3012 InternalLinkage = G->getGlobal()->hasInternalLinkage(); 3013 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() || 3014 G->getGlobal()->hasPrivateLinkage() || 3015 G->getGlobal()->hasHiddenVisibility() || 3016 G->getGlobal()->hasProtectedVisibility()); 3017 } 3018 } 3019 if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall()) 3020 report_fatal_error("failed to perform tail call elimination on a call " 3021 "site marked musttail"); 3022 3023 if (IsTailCall) 3024 ++NumTailCalls; 3025 3026 // Chain is the output chain of the last Load/Store or CopyToReg node. 3027 // ByValChain is the output chain of the last Memcpy node created for copying 3028 // byval arguments to the stack. 3029 unsigned StackAlignment = TFL->getStackAlignment(); 3030 NextStackOffset = alignTo(NextStackOffset, StackAlignment); 3031 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); 3032 3033 if (!(IsTailCall || MemcpyInByVal)) 3034 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL); 3035 3036 SDValue StackPtr = 3037 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, 3038 getPointerTy(DAG.getDataLayout())); 3039 3040 std::deque<std::pair<unsigned, SDValue>> RegsToPass; 3041 SmallVector<SDValue, 8> MemOpChains; 3042 3043 CCInfo.rewindByValRegsInfo(); 3044 3045 // Walk the register/memloc assignments, inserting copies/loads. 3046 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3047 SDValue Arg = OutVals[i]; 3048 CCValAssign &VA = ArgLocs[i]; 3049 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 3050 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3051 bool UseUpperBits = false; 3052 3053 // ByVal Arg. 3054 if (Flags.isByVal()) { 3055 unsigned FirstByValReg, LastByValReg; 3056 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3057 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3058 3059 assert(Flags.getByValSize() && 3060 "ByVal args of size 0 should have been ignored by front-end."); 3061 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3062 assert(!IsTailCall && 3063 "Do not tail-call optimize if there is a byval argument."); 3064 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 3065 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), 3066 VA); 3067 CCInfo.nextInRegsParam(); 3068 continue; 3069 } 3070 3071 // Promote the value if needed. 3072 switch (VA.getLocInfo()) { 3073 default: 3074 llvm_unreachable("Unknown loc info!"); 3075 case CCValAssign::Full: 3076 if (VA.isRegLoc()) { 3077 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 3078 (ValVT == MVT::f64 && LocVT == MVT::i64) || 3079 (ValVT == MVT::i64 && LocVT == MVT::f64)) 3080 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3081 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 3082 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3083 Arg, DAG.getConstant(0, DL, MVT::i32)); 3084 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3085 Arg, DAG.getConstant(1, DL, MVT::i32)); 3086 if (!Subtarget.isLittle()) 3087 std::swap(Lo, Hi); 3088 unsigned LocRegLo = VA.getLocReg(); 3089 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 3090 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 3091 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 3092 continue; 3093 } 3094 } 3095 break; 3096 case CCValAssign::BCvt: 3097 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3098 break; 3099 case CCValAssign::SExtUpper: 3100 UseUpperBits = true; 3101 LLVM_FALLTHROUGH; 3102 case CCValAssign::SExt: 3103 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 3104 break; 3105 case CCValAssign::ZExtUpper: 3106 UseUpperBits = true; 3107 LLVM_FALLTHROUGH; 3108 case CCValAssign::ZExt: 3109 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 3110 break; 3111 case CCValAssign::AExtUpper: 3112 UseUpperBits = true; 3113 LLVM_FALLTHROUGH; 3114 case CCValAssign::AExt: 3115 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 3116 break; 3117 } 3118 3119 if (UseUpperBits) { 3120 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3121 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3122 Arg = DAG.getNode( 3123 ISD::SHL, DL, VA.getLocVT(), Arg, 3124 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3125 } 3126 3127 // Arguments that can be passed on register must be kept at 3128 // RegsToPass vector 3129 if (VA.isRegLoc()) { 3130 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 3131 continue; 3132 } 3133 3134 // Register can't get to this point... 3135 assert(VA.isMemLoc()); 3136 3137 // emit ISD::STORE whichs stores the 3138 // parameter value to a stack Location 3139 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 3140 Chain, Arg, DL, IsTailCall, DAG)); 3141 } 3142 3143 // Transform all store nodes into one single node because all store 3144 // nodes are independent of each other. 3145 if (!MemOpChains.empty()) 3146 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 3147 3148 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 3149 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 3150 // node so that legalize doesn't hack it. 3151 3152 EVT Ty = Callee.getValueType(); 3153 bool GlobalOrExternal = false, IsCallReloc = false; 3154 3155 // The long-calls feature is ignored in case of PIC. 3156 // While we do not support -mshared / -mno-shared properly, 3157 // ignore long-calls in case of -mabicalls too. 3158 if (!Subtarget.isABICalls() && !IsPIC) { 3159 // If the function should be called using "long call", 3160 // get its address into a register to prevent using 3161 // of the `jal` instruction for the direct call. 3162 if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3163 if (Subtarget.useLongCalls()) 3164 Callee = Subtarget.hasSym32() 3165 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3166 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3167 } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) { 3168 bool UseLongCalls = Subtarget.useLongCalls(); 3169 // If the function has long-call/far/near attribute 3170 // it overrides command line switch pased to the backend. 3171 if (auto *F = dyn_cast<Function>(N->getGlobal())) { 3172 if (F->hasFnAttribute("long-call")) 3173 UseLongCalls = true; 3174 else if (F->hasFnAttribute("short-call")) 3175 UseLongCalls = false; 3176 } 3177 if (UseLongCalls) 3178 Callee = Subtarget.hasSym32() 3179 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3180 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3181 } 3182 } 3183 3184 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3185 if (IsPIC) { 3186 const GlobalValue *Val = G->getGlobal(); 3187 InternalLinkage = Val->hasInternalLinkage(); 3188 3189 if (InternalLinkage) 3190 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); 3191 else if (LargeGOT) { 3192 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3193 MipsII::MO_CALL_LO16, Chain, 3194 FuncInfo->callPtrInfo(Val)); 3195 IsCallReloc = true; 3196 } else { 3197 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3198 FuncInfo->callPtrInfo(Val)); 3199 IsCallReloc = true; 3200 } 3201 } else 3202 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, 3203 getPointerTy(DAG.getDataLayout()), 0, 3204 MipsII::MO_NO_FLAG); 3205 GlobalOrExternal = true; 3206 } 3207 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3208 const char *Sym = S->getSymbol(); 3209 3210 if (!IsPIC) // static 3211 Callee = DAG.getTargetExternalSymbol( 3212 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); 3213 else if (LargeGOT) { 3214 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3215 MipsII::MO_CALL_LO16, Chain, 3216 FuncInfo->callPtrInfo(Sym)); 3217 IsCallReloc = true; 3218 } else { // PIC 3219 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3220 FuncInfo->callPtrInfo(Sym)); 3221 IsCallReloc = true; 3222 } 3223 3224 GlobalOrExternal = true; 3225 } 3226 3227 SmallVector<SDValue, 8> Ops(1, Chain); 3228 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 3229 3230 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage, 3231 IsCallReloc, CLI, Callee, Chain); 3232 3233 if (IsTailCall) { 3234 MF.getFrameInfo().setHasTailCall(); 3235 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); 3236 } 3237 3238 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); 3239 SDValue InFlag = Chain.getValue(1); 3240 3241 // Create the CALLSEQ_END node in the case of where it is not a call to 3242 // memcpy. 3243 if (!(MemcpyInByVal)) { 3244 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 3245 DAG.getIntPtrConstant(0, DL, true), InFlag, DL); 3246 InFlag = Chain.getValue(1); 3247 } 3248 3249 // Handle result values, copying them out of physregs into vregs that we 3250 // return. 3251 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, 3252 InVals, CLI); 3253 } 3254 3255 /// LowerCallResult - Lower the result values of a call into the 3256 /// appropriate copies out of appropriate physical registers. 3257 SDValue MipsTargetLowering::LowerCallResult( 3258 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 3259 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3260 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 3261 TargetLowering::CallLoweringInfo &CLI) const { 3262 // Assign locations to each value returned by this call. 3263 SmallVector<CCValAssign, 16> RVLocs; 3264 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 3265 *DAG.getContext()); 3266 3267 const ExternalSymbolSDNode *ES = 3268 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode()); 3269 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy, 3270 ES ? ES->getSymbol() : nullptr); 3271 3272 // Copy all of the result registers out of their specified physreg. 3273 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3274 CCValAssign &VA = RVLocs[i]; 3275 assert(VA.isRegLoc() && "Can only return in registers!"); 3276 3277 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 3278 RVLocs[i].getLocVT(), InFlag); 3279 Chain = Val.getValue(1); 3280 InFlag = Val.getValue(2); 3281 3282 if (VA.isUpperBitsInLoc()) { 3283 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); 3284 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3285 unsigned Shift = 3286 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3287 Val = DAG.getNode( 3288 Shift, DL, VA.getLocVT(), Val, 3289 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3290 } 3291 3292 switch (VA.getLocInfo()) { 3293 default: 3294 llvm_unreachable("Unknown loc info!"); 3295 case CCValAssign::Full: 3296 break; 3297 case CCValAssign::BCvt: 3298 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 3299 break; 3300 case CCValAssign::AExt: 3301 case CCValAssign::AExtUpper: 3302 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3303 break; 3304 case CCValAssign::ZExt: 3305 case CCValAssign::ZExtUpper: 3306 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, 3307 DAG.getValueType(VA.getValVT())); 3308 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3309 break; 3310 case CCValAssign::SExt: 3311 case CCValAssign::SExtUpper: 3312 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, 3313 DAG.getValueType(VA.getValVT())); 3314 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3315 break; 3316 } 3317 3318 InVals.push_back(Val); 3319 } 3320 3321 return Chain; 3322 } 3323 3324 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, 3325 EVT ArgVT, const SDLoc &DL, 3326 SelectionDAG &DAG) { 3327 MVT LocVT = VA.getLocVT(); 3328 EVT ValVT = VA.getValVT(); 3329 3330 // Shift into the upper bits if necessary. 3331 switch (VA.getLocInfo()) { 3332 default: 3333 break; 3334 case CCValAssign::AExtUpper: 3335 case CCValAssign::SExtUpper: 3336 case CCValAssign::ZExtUpper: { 3337 unsigned ValSizeInBits = ArgVT.getSizeInBits(); 3338 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3339 unsigned Opcode = 3340 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3341 Val = DAG.getNode( 3342 Opcode, DL, VA.getLocVT(), Val, 3343 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3344 break; 3345 } 3346 } 3347 3348 // If this is an value smaller than the argument slot size (32-bit for O32, 3349 // 64-bit for N32/N64), it has been promoted in some way to the argument slot 3350 // size. Extract the value and insert any appropriate assertions regarding 3351 // sign/zero extension. 3352 switch (VA.getLocInfo()) { 3353 default: 3354 llvm_unreachable("Unknown loc info!"); 3355 case CCValAssign::Full: 3356 break; 3357 case CCValAssign::AExtUpper: 3358 case CCValAssign::AExt: 3359 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3360 break; 3361 case CCValAssign::SExtUpper: 3362 case CCValAssign::SExt: 3363 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3364 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3365 break; 3366 case CCValAssign::ZExtUpper: 3367 case CCValAssign::ZExt: 3368 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3369 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3370 break; 3371 case CCValAssign::BCvt: 3372 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); 3373 break; 3374 } 3375 3376 return Val; 3377 } 3378 3379 //===----------------------------------------------------------------------===// 3380 // Formal Arguments Calling Convention Implementation 3381 //===----------------------------------------------------------------------===// 3382 /// LowerFormalArguments - transform physical registers into virtual registers 3383 /// and generate load operations for arguments places on the stack. 3384 SDValue MipsTargetLowering::LowerFormalArguments( 3385 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 3386 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3387 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 3388 MachineFunction &MF = DAG.getMachineFunction(); 3389 MachineFrameInfo &MFI = MF.getFrameInfo(); 3390 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3391 3392 MipsFI->setVarArgsFrameIndex(0); 3393 3394 // Used with vargs to acumulate store chains. 3395 std::vector<SDValue> OutChains; 3396 3397 // Assign locations to all of the incoming arguments. 3398 SmallVector<CCValAssign, 16> ArgLocs; 3399 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 3400 *DAG.getContext()); 3401 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 3402 const Function &Func = DAG.getMachineFunction().getFunction(); 3403 Function::const_arg_iterator FuncArg = Func.arg_begin(); 3404 3405 if (Func.hasFnAttribute("interrupt") && !Func.arg_empty()) 3406 report_fatal_error( 3407 "Functions with the interrupt attribute cannot have arguments!"); 3408 3409 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); 3410 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 3411 CCInfo.getInRegsParamsCount() > 0); 3412 3413 unsigned CurArgIdx = 0; 3414 CCInfo.rewindByValRegsInfo(); 3415 3416 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3417 CCValAssign &VA = ArgLocs[i]; 3418 if (Ins[i].isOrigArg()) { 3419 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx); 3420 CurArgIdx = Ins[i].getOrigArgIndex(); 3421 } 3422 EVT ValVT = VA.getValVT(); 3423 ISD::ArgFlagsTy Flags = Ins[i].Flags; 3424 bool IsRegLoc = VA.isRegLoc(); 3425 3426 if (Flags.isByVal()) { 3427 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit"); 3428 unsigned FirstByValReg, LastByValReg; 3429 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3430 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3431 3432 assert(Flags.getByValSize() && 3433 "ByVal args of size 0 should have been ignored by front-end."); 3434 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3435 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 3436 FirstByValReg, LastByValReg, VA, CCInfo); 3437 CCInfo.nextInRegsParam(); 3438 continue; 3439 } 3440 3441 // Arguments stored on registers 3442 if (IsRegLoc) { 3443 MVT RegVT = VA.getLocVT(); 3444 unsigned ArgReg = VA.getLocReg(); 3445 const TargetRegisterClass *RC = getRegClassFor(RegVT); 3446 3447 // Transform the arguments stored on 3448 // physical registers into virtual ones 3449 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3450 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 3451 3452 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3453 3454 // Handle floating point arguments passed in integer registers and 3455 // long double arguments passed in floating point registers. 3456 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3457 (RegVT == MVT::i64 && ValVT == MVT::f64) || 3458 (RegVT == MVT::f64 && ValVT == MVT::i64)) 3459 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 3460 else if (ABI.IsO32() && RegVT == MVT::i32 && 3461 ValVT == MVT::f64) { 3462 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 3463 getNextIntArgReg(ArgReg), RC); 3464 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 3465 if (!Subtarget.isLittle()) 3466 std::swap(ArgValue, ArgValue2); 3467 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 3468 ArgValue, ArgValue2); 3469 } 3470 3471 InVals.push_back(ArgValue); 3472 } else { // VA.isRegLoc() 3473 MVT LocVT = VA.getLocVT(); 3474 3475 if (ABI.IsO32()) { 3476 // We ought to be able to use LocVT directly but O32 sets it to i32 3477 // when allocating floating point values to integer registers. 3478 // This shouldn't influence how we load the value into registers unless 3479 // we are targeting softfloat. 3480 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) 3481 LocVT = VA.getValVT(); 3482 } 3483 3484 // sanity check 3485 assert(VA.isMemLoc()); 3486 3487 // The stack pointer offset is relative to the caller stack frame. 3488 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, 3489 VA.getLocMemOffset(), true); 3490 3491 // Create load nodes to retrieve arguments from the stack 3492 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3493 SDValue ArgValue = DAG.getLoad( 3494 LocVT, DL, Chain, FIN, 3495 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); 3496 OutChains.push_back(ArgValue.getValue(1)); 3497 3498 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3499 3500 InVals.push_back(ArgValue); 3501 } 3502 } 3503 3504 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3505 // The mips ABIs for returning structs by value requires that we copy 3506 // the sret argument into $v0 for the return. Save the argument into 3507 // a virtual register so that we can access it from the return points. 3508 if (Ins[i].Flags.isSRet()) { 3509 unsigned Reg = MipsFI->getSRetReturnReg(); 3510 if (!Reg) { 3511 Reg = MF.getRegInfo().createVirtualRegister( 3512 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); 3513 MipsFI->setSRetReturnReg(Reg); 3514 } 3515 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); 3516 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 3517 break; 3518 } 3519 } 3520 3521 if (IsVarArg) 3522 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); 3523 3524 // All stores are grouped in one node to allow the matching between 3525 // the size of Ins and InVals. This only happens when on varg functions 3526 if (!OutChains.empty()) { 3527 OutChains.push_back(Chain); 3528 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 3529 } 3530 3531 return Chain; 3532 } 3533 3534 //===----------------------------------------------------------------------===// 3535 // Return Value Calling Convention Implementation 3536 //===----------------------------------------------------------------------===// 3537 3538 bool 3539 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3540 MachineFunction &MF, bool IsVarArg, 3541 const SmallVectorImpl<ISD::OutputArg> &Outs, 3542 LLVMContext &Context) const { 3543 SmallVector<CCValAssign, 16> RVLocs; 3544 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 3545 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3546 } 3547 3548 bool 3549 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { 3550 if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32) 3551 return true; 3552 3553 return IsSigned; 3554 } 3555 3556 SDValue 3557 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, 3558 const SDLoc &DL, 3559 SelectionDAG &DAG) const { 3560 MachineFunction &MF = DAG.getMachineFunction(); 3561 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3562 3563 MipsFI->setISR(); 3564 3565 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps); 3566 } 3567 3568 SDValue 3569 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 3570 bool IsVarArg, 3571 const SmallVectorImpl<ISD::OutputArg> &Outs, 3572 const SmallVectorImpl<SDValue> &OutVals, 3573 const SDLoc &DL, SelectionDAG &DAG) const { 3574 // CCValAssign - represent the assignment of 3575 // the return value to a location 3576 SmallVector<CCValAssign, 16> RVLocs; 3577 MachineFunction &MF = DAG.getMachineFunction(); 3578 3579 // CCState - Info about the registers and stack slot. 3580 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 3581 3582 // Analyze return values. 3583 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3584 3585 SDValue Flag; 3586 SmallVector<SDValue, 4> RetOps(1, Chain); 3587 3588 // Copy the result values into the output registers. 3589 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3590 SDValue Val = OutVals[i]; 3591 CCValAssign &VA = RVLocs[i]; 3592 assert(VA.isRegLoc() && "Can only return in registers!"); 3593 bool UseUpperBits = false; 3594 3595 switch (VA.getLocInfo()) { 3596 default: 3597 llvm_unreachable("Unknown loc info!"); 3598 case CCValAssign::Full: 3599 break; 3600 case CCValAssign::BCvt: 3601 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); 3602 break; 3603 case CCValAssign::AExtUpper: 3604 UseUpperBits = true; 3605 LLVM_FALLTHROUGH; 3606 case CCValAssign::AExt: 3607 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); 3608 break; 3609 case CCValAssign::ZExtUpper: 3610 UseUpperBits = true; 3611 LLVM_FALLTHROUGH; 3612 case CCValAssign::ZExt: 3613 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); 3614 break; 3615 case CCValAssign::SExtUpper: 3616 UseUpperBits = true; 3617 LLVM_FALLTHROUGH; 3618 case CCValAssign::SExt: 3619 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); 3620 break; 3621 } 3622 3623 if (UseUpperBits) { 3624 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3625 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3626 Val = DAG.getNode( 3627 ISD::SHL, DL, VA.getLocVT(), Val, 3628 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3629 } 3630 3631 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 3632 3633 // Guarantee that all emitted copies are stuck together with flags. 3634 Flag = Chain.getValue(1); 3635 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3636 } 3637 3638 // The mips ABIs for returning structs by value requires that we copy 3639 // the sret argument into $v0 for the return. We saved the argument into 3640 // a virtual register in the entry block, so now we copy the value out 3641 // and into $v0. 3642 if (MF.getFunction().hasStructRetAttr()) { 3643 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3644 unsigned Reg = MipsFI->getSRetReturnReg(); 3645 3646 if (!Reg) 3647 llvm_unreachable("sret virtual register not created in the entry block"); 3648 SDValue Val = 3649 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); 3650 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 3651 3652 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 3653 Flag = Chain.getValue(1); 3654 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); 3655 } 3656 3657 RetOps[0] = Chain; // Update chain. 3658 3659 // Add the flag if we have it. 3660 if (Flag.getNode()) 3661 RetOps.push_back(Flag); 3662 3663 // ISRs must use "eret". 3664 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt")) 3665 return LowerInterruptReturn(RetOps, DL, DAG); 3666 3667 // Standard return on Mips is a "jr $ra" 3668 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); 3669 } 3670 3671 //===----------------------------------------------------------------------===// 3672 // Mips Inline Assembly Support 3673 //===----------------------------------------------------------------------===// 3674 3675 /// getConstraintType - Given a constraint letter, return the type of 3676 /// constraint it is for this target. 3677 MipsTargetLowering::ConstraintType 3678 MipsTargetLowering::getConstraintType(StringRef Constraint) const { 3679 // Mips specific constraints 3680 // GCC config/mips/constraints.md 3681 // 3682 // 'd' : An address register. Equivalent to r 3683 // unless generating MIPS16 code. 3684 // 'y' : Equivalent to r; retained for 3685 // backwards compatibility. 3686 // 'c' : A register suitable for use in an indirect 3687 // jump. This will always be $25 for -mabicalls. 3688 // 'l' : The lo register. 1 word storage. 3689 // 'x' : The hilo register pair. Double word storage. 3690 if (Constraint.size() == 1) { 3691 switch (Constraint[0]) { 3692 default : break; 3693 case 'd': 3694 case 'y': 3695 case 'f': 3696 case 'c': 3697 case 'l': 3698 case 'x': 3699 return C_RegisterClass; 3700 case 'R': 3701 return C_Memory; 3702 } 3703 } 3704 3705 if (Constraint == "ZC") 3706 return C_Memory; 3707 3708 return TargetLowering::getConstraintType(Constraint); 3709 } 3710 3711 /// Examine constraint type and operand type and determine a weight value. 3712 /// This object must already have been set up with the operand type 3713 /// and the current alternative constraint selected. 3714 TargetLowering::ConstraintWeight 3715 MipsTargetLowering::getSingleConstraintMatchWeight( 3716 AsmOperandInfo &info, const char *constraint) const { 3717 ConstraintWeight weight = CW_Invalid; 3718 Value *CallOperandVal = info.CallOperandVal; 3719 // If we don't have a value, we can't do a match, 3720 // but allow it at the lowest weight. 3721 if (!CallOperandVal) 3722 return CW_Default; 3723 Type *type = CallOperandVal->getType(); 3724 // Look at the constraint type. 3725 switch (*constraint) { 3726 default: 3727 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3728 break; 3729 case 'd': 3730 case 'y': 3731 if (type->isIntegerTy()) 3732 weight = CW_Register; 3733 break; 3734 case 'f': // FPU or MSA register 3735 if (Subtarget.hasMSA() && type->isVectorTy() && 3736 cast<VectorType>(type)->getBitWidth() == 128) 3737 weight = CW_Register; 3738 else if (type->isFloatTy()) 3739 weight = CW_Register; 3740 break; 3741 case 'c': // $25 for indirect jumps 3742 case 'l': // lo register 3743 case 'x': // hilo register pair 3744 if (type->isIntegerTy()) 3745 weight = CW_SpecificReg; 3746 break; 3747 case 'I': // signed 16 bit immediate 3748 case 'J': // integer zero 3749 case 'K': // unsigned 16 bit immediate 3750 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3751 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3752 case 'O': // signed 15 bit immediate (+- 16383) 3753 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3754 if (isa<ConstantInt>(CallOperandVal)) 3755 weight = CW_Constant; 3756 break; 3757 case 'R': 3758 weight = CW_Memory; 3759 break; 3760 } 3761 return weight; 3762 } 3763 3764 /// This is a helper function to parse a physical register string and split it 3765 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 3766 /// that is returned indicates whether parsing was successful. The second flag 3767 /// is true if the numeric part exists. 3768 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix, 3769 unsigned long long &Reg) { 3770 if (C.front() != '{' || C.back() != '}') 3771 return std::make_pair(false, false); 3772 3773 // Search for the first numeric character. 3774 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 3775 I = std::find_if(B, E, isdigit); 3776 3777 Prefix = StringRef(B, I - B); 3778 3779 // The second flag is set to false if no numeric characters were found. 3780 if (I == E) 3781 return std::make_pair(true, false); 3782 3783 // Parse the numeric characters. 3784 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 3785 true); 3786 } 3787 3788 EVT MipsTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT, 3789 ISD::NodeType) const { 3790 bool Cond = !Subtarget.isABI_O32() && VT.getSizeInBits() == 32; 3791 EVT MinVT = getRegisterType(Context, Cond ? MVT::i64 : MVT::i32); 3792 return VT.bitsLT(MinVT) ? MinVT : VT; 3793 } 3794 3795 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 3796 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const { 3797 const TargetRegisterInfo *TRI = 3798 Subtarget.getRegisterInfo(); 3799 const TargetRegisterClass *RC; 3800 StringRef Prefix; 3801 unsigned long long Reg; 3802 3803 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 3804 3805 if (!R.first) 3806 return std::make_pair(0U, nullptr); 3807 3808 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 3809 // No numeric characters follow "hi" or "lo". 3810 if (R.second) 3811 return std::make_pair(0U, nullptr); 3812 3813 RC = TRI->getRegClass(Prefix == "hi" ? 3814 Mips::HI32RegClassID : Mips::LO32RegClassID); 3815 return std::make_pair(*(RC->begin()), RC); 3816 } else if (Prefix.startswith("$msa")) { 3817 // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 3818 3819 // No numeric characters follow the name. 3820 if (R.second) 3821 return std::make_pair(0U, nullptr); 3822 3823 Reg = StringSwitch<unsigned long long>(Prefix) 3824 .Case("$msair", Mips::MSAIR) 3825 .Case("$msacsr", Mips::MSACSR) 3826 .Case("$msaaccess", Mips::MSAAccess) 3827 .Case("$msasave", Mips::MSASave) 3828 .Case("$msamodify", Mips::MSAModify) 3829 .Case("$msarequest", Mips::MSARequest) 3830 .Case("$msamap", Mips::MSAMap) 3831 .Case("$msaunmap", Mips::MSAUnmap) 3832 .Default(0); 3833 3834 if (!Reg) 3835 return std::make_pair(0U, nullptr); 3836 3837 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 3838 return std::make_pair(Reg, RC); 3839 } 3840 3841 if (!R.second) 3842 return std::make_pair(0U, nullptr); 3843 3844 if (Prefix == "$f") { // Parse $f0-$f31. 3845 // If the size of FP registers is 64-bit or Reg is an even number, select 3846 // the 64-bit register class. Otherwise, select the 32-bit register class. 3847 if (VT == MVT::Other) 3848 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 3849 3850 RC = getRegClassFor(VT); 3851 3852 if (RC == &Mips::AFGR64RegClass) { 3853 assert(Reg % 2 == 0); 3854 Reg >>= 1; 3855 } 3856 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 3857 RC = TRI->getRegClass(Mips::FCCRegClassID); 3858 else if (Prefix == "$w") { // Parse $w0-$w31. 3859 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 3860 } else { // Parse $0-$31. 3861 assert(Prefix == "$"); 3862 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 3863 } 3864 3865 assert(Reg < RC->getNumRegs()); 3866 return std::make_pair(*(RC->begin() + Reg), RC); 3867 } 3868 3869 /// Given a register class constraint, like 'r', if this corresponds directly 3870 /// to an LLVM register class, return a register of 0 and the register class 3871 /// pointer. 3872 std::pair<unsigned, const TargetRegisterClass *> 3873 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 3874 StringRef Constraint, 3875 MVT VT) const { 3876 if (Constraint.size() == 1) { 3877 switch (Constraint[0]) { 3878 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3879 case 'y': // Same as 'r'. Exists for compatibility. 3880 case 'r': 3881 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3882 if (Subtarget.inMips16Mode()) 3883 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3884 return std::make_pair(0U, &Mips::GPR32RegClass); 3885 } 3886 if (VT == MVT::i64 && !Subtarget.isGP64bit()) 3887 return std::make_pair(0U, &Mips::GPR32RegClass); 3888 if (VT == MVT::i64 && Subtarget.isGP64bit()) 3889 return std::make_pair(0U, &Mips::GPR64RegClass); 3890 // This will generate an error message 3891 return std::make_pair(0U, nullptr); 3892 case 'f': // FPU or MSA register 3893 if (VT == MVT::v16i8) 3894 return std::make_pair(0U, &Mips::MSA128BRegClass); 3895 else if (VT == MVT::v8i16 || VT == MVT::v8f16) 3896 return std::make_pair(0U, &Mips::MSA128HRegClass); 3897 else if (VT == MVT::v4i32 || VT == MVT::v4f32) 3898 return std::make_pair(0U, &Mips::MSA128WRegClass); 3899 else if (VT == MVT::v2i64 || VT == MVT::v2f64) 3900 return std::make_pair(0U, &Mips::MSA128DRegClass); 3901 else if (VT == MVT::f32) 3902 return std::make_pair(0U, &Mips::FGR32RegClass); 3903 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { 3904 if (Subtarget.isFP64bit()) 3905 return std::make_pair(0U, &Mips::FGR64RegClass); 3906 return std::make_pair(0U, &Mips::AFGR64RegClass); 3907 } 3908 break; 3909 case 'c': // register suitable for indirect jump 3910 if (VT == MVT::i32) 3911 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 3912 if (VT == MVT::i64) 3913 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 3914 // This will generate an error message 3915 return std::make_pair(0U, nullptr); 3916 case 'l': // use the `lo` register to store values 3917 // that are no bigger than a word 3918 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) 3919 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 3920 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 3921 case 'x': // use the concatenated `hi` and `lo` registers 3922 // to store doubleword values 3923 // Fixme: Not triggering the use of both hi and low 3924 // This will generate an error message 3925 return std::make_pair(0U, nullptr); 3926 } 3927 } 3928 3929 std::pair<unsigned, const TargetRegisterClass *> R; 3930 R = parseRegForInlineAsmConstraint(Constraint, VT); 3931 3932 if (R.second) 3933 return R; 3934 3935 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 3936 } 3937 3938 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3939 /// vector. If it is invalid, don't add anything to Ops. 3940 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3941 std::string &Constraint, 3942 std::vector<SDValue>&Ops, 3943 SelectionDAG &DAG) const { 3944 SDLoc DL(Op); 3945 SDValue Result; 3946 3947 // Only support length 1 constraints for now. 3948 if (Constraint.length() > 1) return; 3949 3950 char ConstraintLetter = Constraint[0]; 3951 switch (ConstraintLetter) { 3952 default: break; // This will fall through to the generic implementation 3953 case 'I': // Signed 16 bit constant 3954 // If this fails, the parent routine will give an error 3955 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3956 EVT Type = Op.getValueType(); 3957 int64_t Val = C->getSExtValue(); 3958 if (isInt<16>(Val)) { 3959 Result = DAG.getTargetConstant(Val, DL, Type); 3960 break; 3961 } 3962 } 3963 return; 3964 case 'J': // integer zero 3965 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3966 EVT Type = Op.getValueType(); 3967 int64_t Val = C->getZExtValue(); 3968 if (Val == 0) { 3969 Result = DAG.getTargetConstant(0, DL, Type); 3970 break; 3971 } 3972 } 3973 return; 3974 case 'K': // unsigned 16 bit immediate 3975 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3976 EVT Type = Op.getValueType(); 3977 uint64_t Val = (uint64_t)C->getZExtValue(); 3978 if (isUInt<16>(Val)) { 3979 Result = DAG.getTargetConstant(Val, DL, Type); 3980 break; 3981 } 3982 } 3983 return; 3984 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3985 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3986 EVT Type = Op.getValueType(); 3987 int64_t Val = C->getSExtValue(); 3988 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3989 Result = DAG.getTargetConstant(Val, DL, Type); 3990 break; 3991 } 3992 } 3993 return; 3994 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3995 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3996 EVT Type = Op.getValueType(); 3997 int64_t Val = C->getSExtValue(); 3998 if ((Val >= -65535) && (Val <= -1)) { 3999 Result = DAG.getTargetConstant(Val, DL, Type); 4000 break; 4001 } 4002 } 4003 return; 4004 case 'O': // signed 15 bit immediate 4005 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4006 EVT Type = Op.getValueType(); 4007 int64_t Val = C->getSExtValue(); 4008 if ((isInt<15>(Val))) { 4009 Result = DAG.getTargetConstant(Val, DL, Type); 4010 break; 4011 } 4012 } 4013 return; 4014 case 'P': // immediate in the range of 1 to 65535 (inclusive) 4015 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4016 EVT Type = Op.getValueType(); 4017 int64_t Val = C->getSExtValue(); 4018 if ((Val <= 65535) && (Val >= 1)) { 4019 Result = DAG.getTargetConstant(Val, DL, Type); 4020 break; 4021 } 4022 } 4023 return; 4024 } 4025 4026 if (Result.getNode()) { 4027 Ops.push_back(Result); 4028 return; 4029 } 4030 4031 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 4032 } 4033 4034 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, 4035 const AddrMode &AM, Type *Ty, 4036 unsigned AS, Instruction *I) const { 4037 // No global is ever allowed as a base. 4038 if (AM.BaseGV) 4039 return false; 4040 4041 switch (AM.Scale) { 4042 case 0: // "r+i" or just "i", depending on HasBaseReg. 4043 break; 4044 case 1: 4045 if (!AM.HasBaseReg) // allow "r+i". 4046 break; 4047 return false; // disallow "r+r" or "r+r+i". 4048 default: 4049 return false; 4050 } 4051 4052 return true; 4053 } 4054 4055 bool 4056 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 4057 // The Mips target isn't yet aware of offsets. 4058 return false; 4059 } 4060 4061 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 4062 unsigned SrcAlign, 4063 bool IsMemset, bool ZeroMemset, 4064 bool MemcpyStrSrc, 4065 MachineFunction &MF) const { 4066 if (Subtarget.hasMips64()) 4067 return MVT::i64; 4068 4069 return MVT::i32; 4070 } 4071 4072 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 4073 if (VT != MVT::f32 && VT != MVT::f64) 4074 return false; 4075 if (Imm.isNegZero()) 4076 return false; 4077 return Imm.isZero(); 4078 } 4079 4080 unsigned MipsTargetLowering::getJumpTableEncoding() const { 4081 4082 // FIXME: For space reasons this should be: EK_GPRel32BlockAddress. 4083 if (ABI.IsN64() && isPositionIndependent()) 4084 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 4085 4086 return TargetLowering::getJumpTableEncoding(); 4087 } 4088 4089 bool MipsTargetLowering::useSoftFloat() const { 4090 return Subtarget.useSoftFloat(); 4091 } 4092 4093 void MipsTargetLowering::copyByValRegs( 4094 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains, 4095 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 4096 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 4097 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, 4098 MipsCCState &State) const { 4099 MachineFunction &MF = DAG.getMachineFunction(); 4100 MachineFrameInfo &MFI = MF.getFrameInfo(); 4101 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); 4102 unsigned NumRegs = LastReg - FirstReg; 4103 unsigned RegAreaSize = NumRegs * GPRSizeInBytes; 4104 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 4105 int FrameObjOffset; 4106 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs(); 4107 4108 if (RegAreaSize) 4109 FrameObjOffset = 4110 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4111 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); 4112 else 4113 FrameObjOffset = VA.getLocMemOffset(); 4114 4115 // Create frame object. 4116 EVT PtrTy = getPointerTy(DAG.getDataLayout()); 4117 // Make the fixed object stored to mutable so that the load instructions 4118 // referencing it have their memory dependencies added. 4119 // Set the frame object as isAliased which clears the underlying objects 4120 // vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all 4121 // stores as dependencies for loads referencing this fixed object. 4122 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, false, true); 4123 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4124 InVals.push_back(FIN); 4125 4126 if (!NumRegs) 4127 return; 4128 4129 // Copy arg registers. 4130 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); 4131 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4132 4133 for (unsigned I = 0; I < NumRegs; ++I) { 4134 unsigned ArgReg = ByValArgRegs[FirstReg + I]; 4135 unsigned VReg = addLiveIn(MF, ArgReg, RC); 4136 unsigned Offset = I * GPRSizeInBytes; 4137 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 4138 DAG.getConstant(Offset, DL, PtrTy)); 4139 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 4140 StorePtr, MachinePointerInfo(FuncArg, Offset)); 4141 OutChains.push_back(Store); 4142 } 4143 } 4144 4145 // Copy byVal arg to registers and stack. 4146 void MipsTargetLowering::passByValArg( 4147 SDValue Chain, const SDLoc &DL, 4148 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 4149 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 4150 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, 4151 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, 4152 const CCValAssign &VA) const { 4153 unsigned ByValSizeInBytes = Flags.getByValSize(); 4154 unsigned OffsetInBytes = 0; // From beginning of struct 4155 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4156 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes); 4157 EVT PtrTy = getPointerTy(DAG.getDataLayout()), 4158 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4159 unsigned NumRegs = LastReg - FirstReg; 4160 4161 if (NumRegs) { 4162 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); 4163 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); 4164 unsigned I = 0; 4165 4166 // Copy words to registers. 4167 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { 4168 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4169 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4170 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 4171 MachinePointerInfo(), Alignment); 4172 MemOpChains.push_back(LoadVal.getValue(1)); 4173 unsigned ArgReg = ArgRegs[FirstReg + I]; 4174 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 4175 } 4176 4177 // Return if the struct has been fully copied. 4178 if (ByValSizeInBytes == OffsetInBytes) 4179 return; 4180 4181 // Copy the remainder of the byval argument with sub-word loads and shifts. 4182 if (LeftoverBytes) { 4183 SDValue Val; 4184 4185 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0; 4186 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) { 4187 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes; 4188 4189 if (RemainingSizeInBytes < LoadSizeInBytes) 4190 continue; 4191 4192 // Load subword. 4193 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4194 DAG.getConstant(OffsetInBytes, DL, 4195 PtrTy)); 4196 SDValue LoadVal = DAG.getExtLoad( 4197 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), 4198 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment); 4199 MemOpChains.push_back(LoadVal.getValue(1)); 4200 4201 // Shift the loaded value. 4202 unsigned Shamt; 4203 4204 if (isLittle) 4205 Shamt = TotalBytesLoaded * 8; 4206 else 4207 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; 4208 4209 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 4210 DAG.getConstant(Shamt, DL, MVT::i32)); 4211 4212 if (Val.getNode()) 4213 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 4214 else 4215 Val = Shift; 4216 4217 OffsetInBytes += LoadSizeInBytes; 4218 TotalBytesLoaded += LoadSizeInBytes; 4219 Alignment = std::min(Alignment, LoadSizeInBytes); 4220 } 4221 4222 unsigned ArgReg = ArgRegs[FirstReg + I]; 4223 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 4224 return; 4225 } 4226 } 4227 4228 // Copy remainder of byval arg to it with memcpy. 4229 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; 4230 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4231 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4232 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 4233 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); 4234 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 4235 DAG.getConstant(MemCpySize, DL, PtrTy), 4236 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, 4237 /*isTailCall=*/false, 4238 MachinePointerInfo(), MachinePointerInfo()); 4239 MemOpChains.push_back(Chain); 4240 } 4241 4242 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 4243 SDValue Chain, const SDLoc &DL, 4244 SelectionDAG &DAG, 4245 CCState &State) const { 4246 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); 4247 unsigned Idx = State.getFirstUnallocated(ArgRegs); 4248 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4249 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4250 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4251 MachineFunction &MF = DAG.getMachineFunction(); 4252 MachineFrameInfo &MFI = MF.getFrameInfo(); 4253 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 4254 4255 // Offset of the first variable argument from stack pointer. 4256 int VaArgOffset; 4257 4258 if (ArgRegs.size() == Idx) 4259 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes); 4260 else { 4261 VaArgOffset = 4262 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4263 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); 4264 } 4265 4266 // Record the frame index of the first variable argument 4267 // which is a value necessary to VASTART. 4268 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4269 MipsFI->setVarArgsFrameIndex(FI); 4270 4271 // Copy the integer registers that have not been used for argument passing 4272 // to the argument register save area. For O32, the save area is allocated 4273 // in the caller's stack frame, while for N32/64, it is allocated in the 4274 // callee's stack frame. 4275 for (unsigned I = Idx; I < ArgRegs.size(); 4276 ++I, VaArgOffset += RegSizeInBytes) { 4277 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 4278 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 4279 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4280 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 4281 SDValue Store = 4282 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo()); 4283 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( 4284 (Value *)nullptr); 4285 OutChains.push_back(Store); 4286 } 4287 } 4288 4289 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, 4290 unsigned Align) const { 4291 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 4292 4293 assert(Size && "Byval argument's size shouldn't be 0."); 4294 4295 Align = std::min(Align, TFL->getStackAlignment()); 4296 4297 unsigned FirstReg = 0; 4298 unsigned NumRegs = 0; 4299 4300 if (State->getCallingConv() != CallingConv::Fast) { 4301 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4302 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs(); 4303 // FIXME: The O32 case actually describes no shadow registers. 4304 const MCPhysReg *ShadowRegs = 4305 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs; 4306 4307 // We used to check the size as well but we can't do that anymore since 4308 // CCState::HandleByVal() rounds up the size after calling this function. 4309 assert(!(Align % RegSizeInBytes) && 4310 "Byval argument's alignment should be a multiple of" 4311 "RegSizeInBytes."); 4312 4313 FirstReg = State->getFirstUnallocated(IntArgRegs); 4314 4315 // If Align > RegSizeInBytes, the first arg register must be even. 4316 // FIXME: This condition happens to do the right thing but it's not the 4317 // right way to test it. We want to check that the stack frame offset 4318 // of the register is aligned. 4319 if ((Align > RegSizeInBytes) && (FirstReg % 2)) { 4320 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); 4321 ++FirstReg; 4322 } 4323 4324 // Mark the registers allocated. 4325 Size = alignTo(Size, RegSizeInBytes); 4326 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size()); 4327 Size -= RegSizeInBytes, ++I, ++NumRegs) 4328 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); 4329 } 4330 4331 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); 4332 } 4333 4334 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI, 4335 MachineBasicBlock *BB, 4336 bool isFPCmp, 4337 unsigned Opc) const { 4338 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4339 "Subtarget already supports SELECT nodes with the use of" 4340 "conditional-move instructions."); 4341 4342 const TargetInstrInfo *TII = 4343 Subtarget.getInstrInfo(); 4344 DebugLoc DL = MI.getDebugLoc(); 4345 4346 // To "insert" a SELECT instruction, we actually have to insert the 4347 // diamond control-flow pattern. The incoming instruction knows the 4348 // destination vreg to set, the condition code register to branch on, the 4349 // true/false values to select between, and a branch opcode to use. 4350 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4351 MachineFunction::iterator It = ++BB->getIterator(); 4352 4353 // thisMBB: 4354 // ... 4355 // TrueVal = ... 4356 // setcc r1, r2, r3 4357 // bNE r1, r0, copy1MBB 4358 // fallthrough --> copy0MBB 4359 MachineBasicBlock *thisMBB = BB; 4360 MachineFunction *F = BB->getParent(); 4361 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4362 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4363 F->insert(It, copy0MBB); 4364 F->insert(It, sinkMBB); 4365 4366 // Transfer the remainder of BB and its successor edges to sinkMBB. 4367 sinkMBB->splice(sinkMBB->begin(), BB, 4368 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 4369 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4370 4371 // Next, add the true and fallthrough blocks as its successors. 4372 BB->addSuccessor(copy0MBB); 4373 BB->addSuccessor(sinkMBB); 4374 4375 if (isFPCmp) { 4376 // bc1[tf] cc, sinkMBB 4377 BuildMI(BB, DL, TII->get(Opc)) 4378 .addReg(MI.getOperand(1).getReg()) 4379 .addMBB(sinkMBB); 4380 } else { 4381 // bne rs, $0, sinkMBB 4382 BuildMI(BB, DL, TII->get(Opc)) 4383 .addReg(MI.getOperand(1).getReg()) 4384 .addReg(Mips::ZERO) 4385 .addMBB(sinkMBB); 4386 } 4387 4388 // copy0MBB: 4389 // %FalseValue = ... 4390 // # fallthrough to sinkMBB 4391 BB = copy0MBB; 4392 4393 // Update machine-CFG edges 4394 BB->addSuccessor(sinkMBB); 4395 4396 // sinkMBB: 4397 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4398 // ... 4399 BB = sinkMBB; 4400 4401 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4402 .addReg(MI.getOperand(2).getReg()) 4403 .addMBB(thisMBB) 4404 .addReg(MI.getOperand(3).getReg()) 4405 .addMBB(copy0MBB); 4406 4407 MI.eraseFromParent(); // The pseudo instruction is gone now. 4408 4409 return BB; 4410 } 4411 4412 MachineBasicBlock *MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI, 4413 MachineBasicBlock *BB) const { 4414 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4415 "Subtarget already supports SELECT nodes with the use of" 4416 "conditional-move instructions."); 4417 4418 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4419 DebugLoc DL = MI.getDebugLoc(); 4420 4421 // D_SELECT substitutes two SELECT nodes that goes one after another and 4422 // have the same condition operand. On machines which don't have 4423 // conditional-move instruction, it reduces unnecessary branch instructions 4424 // which are result of using two diamond patterns that are result of two 4425 // SELECT pseudo instructions. 4426 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4427 MachineFunction::iterator It = ++BB->getIterator(); 4428 4429 // thisMBB: 4430 // ... 4431 // TrueVal = ... 4432 // setcc r1, r2, r3 4433 // bNE r1, r0, copy1MBB 4434 // fallthrough --> copy0MBB 4435 MachineBasicBlock *thisMBB = BB; 4436 MachineFunction *F = BB->getParent(); 4437 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4438 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4439 F->insert(It, copy0MBB); 4440 F->insert(It, sinkMBB); 4441 4442 // Transfer the remainder of BB and its successor edges to sinkMBB. 4443 sinkMBB->splice(sinkMBB->begin(), BB, 4444 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 4445 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4446 4447 // Next, add the true and fallthrough blocks as its successors. 4448 BB->addSuccessor(copy0MBB); 4449 BB->addSuccessor(sinkMBB); 4450 4451 // bne rs, $0, sinkMBB 4452 BuildMI(BB, DL, TII->get(Mips::BNE)) 4453 .addReg(MI.getOperand(2).getReg()) 4454 .addReg(Mips::ZERO) 4455 .addMBB(sinkMBB); 4456 4457 // copy0MBB: 4458 // %FalseValue = ... 4459 // # fallthrough to sinkMBB 4460 BB = copy0MBB; 4461 4462 // Update machine-CFG edges 4463 BB->addSuccessor(sinkMBB); 4464 4465 // sinkMBB: 4466 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4467 // ... 4468 BB = sinkMBB; 4469 4470 // Use two PHI nodes to select two reults 4471 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4472 .addReg(MI.getOperand(3).getReg()) 4473 .addMBB(thisMBB) 4474 .addReg(MI.getOperand(5).getReg()) 4475 .addMBB(copy0MBB); 4476 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(1).getReg()) 4477 .addReg(MI.getOperand(4).getReg()) 4478 .addMBB(thisMBB) 4479 .addReg(MI.getOperand(6).getReg()) 4480 .addMBB(copy0MBB); 4481 4482 MI.eraseFromParent(); // The pseudo instruction is gone now. 4483 4484 return BB; 4485 } 4486 4487 // FIXME? Maybe this could be a TableGen attribute on some registers and 4488 // this table could be generated automatically from RegInfo. 4489 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT, 4490 SelectionDAG &DAG) const { 4491 // Named registers is expected to be fairly rare. For now, just support $28 4492 // since the linux kernel uses it. 4493 if (Subtarget.isGP64bit()) { 4494 unsigned Reg = StringSwitch<unsigned>(RegName) 4495 .Case("$28", Mips::GP_64) 4496 .Default(0); 4497 if (Reg) 4498 return Reg; 4499 } else { 4500 unsigned Reg = StringSwitch<unsigned>(RegName) 4501 .Case("$28", Mips::GP) 4502 .Default(0); 4503 if (Reg) 4504 return Reg; 4505 } 4506 report_fatal_error("Invalid register name global variable"); 4507 } 4508