1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 #include "MipsISelLowering.h" 15 #include "InstPrinter/MipsInstPrinter.h" 16 #include "MCTargetDesc/MipsBaseInfo.h" 17 #include "MipsCCState.h" 18 #include "MipsMachineFunction.h" 19 #include "MipsSubtarget.h" 20 #include "MipsTargetMachine.h" 21 #include "MipsTargetObjectFile.h" 22 #include "llvm/ADT/Statistic.h" 23 #include "llvm/ADT/StringSwitch.h" 24 #include "llvm/CodeGen/CallingConvLower.h" 25 #include "llvm/CodeGen/MachineFrameInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 #include "llvm/CodeGen/SelectionDAGISel.h" 30 #include "llvm/CodeGen/ValueTypes.h" 31 #include "llvm/IR/CallingConv.h" 32 #include "llvm/IR/DerivedTypes.h" 33 #include "llvm/IR/GlobalVariable.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/ErrorHandling.h" 37 #include "llvm/Support/raw_ostream.h" 38 #include <cctype> 39 40 using namespace llvm; 41 42 #define DEBUG_TYPE "mips-lower" 43 44 STATISTIC(NumTailCalls, "Number of tail calls"); 45 46 static cl::opt<bool> 47 LargeGOT("mxgot", cl::Hidden, 48 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 49 50 static cl::opt<bool> 51 NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 52 cl::desc("MIPS: Don't trap on integer division by zero."), 53 cl::init(false)); 54 55 cl::opt<bool> 56 EnableMipsFastISel("mips-fast-isel", cl::Hidden, 57 cl::desc("Allow mips-fast-isel to be used"), 58 cl::init(false)); 59 60 static const MCPhysReg Mips64DPRegs[8] = { 61 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 62 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 63 }; 64 65 // If I is a shifted mask, set the size (Size) and the first bit of the 66 // mask (Pos), and return true. 67 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 68 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 69 if (!isShiftedMask_64(I)) 70 return false; 71 72 Size = CountPopulation_64(I); 73 Pos = countTrailingZeros(I); 74 return true; 75 } 76 77 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 78 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 79 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 80 } 81 82 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 83 SelectionDAG &DAG, 84 unsigned Flag) const { 85 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 86 } 87 88 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 89 SelectionDAG &DAG, 90 unsigned Flag) const { 91 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 92 } 93 94 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 95 SelectionDAG &DAG, 96 unsigned Flag) const { 97 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 98 } 99 100 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 101 SelectionDAG &DAG, 102 unsigned Flag) const { 103 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 104 } 105 106 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 107 SelectionDAG &DAG, 108 unsigned Flag) const { 109 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 110 N->getOffset(), Flag); 111 } 112 113 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 114 switch (Opcode) { 115 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 116 case MipsISD::TailCall: return "MipsISD::TailCall"; 117 case MipsISD::Hi: return "MipsISD::Hi"; 118 case MipsISD::Lo: return "MipsISD::Lo"; 119 case MipsISD::GPRel: return "MipsISD::GPRel"; 120 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 121 case MipsISD::Ret: return "MipsISD::Ret"; 122 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 123 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 124 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 125 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 126 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 127 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 128 case MipsISD::MFHI: return "MipsISD::MFHI"; 129 case MipsISD::MFLO: return "MipsISD::MFLO"; 130 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 131 case MipsISD::Mult: return "MipsISD::Mult"; 132 case MipsISD::Multu: return "MipsISD::Multu"; 133 case MipsISD::MAdd: return "MipsISD::MAdd"; 134 case MipsISD::MAddu: return "MipsISD::MAddu"; 135 case MipsISD::MSub: return "MipsISD::MSub"; 136 case MipsISD::MSubu: return "MipsISD::MSubu"; 137 case MipsISD::DivRem: return "MipsISD::DivRem"; 138 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 139 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 140 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 141 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 142 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 143 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 144 case MipsISD::Sync: return "MipsISD::Sync"; 145 case MipsISD::Ext: return "MipsISD::Ext"; 146 case MipsISD::Ins: return "MipsISD::Ins"; 147 case MipsISD::LWL: return "MipsISD::LWL"; 148 case MipsISD::LWR: return "MipsISD::LWR"; 149 case MipsISD::SWL: return "MipsISD::SWL"; 150 case MipsISD::SWR: return "MipsISD::SWR"; 151 case MipsISD::LDL: return "MipsISD::LDL"; 152 case MipsISD::LDR: return "MipsISD::LDR"; 153 case MipsISD::SDL: return "MipsISD::SDL"; 154 case MipsISD::SDR: return "MipsISD::SDR"; 155 case MipsISD::EXTP: return "MipsISD::EXTP"; 156 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 157 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 158 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 159 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 160 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 161 case MipsISD::SHILO: return "MipsISD::SHILO"; 162 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 163 case MipsISD::MULT: return "MipsISD::MULT"; 164 case MipsISD::MULTU: return "MipsISD::MULTU"; 165 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 166 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 167 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 168 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 169 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 170 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 171 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 172 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 173 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 174 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 175 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 176 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 177 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 178 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 179 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 180 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 181 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 182 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 183 case MipsISD::VSMAX: return "MipsISD::VSMAX"; 184 case MipsISD::VSMIN: return "MipsISD::VSMIN"; 185 case MipsISD::VUMAX: return "MipsISD::VUMAX"; 186 case MipsISD::VUMIN: return "MipsISD::VUMIN"; 187 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 188 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 189 case MipsISD::VNOR: return "MipsISD::VNOR"; 190 case MipsISD::VSHF: return "MipsISD::VSHF"; 191 case MipsISD::SHF: return "MipsISD::SHF"; 192 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 193 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 194 case MipsISD::ILVL: return "MipsISD::ILVL"; 195 case MipsISD::ILVR: return "MipsISD::ILVR"; 196 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 197 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 198 case MipsISD::INSVE: return "MipsISD::INSVE"; 199 default: return nullptr; 200 } 201 } 202 203 MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM, 204 const MipsSubtarget &STI) 205 : TargetLowering(TM, new MipsTargetObjectFile()), Subtarget(STI) { 206 // Mips does not have i1 type, so use i32 for 207 // setcc operations results (slt, sgt, ...). 208 setBooleanContents(ZeroOrOneBooleanContent); 209 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 210 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA 211 // does. Integer booleans still use 0 and 1. 212 if (Subtarget.hasMips32r6()) 213 setBooleanContents(ZeroOrOneBooleanContent, 214 ZeroOrNegativeOneBooleanContent); 215 216 // Load extented operations for i1 types must be promoted 217 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 218 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 219 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 220 221 // MIPS doesn't have extending float->double load/store 222 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 223 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 224 225 // Used by legalize types to correctly generate the setcc result. 226 // Without this, every float setcc comes with a AND/OR with the result, 227 // we don't want this, since the fpcmp result goes to a flag register, 228 // which is used implicitly by brcond and select operations. 229 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 230 231 // Mips Custom Operations 232 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 233 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 234 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 235 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 236 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 237 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 238 setOperationAction(ISD::SELECT, MVT::f32, Custom); 239 setOperationAction(ISD::SELECT, MVT::f64, Custom); 240 setOperationAction(ISD::SELECT, MVT::i32, Custom); 241 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 242 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 243 setOperationAction(ISD::SETCC, MVT::f32, Custom); 244 setOperationAction(ISD::SETCC, MVT::f64, Custom); 245 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 246 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 247 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 248 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 249 250 if (Subtarget.isGP64bit()) { 251 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 252 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 253 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 254 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 255 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 256 setOperationAction(ISD::SELECT, MVT::i64, Custom); 257 setOperationAction(ISD::LOAD, MVT::i64, Custom); 258 setOperationAction(ISD::STORE, MVT::i64, Custom); 259 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 260 } 261 262 if (!Subtarget.isGP64bit()) { 263 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 264 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 265 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 266 } 267 268 setOperationAction(ISD::ADD, MVT::i32, Custom); 269 if (Subtarget.isGP64bit()) 270 setOperationAction(ISD::ADD, MVT::i64, Custom); 271 272 setOperationAction(ISD::SDIV, MVT::i32, Expand); 273 setOperationAction(ISD::SREM, MVT::i32, Expand); 274 setOperationAction(ISD::UDIV, MVT::i32, Expand); 275 setOperationAction(ISD::UREM, MVT::i32, Expand); 276 setOperationAction(ISD::SDIV, MVT::i64, Expand); 277 setOperationAction(ISD::SREM, MVT::i64, Expand); 278 setOperationAction(ISD::UDIV, MVT::i64, Expand); 279 setOperationAction(ISD::UREM, MVT::i64, Expand); 280 281 // Operations not directly supported by Mips. 282 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 283 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 284 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 285 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 286 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 287 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 288 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 289 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 290 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 291 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 292 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 293 if (Subtarget.hasCnMips()) { 294 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 295 setOperationAction(ISD::CTPOP, MVT::i64, Legal); 296 } else { 297 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 298 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 299 } 300 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 301 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 302 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 303 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 304 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 305 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 306 setOperationAction(ISD::ROTL, MVT::i32, Expand); 307 setOperationAction(ISD::ROTL, MVT::i64, Expand); 308 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 309 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 310 311 if (!Subtarget.hasMips32r2()) 312 setOperationAction(ISD::ROTR, MVT::i32, Expand); 313 314 if (!Subtarget.hasMips64r2()) 315 setOperationAction(ISD::ROTR, MVT::i64, Expand); 316 317 setOperationAction(ISD::FSIN, MVT::f32, Expand); 318 setOperationAction(ISD::FSIN, MVT::f64, Expand); 319 setOperationAction(ISD::FCOS, MVT::f32, Expand); 320 setOperationAction(ISD::FCOS, MVT::f64, Expand); 321 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 322 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 323 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 324 setOperationAction(ISD::FPOW, MVT::f32, Expand); 325 setOperationAction(ISD::FPOW, MVT::f64, Expand); 326 setOperationAction(ISD::FLOG, MVT::f32, Expand); 327 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 328 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 329 setOperationAction(ISD::FEXP, MVT::f32, Expand); 330 setOperationAction(ISD::FMA, MVT::f32, Expand); 331 setOperationAction(ISD::FMA, MVT::f64, Expand); 332 setOperationAction(ISD::FREM, MVT::f32, Expand); 333 setOperationAction(ISD::FREM, MVT::f64, Expand); 334 335 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 336 337 setOperationAction(ISD::VASTART, MVT::Other, Custom); 338 setOperationAction(ISD::VAARG, MVT::Other, Custom); 339 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 340 setOperationAction(ISD::VAEND, MVT::Other, Expand); 341 342 // Use the default for now 343 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 344 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 345 346 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 347 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 348 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 349 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 350 351 setInsertFencesForAtomic(true); 352 353 if (!Subtarget.hasMips32r2()) { 354 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 355 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 356 } 357 358 // MIPS16 lacks MIPS32's clz and clo instructions. 359 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 360 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 361 if (!Subtarget.hasMips64()) 362 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 363 364 if (!Subtarget.hasMips32r2()) 365 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 366 if (!Subtarget.hasMips64r2()) 367 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 368 369 if (Subtarget.isGP64bit()) { 370 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom); 371 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom); 372 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom); 373 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 374 } 375 376 setOperationAction(ISD::TRAP, MVT::Other, Legal); 377 378 setTargetDAGCombine(ISD::SDIVREM); 379 setTargetDAGCombine(ISD::UDIVREM); 380 setTargetDAGCombine(ISD::SELECT); 381 setTargetDAGCombine(ISD::AND); 382 setTargetDAGCombine(ISD::OR); 383 setTargetDAGCombine(ISD::ADD); 384 385 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2); 386 387 // The arguments on the stack are defined in terms of 4-byte slots on O32 388 // and 8-byte slots on N32/N64. 389 setMinStackArgumentAlignment( 390 (Subtarget.isABI_N32() || Subtarget.isABI_N64()) ? 8 : 4); 391 392 setStackPointerRegisterToSaveRestore(Subtarget.isABI_N64() ? Mips::SP_64 393 : Mips::SP); 394 395 setExceptionPointerRegister(Subtarget.isABI_N64() ? Mips::A0_64 : Mips::A0); 396 setExceptionSelectorRegister(Subtarget.isABI_N64() ? Mips::A1_64 : Mips::A1); 397 398 MaxStoresPerMemcpy = 16; 399 400 isMicroMips = Subtarget.inMicroMipsMode(); 401 } 402 403 const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM, 404 const MipsSubtarget &STI) { 405 if (STI.inMips16Mode()) 406 return llvm::createMips16TargetLowering(TM, STI); 407 408 return llvm::createMipsSETargetLowering(TM, STI); 409 } 410 411 // Create a fast isel object. 412 FastISel * 413 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 414 const TargetLibraryInfo *libInfo) const { 415 if (!EnableMipsFastISel) 416 return TargetLowering::createFastISel(funcInfo, libInfo); 417 return Mips::createFastISel(funcInfo, libInfo); 418 } 419 420 EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { 421 if (!VT.isVector()) 422 return MVT::i32; 423 return VT.changeVectorElementTypeToInteger(); 424 } 425 426 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 427 TargetLowering::DAGCombinerInfo &DCI, 428 const MipsSubtarget &Subtarget) { 429 if (DCI.isBeforeLegalizeOps()) 430 return SDValue(); 431 432 EVT Ty = N->getValueType(0); 433 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 434 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 435 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 436 MipsISD::DivRemU16; 437 SDLoc DL(N); 438 439 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 440 N->getOperand(0), N->getOperand(1)); 441 SDValue InChain = DAG.getEntryNode(); 442 SDValue InGlue = DivRem; 443 444 // insert MFLO 445 if (N->hasAnyUseOfValue(0)) { 446 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 447 InGlue); 448 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 449 InChain = CopyFromLo.getValue(1); 450 InGlue = CopyFromLo.getValue(2); 451 } 452 453 // insert MFHI 454 if (N->hasAnyUseOfValue(1)) { 455 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 456 HI, Ty, InGlue); 457 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 458 } 459 460 return SDValue(); 461 } 462 463 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 464 switch (CC) { 465 default: llvm_unreachable("Unknown fp condition code!"); 466 case ISD::SETEQ: 467 case ISD::SETOEQ: return Mips::FCOND_OEQ; 468 case ISD::SETUNE: return Mips::FCOND_UNE; 469 case ISD::SETLT: 470 case ISD::SETOLT: return Mips::FCOND_OLT; 471 case ISD::SETGT: 472 case ISD::SETOGT: return Mips::FCOND_OGT; 473 case ISD::SETLE: 474 case ISD::SETOLE: return Mips::FCOND_OLE; 475 case ISD::SETGE: 476 case ISD::SETOGE: return Mips::FCOND_OGE; 477 case ISD::SETULT: return Mips::FCOND_ULT; 478 case ISD::SETULE: return Mips::FCOND_ULE; 479 case ISD::SETUGT: return Mips::FCOND_UGT; 480 case ISD::SETUGE: return Mips::FCOND_UGE; 481 case ISD::SETUO: return Mips::FCOND_UN; 482 case ISD::SETO: return Mips::FCOND_OR; 483 case ISD::SETNE: 484 case ISD::SETONE: return Mips::FCOND_ONE; 485 case ISD::SETUEQ: return Mips::FCOND_UEQ; 486 } 487 } 488 489 490 /// This function returns true if the floating point conditional branches and 491 /// conditional moves which use condition code CC should be inverted. 492 static bool invertFPCondCodeUser(Mips::CondCode CC) { 493 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 494 return false; 495 496 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 497 "Illegal Condition Code"); 498 499 return true; 500 } 501 502 // Creates and returns an FPCmp node from a setcc node. 503 // Returns Op if setcc is not a floating point comparison. 504 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 505 // must be a SETCC node 506 if (Op.getOpcode() != ISD::SETCC) 507 return Op; 508 509 SDValue LHS = Op.getOperand(0); 510 511 if (!LHS.getValueType().isFloatingPoint()) 512 return Op; 513 514 SDValue RHS = Op.getOperand(1); 515 SDLoc DL(Op); 516 517 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 518 // node if necessary. 519 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 520 521 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 522 DAG.getConstant(condCodeToFCC(CC), MVT::i32)); 523 } 524 525 // Creates and returns a CMovFPT/F node. 526 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 527 SDValue False, SDLoc DL) { 528 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 529 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 530 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 531 532 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 533 True.getValueType(), True, FCC0, False, Cond); 534 } 535 536 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 537 TargetLowering::DAGCombinerInfo &DCI, 538 const MipsSubtarget &Subtarget) { 539 if (DCI.isBeforeLegalizeOps()) 540 return SDValue(); 541 542 SDValue SetCC = N->getOperand(0); 543 544 if ((SetCC.getOpcode() != ISD::SETCC) || 545 !SetCC.getOperand(0).getValueType().isInteger()) 546 return SDValue(); 547 548 SDValue False = N->getOperand(2); 549 EVT FalseTy = False.getValueType(); 550 551 if (!FalseTy.isInteger()) 552 return SDValue(); 553 554 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); 555 556 // If the RHS (False) is 0, we swap the order of the operands 557 // of ISD::SELECT (obviously also inverting the condition) so that we can 558 // take advantage of conditional moves using the $0 register. 559 // Example: 560 // return (a != 0) ? x : 0; 561 // load $reg, x 562 // movz $reg, $0, a 563 if (!FalseC) 564 return SDValue(); 565 566 const SDLoc DL(N); 567 568 if (!FalseC->getZExtValue()) { 569 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 570 SDValue True = N->getOperand(1); 571 572 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 573 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 574 575 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 576 } 577 578 // If both operands are integer constants there's a possibility that we 579 // can do some interesting optimizations. 580 SDValue True = N->getOperand(1); 581 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); 582 583 if (!TrueC || !True.getValueType().isInteger()) 584 return SDValue(); 585 586 // We'll also ignore MVT::i64 operands as this optimizations proves 587 // to be ineffective because of the required sign extensions as the result 588 // of a SETCC operator is always MVT::i32 for non-vector types. 589 if (True.getValueType() == MVT::i64) 590 return SDValue(); 591 592 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); 593 594 // 1) (a < x) ? y : y-1 595 // slti $reg1, a, x 596 // addiu $reg2, $reg1, y-1 597 if (Diff == 1) 598 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); 599 600 // 2) (a < x) ? y-1 : y 601 // slti $reg1, a, x 602 // xor $reg1, $reg1, 1 603 // addiu $reg2, $reg1, y-1 604 if (Diff == -1) { 605 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 606 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 607 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 608 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); 609 } 610 611 // Couldn't optimize. 612 return SDValue(); 613 } 614 615 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 616 TargetLowering::DAGCombinerInfo &DCI, 617 const MipsSubtarget &Subtarget) { 618 // Pattern match EXT. 619 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 620 // => ext $dst, $src, size, pos 621 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 622 return SDValue(); 623 624 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 625 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 626 627 // Op's first operand must be a shift right. 628 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 629 return SDValue(); 630 631 // The second operand of the shift must be an immediate. 632 ConstantSDNode *CN; 633 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 634 return SDValue(); 635 636 uint64_t Pos = CN->getZExtValue(); 637 uint64_t SMPos, SMSize; 638 639 // Op's second operand must be a shifted mask. 640 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 641 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 642 return SDValue(); 643 644 // Return if the shifted mask does not start at bit 0 or the sum of its size 645 // and Pos exceeds the word's size. 646 EVT ValTy = N->getValueType(0); 647 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 648 return SDValue(); 649 650 return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy, 651 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32), 652 DAG.getConstant(SMSize, MVT::i32)); 653 } 654 655 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 656 TargetLowering::DAGCombinerInfo &DCI, 657 const MipsSubtarget &Subtarget) { 658 // Pattern match INS. 659 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 660 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 661 // => ins $dst, $src, size, pos, $src1 662 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 663 return SDValue(); 664 665 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 666 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 667 ConstantSDNode *CN; 668 669 // See if Op's first operand matches (and $src1 , mask0). 670 if (And0.getOpcode() != ISD::AND) 671 return SDValue(); 672 673 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 674 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 675 return SDValue(); 676 677 // See if Op's second operand matches (and (shl $src, pos), mask1). 678 if (And1.getOpcode() != ISD::AND) 679 return SDValue(); 680 681 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 682 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 683 return SDValue(); 684 685 // The shift masks must have the same position and size. 686 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 687 return SDValue(); 688 689 SDValue Shl = And1.getOperand(0); 690 if (Shl.getOpcode() != ISD::SHL) 691 return SDValue(); 692 693 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 694 return SDValue(); 695 696 unsigned Shamt = CN->getZExtValue(); 697 698 // Return if the shift amount and the first bit position of mask are not the 699 // same. 700 EVT ValTy = N->getValueType(0); 701 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 702 return SDValue(); 703 704 return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0), 705 DAG.getConstant(SMPos0, MVT::i32), 706 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0)); 707 } 708 709 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 710 TargetLowering::DAGCombinerInfo &DCI, 711 const MipsSubtarget &Subtarget) { 712 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 713 714 if (DCI.isBeforeLegalizeOps()) 715 return SDValue(); 716 717 SDValue Add = N->getOperand(1); 718 719 if (Add.getOpcode() != ISD::ADD) 720 return SDValue(); 721 722 SDValue Lo = Add.getOperand(1); 723 724 if ((Lo.getOpcode() != MipsISD::Lo) || 725 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 726 return SDValue(); 727 728 EVT ValTy = N->getValueType(0); 729 SDLoc DL(N); 730 731 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 732 Add.getOperand(0)); 733 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 734 } 735 736 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 737 const { 738 SelectionDAG &DAG = DCI.DAG; 739 unsigned Opc = N->getOpcode(); 740 741 switch (Opc) { 742 default: break; 743 case ISD::SDIVREM: 744 case ISD::UDIVREM: 745 return performDivRemCombine(N, DAG, DCI, Subtarget); 746 case ISD::SELECT: 747 return performSELECTCombine(N, DAG, DCI, Subtarget); 748 case ISD::AND: 749 return performANDCombine(N, DAG, DCI, Subtarget); 750 case ISD::OR: 751 return performORCombine(N, DAG, DCI, Subtarget); 752 case ISD::ADD: 753 return performADDCombine(N, DAG, DCI, Subtarget); 754 } 755 756 return SDValue(); 757 } 758 759 void 760 MipsTargetLowering::LowerOperationWrapper(SDNode *N, 761 SmallVectorImpl<SDValue> &Results, 762 SelectionDAG &DAG) const { 763 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 764 765 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 766 Results.push_back(Res.getValue(I)); 767 } 768 769 void 770 MipsTargetLowering::ReplaceNodeResults(SDNode *N, 771 SmallVectorImpl<SDValue> &Results, 772 SelectionDAG &DAG) const { 773 return LowerOperationWrapper(N, Results, DAG); 774 } 775 776 SDValue MipsTargetLowering:: 777 LowerOperation(SDValue Op, SelectionDAG &DAG) const 778 { 779 switch (Op.getOpcode()) 780 { 781 case ISD::BR_JT: return lowerBR_JT(Op, DAG); 782 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 783 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 784 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 785 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 786 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 787 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 788 case ISD::SELECT: return lowerSELECT(Op, DAG); 789 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG); 790 case ISD::SETCC: return lowerSETCC(Op, DAG); 791 case ISD::VASTART: return lowerVASTART(Op, DAG); 792 case ISD::VAARG: return lowerVAARG(Op, DAG); 793 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 794 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 795 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 796 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 797 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 798 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 799 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 800 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 801 case ISD::LOAD: return lowerLOAD(Op, DAG); 802 case ISD::STORE: return lowerSTORE(Op, DAG); 803 case ISD::ADD: return lowerADD(Op, DAG); 804 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 805 } 806 return SDValue(); 807 } 808 809 //===----------------------------------------------------------------------===// 810 // Lower helper functions 811 //===----------------------------------------------------------------------===// 812 813 // addLiveIn - This helper function adds the specified physical register to the 814 // MachineFunction as a live in value. It also creates a corresponding 815 // virtual register for it. 816 static unsigned 817 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 818 { 819 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 820 MF.getRegInfo().addLiveIn(PReg, VReg); 821 return VReg; 822 } 823 824 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr *MI, 825 MachineBasicBlock &MBB, 826 const TargetInstrInfo &TII, 827 bool Is64Bit) { 828 if (NoZeroDivCheck) 829 return &MBB; 830 831 // Insert instruction "teq $divisor_reg, $zero, 7". 832 MachineBasicBlock::iterator I(MI); 833 MachineInstrBuilder MIB; 834 MachineOperand &Divisor = MI->getOperand(2); 835 MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ)) 836 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 837 .addReg(Mips::ZERO).addImm(7); 838 839 // Use the 32-bit sub-register if this is a 64-bit division. 840 if (Is64Bit) 841 MIB->getOperand(0).setSubReg(Mips::sub_32); 842 843 // Clear Divisor's kill flag. 844 Divisor.setIsKill(false); 845 846 // We would normally delete the original instruction here but in this case 847 // we only needed to inject an additional instruction rather than replace it. 848 849 return &MBB; 850 } 851 852 MachineBasicBlock * 853 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 854 MachineBasicBlock *BB) const { 855 switch (MI->getOpcode()) { 856 default: 857 llvm_unreachable("Unexpected instr type to insert"); 858 case Mips::ATOMIC_LOAD_ADD_I8: 859 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 860 case Mips::ATOMIC_LOAD_ADD_I16: 861 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 862 case Mips::ATOMIC_LOAD_ADD_I32: 863 return emitAtomicBinary(MI, BB, 4, Mips::ADDu); 864 case Mips::ATOMIC_LOAD_ADD_I64: 865 return emitAtomicBinary(MI, BB, 8, Mips::DADDu); 866 867 case Mips::ATOMIC_LOAD_AND_I8: 868 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 869 case Mips::ATOMIC_LOAD_AND_I16: 870 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 871 case Mips::ATOMIC_LOAD_AND_I32: 872 return emitAtomicBinary(MI, BB, 4, Mips::AND); 873 case Mips::ATOMIC_LOAD_AND_I64: 874 return emitAtomicBinary(MI, BB, 8, Mips::AND64); 875 876 case Mips::ATOMIC_LOAD_OR_I8: 877 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 878 case Mips::ATOMIC_LOAD_OR_I16: 879 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 880 case Mips::ATOMIC_LOAD_OR_I32: 881 return emitAtomicBinary(MI, BB, 4, Mips::OR); 882 case Mips::ATOMIC_LOAD_OR_I64: 883 return emitAtomicBinary(MI, BB, 8, Mips::OR64); 884 885 case Mips::ATOMIC_LOAD_XOR_I8: 886 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 887 case Mips::ATOMIC_LOAD_XOR_I16: 888 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 889 case Mips::ATOMIC_LOAD_XOR_I32: 890 return emitAtomicBinary(MI, BB, 4, Mips::XOR); 891 case Mips::ATOMIC_LOAD_XOR_I64: 892 return emitAtomicBinary(MI, BB, 8, Mips::XOR64); 893 894 case Mips::ATOMIC_LOAD_NAND_I8: 895 return emitAtomicBinaryPartword(MI, BB, 1, 0, true); 896 case Mips::ATOMIC_LOAD_NAND_I16: 897 return emitAtomicBinaryPartword(MI, BB, 2, 0, true); 898 case Mips::ATOMIC_LOAD_NAND_I32: 899 return emitAtomicBinary(MI, BB, 4, 0, true); 900 case Mips::ATOMIC_LOAD_NAND_I64: 901 return emitAtomicBinary(MI, BB, 8, 0, true); 902 903 case Mips::ATOMIC_LOAD_SUB_I8: 904 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 905 case Mips::ATOMIC_LOAD_SUB_I16: 906 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 907 case Mips::ATOMIC_LOAD_SUB_I32: 908 return emitAtomicBinary(MI, BB, 4, Mips::SUBu); 909 case Mips::ATOMIC_LOAD_SUB_I64: 910 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu); 911 912 case Mips::ATOMIC_SWAP_I8: 913 return emitAtomicBinaryPartword(MI, BB, 1, 0); 914 case Mips::ATOMIC_SWAP_I16: 915 return emitAtomicBinaryPartword(MI, BB, 2, 0); 916 case Mips::ATOMIC_SWAP_I32: 917 return emitAtomicBinary(MI, BB, 4, 0); 918 case Mips::ATOMIC_SWAP_I64: 919 return emitAtomicBinary(MI, BB, 8, 0); 920 921 case Mips::ATOMIC_CMP_SWAP_I8: 922 return emitAtomicCmpSwapPartword(MI, BB, 1); 923 case Mips::ATOMIC_CMP_SWAP_I16: 924 return emitAtomicCmpSwapPartword(MI, BB, 2); 925 case Mips::ATOMIC_CMP_SWAP_I32: 926 return emitAtomicCmpSwap(MI, BB, 4); 927 case Mips::ATOMIC_CMP_SWAP_I64: 928 return emitAtomicCmpSwap(MI, BB, 8); 929 case Mips::PseudoSDIV: 930 case Mips::PseudoUDIV: 931 case Mips::DIV: 932 case Mips::DIVU: 933 case Mips::MOD: 934 case Mips::MODU: 935 return insertDivByZeroTrap(MI, *BB, *getTargetMachine().getInstrInfo(), 936 false); 937 case Mips::PseudoDSDIV: 938 case Mips::PseudoDUDIV: 939 case Mips::DDIV: 940 case Mips::DDIVU: 941 case Mips::DMOD: 942 case Mips::DMODU: 943 return insertDivByZeroTrap(MI, *BB, *getTargetMachine().getInstrInfo(), 944 true); 945 case Mips::SEL_D: 946 return emitSEL_D(MI, BB); 947 } 948 } 949 950 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 951 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 952 MachineBasicBlock * 953 MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 954 unsigned Size, unsigned BinOpcode, 955 bool Nand) const { 956 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 957 958 MachineFunction *MF = BB->getParent(); 959 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 960 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 961 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 962 DebugLoc DL = MI->getDebugLoc(); 963 unsigned LL, SC, AND, NOR, ZERO, BEQ; 964 965 if (Size == 4) { 966 if (isMicroMips) { 967 LL = Mips::LL_MM; 968 SC = Mips::SC_MM; 969 } else { 970 LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL; 971 SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC; 972 } 973 AND = Mips::AND; 974 NOR = Mips::NOR; 975 ZERO = Mips::ZERO; 976 BEQ = Mips::BEQ; 977 } else { 978 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 979 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 980 AND = Mips::AND64; 981 NOR = Mips::NOR64; 982 ZERO = Mips::ZERO_64; 983 BEQ = Mips::BEQ64; 984 } 985 986 unsigned OldVal = MI->getOperand(0).getReg(); 987 unsigned Ptr = MI->getOperand(1).getReg(); 988 unsigned Incr = MI->getOperand(2).getReg(); 989 990 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 991 unsigned AndRes = RegInfo.createVirtualRegister(RC); 992 unsigned Success = RegInfo.createVirtualRegister(RC); 993 994 // insert new blocks after the current block 995 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 996 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 997 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 998 MachineFunction::iterator It = BB; 999 ++It; 1000 MF->insert(It, loopMBB); 1001 MF->insert(It, exitMBB); 1002 1003 // Transfer the remainder of BB and its successor edges to exitMBB. 1004 exitMBB->splice(exitMBB->begin(), BB, 1005 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1006 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1007 1008 // thisMBB: 1009 // ... 1010 // fallthrough --> loopMBB 1011 BB->addSuccessor(loopMBB); 1012 loopMBB->addSuccessor(loopMBB); 1013 loopMBB->addSuccessor(exitMBB); 1014 1015 // loopMBB: 1016 // ll oldval, 0(ptr) 1017 // <binop> storeval, oldval, incr 1018 // sc success, storeval, 0(ptr) 1019 // beq success, $0, loopMBB 1020 BB = loopMBB; 1021 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1022 if (Nand) { 1023 // and andres, oldval, incr 1024 // nor storeval, $0, andres 1025 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1026 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1027 } else if (BinOpcode) { 1028 // <binop> storeval, oldval, incr 1029 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1030 } else { 1031 StoreVal = Incr; 1032 } 1033 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1034 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1035 1036 MI->eraseFromParent(); // The instruction is gone now. 1037 1038 return exitMBB; 1039 } 1040 1041 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( 1042 MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, 1043 unsigned SrcReg) const { 1044 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1045 DebugLoc DL = MI->getDebugLoc(); 1046 1047 if (Subtarget.hasMips32r2() && Size == 1) { 1048 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); 1049 return BB; 1050 } 1051 1052 if (Subtarget.hasMips32r2() && Size == 2) { 1053 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); 1054 return BB; 1055 } 1056 1057 MachineFunction *MF = BB->getParent(); 1058 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1059 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1060 unsigned ScrReg = RegInfo.createVirtualRegister(RC); 1061 1062 assert(Size < 32); 1063 int64_t ShiftImm = 32 - (Size * 8); 1064 1065 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); 1066 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); 1067 1068 return BB; 1069 } 1070 1071 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( 1072 MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 1073 bool Nand) const { 1074 assert((Size == 1 || Size == 2) && 1075 "Unsupported size for EmitAtomicBinaryPartial."); 1076 1077 MachineFunction *MF = BB->getParent(); 1078 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1079 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1080 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1081 DebugLoc DL = MI->getDebugLoc(); 1082 1083 unsigned Dest = MI->getOperand(0).getReg(); 1084 unsigned Ptr = MI->getOperand(1).getReg(); 1085 unsigned Incr = MI->getOperand(2).getReg(); 1086 1087 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1088 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1089 unsigned Mask = RegInfo.createVirtualRegister(RC); 1090 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1091 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1092 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1093 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1094 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1095 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1096 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1097 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1098 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1099 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1100 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1101 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1102 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1103 unsigned Success = RegInfo.createVirtualRegister(RC); 1104 1105 // insert new blocks after the current block 1106 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1107 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1108 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1109 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1110 MachineFunction::iterator It = BB; 1111 ++It; 1112 MF->insert(It, loopMBB); 1113 MF->insert(It, sinkMBB); 1114 MF->insert(It, exitMBB); 1115 1116 // Transfer the remainder of BB and its successor edges to exitMBB. 1117 exitMBB->splice(exitMBB->begin(), BB, 1118 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1119 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1120 1121 BB->addSuccessor(loopMBB); 1122 loopMBB->addSuccessor(loopMBB); 1123 loopMBB->addSuccessor(sinkMBB); 1124 sinkMBB->addSuccessor(exitMBB); 1125 1126 // thisMBB: 1127 // addiu masklsb2,$0,-4 # 0xfffffffc 1128 // and alignedaddr,ptr,masklsb2 1129 // andi ptrlsb2,ptr,3 1130 // sll shiftamt,ptrlsb2,3 1131 // ori maskupper,$0,255 # 0xff 1132 // sll mask,maskupper,shiftamt 1133 // nor mask2,$0,mask 1134 // sll incr2,incr,shiftamt 1135 1136 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1137 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) 1138 .addReg(Mips::ZERO).addImm(-4); 1139 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1140 .addReg(Ptr).addReg(MaskLSB2); 1141 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1142 if (Subtarget.isLittle()) { 1143 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1144 } else { 1145 unsigned Off = RegInfo.createVirtualRegister(RC); 1146 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1147 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1148 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1149 } 1150 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1151 .addReg(Mips::ZERO).addImm(MaskImm); 1152 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1153 .addReg(MaskUpper).addReg(ShiftAmt); 1154 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1155 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1156 1157 // atomic.load.binop 1158 // loopMBB: 1159 // ll oldval,0(alignedaddr) 1160 // binop binopres,oldval,incr2 1161 // and newval,binopres,mask 1162 // and maskedoldval0,oldval,mask2 1163 // or storeval,maskedoldval0,newval 1164 // sc success,storeval,0(alignedaddr) 1165 // beq success,$0,loopMBB 1166 1167 // atomic.swap 1168 // loopMBB: 1169 // ll oldval,0(alignedaddr) 1170 // and newval,incr2,mask 1171 // and maskedoldval0,oldval,mask2 1172 // or storeval,maskedoldval0,newval 1173 // sc success,storeval,0(alignedaddr) 1174 // beq success,$0,loopMBB 1175 1176 BB = loopMBB; 1177 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1178 if (Nand) { 1179 // and andres, oldval, incr2 1180 // nor binopres, $0, andres 1181 // and newval, binopres, mask 1182 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1183 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes) 1184 .addReg(Mips::ZERO).addReg(AndRes); 1185 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1186 } else if (BinOpcode) { 1187 // <binop> binopres, oldval, incr2 1188 // and newval, binopres, mask 1189 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1190 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1191 } else { // atomic.swap 1192 // and newval, incr2, mask 1193 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1194 } 1195 1196 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1197 .addReg(OldVal).addReg(Mask2); 1198 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1199 .addReg(MaskedOldVal0).addReg(NewVal); 1200 BuildMI(BB, DL, TII->get(Mips::SC), Success) 1201 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1202 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1203 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1204 1205 // sinkMBB: 1206 // and maskedoldval1,oldval,mask 1207 // srl srlres,maskedoldval1,shiftamt 1208 // sign_extend dest,srlres 1209 BB = sinkMBB; 1210 1211 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1212 .addReg(OldVal).addReg(Mask); 1213 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1214 .addReg(MaskedOldVal1).addReg(ShiftAmt); 1215 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1216 1217 MI->eraseFromParent(); // The instruction is gone now. 1218 1219 return exitMBB; 1220 } 1221 1222 MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI, 1223 MachineBasicBlock *BB, 1224 unsigned Size) const { 1225 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1226 1227 MachineFunction *MF = BB->getParent(); 1228 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1229 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1230 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1231 DebugLoc DL = MI->getDebugLoc(); 1232 unsigned LL, SC, ZERO, BNE, BEQ; 1233 1234 if (Size == 4) { 1235 LL = isMicroMips ? Mips::LL_MM : Mips::LL; 1236 SC = isMicroMips ? Mips::SC_MM : Mips::SC; 1237 ZERO = Mips::ZERO; 1238 BNE = Mips::BNE; 1239 BEQ = Mips::BEQ; 1240 } else { 1241 LL = Mips::LLD; 1242 SC = Mips::SCD; 1243 ZERO = Mips::ZERO_64; 1244 BNE = Mips::BNE64; 1245 BEQ = Mips::BEQ64; 1246 } 1247 1248 unsigned Dest = MI->getOperand(0).getReg(); 1249 unsigned Ptr = MI->getOperand(1).getReg(); 1250 unsigned OldVal = MI->getOperand(2).getReg(); 1251 unsigned NewVal = MI->getOperand(3).getReg(); 1252 1253 unsigned Success = RegInfo.createVirtualRegister(RC); 1254 1255 // insert new blocks after the current block 1256 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1257 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1258 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1259 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1260 MachineFunction::iterator It = BB; 1261 ++It; 1262 MF->insert(It, loop1MBB); 1263 MF->insert(It, loop2MBB); 1264 MF->insert(It, exitMBB); 1265 1266 // Transfer the remainder of BB and its successor edges to exitMBB. 1267 exitMBB->splice(exitMBB->begin(), BB, 1268 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1269 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1270 1271 // thisMBB: 1272 // ... 1273 // fallthrough --> loop1MBB 1274 BB->addSuccessor(loop1MBB); 1275 loop1MBB->addSuccessor(exitMBB); 1276 loop1MBB->addSuccessor(loop2MBB); 1277 loop2MBB->addSuccessor(loop1MBB); 1278 loop2MBB->addSuccessor(exitMBB); 1279 1280 // loop1MBB: 1281 // ll dest, 0(ptr) 1282 // bne dest, oldval, exitMBB 1283 BB = loop1MBB; 1284 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1285 BuildMI(BB, DL, TII->get(BNE)) 1286 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1287 1288 // loop2MBB: 1289 // sc success, newval, 0(ptr) 1290 // beq success, $0, loop1MBB 1291 BB = loop2MBB; 1292 BuildMI(BB, DL, TII->get(SC), Success) 1293 .addReg(NewVal).addReg(Ptr).addImm(0); 1294 BuildMI(BB, DL, TII->get(BEQ)) 1295 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1296 1297 MI->eraseFromParent(); // The instruction is gone now. 1298 1299 return exitMBB; 1300 } 1301 1302 MachineBasicBlock * 1303 MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI, 1304 MachineBasicBlock *BB, 1305 unsigned Size) const { 1306 assert((Size == 1 || Size == 2) && 1307 "Unsupported size for EmitAtomicCmpSwapPartial."); 1308 1309 MachineFunction *MF = BB->getParent(); 1310 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1311 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1312 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1313 DebugLoc DL = MI->getDebugLoc(); 1314 1315 unsigned Dest = MI->getOperand(0).getReg(); 1316 unsigned Ptr = MI->getOperand(1).getReg(); 1317 unsigned CmpVal = MI->getOperand(2).getReg(); 1318 unsigned NewVal = MI->getOperand(3).getReg(); 1319 1320 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1321 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1322 unsigned Mask = RegInfo.createVirtualRegister(RC); 1323 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1324 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1325 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1326 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1327 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1328 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1329 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1330 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1331 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1332 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1333 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1334 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1335 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1336 unsigned Success = RegInfo.createVirtualRegister(RC); 1337 1338 // insert new blocks after the current block 1339 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1340 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1341 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1342 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1343 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1344 MachineFunction::iterator It = BB; 1345 ++It; 1346 MF->insert(It, loop1MBB); 1347 MF->insert(It, loop2MBB); 1348 MF->insert(It, sinkMBB); 1349 MF->insert(It, exitMBB); 1350 1351 // Transfer the remainder of BB and its successor edges to exitMBB. 1352 exitMBB->splice(exitMBB->begin(), BB, 1353 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1354 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1355 1356 BB->addSuccessor(loop1MBB); 1357 loop1MBB->addSuccessor(sinkMBB); 1358 loop1MBB->addSuccessor(loop2MBB); 1359 loop2MBB->addSuccessor(loop1MBB); 1360 loop2MBB->addSuccessor(sinkMBB); 1361 sinkMBB->addSuccessor(exitMBB); 1362 1363 // FIXME: computation of newval2 can be moved to loop2MBB. 1364 // thisMBB: 1365 // addiu masklsb2,$0,-4 # 0xfffffffc 1366 // and alignedaddr,ptr,masklsb2 1367 // andi ptrlsb2,ptr,3 1368 // sll shiftamt,ptrlsb2,3 1369 // ori maskupper,$0,255 # 0xff 1370 // sll mask,maskupper,shiftamt 1371 // nor mask2,$0,mask 1372 // andi maskedcmpval,cmpval,255 1373 // sll shiftedcmpval,maskedcmpval,shiftamt 1374 // andi maskednewval,newval,255 1375 // sll shiftednewval,maskednewval,shiftamt 1376 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1377 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) 1378 .addReg(Mips::ZERO).addImm(-4); 1379 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1380 .addReg(Ptr).addReg(MaskLSB2); 1381 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1382 if (Subtarget.isLittle()) { 1383 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1384 } else { 1385 unsigned Off = RegInfo.createVirtualRegister(RC); 1386 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1387 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1388 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1389 } 1390 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1391 .addReg(Mips::ZERO).addImm(MaskImm); 1392 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1393 .addReg(MaskUpper).addReg(ShiftAmt); 1394 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1395 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1396 .addReg(CmpVal).addImm(MaskImm); 1397 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1398 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1399 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1400 .addReg(NewVal).addImm(MaskImm); 1401 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1402 .addReg(MaskedNewVal).addReg(ShiftAmt); 1403 1404 // loop1MBB: 1405 // ll oldval,0(alginedaddr) 1406 // and maskedoldval0,oldval,mask 1407 // bne maskedoldval0,shiftedcmpval,sinkMBB 1408 BB = loop1MBB; 1409 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1410 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1411 .addReg(OldVal).addReg(Mask); 1412 BuildMI(BB, DL, TII->get(Mips::BNE)) 1413 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1414 1415 // loop2MBB: 1416 // and maskedoldval1,oldval,mask2 1417 // or storeval,maskedoldval1,shiftednewval 1418 // sc success,storeval,0(alignedaddr) 1419 // beq success,$0,loop1MBB 1420 BB = loop2MBB; 1421 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1422 .addReg(OldVal).addReg(Mask2); 1423 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1424 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1425 BuildMI(BB, DL, TII->get(Mips::SC), Success) 1426 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1427 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1428 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1429 1430 // sinkMBB: 1431 // srl srlres,maskedoldval0,shiftamt 1432 // sign_extend dest,srlres 1433 BB = sinkMBB; 1434 1435 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1436 .addReg(MaskedOldVal0).addReg(ShiftAmt); 1437 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1438 1439 MI->eraseFromParent(); // The instruction is gone now. 1440 1441 return exitMBB; 1442 } 1443 1444 MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr *MI, 1445 MachineBasicBlock *BB) const { 1446 MachineFunction *MF = BB->getParent(); 1447 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 1448 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1449 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1450 DebugLoc DL = MI->getDebugLoc(); 1451 MachineBasicBlock::iterator II(MI); 1452 1453 unsigned Fc = MI->getOperand(1).getReg(); 1454 const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID); 1455 1456 unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass); 1457 1458 BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2) 1459 .addImm(0) 1460 .addReg(Fc) 1461 .addImm(Mips::sub_lo); 1462 1463 // We don't erase the original instruction, we just replace the condition 1464 // register with the 64-bit super-register. 1465 MI->getOperand(1).setReg(Fc2); 1466 1467 return BB; 1468 } 1469 1470 //===----------------------------------------------------------------------===// 1471 // Misc Lower Operation implementation 1472 //===----------------------------------------------------------------------===// 1473 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 1474 SDValue Chain = Op.getOperand(0); 1475 SDValue Table = Op.getOperand(1); 1476 SDValue Index = Op.getOperand(2); 1477 SDLoc DL(Op); 1478 EVT PTy = getPointerTy(); 1479 unsigned EntrySize = 1480 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout()); 1481 1482 Index = DAG.getNode(ISD::MUL, DL, PTy, Index, 1483 DAG.getConstant(EntrySize, PTy)); 1484 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table); 1485 1486 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 1487 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr, 1488 MachinePointerInfo::getJumpTable(), MemVT, false, false, 1489 0); 1490 Chain = Addr.getValue(1); 1491 1492 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || 1493 Subtarget.isABI_N64()) { 1494 // For PIC, the sequence is: 1495 // BRIND(load(Jumptable + index) + RelocBase) 1496 // RelocBase can be JumpTable, GOT or some sort of global base. 1497 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr, 1498 getPICJumpTableRelocBase(Table, DAG)); 1499 } 1500 1501 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr); 1502 } 1503 1504 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 1505 // The first operand is the chain, the second is the condition, the third is 1506 // the block to branch to if the condition is true. 1507 SDValue Chain = Op.getOperand(0); 1508 SDValue Dest = Op.getOperand(2); 1509 SDLoc DL(Op); 1510 1511 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1512 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1513 1514 // Return if flag is not set by a floating point comparison. 1515 if (CondRes.getOpcode() != MipsISD::FPCmp) 1516 return Op; 1517 1518 SDValue CCNode = CondRes.getOperand(2); 1519 Mips::CondCode CC = 1520 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1521 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1522 SDValue BrCode = DAG.getConstant(Opc, MVT::i32); 1523 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1524 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1525 FCC0, Dest, CondRes); 1526 } 1527 1528 SDValue MipsTargetLowering:: 1529 lowerSELECT(SDValue Op, SelectionDAG &DAG) const 1530 { 1531 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1532 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1533 1534 // Return if flag is not set by a floating point comparison. 1535 if (Cond.getOpcode() != MipsISD::FPCmp) 1536 return Op; 1537 1538 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1539 SDLoc(Op)); 1540 } 1541 1542 SDValue MipsTargetLowering:: 1543 lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const 1544 { 1545 SDLoc DL(Op); 1546 EVT Ty = Op.getOperand(0).getValueType(); 1547 SDValue Cond = DAG.getNode(ISD::SETCC, DL, 1548 getSetCCResultType(*DAG.getContext(), Ty), 1549 Op.getOperand(0), Op.getOperand(1), 1550 Op.getOperand(4)); 1551 1552 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2), 1553 Op.getOperand(3)); 1554 } 1555 1556 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1557 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1558 SDValue Cond = createFPCmp(DAG, Op); 1559 1560 assert(Cond.getOpcode() == MipsISD::FPCmp && 1561 "Floating point operand expected."); 1562 1563 SDValue True = DAG.getConstant(1, MVT::i32); 1564 SDValue False = DAG.getConstant(0, MVT::i32); 1565 1566 return createCMovFP(DAG, Cond, True, False, SDLoc(Op)); 1567 } 1568 1569 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 1570 SelectionDAG &DAG) const { 1571 // FIXME there isn't actually debug info here 1572 SDLoc DL(Op); 1573 EVT Ty = Op.getValueType(); 1574 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 1575 const GlobalValue *GV = N->getGlobal(); 1576 1577 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && 1578 !Subtarget.isABI_N64()) { 1579 const MipsTargetObjectFile &TLOF = 1580 (const MipsTargetObjectFile&)getObjFileLowering(); 1581 1582 // %gp_rel relocation 1583 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1584 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0, 1585 MipsII::MO_GPREL); 1586 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, DL, 1587 DAG.getVTList(MVT::i32), GA); 1588 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32); 1589 return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode); 1590 } 1591 1592 // %hi/%lo relocation 1593 return getAddrNonPIC(N, Ty, DAG); 1594 } 1595 1596 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV))) 1597 return getAddrLocal(N, Ty, DAG, 1598 Subtarget.isABI_N32() || Subtarget.isABI_N64()); 1599 1600 if (LargeGOT) 1601 return getAddrGlobalLargeGOT(N, Ty, DAG, MipsII::MO_GOT_HI16, 1602 MipsII::MO_GOT_LO16, DAG.getEntryNode(), 1603 MachinePointerInfo::getGOT()); 1604 1605 return getAddrGlobal(N, Ty, DAG, 1606 (Subtarget.isABI_N32() || Subtarget.isABI_N64()) 1607 ? MipsII::MO_GOT_DISP 1608 : MipsII::MO_GOT16, 1609 DAG.getEntryNode(), MachinePointerInfo::getGOT()); 1610 } 1611 1612 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 1613 SelectionDAG &DAG) const { 1614 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 1615 EVT Ty = Op.getValueType(); 1616 1617 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && 1618 !Subtarget.isABI_N64()) 1619 return getAddrNonPIC(N, Ty, DAG); 1620 1621 return getAddrLocal(N, Ty, DAG, 1622 Subtarget.isABI_N32() || Subtarget.isABI_N64()); 1623 } 1624 1625 SDValue MipsTargetLowering:: 1626 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1627 { 1628 // If the relocation model is PIC, use the General Dynamic TLS Model or 1629 // Local Dynamic TLS model, otherwise use the Initial Exec or 1630 // Local Exec TLS Model. 1631 1632 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1633 SDLoc DL(GA); 1634 const GlobalValue *GV = GA->getGlobal(); 1635 EVT PtrVT = getPointerTy(); 1636 1637 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1638 1639 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1640 // General Dynamic and Local Dynamic TLS Model. 1641 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1642 : MipsII::MO_TLSGD; 1643 1644 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 1645 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 1646 getGlobalReg(DAG, PtrVT), TGA); 1647 unsigned PtrSize = PtrVT.getSizeInBits(); 1648 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1649 1650 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1651 1652 ArgListTy Args; 1653 ArgListEntry Entry; 1654 Entry.Node = Argument; 1655 Entry.Ty = PtrTy; 1656 Args.push_back(Entry); 1657 1658 TargetLowering::CallLoweringInfo CLI(DAG); 1659 CLI.setDebugLoc(DL).setChain(DAG.getEntryNode()) 1660 .setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args), 0); 1661 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1662 1663 SDValue Ret = CallResult.first; 1664 1665 if (model != TLSModel::LocalDynamic) 1666 return Ret; 1667 1668 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1669 MipsII::MO_DTPREL_HI); 1670 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1671 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1672 MipsII::MO_DTPREL_LO); 1673 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1674 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 1675 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 1676 } 1677 1678 SDValue Offset; 1679 if (model == TLSModel::InitialExec) { 1680 // Initial Exec TLS Model 1681 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1682 MipsII::MO_GOTTPREL); 1683 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 1684 TGA); 1685 Offset = DAG.getLoad(PtrVT, DL, 1686 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1687 false, false, false, 0); 1688 } else { 1689 // Local Exec TLS Model 1690 assert(model == TLSModel::LocalExec); 1691 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1692 MipsII::MO_TPREL_HI); 1693 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1694 MipsII::MO_TPREL_LO); 1695 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1696 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1697 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1698 } 1699 1700 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 1701 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 1702 } 1703 1704 SDValue MipsTargetLowering:: 1705 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1706 { 1707 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 1708 EVT Ty = Op.getValueType(); 1709 1710 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && 1711 !Subtarget.isABI_N64()) 1712 return getAddrNonPIC(N, Ty, DAG); 1713 1714 return getAddrLocal(N, Ty, DAG, 1715 Subtarget.isABI_N32() || Subtarget.isABI_N64()); 1716 } 1717 1718 SDValue MipsTargetLowering:: 1719 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1720 { 1721 // gp_rel relocation 1722 // FIXME: we should reference the constant pool using small data sections, 1723 // but the asm printer currently doesn't support this feature without 1724 // hacking it. This feature should come soon so we can uncomment the 1725 // stuff below. 1726 //if (IsInSmallSection(C->getType())) { 1727 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1728 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1729 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1730 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1731 EVT Ty = Op.getValueType(); 1732 1733 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && 1734 !Subtarget.isABI_N64()) 1735 return getAddrNonPIC(N, Ty, DAG); 1736 1737 return getAddrLocal(N, Ty, DAG, 1738 Subtarget.isABI_N32() || Subtarget.isABI_N64()); 1739 } 1740 1741 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1742 MachineFunction &MF = DAG.getMachineFunction(); 1743 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1744 1745 SDLoc DL(Op); 1746 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1747 getPointerTy()); 1748 1749 // vastart just stores the address of the VarArgsFrameIndex slot into the 1750 // memory location argument. 1751 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1752 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 1753 MachinePointerInfo(SV), false, false, 0); 1754 } 1755 1756 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { 1757 SDNode *Node = Op.getNode(); 1758 EVT VT = Node->getValueType(0); 1759 SDValue Chain = Node->getOperand(0); 1760 SDValue VAListPtr = Node->getOperand(1); 1761 unsigned Align = Node->getConstantOperandVal(3); 1762 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1763 SDLoc DL(Node); 1764 unsigned ArgSlotSizeInBytes = 1765 (Subtarget.isABI_N32() || Subtarget.isABI_N64()) ? 8 : 4; 1766 1767 SDValue VAListLoad = DAG.getLoad(getPointerTy(), DL, Chain, VAListPtr, 1768 MachinePointerInfo(SV), false, false, false, 1769 0); 1770 SDValue VAList = VAListLoad; 1771 1772 // Re-align the pointer if necessary. 1773 // It should only ever be necessary for 64-bit types on O32 since the minimum 1774 // argument alignment is the same as the maximum type alignment for N32/N64. 1775 // 1776 // FIXME: We currently align too often. The code generator doesn't notice 1777 // when the pointer is still aligned from the last va_arg (or pair of 1778 // va_args for the i64 on O32 case). 1779 if (Align > getMinStackArgumentAlignment()) { 1780 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 1781 1782 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 1783 DAG.getConstant(Align - 1, 1784 VAList.getValueType())); 1785 1786 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList, 1787 DAG.getConstant(-(int64_t)Align, 1788 VAList.getValueType())); 1789 } 1790 1791 // Increment the pointer, VAList, to the next vaarg. 1792 unsigned ArgSizeInBytes = getDataLayout()->getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); 1793 SDValue Tmp3 = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 1794 DAG.getConstant(RoundUpToAlignment(ArgSizeInBytes, ArgSlotSizeInBytes), 1795 VAList.getValueType())); 1796 // Store the incremented VAList to the legalized pointer 1797 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, 1798 MachinePointerInfo(SV), false, false, 0); 1799 1800 // In big-endian mode we must adjust the pointer when the load size is smaller 1801 // than the argument slot size. We must also reduce the known alignment to 1802 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get 1803 // the correct half of the slot, and reduce the alignment from 8 (slot 1804 // alignment) down to 4 (type alignment). 1805 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { 1806 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; 1807 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, 1808 DAG.getIntPtrConstant(Adjustment)); 1809 } 1810 // Load the actual argument out of the pointer VAList 1811 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo(), false, false, 1812 false, 0); 1813 } 1814 1815 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 1816 bool HasExtractInsert) { 1817 EVT TyX = Op.getOperand(0).getValueType(); 1818 EVT TyY = Op.getOperand(1).getValueType(); 1819 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1820 SDValue Const31 = DAG.getConstant(31, MVT::i32); 1821 SDLoc DL(Op); 1822 SDValue Res; 1823 1824 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1825 // to i32. 1826 SDValue X = (TyX == MVT::f32) ? 1827 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1828 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1829 Const1); 1830 SDValue Y = (TyY == MVT::f32) ? 1831 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 1832 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 1833 Const1); 1834 1835 if (HasExtractInsert) { 1836 // ext E, Y, 31, 1 ; extract bit31 of Y 1837 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 1838 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 1839 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 1840 } else { 1841 // sll SllX, X, 1 1842 // srl SrlX, SllX, 1 1843 // srl SrlY, Y, 31 1844 // sll SllY, SrlX, 31 1845 // or Or, SrlX, SllY 1846 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1847 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1848 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 1849 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 1850 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 1851 } 1852 1853 if (TyX == MVT::f32) 1854 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 1855 1856 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1857 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1858 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1859 } 1860 1861 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 1862 bool HasExtractInsert) { 1863 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 1864 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 1865 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 1866 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1867 SDLoc DL(Op); 1868 1869 // Bitcast to integer nodes. 1870 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 1871 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 1872 1873 if (HasExtractInsert) { 1874 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 1875 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 1876 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 1877 DAG.getConstant(WidthY - 1, MVT::i32), Const1); 1878 1879 if (WidthX > WidthY) 1880 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 1881 else if (WidthY > WidthX) 1882 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 1883 1884 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 1885 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X); 1886 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 1887 } 1888 1889 // (d)sll SllX, X, 1 1890 // (d)srl SrlX, SllX, 1 1891 // (d)srl SrlY, Y, width(Y)-1 1892 // (d)sll SllY, SrlX, width(Y)-1 1893 // or Or, SrlX, SllY 1894 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 1895 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 1896 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 1897 DAG.getConstant(WidthY - 1, MVT::i32)); 1898 1899 if (WidthX > WidthY) 1900 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 1901 else if (WidthY > WidthX) 1902 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 1903 1904 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 1905 DAG.getConstant(WidthX - 1, MVT::i32)); 1906 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 1907 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 1908 } 1909 1910 SDValue 1911 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 1912 if (Subtarget.isGP64bit()) 1913 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); 1914 1915 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); 1916 } 1917 1918 SDValue MipsTargetLowering:: 1919 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 1920 // check the depth 1921 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1922 "Frame address can only be determined for current frame."); 1923 1924 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1925 MFI->setFrameAddressIsTaken(true); 1926 EVT VT = Op.getValueType(); 1927 SDLoc DL(Op); 1928 SDValue FrameAddr = 1929 DAG.getCopyFromReg(DAG.getEntryNode(), DL, 1930 Subtarget.isABI_N64() ? Mips::FP_64 : Mips::FP, VT); 1931 return FrameAddr; 1932 } 1933 1934 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 1935 SelectionDAG &DAG) const { 1936 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 1937 return SDValue(); 1938 1939 // check the depth 1940 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1941 "Return address can be determined only for current frame."); 1942 1943 MachineFunction &MF = DAG.getMachineFunction(); 1944 MachineFrameInfo *MFI = MF.getFrameInfo(); 1945 MVT VT = Op.getSimpleValueType(); 1946 unsigned RA = Subtarget.isABI_N64() ? Mips::RA_64 : Mips::RA; 1947 MFI->setReturnAddressIsTaken(true); 1948 1949 // Return RA, which contains the return address. Mark it an implicit live-in. 1950 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 1951 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 1952 } 1953 1954 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is 1955 // generated from __builtin_eh_return (offset, handler) 1956 // The effect of this is to adjust the stack pointer by "offset" 1957 // and then branch to "handler". 1958 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 1959 const { 1960 MachineFunction &MF = DAG.getMachineFunction(); 1961 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1962 1963 MipsFI->setCallsEhReturn(); 1964 SDValue Chain = Op.getOperand(0); 1965 SDValue Offset = Op.getOperand(1); 1966 SDValue Handler = Op.getOperand(2); 1967 SDLoc DL(Op); 1968 EVT Ty = Subtarget.isABI_N64() ? MVT::i64 : MVT::i32; 1969 1970 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 1971 // EH_RETURN nodes, so that instructions are emitted back-to-back. 1972 unsigned OffsetReg = Subtarget.isABI_N64() ? Mips::V1_64 : Mips::V1; 1973 unsigned AddrReg = Subtarget.isABI_N64() ? Mips::V0_64 : Mips::V0; 1974 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 1975 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 1976 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 1977 DAG.getRegister(OffsetReg, Ty), 1978 DAG.getRegister(AddrReg, getPointerTy()), 1979 Chain.getValue(1)); 1980 } 1981 1982 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 1983 SelectionDAG &DAG) const { 1984 // FIXME: Need pseudo-fence for 'singlethread' fences 1985 // FIXME: Set SType for weaker fences where supported/appropriate. 1986 unsigned SType = 0; 1987 SDLoc DL(Op); 1988 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 1989 DAG.getConstant(SType, MVT::i32)); 1990 } 1991 1992 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 1993 SelectionDAG &DAG) const { 1994 SDLoc DL(Op); 1995 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 1996 SDValue Shamt = Op.getOperand(2); 1997 1998 // if shamt < 32: 1999 // lo = (shl lo, shamt) 2000 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2001 // else: 2002 // lo = 0 2003 // hi = (shl lo, shamt[4:0]) 2004 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2005 DAG.getConstant(-1, MVT::i32)); 2006 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, 2007 DAG.getConstant(1, MVT::i32)); 2008 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, 2009 Not); 2010 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt); 2011 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 2012 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt); 2013 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2014 DAG.getConstant(0x20, MVT::i32)); 2015 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 2016 DAG.getConstant(0, MVT::i32), ShiftLeftLo); 2017 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or); 2018 2019 SDValue Ops[2] = {Lo, Hi}; 2020 return DAG.getMergeValues(Ops, DL); 2021 } 2022 2023 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2024 bool IsSRA) const { 2025 SDLoc DL(Op); 2026 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2027 SDValue Shamt = Op.getOperand(2); 2028 2029 // if shamt < 32: 2030 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2031 // if isSRA: 2032 // hi = (sra hi, shamt) 2033 // else: 2034 // hi = (srl hi, shamt) 2035 // else: 2036 // if isSRA: 2037 // lo = (sra hi, shamt[4:0]) 2038 // hi = (sra hi, 31) 2039 // else: 2040 // lo = (srl hi, shamt[4:0]) 2041 // hi = 0 2042 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2043 DAG.getConstant(-1, MVT::i32)); 2044 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, 2045 DAG.getConstant(1, MVT::i32)); 2046 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not); 2047 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); 2048 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 2049 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32, 2050 Hi, Shamt); 2051 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2052 DAG.getConstant(0x20, MVT::i32)); 2053 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi, 2054 DAG.getConstant(31, MVT::i32)); 2055 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or); 2056 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 2057 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32), 2058 ShiftRightHi); 2059 2060 SDValue Ops[2] = {Lo, Hi}; 2061 return DAG.getMergeValues(Ops, DL); 2062 } 2063 2064 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2065 SDValue Chain, SDValue Src, unsigned Offset) { 2066 SDValue Ptr = LD->getBasePtr(); 2067 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2068 EVT BasePtrVT = Ptr.getValueType(); 2069 SDLoc DL(LD); 2070 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2071 2072 if (Offset) 2073 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2074 DAG.getConstant(Offset, BasePtrVT)); 2075 2076 SDValue Ops[] = { Chain, Ptr, Src }; 2077 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2078 LD->getMemOperand()); 2079 } 2080 2081 // Expand an unaligned 32 or 64-bit integer load node. 2082 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2083 LoadSDNode *LD = cast<LoadSDNode>(Op); 2084 EVT MemVT = LD->getMemoryVT(); 2085 2086 if (Subtarget.systemSupportsUnalignedAccess()) 2087 return Op; 2088 2089 // Return if load is aligned or if MemVT is neither i32 nor i64. 2090 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2091 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2092 return SDValue(); 2093 2094 bool IsLittle = Subtarget.isLittle(); 2095 EVT VT = Op.getValueType(); 2096 ISD::LoadExtType ExtType = LD->getExtensionType(); 2097 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2098 2099 assert((VT == MVT::i32) || (VT == MVT::i64)); 2100 2101 // Expand 2102 // (set dst, (i64 (load baseptr))) 2103 // to 2104 // (set tmp, (ldl (add baseptr, 7), undef)) 2105 // (set dst, (ldr baseptr, tmp)) 2106 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2107 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2108 IsLittle ? 7 : 0); 2109 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2110 IsLittle ? 0 : 7); 2111 } 2112 2113 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2114 IsLittle ? 3 : 0); 2115 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2116 IsLittle ? 0 : 3); 2117 2118 // Expand 2119 // (set dst, (i32 (load baseptr))) or 2120 // (set dst, (i64 (sextload baseptr))) or 2121 // (set dst, (i64 (extload baseptr))) 2122 // to 2123 // (set tmp, (lwl (add baseptr, 3), undef)) 2124 // (set dst, (lwr baseptr, tmp)) 2125 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2126 (ExtType == ISD::EXTLOAD)) 2127 return LWR; 2128 2129 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2130 2131 // Expand 2132 // (set dst, (i64 (zextload baseptr))) 2133 // to 2134 // (set tmp0, (lwl (add baseptr, 3), undef)) 2135 // (set tmp1, (lwr baseptr, tmp0)) 2136 // (set tmp2, (shl tmp1, 32)) 2137 // (set dst, (srl tmp2, 32)) 2138 SDLoc DL(LD); 2139 SDValue Const32 = DAG.getConstant(32, MVT::i32); 2140 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2141 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2142 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2143 return DAG.getMergeValues(Ops, DL); 2144 } 2145 2146 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2147 SDValue Chain, unsigned Offset) { 2148 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2149 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2150 SDLoc DL(SD); 2151 SDVTList VTList = DAG.getVTList(MVT::Other); 2152 2153 if (Offset) 2154 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2155 DAG.getConstant(Offset, BasePtrVT)); 2156 2157 SDValue Ops[] = { Chain, Value, Ptr }; 2158 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2159 SD->getMemOperand()); 2160 } 2161 2162 // Expand an unaligned 32 or 64-bit integer store node. 2163 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2164 bool IsLittle) { 2165 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2166 EVT VT = Value.getValueType(); 2167 2168 // Expand 2169 // (store val, baseptr) or 2170 // (truncstore val, baseptr) 2171 // to 2172 // (swl val, (add baseptr, 3)) 2173 // (swr val, baseptr) 2174 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2175 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2176 IsLittle ? 3 : 0); 2177 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2178 } 2179 2180 assert(VT == MVT::i64); 2181 2182 // Expand 2183 // (store val, baseptr) 2184 // to 2185 // (sdl val, (add baseptr, 7)) 2186 // (sdr val, baseptr) 2187 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2188 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2189 } 2190 2191 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2192 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) { 2193 SDValue Val = SD->getValue(); 2194 2195 if (Val.getOpcode() != ISD::FP_TO_SINT) 2196 return SDValue(); 2197 2198 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2199 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2200 Val.getOperand(0)); 2201 2202 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2203 SD->getPointerInfo(), SD->isVolatile(), 2204 SD->isNonTemporal(), SD->getAlignment()); 2205 } 2206 2207 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2208 StoreSDNode *SD = cast<StoreSDNode>(Op); 2209 EVT MemVT = SD->getMemoryVT(); 2210 2211 // Lower unaligned integer stores. 2212 if (!Subtarget.systemSupportsUnalignedAccess() && 2213 (SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2214 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2215 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); 2216 2217 return lowerFP_TO_SINT_STORE(SD, DAG); 2218 } 2219 2220 SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const { 2221 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR 2222 || cast<ConstantSDNode> 2223 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0 2224 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET) 2225 return SDValue(); 2226 2227 // The pattern 2228 // (add (frameaddr 0), (frame_to_args_offset)) 2229 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to 2230 // (add FrameObject, 0) 2231 // where FrameObject is a fixed StackObject with offset 0 which points to 2232 // the old stack pointer. 2233 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2234 EVT ValTy = Op->getValueType(0); 2235 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2236 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy); 2237 return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr, 2238 DAG.getConstant(0, ValTy)); 2239 } 2240 2241 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2242 SelectionDAG &DAG) const { 2243 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2244 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2245 Op.getOperand(0)); 2246 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2247 } 2248 2249 //===----------------------------------------------------------------------===// 2250 // Calling Convention Implementation 2251 //===----------------------------------------------------------------------===// 2252 2253 //===----------------------------------------------------------------------===// 2254 // TODO: Implement a generic logic using tblgen that can support this. 2255 // Mips O32 ABI rules: 2256 // --- 2257 // i32 - Passed in A0, A1, A2, A3 and stack 2258 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 2259 // an argument. Otherwise, passed in A1, A2, A3 and stack. 2260 // f64 - Only passed in two aliased f32 registers if no int reg has been used 2261 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2262 // not used, it must be shadowed. If only A3 is avaiable, shadow it and 2263 // go to stack. 2264 // 2265 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2266 //===----------------------------------------------------------------------===// 2267 2268 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2269 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2270 CCState &State, const MCPhysReg *F64Regs) { 2271 const MipsSubtarget &Subtarget = 2272 State.getMachineFunction().getTarget() 2273 .getSubtarget<const MipsSubtarget>(); 2274 2275 static const unsigned IntRegsSize = 4, FloatRegsSize = 2; 2276 2277 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2278 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 }; 2279 2280 // Do not process byval args here. 2281 if (ArgFlags.isByVal()) 2282 return true; 2283 2284 // Promote i8 and i16 2285 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { 2286 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) { 2287 LocVT = MVT::i32; 2288 if (ArgFlags.isSExt()) 2289 LocInfo = CCValAssign::SExtUpper; 2290 else if (ArgFlags.isZExt()) 2291 LocInfo = CCValAssign::ZExtUpper; 2292 else 2293 LocInfo = CCValAssign::AExtUpper; 2294 } 2295 } 2296 2297 // Promote i8 and i16 2298 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2299 LocVT = MVT::i32; 2300 if (ArgFlags.isSExt()) 2301 LocInfo = CCValAssign::SExt; 2302 else if (ArgFlags.isZExt()) 2303 LocInfo = CCValAssign::ZExt; 2304 else 2305 LocInfo = CCValAssign::AExt; 2306 } 2307 2308 unsigned Reg; 2309 2310 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2311 // is true: function is vararg, argument is 3rd or higher, there is previous 2312 // argument which is not f32 or f64. 2313 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 2314 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 2315 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2316 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2317 2318 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2319 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2320 // If this is the first part of an i64 arg, 2321 // the allocated register must be either A0 or A2. 2322 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2323 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2324 LocVT = MVT::i32; 2325 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2326 // Allocate int register and shadow next int register. If first 2327 // available register is Mips::A1 or Mips::A3, shadow it too. 2328 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2329 if (Reg == Mips::A1 || Reg == Mips::A3) 2330 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2331 State.AllocateReg(IntRegs, IntRegsSize); 2332 LocVT = MVT::i32; 2333 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2334 // we are guaranteed to find an available float register 2335 if (ValVT == MVT::f32) { 2336 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 2337 // Shadow int register 2338 State.AllocateReg(IntRegs, IntRegsSize); 2339 } else { 2340 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 2341 // Shadow int registers 2342 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 2343 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2344 State.AllocateReg(IntRegs, IntRegsSize); 2345 State.AllocateReg(IntRegs, IntRegsSize); 2346 } 2347 } else 2348 llvm_unreachable("Cannot handle this ValVT."); 2349 2350 if (!Reg) { 2351 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 2352 OrigAlign); 2353 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2354 } else 2355 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2356 2357 return false; 2358 } 2359 2360 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2361 MVT LocVT, CCValAssign::LocInfo LocInfo, 2362 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2363 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 }; 2364 2365 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2366 } 2367 2368 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2369 MVT LocVT, CCValAssign::LocInfo LocInfo, 2370 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2371 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 2372 2373 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2374 } 2375 2376 #include "MipsGenCallingConv.inc" 2377 2378 //===----------------------------------------------------------------------===// 2379 // Call Calling Convention Implementation 2380 //===----------------------------------------------------------------------===// 2381 2382 // Return next O32 integer argument register. 2383 static unsigned getNextIntArgReg(unsigned Reg) { 2384 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2385 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2386 } 2387 2388 SDValue 2389 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2390 SDValue Chain, SDValue Arg, SDLoc DL, 2391 bool IsTailCall, SelectionDAG &DAG) const { 2392 if (!IsTailCall) { 2393 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, 2394 DAG.getIntPtrConstant(Offset)); 2395 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false, 2396 false, 0); 2397 } 2398 2399 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2400 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2401 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2402 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2403 /*isVolatile=*/ true, false, 0); 2404 } 2405 2406 void MipsTargetLowering:: 2407 getOpndList(SmallVectorImpl<SDValue> &Ops, 2408 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 2409 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2410 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const { 2411 // Insert node "GP copy globalreg" before call to function. 2412 // 2413 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2414 // in PIC mode) allow symbols to be resolved via lazy binding. 2415 // The lazy binding stub requires GP to point to the GOT. 2416 if (IsPICCall && !InternalLinkage) { 2417 unsigned GPReg = Subtarget.isABI_N64() ? Mips::GP_64 : Mips::GP; 2418 EVT Ty = Subtarget.isABI_N64() ? MVT::i64 : MVT::i32; 2419 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2420 } 2421 2422 // Build a sequence of copy-to-reg nodes chained together with token 2423 // chain and flag operands which copy the outgoing args into registers. 2424 // The InFlag in necessary since all emitted instructions must be 2425 // stuck together. 2426 SDValue InFlag; 2427 2428 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2429 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2430 RegsToPass[i].second, InFlag); 2431 InFlag = Chain.getValue(1); 2432 } 2433 2434 // Add argument registers to the end of the list so that they are 2435 // known live into the call. 2436 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2437 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2438 RegsToPass[i].second.getValueType())); 2439 2440 // Add a register mask operand representing the call-preserved registers. 2441 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2442 const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv); 2443 assert(Mask && "Missing call preserved mask for calling convention"); 2444 if (Subtarget.inMips16HardFloat()) { 2445 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2446 llvm::StringRef Sym = G->getGlobal()->getName(); 2447 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2448 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 2449 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2450 } 2451 } 2452 } 2453 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2454 2455 if (InFlag.getNode()) 2456 Ops.push_back(InFlag); 2457 } 2458 2459 /// LowerCall - functions arguments are copied from virtual regs to 2460 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2461 SDValue 2462 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2463 SmallVectorImpl<SDValue> &InVals) const { 2464 SelectionDAG &DAG = CLI.DAG; 2465 SDLoc DL = CLI.DL; 2466 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2467 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2468 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2469 SDValue Chain = CLI.Chain; 2470 SDValue Callee = CLI.Callee; 2471 bool &IsTailCall = CLI.IsTailCall; 2472 CallingConv::ID CallConv = CLI.CallConv; 2473 bool IsVarArg = CLI.IsVarArg; 2474 2475 MachineFunction &MF = DAG.getMachineFunction(); 2476 MachineFrameInfo *MFI = MF.getFrameInfo(); 2477 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 2478 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2479 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 2480 2481 // Analyze operands of the call, assigning locations to each operand. 2482 SmallVector<CCValAssign, 16> ArgLocs; 2483 MipsCCState CCInfo( 2484 CallConv, IsVarArg, DAG.getMachineFunction(), 2485 getTargetMachine(), ArgLocs, *DAG.getContext(), 2486 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); 2487 2488 // Allocate the reserved argument area. It seems strange to do this from the 2489 // caller side but removing it breaks the frame size calculation. 2490 const MipsABIInfo &ABI = Subtarget.getABI(); 2491 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 2492 2493 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), Callee.getNode()); 2494 2495 // Get a count of how many bytes are to be pushed on the stack. 2496 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2497 2498 // Check if it's really possible to do a tail call. 2499 if (IsTailCall) 2500 IsTailCall = isEligibleForTailCallOptimization( 2501 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>()); 2502 2503 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall()) 2504 report_fatal_error("failed to perform tail call elimination on a call " 2505 "site marked musttail"); 2506 2507 if (IsTailCall) 2508 ++NumTailCalls; 2509 2510 // Chain is the output chain of the last Load/Store or CopyToReg node. 2511 // ByValChain is the output chain of the last Memcpy node created for copying 2512 // byval arguments to the stack. 2513 unsigned StackAlignment = TFL->getStackAlignment(); 2514 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment); 2515 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 2516 2517 if (!IsTailCall) 2518 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL); 2519 2520 SDValue StackPtr = DAG.getCopyFromReg( 2521 Chain, DL, Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP, 2522 getPointerTy()); 2523 2524 // With EABI is it possible to have 16 args on registers. 2525 std::deque< std::pair<unsigned, SDValue> > RegsToPass; 2526 SmallVector<SDValue, 8> MemOpChains; 2527 2528 CCInfo.rewindByValRegsInfo(); 2529 2530 // Walk the register/memloc assignments, inserting copies/loads. 2531 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2532 SDValue Arg = OutVals[i]; 2533 CCValAssign &VA = ArgLocs[i]; 2534 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2535 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2536 bool UseUpperBits = false; 2537 2538 // ByVal Arg. 2539 if (Flags.isByVal()) { 2540 unsigned FirstByValReg, LastByValReg; 2541 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 2542 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 2543 2544 assert(Flags.getByValSize() && 2545 "ByVal args of size 0 should have been ignored by front-end."); 2546 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 2547 assert(!IsTailCall && 2548 "Do not tail-call optimize if there is a byval argument."); 2549 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 2550 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), 2551 VA); 2552 CCInfo.nextInRegsParam(); 2553 continue; 2554 } 2555 2556 // Promote the value if needed. 2557 switch (VA.getLocInfo()) { 2558 default: 2559 llvm_unreachable("Unknown loc info!"); 2560 case CCValAssign::Full: 2561 if (VA.isRegLoc()) { 2562 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2563 (ValVT == MVT::f64 && LocVT == MVT::i64) || 2564 (ValVT == MVT::i64 && LocVT == MVT::f64)) 2565 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2566 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2567 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2568 Arg, DAG.getConstant(0, MVT::i32)); 2569 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2570 Arg, DAG.getConstant(1, MVT::i32)); 2571 if (!Subtarget.isLittle()) 2572 std::swap(Lo, Hi); 2573 unsigned LocRegLo = VA.getLocReg(); 2574 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2575 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2576 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2577 continue; 2578 } 2579 } 2580 break; 2581 case CCValAssign::BCvt: 2582 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2583 break; 2584 case CCValAssign::SExtUpper: 2585 UseUpperBits = true; 2586 // Fallthrough 2587 case CCValAssign::SExt: 2588 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 2589 break; 2590 case CCValAssign::ZExtUpper: 2591 UseUpperBits = true; 2592 // Fallthrough 2593 case CCValAssign::ZExt: 2594 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 2595 break; 2596 case CCValAssign::AExtUpper: 2597 UseUpperBits = true; 2598 // Fallthrough 2599 case CCValAssign::AExt: 2600 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 2601 break; 2602 } 2603 2604 if (UseUpperBits) { 2605 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 2606 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2607 Arg = DAG.getNode( 2608 ISD::SHL, DL, VA.getLocVT(), Arg, 2609 DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT())); 2610 } 2611 2612 // Arguments that can be passed on register must be kept at 2613 // RegsToPass vector 2614 if (VA.isRegLoc()) { 2615 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2616 continue; 2617 } 2618 2619 // Register can't get to this point... 2620 assert(VA.isMemLoc()); 2621 2622 // emit ISD::STORE whichs stores the 2623 // parameter value to a stack Location 2624 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 2625 Chain, Arg, DL, IsTailCall, DAG)); 2626 } 2627 2628 // Transform all store nodes into one single node because all store 2629 // nodes are independent of each other. 2630 if (!MemOpChains.empty()) 2631 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 2632 2633 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2634 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2635 // node so that legalize doesn't hack it. 2636 bool IsPICCall = 2637 (Subtarget.isABI_N64() || IsPIC); // true if calls are translated to 2638 // jalr $25 2639 bool GlobalOrExternal = false, InternalLinkage = false; 2640 SDValue CalleeLo; 2641 EVT Ty = Callee.getValueType(); 2642 2643 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2644 if (IsPICCall) { 2645 const GlobalValue *Val = G->getGlobal(); 2646 InternalLinkage = Val->hasInternalLinkage(); 2647 2648 if (InternalLinkage) 2649 Callee = getAddrLocal(G, Ty, DAG, 2650 Subtarget.isABI_N32() || Subtarget.isABI_N64()); 2651 else if (LargeGOT) 2652 Callee = getAddrGlobalLargeGOT(G, Ty, DAG, MipsII::MO_CALL_HI16, 2653 MipsII::MO_CALL_LO16, Chain, 2654 FuncInfo->callPtrInfo(Val)); 2655 else 2656 Callee = getAddrGlobal(G, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 2657 FuncInfo->callPtrInfo(Val)); 2658 } else 2659 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0, 2660 MipsII::MO_NO_FLAG); 2661 GlobalOrExternal = true; 2662 } 2663 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2664 const char *Sym = S->getSymbol(); 2665 2666 if (!Subtarget.isABI_N64() && !IsPIC) // !N64 && static 2667 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 2668 MipsII::MO_NO_FLAG); 2669 else if (LargeGOT) 2670 Callee = getAddrGlobalLargeGOT(S, Ty, DAG, MipsII::MO_CALL_HI16, 2671 MipsII::MO_CALL_LO16, Chain, 2672 FuncInfo->callPtrInfo(Sym)); 2673 else // N64 || PIC 2674 Callee = getAddrGlobal(S, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 2675 FuncInfo->callPtrInfo(Sym)); 2676 2677 GlobalOrExternal = true; 2678 } 2679 2680 SmallVector<SDValue, 8> Ops(1, Chain); 2681 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2682 2683 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage, 2684 CLI, Callee, Chain); 2685 2686 if (IsTailCall) 2687 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); 2688 2689 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); 2690 SDValue InFlag = Chain.getValue(1); 2691 2692 // Create the CALLSEQ_END node. 2693 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 2694 DAG.getIntPtrConstant(0, true), InFlag, DL); 2695 InFlag = Chain.getValue(1); 2696 2697 // Handle result values, copying them out of physregs into vregs that we 2698 // return. 2699 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, 2700 InVals, CLI); 2701 } 2702 2703 /// LowerCallResult - Lower the result values of a call into the 2704 /// appropriate copies out of appropriate physical registers. 2705 SDValue MipsTargetLowering::LowerCallResult( 2706 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 2707 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, 2708 SmallVectorImpl<SDValue> &InVals, 2709 TargetLowering::CallLoweringInfo &CLI) const { 2710 // Assign locations to each value returned by this call. 2711 SmallVector<CCValAssign, 16> RVLocs; 2712 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2713 getTargetMachine(), RVLocs, *DAG.getContext()); 2714 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI); 2715 2716 // Copy all of the result registers out of their specified physreg. 2717 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2718 CCValAssign &VA = RVLocs[i]; 2719 assert(VA.isRegLoc() && "Can only return in registers!"); 2720 2721 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 2722 RVLocs[i].getLocVT(), InFlag); 2723 Chain = Val.getValue(1); 2724 InFlag = Val.getValue(2); 2725 2726 if (VA.isUpperBitsInLoc()) { 2727 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); 2728 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2729 unsigned Shift = 2730 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 2731 Val = DAG.getNode( 2732 Shift, DL, VA.getLocVT(), Val, 2733 DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT())); 2734 } 2735 2736 switch (VA.getLocInfo()) { 2737 default: 2738 llvm_unreachable("Unknown loc info!"); 2739 case CCValAssign::Full: 2740 break; 2741 case CCValAssign::BCvt: 2742 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 2743 break; 2744 case CCValAssign::AExt: 2745 case CCValAssign::AExtUpper: 2746 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2747 break; 2748 case CCValAssign::ZExt: 2749 case CCValAssign::ZExtUpper: 2750 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, 2751 DAG.getValueType(VA.getValVT())); 2752 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2753 break; 2754 case CCValAssign::SExt: 2755 case CCValAssign::SExtUpper: 2756 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, 2757 DAG.getValueType(VA.getValVT())); 2758 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2759 break; 2760 } 2761 2762 InVals.push_back(Val); 2763 } 2764 2765 return Chain; 2766 } 2767 2768 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, 2769 EVT ArgVT, SDLoc DL, SelectionDAG &DAG) { 2770 MVT LocVT = VA.getLocVT(); 2771 EVT ValVT = VA.getValVT(); 2772 2773 // Shift into the upper bits if necessary. 2774 switch (VA.getLocInfo()) { 2775 default: 2776 break; 2777 case CCValAssign::AExtUpper: 2778 case CCValAssign::SExtUpper: 2779 case CCValAssign::ZExtUpper: { 2780 unsigned ValSizeInBits = ArgVT.getSizeInBits(); 2781 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2782 unsigned Opcode = 2783 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 2784 Val = DAG.getNode( 2785 Opcode, DL, VA.getLocVT(), Val, 2786 DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT())); 2787 break; 2788 } 2789 } 2790 2791 // If this is an value smaller than the argument slot size (32-bit for O32, 2792 // 64-bit for N32/N64), it has been promoted in some way to the argument slot 2793 // size. Extract the value and insert any appropriate assertions regarding 2794 // sign/zero extension. 2795 switch (VA.getLocInfo()) { 2796 default: 2797 llvm_unreachable("Unknown loc info!"); 2798 case CCValAssign::Full: 2799 break; 2800 case CCValAssign::AExtUpper: 2801 case CCValAssign::AExt: 2802 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 2803 break; 2804 case CCValAssign::SExtUpper: 2805 case CCValAssign::SExt: 2806 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); 2807 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 2808 break; 2809 case CCValAssign::ZExtUpper: 2810 case CCValAssign::ZExt: 2811 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); 2812 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 2813 break; 2814 case CCValAssign::BCvt: 2815 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); 2816 break; 2817 } 2818 2819 return Val; 2820 } 2821 2822 //===----------------------------------------------------------------------===// 2823 // Formal Arguments Calling Convention Implementation 2824 //===----------------------------------------------------------------------===// 2825 /// LowerFormalArguments - transform physical registers into virtual registers 2826 /// and generate load operations for arguments places on the stack. 2827 SDValue 2828 MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2829 CallingConv::ID CallConv, 2830 bool IsVarArg, 2831 const SmallVectorImpl<ISD::InputArg> &Ins, 2832 SDLoc DL, SelectionDAG &DAG, 2833 SmallVectorImpl<SDValue> &InVals) 2834 const { 2835 MachineFunction &MF = DAG.getMachineFunction(); 2836 MachineFrameInfo *MFI = MF.getFrameInfo(); 2837 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2838 2839 MipsFI->setVarArgsFrameIndex(0); 2840 2841 // Used with vargs to acumulate store chains. 2842 std::vector<SDValue> OutChains; 2843 2844 // Assign locations to all of the incoming arguments. 2845 SmallVector<CCValAssign, 16> ArgLocs; 2846 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2847 getTargetMachine(), ArgLocs, *DAG.getContext()); 2848 const MipsABIInfo &ABI = Subtarget.getABI(); 2849 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 2850 Function::const_arg_iterator FuncArg = 2851 DAG.getMachineFunction().getFunction()->arg_begin(); 2852 2853 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); 2854 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 2855 CCInfo.getInRegsParamsCount() > 0); 2856 2857 unsigned CurArgIdx = 0; 2858 CCInfo.rewindByValRegsInfo(); 2859 2860 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2861 CCValAssign &VA = ArgLocs[i]; 2862 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx); 2863 CurArgIdx = Ins[i].OrigArgIndex; 2864 EVT ValVT = VA.getValVT(); 2865 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2866 bool IsRegLoc = VA.isRegLoc(); 2867 2868 if (Flags.isByVal()) { 2869 unsigned FirstByValReg, LastByValReg; 2870 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 2871 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 2872 2873 assert(Flags.getByValSize() && 2874 "ByVal args of size 0 should have been ignored by front-end."); 2875 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 2876 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 2877 FirstByValReg, LastByValReg, VA, CCInfo); 2878 CCInfo.nextInRegsParam(); 2879 continue; 2880 } 2881 2882 // Arguments stored on registers 2883 if (IsRegLoc) { 2884 MVT RegVT = VA.getLocVT(); 2885 unsigned ArgReg = VA.getLocReg(); 2886 const TargetRegisterClass *RC = getRegClassFor(RegVT); 2887 2888 // Transform the arguments stored on 2889 // physical registers into virtual ones 2890 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 2891 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 2892 2893 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 2894 2895 // Handle floating point arguments passed in integer registers and 2896 // long double arguments passed in floating point registers. 2897 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 2898 (RegVT == MVT::i64 && ValVT == MVT::f64) || 2899 (RegVT == MVT::f64 && ValVT == MVT::i64)) 2900 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 2901 else if (Subtarget.isABI_O32() && RegVT == MVT::i32 && 2902 ValVT == MVT::f64) { 2903 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 2904 getNextIntArgReg(ArgReg), RC); 2905 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 2906 if (!Subtarget.isLittle()) 2907 std::swap(ArgValue, ArgValue2); 2908 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 2909 ArgValue, ArgValue2); 2910 } 2911 2912 InVals.push_back(ArgValue); 2913 } else { // VA.isRegLoc() 2914 MVT LocVT = VA.getLocVT(); 2915 2916 if (Subtarget.isABI_O32()) { 2917 // We ought to be able to use LocVT directly but O32 sets it to i32 2918 // when allocating floating point values to integer registers. 2919 // This shouldn't influence how we load the value into registers unless 2920 // we are targetting softfloat. 2921 if (VA.getValVT().isFloatingPoint() && !Subtarget.abiUsesSoftFloat()) 2922 LocVT = VA.getValVT(); 2923 } 2924 2925 // sanity check 2926 assert(VA.isMemLoc()); 2927 2928 // The stack pointer offset is relative to the caller stack frame. 2929 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8, 2930 VA.getLocMemOffset(), true); 2931 2932 // Create load nodes to retrieve arguments from the stack 2933 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2934 SDValue ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN, 2935 MachinePointerInfo::getFixedStack(FI), 2936 false, false, false, 0); 2937 OutChains.push_back(ArgValue.getValue(1)); 2938 2939 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 2940 2941 InVals.push_back(ArgValue); 2942 } 2943 } 2944 2945 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2946 // The mips ABIs for returning structs by value requires that we copy 2947 // the sret argument into $v0 for the return. Save the argument into 2948 // a virtual register so that we can access it from the return points. 2949 if (Ins[i].Flags.isSRet()) { 2950 unsigned Reg = MipsFI->getSRetReturnReg(); 2951 if (!Reg) { 2952 Reg = MF.getRegInfo().createVirtualRegister( 2953 getRegClassFor(Subtarget.isABI_N64() ? MVT::i64 : MVT::i32)); 2954 MipsFI->setSRetReturnReg(Reg); 2955 } 2956 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); 2957 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 2958 break; 2959 } 2960 } 2961 2962 if (IsVarArg) 2963 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); 2964 2965 // All stores are grouped in one node to allow the matching between 2966 // the size of Ins and InVals. This only happens when on varg functions 2967 if (!OutChains.empty()) { 2968 OutChains.push_back(Chain); 2969 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 2970 } 2971 2972 return Chain; 2973 } 2974 2975 //===----------------------------------------------------------------------===// 2976 // Return Value Calling Convention Implementation 2977 //===----------------------------------------------------------------------===// 2978 2979 bool 2980 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 2981 MachineFunction &MF, bool IsVarArg, 2982 const SmallVectorImpl<ISD::OutputArg> &Outs, 2983 LLVMContext &Context) const { 2984 SmallVector<CCValAssign, 16> RVLocs; 2985 MipsCCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), 2986 RVLocs, Context); 2987 return CCInfo.CheckReturn(Outs, RetCC_Mips); 2988 } 2989 2990 SDValue 2991 MipsTargetLowering::LowerReturn(SDValue Chain, 2992 CallingConv::ID CallConv, bool IsVarArg, 2993 const SmallVectorImpl<ISD::OutputArg> &Outs, 2994 const SmallVectorImpl<SDValue> &OutVals, 2995 SDLoc DL, SelectionDAG &DAG) const { 2996 // CCValAssign - represent the assignment of 2997 // the return value to a location 2998 SmallVector<CCValAssign, 16> RVLocs; 2999 MachineFunction &MF = DAG.getMachineFunction(); 3000 3001 // CCState - Info about the registers and stack slot. 3002 MipsCCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs, 3003 *DAG.getContext()); 3004 3005 // Analyze return values. 3006 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3007 3008 SDValue Flag; 3009 SmallVector<SDValue, 4> RetOps(1, Chain); 3010 3011 // Copy the result values into the output registers. 3012 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3013 SDValue Val = OutVals[i]; 3014 CCValAssign &VA = RVLocs[i]; 3015 assert(VA.isRegLoc() && "Can only return in registers!"); 3016 bool UseUpperBits = false; 3017 3018 switch (VA.getLocInfo()) { 3019 default: 3020 llvm_unreachable("Unknown loc info!"); 3021 case CCValAssign::Full: 3022 break; 3023 case CCValAssign::BCvt: 3024 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); 3025 break; 3026 case CCValAssign::AExtUpper: 3027 UseUpperBits = true; 3028 // Fallthrough 3029 case CCValAssign::AExt: 3030 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); 3031 break; 3032 case CCValAssign::ZExtUpper: 3033 UseUpperBits = true; 3034 // Fallthrough 3035 case CCValAssign::ZExt: 3036 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); 3037 break; 3038 case CCValAssign::SExtUpper: 3039 UseUpperBits = true; 3040 // Fallthrough 3041 case CCValAssign::SExt: 3042 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); 3043 break; 3044 } 3045 3046 if (UseUpperBits) { 3047 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3048 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3049 Val = DAG.getNode( 3050 ISD::SHL, DL, VA.getLocVT(), Val, 3051 DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT())); 3052 } 3053 3054 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 3055 3056 // Guarantee that all emitted copies are stuck together with flags. 3057 Flag = Chain.getValue(1); 3058 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3059 } 3060 3061 // The mips ABIs for returning structs by value requires that we copy 3062 // the sret argument into $v0 for the return. We saved the argument into 3063 // a virtual register in the entry block, so now we copy the value out 3064 // and into $v0. 3065 if (MF.getFunction()->hasStructRetAttr()) { 3066 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3067 unsigned Reg = MipsFI->getSRetReturnReg(); 3068 3069 if (!Reg) 3070 llvm_unreachable("sret virtual register not created in the entry block"); 3071 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 3072 unsigned V0 = Subtarget.isABI_N64() ? Mips::V0_64 : Mips::V0; 3073 3074 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 3075 Flag = Chain.getValue(1); 3076 RetOps.push_back(DAG.getRegister(V0, getPointerTy())); 3077 } 3078 3079 RetOps[0] = Chain; // Update chain. 3080 3081 // Add the flag if we have it. 3082 if (Flag.getNode()) 3083 RetOps.push_back(Flag); 3084 3085 // Return on Mips is always a "jr $ra" 3086 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); 3087 } 3088 3089 //===----------------------------------------------------------------------===// 3090 // Mips Inline Assembly Support 3091 //===----------------------------------------------------------------------===// 3092 3093 /// getConstraintType - Given a constraint letter, return the type of 3094 /// constraint it is for this target. 3095 MipsTargetLowering::ConstraintType MipsTargetLowering:: 3096 getConstraintType(const std::string &Constraint) const 3097 { 3098 // Mips specific constraints 3099 // GCC config/mips/constraints.md 3100 // 3101 // 'd' : An address register. Equivalent to r 3102 // unless generating MIPS16 code. 3103 // 'y' : Equivalent to r; retained for 3104 // backwards compatibility. 3105 // 'c' : A register suitable for use in an indirect 3106 // jump. This will always be $25 for -mabicalls. 3107 // 'l' : The lo register. 1 word storage. 3108 // 'x' : The hilo register pair. Double word storage. 3109 if (Constraint.size() == 1) { 3110 switch (Constraint[0]) { 3111 default : break; 3112 case 'd': 3113 case 'y': 3114 case 'f': 3115 case 'c': 3116 case 'l': 3117 case 'x': 3118 return C_RegisterClass; 3119 case 'R': 3120 return C_Memory; 3121 } 3122 } 3123 return TargetLowering::getConstraintType(Constraint); 3124 } 3125 3126 /// Examine constraint type and operand type and determine a weight value. 3127 /// This object must already have been set up with the operand type 3128 /// and the current alternative constraint selected. 3129 TargetLowering::ConstraintWeight 3130 MipsTargetLowering::getSingleConstraintMatchWeight( 3131 AsmOperandInfo &info, const char *constraint) const { 3132 ConstraintWeight weight = CW_Invalid; 3133 Value *CallOperandVal = info.CallOperandVal; 3134 // If we don't have a value, we can't do a match, 3135 // but allow it at the lowest weight. 3136 if (!CallOperandVal) 3137 return CW_Default; 3138 Type *type = CallOperandVal->getType(); 3139 // Look at the constraint type. 3140 switch (*constraint) { 3141 default: 3142 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3143 break; 3144 case 'd': 3145 case 'y': 3146 if (type->isIntegerTy()) 3147 weight = CW_Register; 3148 break; 3149 case 'f': // FPU or MSA register 3150 if (Subtarget.hasMSA() && type->isVectorTy() && 3151 cast<VectorType>(type)->getBitWidth() == 128) 3152 weight = CW_Register; 3153 else if (type->isFloatTy()) 3154 weight = CW_Register; 3155 break; 3156 case 'c': // $25 for indirect jumps 3157 case 'l': // lo register 3158 case 'x': // hilo register pair 3159 if (type->isIntegerTy()) 3160 weight = CW_SpecificReg; 3161 break; 3162 case 'I': // signed 16 bit immediate 3163 case 'J': // integer zero 3164 case 'K': // unsigned 16 bit immediate 3165 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3166 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3167 case 'O': // signed 15 bit immediate (+- 16383) 3168 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3169 if (isa<ConstantInt>(CallOperandVal)) 3170 weight = CW_Constant; 3171 break; 3172 case 'R': 3173 weight = CW_Memory; 3174 break; 3175 } 3176 return weight; 3177 } 3178 3179 /// This is a helper function to parse a physical register string and split it 3180 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 3181 /// that is returned indicates whether parsing was successful. The second flag 3182 /// is true if the numeric part exists. 3183 static std::pair<bool, bool> 3184 parsePhysicalReg(const StringRef &C, std::string &Prefix, 3185 unsigned long long &Reg) { 3186 if (C.front() != '{' || C.back() != '}') 3187 return std::make_pair(false, false); 3188 3189 // Search for the first numeric character. 3190 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 3191 I = std::find_if(B, E, std::ptr_fun(isdigit)); 3192 3193 Prefix.assign(B, I - B); 3194 3195 // The second flag is set to false if no numeric characters were found. 3196 if (I == E) 3197 return std::make_pair(true, false); 3198 3199 // Parse the numeric characters. 3200 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 3201 true); 3202 } 3203 3204 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 3205 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const { 3206 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 3207 const TargetRegisterClass *RC; 3208 std::string Prefix; 3209 unsigned long long Reg; 3210 3211 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 3212 3213 if (!R.first) 3214 return std::make_pair(0U, nullptr); 3215 3216 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 3217 // No numeric characters follow "hi" or "lo". 3218 if (R.second) 3219 return std::make_pair(0U, nullptr); 3220 3221 RC = TRI->getRegClass(Prefix == "hi" ? 3222 Mips::HI32RegClassID : Mips::LO32RegClassID); 3223 return std::make_pair(*(RC->begin()), RC); 3224 } else if (Prefix.compare(0, 4, "$msa") == 0) { 3225 // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 3226 3227 // No numeric characters follow the name. 3228 if (R.second) 3229 return std::make_pair(0U, nullptr); 3230 3231 Reg = StringSwitch<unsigned long long>(Prefix) 3232 .Case("$msair", Mips::MSAIR) 3233 .Case("$msacsr", Mips::MSACSR) 3234 .Case("$msaaccess", Mips::MSAAccess) 3235 .Case("$msasave", Mips::MSASave) 3236 .Case("$msamodify", Mips::MSAModify) 3237 .Case("$msarequest", Mips::MSARequest) 3238 .Case("$msamap", Mips::MSAMap) 3239 .Case("$msaunmap", Mips::MSAUnmap) 3240 .Default(0); 3241 3242 if (!Reg) 3243 return std::make_pair(0U, nullptr); 3244 3245 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 3246 return std::make_pair(Reg, RC); 3247 } 3248 3249 if (!R.second) 3250 return std::make_pair(0U, nullptr); 3251 3252 if (Prefix == "$f") { // Parse $f0-$f31. 3253 // If the size of FP registers is 64-bit or Reg is an even number, select 3254 // the 64-bit register class. Otherwise, select the 32-bit register class. 3255 if (VT == MVT::Other) 3256 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 3257 3258 RC = getRegClassFor(VT); 3259 3260 if (RC == &Mips::AFGR64RegClass) { 3261 assert(Reg % 2 == 0); 3262 Reg >>= 1; 3263 } 3264 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 3265 RC = TRI->getRegClass(Mips::FCCRegClassID); 3266 else if (Prefix == "$w") { // Parse $w0-$w31. 3267 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 3268 } else { // Parse $0-$31. 3269 assert(Prefix == "$"); 3270 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 3271 } 3272 3273 assert(Reg < RC->getNumRegs()); 3274 return std::make_pair(*(RC->begin() + Reg), RC); 3275 } 3276 3277 /// Given a register class constraint, like 'r', if this corresponds directly 3278 /// to an LLVM register class, return a register of 0 and the register class 3279 /// pointer. 3280 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 3281 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const 3282 { 3283 if (Constraint.size() == 1) { 3284 switch (Constraint[0]) { 3285 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3286 case 'y': // Same as 'r'. Exists for compatibility. 3287 case 'r': 3288 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3289 if (Subtarget.inMips16Mode()) 3290 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3291 return std::make_pair(0U, &Mips::GPR32RegClass); 3292 } 3293 if (VT == MVT::i64 && !Subtarget.isGP64bit()) 3294 return std::make_pair(0U, &Mips::GPR32RegClass); 3295 if (VT == MVT::i64 && Subtarget.isGP64bit()) 3296 return std::make_pair(0U, &Mips::GPR64RegClass); 3297 // This will generate an error message 3298 return std::make_pair(0U, nullptr); 3299 case 'f': // FPU or MSA register 3300 if (VT == MVT::v16i8) 3301 return std::make_pair(0U, &Mips::MSA128BRegClass); 3302 else if (VT == MVT::v8i16 || VT == MVT::v8f16) 3303 return std::make_pair(0U, &Mips::MSA128HRegClass); 3304 else if (VT == MVT::v4i32 || VT == MVT::v4f32) 3305 return std::make_pair(0U, &Mips::MSA128WRegClass); 3306 else if (VT == MVT::v2i64 || VT == MVT::v2f64) 3307 return std::make_pair(0U, &Mips::MSA128DRegClass); 3308 else if (VT == MVT::f32) 3309 return std::make_pair(0U, &Mips::FGR32RegClass); 3310 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { 3311 if (Subtarget.isFP64bit()) 3312 return std::make_pair(0U, &Mips::FGR64RegClass); 3313 return std::make_pair(0U, &Mips::AFGR64RegClass); 3314 } 3315 break; 3316 case 'c': // register suitable for indirect jump 3317 if (VT == MVT::i32) 3318 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 3319 assert(VT == MVT::i64 && "Unexpected type."); 3320 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 3321 case 'l': // register suitable for indirect jump 3322 if (VT == MVT::i32) 3323 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 3324 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 3325 case 'x': // register suitable for indirect jump 3326 // Fixme: Not triggering the use of both hi and low 3327 // This will generate an error message 3328 return std::make_pair(0U, nullptr); 3329 } 3330 } 3331 3332 std::pair<unsigned, const TargetRegisterClass *> R; 3333 R = parseRegForInlineAsmConstraint(Constraint, VT); 3334 3335 if (R.second) 3336 return R; 3337 3338 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3339 } 3340 3341 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3342 /// vector. If it is invalid, don't add anything to Ops. 3343 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3344 std::string &Constraint, 3345 std::vector<SDValue>&Ops, 3346 SelectionDAG &DAG) const { 3347 SDValue Result; 3348 3349 // Only support length 1 constraints for now. 3350 if (Constraint.length() > 1) return; 3351 3352 char ConstraintLetter = Constraint[0]; 3353 switch (ConstraintLetter) { 3354 default: break; // This will fall through to the generic implementation 3355 case 'I': // Signed 16 bit constant 3356 // If this fails, the parent routine will give an error 3357 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3358 EVT Type = Op.getValueType(); 3359 int64_t Val = C->getSExtValue(); 3360 if (isInt<16>(Val)) { 3361 Result = DAG.getTargetConstant(Val, Type); 3362 break; 3363 } 3364 } 3365 return; 3366 case 'J': // integer zero 3367 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3368 EVT Type = Op.getValueType(); 3369 int64_t Val = C->getZExtValue(); 3370 if (Val == 0) { 3371 Result = DAG.getTargetConstant(0, Type); 3372 break; 3373 } 3374 } 3375 return; 3376 case 'K': // unsigned 16 bit immediate 3377 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3378 EVT Type = Op.getValueType(); 3379 uint64_t Val = (uint64_t)C->getZExtValue(); 3380 if (isUInt<16>(Val)) { 3381 Result = DAG.getTargetConstant(Val, Type); 3382 break; 3383 } 3384 } 3385 return; 3386 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3387 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3388 EVT Type = Op.getValueType(); 3389 int64_t Val = C->getSExtValue(); 3390 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3391 Result = DAG.getTargetConstant(Val, Type); 3392 break; 3393 } 3394 } 3395 return; 3396 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3397 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3398 EVT Type = Op.getValueType(); 3399 int64_t Val = C->getSExtValue(); 3400 if ((Val >= -65535) && (Val <= -1)) { 3401 Result = DAG.getTargetConstant(Val, Type); 3402 break; 3403 } 3404 } 3405 return; 3406 case 'O': // signed 15 bit immediate 3407 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3408 EVT Type = Op.getValueType(); 3409 int64_t Val = C->getSExtValue(); 3410 if ((isInt<15>(Val))) { 3411 Result = DAG.getTargetConstant(Val, Type); 3412 break; 3413 } 3414 } 3415 return; 3416 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3417 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3418 EVT Type = Op.getValueType(); 3419 int64_t Val = C->getSExtValue(); 3420 if ((Val <= 65535) && (Val >= 1)) { 3421 Result = DAG.getTargetConstant(Val, Type); 3422 break; 3423 } 3424 } 3425 return; 3426 } 3427 3428 if (Result.getNode()) { 3429 Ops.push_back(Result); 3430 return; 3431 } 3432 3433 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3434 } 3435 3436 bool MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, 3437 Type *Ty) const { 3438 // No global is ever allowed as a base. 3439 if (AM.BaseGV) 3440 return false; 3441 3442 switch (AM.Scale) { 3443 case 0: // "r+i" or just "i", depending on HasBaseReg. 3444 break; 3445 case 1: 3446 if (!AM.HasBaseReg) // allow "r+i". 3447 break; 3448 return false; // disallow "r+r" or "r+r+i". 3449 default: 3450 return false; 3451 } 3452 3453 return true; 3454 } 3455 3456 bool 3457 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3458 // The Mips target isn't yet aware of offsets. 3459 return false; 3460 } 3461 3462 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3463 unsigned SrcAlign, 3464 bool IsMemset, bool ZeroMemset, 3465 bool MemcpyStrSrc, 3466 MachineFunction &MF) const { 3467 if (Subtarget.hasMips64()) 3468 return MVT::i64; 3469 3470 return MVT::i32; 3471 } 3472 3473 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3474 if (VT != MVT::f32 && VT != MVT::f64) 3475 return false; 3476 if (Imm.isNegZero()) 3477 return false; 3478 return Imm.isZero(); 3479 } 3480 3481 unsigned MipsTargetLowering::getJumpTableEncoding() const { 3482 if (Subtarget.isABI_N64()) 3483 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3484 3485 return TargetLowering::getJumpTableEncoding(); 3486 } 3487 3488 void MipsTargetLowering::copyByValRegs( 3489 SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG, 3490 const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals, 3491 const Argument *FuncArg, unsigned FirstReg, unsigned LastReg, 3492 const CCValAssign &VA, MipsCCState &State) const { 3493 MachineFunction &MF = DAG.getMachineFunction(); 3494 MachineFrameInfo *MFI = MF.getFrameInfo(); 3495 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); 3496 unsigned NumRegs = LastReg - FirstReg; 3497 unsigned RegAreaSize = NumRegs * GPRSizeInBytes; 3498 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 3499 int FrameObjOffset; 3500 const MipsABIInfo &ABI = Subtarget.getABI(); 3501 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs(); 3502 3503 if (RegAreaSize) 3504 FrameObjOffset = 3505 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 3506 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); 3507 else 3508 FrameObjOffset = VA.getLocMemOffset(); 3509 3510 // Create frame object. 3511 EVT PtrTy = getPointerTy(); 3512 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true); 3513 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 3514 InVals.push_back(FIN); 3515 3516 if (!NumRegs) 3517 return; 3518 3519 // Copy arg registers. 3520 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); 3521 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3522 3523 for (unsigned I = 0; I < NumRegs; ++I) { 3524 unsigned ArgReg = ByValArgRegs[FirstReg + I]; 3525 unsigned VReg = addLiveIn(MF, ArgReg, RC); 3526 unsigned Offset = I * GPRSizeInBytes; 3527 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 3528 DAG.getConstant(Offset, PtrTy)); 3529 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 3530 StorePtr, MachinePointerInfo(FuncArg, Offset), 3531 false, false, 0); 3532 OutChains.push_back(Store); 3533 } 3534 } 3535 3536 // Copy byVal arg to registers and stack. 3537 void MipsTargetLowering::passByValArg( 3538 SDValue Chain, SDLoc DL, 3539 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 3540 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 3541 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, 3542 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, 3543 const CCValAssign &VA) const { 3544 unsigned ByValSizeInBytes = Flags.getByValSize(); 3545 unsigned OffsetInBytes = 0; // From beginning of struct 3546 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3547 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes); 3548 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 3549 unsigned NumRegs = LastReg - FirstReg; 3550 3551 if (NumRegs) { 3552 const ArrayRef<MCPhysReg> ArgRegs = Subtarget.getABI().GetByValArgRegs(); 3553 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); 3554 unsigned I = 0; 3555 3556 // Copy words to registers. 3557 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { 3558 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3559 DAG.getConstant(OffsetInBytes, PtrTy)); 3560 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 3561 MachinePointerInfo(), false, false, false, 3562 Alignment); 3563 MemOpChains.push_back(LoadVal.getValue(1)); 3564 unsigned ArgReg = ArgRegs[FirstReg + I]; 3565 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 3566 } 3567 3568 // Return if the struct has been fully copied. 3569 if (ByValSizeInBytes == OffsetInBytes) 3570 return; 3571 3572 // Copy the remainder of the byval argument with sub-word loads and shifts. 3573 if (LeftoverBytes) { 3574 SDValue Val; 3575 3576 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0; 3577 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) { 3578 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes; 3579 3580 if (RemainingSizeInBytes < LoadSizeInBytes) 3581 continue; 3582 3583 // Load subword. 3584 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3585 DAG.getConstant(OffsetInBytes, PtrTy)); 3586 SDValue LoadVal = DAG.getExtLoad( 3587 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), 3588 MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, Alignment); 3589 MemOpChains.push_back(LoadVal.getValue(1)); 3590 3591 // Shift the loaded value. 3592 unsigned Shamt; 3593 3594 if (isLittle) 3595 Shamt = TotalBytesLoaded * 8; 3596 else 3597 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; 3598 3599 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 3600 DAG.getConstant(Shamt, MVT::i32)); 3601 3602 if (Val.getNode()) 3603 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 3604 else 3605 Val = Shift; 3606 3607 OffsetInBytes += LoadSizeInBytes; 3608 TotalBytesLoaded += LoadSizeInBytes; 3609 Alignment = std::min(Alignment, LoadSizeInBytes); 3610 } 3611 3612 unsigned ArgReg = ArgRegs[FirstReg + I]; 3613 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 3614 return; 3615 } 3616 } 3617 3618 // Copy remainder of byval arg to it with memcpy. 3619 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; 3620 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3621 DAG.getConstant(OffsetInBytes, PtrTy)); 3622 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 3623 DAG.getIntPtrConstant(VA.getLocMemOffset())); 3624 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, PtrTy), 3625 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, 3626 MachinePointerInfo(), MachinePointerInfo()); 3627 MemOpChains.push_back(Chain); 3628 } 3629 3630 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 3631 SDValue Chain, SDLoc DL, 3632 SelectionDAG &DAG, 3633 CCState &State) const { 3634 const ArrayRef<MCPhysReg> ArgRegs = Subtarget.getABI().GetVarArgRegs(); 3635 unsigned Idx = State.getFirstUnallocated(ArgRegs.data(), ArgRegs.size()); 3636 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3637 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 3638 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3639 MachineFunction &MF = DAG.getMachineFunction(); 3640 MachineFrameInfo *MFI = MF.getFrameInfo(); 3641 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3642 3643 // Offset of the first variable argument from stack pointer. 3644 int VaArgOffset; 3645 3646 if (ArgRegs.size() == Idx) 3647 VaArgOffset = 3648 RoundUpToAlignment(State.getNextStackOffset(), RegSizeInBytes); 3649 else { 3650 const MipsABIInfo &ABI = Subtarget.getABI(); 3651 VaArgOffset = 3652 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 3653 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); 3654 } 3655 3656 // Record the frame index of the first variable argument 3657 // which is a value necessary to VASTART. 3658 int FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 3659 MipsFI->setVarArgsFrameIndex(FI); 3660 3661 // Copy the integer registers that have not been used for argument passing 3662 // to the argument register save area. For O32, the save area is allocated 3663 // in the caller's stack frame, while for N32/64, it is allocated in the 3664 // callee's stack frame. 3665 for (unsigned I = Idx; I < ArgRegs.size(); 3666 ++I, VaArgOffset += RegSizeInBytes) { 3667 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 3668 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 3669 FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 3670 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy()); 3671 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, 3672 MachinePointerInfo(), false, false, 0); 3673 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( 3674 (Value *)nullptr); 3675 OutChains.push_back(Store); 3676 } 3677 } 3678 3679 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, 3680 unsigned Align) const { 3681 MachineFunction &MF = State->getMachineFunction(); 3682 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 3683 3684 assert(Size && "Byval argument's size shouldn't be 0."); 3685 3686 Align = std::min(Align, TFL->getStackAlignment()); 3687 3688 unsigned FirstReg = 0; 3689 unsigned NumRegs = 0; 3690 3691 if (State->getCallingConv() != CallingConv::Fast) { 3692 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3693 const ArrayRef<MCPhysReg> IntArgRegs = Subtarget.getABI().GetByValArgRegs(); 3694 // FIXME: The O32 case actually describes no shadow registers. 3695 const MCPhysReg *ShadowRegs = 3696 Subtarget.isABI_O32() ? IntArgRegs.data() : Mips64DPRegs; 3697 3698 // We used to check the size as well but we can't do that anymore since 3699 // CCState::HandleByVal() rounds up the size after calling this function. 3700 assert(!(Align % RegSizeInBytes) && 3701 "Byval argument's alignment should be a multiple of" 3702 "RegSizeInBytes."); 3703 3704 FirstReg = State->getFirstUnallocated(IntArgRegs.data(), IntArgRegs.size()); 3705 3706 // If Align > RegSizeInBytes, the first arg register must be even. 3707 // FIXME: This condition happens to do the right thing but it's not the 3708 // right way to test it. We want to check that the stack frame offset 3709 // of the register is aligned. 3710 if ((Align > RegSizeInBytes) && (FirstReg % 2)) { 3711 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); 3712 ++FirstReg; 3713 } 3714 3715 // Mark the registers allocated. 3716 Size = RoundUpToAlignment(Size, RegSizeInBytes); 3717 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size()); 3718 Size -= RegSizeInBytes, ++I, ++NumRegs) 3719 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); 3720 } 3721 3722 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); 3723 } 3724