1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MipsISelLowering.h"
16 #include "InstPrinter/MipsInstPrinter.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "MCTargetDesc/MipsMCTargetDesc.h"
19 #include "MipsCCState.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMachineFunction.h"
22 #include "MipsRegisterInfo.h"
23 #include "MipsSubtarget.h"
24 #include "MipsTargetMachine.h"
25 #include "MipsTargetObjectFile.h"
26 #include "llvm/ADT/APFloat.h"
27 #include "llvm/ADT/ArrayRef.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/ADT/StringRef.h"
31 #include "llvm/ADT/StringSwitch.h"
32 #include "llvm/CodeGen/CallingConvLower.h"
33 #include "llvm/CodeGen/FunctionLoweringInfo.h"
34 #include "llvm/CodeGen/ISDOpcodes.h"
35 #include "llvm/CodeGen/MachineBasicBlock.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/CodeGen/MachineFunction.h"
38 #include "llvm/CodeGen/MachineInstr.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/CodeGen/MachineJumpTableInfo.h"
41 #include "llvm/CodeGen/MachineMemOperand.h"
42 #include "llvm/CodeGen/MachineOperand.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/MachineValueType.h"
45 #include "llvm/CodeGen/RuntimeLibcalls.h"
46 #include "llvm/CodeGen/SelectionDAG.h"
47 #include "llvm/CodeGen/SelectionDAGNodes.h"
48 #include "llvm/CodeGen/TargetFrameLowering.h"
49 #include "llvm/CodeGen/TargetInstrInfo.h"
50 #include "llvm/CodeGen/TargetRegisterInfo.h"
51 #include "llvm/CodeGen/ValueTypes.h"
52 #include "llvm/IR/CallingConv.h"
53 #include "llvm/IR/Constants.h"
54 #include "llvm/IR/DataLayout.h"
55 #include "llvm/IR/DebugLoc.h"
56 #include "llvm/IR/DerivedTypes.h"
57 #include "llvm/IR/Function.h"
58 #include "llvm/IR/GlobalValue.h"
59 #include "llvm/IR/Type.h"
60 #include "llvm/IR/Value.h"
61 #include "llvm/MC/MCRegisterInfo.h"
62 #include "llvm/Support/Casting.h"
63 #include "llvm/Support/CodeGen.h"
64 #include "llvm/Support/CommandLine.h"
65 #include "llvm/Support/Compiler.h"
66 #include "llvm/Support/ErrorHandling.h"
67 #include "llvm/Support/MathExtras.h"
68 #include "llvm/Target/TargetMachine.h"
69 #include "llvm/Target/TargetOptions.h"
70 #include <algorithm>
71 #include <cassert>
72 #include <cctype>
73 #include <cstdint>
74 #include <deque>
75 #include <iterator>
76 #include <utility>
77 #include <vector>
78 
79 using namespace llvm;
80 
81 #define DEBUG_TYPE "mips-lower"
82 
83 STATISTIC(NumTailCalls, "Number of tail calls");
84 
85 static cl::opt<bool>
86 LargeGOT("mxgot", cl::Hidden,
87          cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
88 
89 static cl::opt<bool>
90 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
91                cl::desc("MIPS: Don't trap on integer division by zero."),
92                cl::init(false));
93 
94 static const MCPhysReg Mips64DPRegs[8] = {
95   Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
96   Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
97 };
98 
99 // If I is a shifted mask, set the size (Size) and the first bit of the
100 // mask (Pos), and return true.
101 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
102 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
103   if (!isShiftedMask_64(I))
104     return false;
105 
106   Size = countPopulation(I);
107   Pos = countTrailingZeros(I);
108   return true;
109 }
110 
111 // The MIPS MSA ABI passes vector arguments in the integer register set.
112 // The number of integer registers used is dependant on the ABI used.
113 MVT MipsTargetLowering::getRegisterTypeForCallingConv(MVT VT) const {
114   if (VT.isVector() && Subtarget.hasMSA())
115     return Subtarget.isABI_O32() ? MVT::i32 : MVT::i64;
116   return MipsTargetLowering::getRegisterType(VT);
117 }
118 
119 MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
120                                                       EVT VT) const {
121   if (VT.isVector()) {
122       if (Subtarget.isABI_O32()) {
123         return MVT::i32;
124       } else {
125         return (VT.getSizeInBits() == 32) ? MVT::i32 : MVT::i64;
126       }
127   }
128   return MipsTargetLowering::getRegisterType(Context, VT);
129 }
130 
131 unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
132                                                            EVT VT) const {
133   if (VT.isVector())
134     return std::max((VT.getSizeInBits() / (Subtarget.isABI_O32() ? 32 : 64)),
135                     1U);
136   return MipsTargetLowering::getNumRegisters(Context, VT);
137 }
138 
139 unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv(
140     LLVMContext &Context, EVT VT, EVT &IntermediateVT,
141     unsigned &NumIntermediates, MVT &RegisterVT) const {
142   // Break down vector types to either 2 i64s or 4 i32s.
143   RegisterVT = getRegisterTypeForCallingConv(Context, VT) ;
144   IntermediateVT = RegisterVT;
145   NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits()
146                          ? VT.getVectorNumElements()
147                          : VT.getSizeInBits() / RegisterVT.getSizeInBits();
148 
149   return NumIntermediates;
150 }
151 
152 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
153   MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
154   return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
155 }
156 
157 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
158                                           SelectionDAG &DAG,
159                                           unsigned Flag) const {
160   return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
161 }
162 
163 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
164                                           SelectionDAG &DAG,
165                                           unsigned Flag) const {
166   return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
167 }
168 
169 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
170                                           SelectionDAG &DAG,
171                                           unsigned Flag) const {
172   return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
173 }
174 
175 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
176                                           SelectionDAG &DAG,
177                                           unsigned Flag) const {
178   return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
179 }
180 
181 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
182                                           SelectionDAG &DAG,
183                                           unsigned Flag) const {
184   return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
185                                    N->getOffset(), Flag);
186 }
187 
188 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
189   switch ((MipsISD::NodeType)Opcode) {
190   case MipsISD::FIRST_NUMBER:      break;
191   case MipsISD::JmpLink:           return "MipsISD::JmpLink";
192   case MipsISD::TailCall:          return "MipsISD::TailCall";
193   case MipsISD::Highest:           return "MipsISD::Highest";
194   case MipsISD::Higher:            return "MipsISD::Higher";
195   case MipsISD::Hi:                return "MipsISD::Hi";
196   case MipsISD::Lo:                return "MipsISD::Lo";
197   case MipsISD::GotHi:             return "MipsISD::GotHi";
198   case MipsISD::GPRel:             return "MipsISD::GPRel";
199   case MipsISD::ThreadPointer:     return "MipsISD::ThreadPointer";
200   case MipsISD::Ret:               return "MipsISD::Ret";
201   case MipsISD::ERet:              return "MipsISD::ERet";
202   case MipsISD::EH_RETURN:         return "MipsISD::EH_RETURN";
203   case MipsISD::FPBrcond:          return "MipsISD::FPBrcond";
204   case MipsISD::FPCmp:             return "MipsISD::FPCmp";
205   case MipsISD::FSELECT:           return "MipsISD::FSELECT";
206   case MipsISD::MTC1_D64:          return "MipsISD::MTC1_D64";
207   case MipsISD::CMovFP_T:          return "MipsISD::CMovFP_T";
208   case MipsISD::CMovFP_F:          return "MipsISD::CMovFP_F";
209   case MipsISD::TruncIntFP:        return "MipsISD::TruncIntFP";
210   case MipsISD::MFHI:              return "MipsISD::MFHI";
211   case MipsISD::MFLO:              return "MipsISD::MFLO";
212   case MipsISD::MTLOHI:            return "MipsISD::MTLOHI";
213   case MipsISD::Mult:              return "MipsISD::Mult";
214   case MipsISD::Multu:             return "MipsISD::Multu";
215   case MipsISD::MAdd:              return "MipsISD::MAdd";
216   case MipsISD::MAddu:             return "MipsISD::MAddu";
217   case MipsISD::MSub:              return "MipsISD::MSub";
218   case MipsISD::MSubu:             return "MipsISD::MSubu";
219   case MipsISD::DivRem:            return "MipsISD::DivRem";
220   case MipsISD::DivRemU:           return "MipsISD::DivRemU";
221   case MipsISD::DivRem16:          return "MipsISD::DivRem16";
222   case MipsISD::DivRemU16:         return "MipsISD::DivRemU16";
223   case MipsISD::BuildPairF64:      return "MipsISD::BuildPairF64";
224   case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
225   case MipsISD::Wrapper:           return "MipsISD::Wrapper";
226   case MipsISD::DynAlloc:          return "MipsISD::DynAlloc";
227   case MipsISD::Sync:              return "MipsISD::Sync";
228   case MipsISD::Ext:               return "MipsISD::Ext";
229   case MipsISD::Ins:               return "MipsISD::Ins";
230   case MipsISD::CIns:              return "MipsISD::CIns";
231   case MipsISD::LWL:               return "MipsISD::LWL";
232   case MipsISD::LWR:               return "MipsISD::LWR";
233   case MipsISD::SWL:               return "MipsISD::SWL";
234   case MipsISD::SWR:               return "MipsISD::SWR";
235   case MipsISD::LDL:               return "MipsISD::LDL";
236   case MipsISD::LDR:               return "MipsISD::LDR";
237   case MipsISD::SDL:               return "MipsISD::SDL";
238   case MipsISD::SDR:               return "MipsISD::SDR";
239   case MipsISD::EXTP:              return "MipsISD::EXTP";
240   case MipsISD::EXTPDP:            return "MipsISD::EXTPDP";
241   case MipsISD::EXTR_S_H:          return "MipsISD::EXTR_S_H";
242   case MipsISD::EXTR_W:            return "MipsISD::EXTR_W";
243   case MipsISD::EXTR_R_W:          return "MipsISD::EXTR_R_W";
244   case MipsISD::EXTR_RS_W:         return "MipsISD::EXTR_RS_W";
245   case MipsISD::SHILO:             return "MipsISD::SHILO";
246   case MipsISD::MTHLIP:            return "MipsISD::MTHLIP";
247   case MipsISD::MULSAQ_S_W_PH:     return "MipsISD::MULSAQ_S_W_PH";
248   case MipsISD::MAQ_S_W_PHL:       return "MipsISD::MAQ_S_W_PHL";
249   case MipsISD::MAQ_S_W_PHR:       return "MipsISD::MAQ_S_W_PHR";
250   case MipsISD::MAQ_SA_W_PHL:      return "MipsISD::MAQ_SA_W_PHL";
251   case MipsISD::MAQ_SA_W_PHR:      return "MipsISD::MAQ_SA_W_PHR";
252   case MipsISD::DPAU_H_QBL:        return "MipsISD::DPAU_H_QBL";
253   case MipsISD::DPAU_H_QBR:        return "MipsISD::DPAU_H_QBR";
254   case MipsISD::DPSU_H_QBL:        return "MipsISD::DPSU_H_QBL";
255   case MipsISD::DPSU_H_QBR:        return "MipsISD::DPSU_H_QBR";
256   case MipsISD::DPAQ_S_W_PH:       return "MipsISD::DPAQ_S_W_PH";
257   case MipsISD::DPSQ_S_W_PH:       return "MipsISD::DPSQ_S_W_PH";
258   case MipsISD::DPAQ_SA_L_W:       return "MipsISD::DPAQ_SA_L_W";
259   case MipsISD::DPSQ_SA_L_W:       return "MipsISD::DPSQ_SA_L_W";
260   case MipsISD::DPA_W_PH:          return "MipsISD::DPA_W_PH";
261   case MipsISD::DPS_W_PH:          return "MipsISD::DPS_W_PH";
262   case MipsISD::DPAQX_S_W_PH:      return "MipsISD::DPAQX_S_W_PH";
263   case MipsISD::DPAQX_SA_W_PH:     return "MipsISD::DPAQX_SA_W_PH";
264   case MipsISD::DPAX_W_PH:         return "MipsISD::DPAX_W_PH";
265   case MipsISD::DPSX_W_PH:         return "MipsISD::DPSX_W_PH";
266   case MipsISD::DPSQX_S_W_PH:      return "MipsISD::DPSQX_S_W_PH";
267   case MipsISD::DPSQX_SA_W_PH:     return "MipsISD::DPSQX_SA_W_PH";
268   case MipsISD::MULSA_W_PH:        return "MipsISD::MULSA_W_PH";
269   case MipsISD::MULT:              return "MipsISD::MULT";
270   case MipsISD::MULTU:             return "MipsISD::MULTU";
271   case MipsISD::MADD_DSP:          return "MipsISD::MADD_DSP";
272   case MipsISD::MADDU_DSP:         return "MipsISD::MADDU_DSP";
273   case MipsISD::MSUB_DSP:          return "MipsISD::MSUB_DSP";
274   case MipsISD::MSUBU_DSP:         return "MipsISD::MSUBU_DSP";
275   case MipsISD::SHLL_DSP:          return "MipsISD::SHLL_DSP";
276   case MipsISD::SHRA_DSP:          return "MipsISD::SHRA_DSP";
277   case MipsISD::SHRL_DSP:          return "MipsISD::SHRL_DSP";
278   case MipsISD::SETCC_DSP:         return "MipsISD::SETCC_DSP";
279   case MipsISD::SELECT_CC_DSP:     return "MipsISD::SELECT_CC_DSP";
280   case MipsISD::VALL_ZERO:         return "MipsISD::VALL_ZERO";
281   case MipsISD::VANY_ZERO:         return "MipsISD::VANY_ZERO";
282   case MipsISD::VALL_NONZERO:      return "MipsISD::VALL_NONZERO";
283   case MipsISD::VANY_NONZERO:      return "MipsISD::VANY_NONZERO";
284   case MipsISD::VCEQ:              return "MipsISD::VCEQ";
285   case MipsISD::VCLE_S:            return "MipsISD::VCLE_S";
286   case MipsISD::VCLE_U:            return "MipsISD::VCLE_U";
287   case MipsISD::VCLT_S:            return "MipsISD::VCLT_S";
288   case MipsISD::VCLT_U:            return "MipsISD::VCLT_U";
289   case MipsISD::VSMAX:             return "MipsISD::VSMAX";
290   case MipsISD::VSMIN:             return "MipsISD::VSMIN";
291   case MipsISD::VUMAX:             return "MipsISD::VUMAX";
292   case MipsISD::VUMIN:             return "MipsISD::VUMIN";
293   case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
294   case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
295   case MipsISD::VNOR:              return "MipsISD::VNOR";
296   case MipsISD::VSHF:              return "MipsISD::VSHF";
297   case MipsISD::SHF:               return "MipsISD::SHF";
298   case MipsISD::ILVEV:             return "MipsISD::ILVEV";
299   case MipsISD::ILVOD:             return "MipsISD::ILVOD";
300   case MipsISD::ILVL:              return "MipsISD::ILVL";
301   case MipsISD::ILVR:              return "MipsISD::ILVR";
302   case MipsISD::PCKEV:             return "MipsISD::PCKEV";
303   case MipsISD::PCKOD:             return "MipsISD::PCKOD";
304   case MipsISD::INSVE:             return "MipsISD::INSVE";
305   }
306   return nullptr;
307 }
308 
309 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
310                                        const MipsSubtarget &STI)
311     : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
312   // Mips does not have i1 type, so use i32 for
313   // setcc operations results (slt, sgt, ...).
314   setBooleanContents(ZeroOrOneBooleanContent);
315   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
316   // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
317   // does. Integer booleans still use 0 and 1.
318   if (Subtarget.hasMips32r6())
319     setBooleanContents(ZeroOrOneBooleanContent,
320                        ZeroOrNegativeOneBooleanContent);
321 
322   // Load extented operations for i1 types must be promoted
323   for (MVT VT : MVT::integer_valuetypes()) {
324     setLoadExtAction(ISD::EXTLOAD,  VT, MVT::i1,  Promote);
325     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1,  Promote);
326     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1,  Promote);
327   }
328 
329   // MIPS doesn't have extending float->double load/store.  Set LoadExtAction
330   // for f32, f16
331   for (MVT VT : MVT::fp_valuetypes()) {
332     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
333     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
334   }
335 
336   // Set LoadExtAction for f16 vectors to Expand
337   for (MVT VT : MVT::fp_vector_valuetypes()) {
338     MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
339     if (F16VT.isValid())
340       setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
341   }
342 
343   setTruncStoreAction(MVT::f32, MVT::f16, Expand);
344   setTruncStoreAction(MVT::f64, MVT::f16, Expand);
345 
346   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
347 
348   // Used by legalize types to correctly generate the setcc result.
349   // Without this, every float setcc comes with a AND/OR with the result,
350   // we don't want this, since the fpcmp result goes to a flag register,
351   // which is used implicitly by brcond and select operations.
352   AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
353 
354   // Mips Custom Operations
355   setOperationAction(ISD::BR_JT,              MVT::Other, Expand);
356   setOperationAction(ISD::GlobalAddress,      MVT::i32,   Custom);
357   setOperationAction(ISD::BlockAddress,       MVT::i32,   Custom);
358   setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);
359   setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);
360   setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);
361   setOperationAction(ISD::SELECT,             MVT::f32,   Custom);
362   setOperationAction(ISD::SELECT,             MVT::f64,   Custom);
363   setOperationAction(ISD::SELECT,             MVT::i32,   Custom);
364   setOperationAction(ISD::SETCC,              MVT::f32,   Custom);
365   setOperationAction(ISD::SETCC,              MVT::f64,   Custom);
366   setOperationAction(ISD::BRCOND,             MVT::Other, Custom);
367   setOperationAction(ISD::FCOPYSIGN,          MVT::f32,   Custom);
368   setOperationAction(ISD::FCOPYSIGN,          MVT::f64,   Custom);
369   setOperationAction(ISD::FP_TO_SINT,         MVT::i32,   Custom);
370 
371   if (Subtarget.isGP64bit()) {
372     setOperationAction(ISD::GlobalAddress,      MVT::i64,   Custom);
373     setOperationAction(ISD::BlockAddress,       MVT::i64,   Custom);
374     setOperationAction(ISD::GlobalTLSAddress,   MVT::i64,   Custom);
375     setOperationAction(ISD::JumpTable,          MVT::i64,   Custom);
376     setOperationAction(ISD::ConstantPool,       MVT::i64,   Custom);
377     setOperationAction(ISD::SELECT,             MVT::i64,   Custom);
378     setOperationAction(ISD::LOAD,               MVT::i64,   Custom);
379     setOperationAction(ISD::STORE,              MVT::i64,   Custom);
380     setOperationAction(ISD::FP_TO_SINT,         MVT::i64,   Custom);
381     setOperationAction(ISD::SHL_PARTS,          MVT::i64,   Custom);
382     setOperationAction(ISD::SRA_PARTS,          MVT::i64,   Custom);
383     setOperationAction(ISD::SRL_PARTS,          MVT::i64,   Custom);
384   }
385 
386   if (!Subtarget.isGP64bit()) {
387     setOperationAction(ISD::SHL_PARTS,          MVT::i32,   Custom);
388     setOperationAction(ISD::SRA_PARTS,          MVT::i32,   Custom);
389     setOperationAction(ISD::SRL_PARTS,          MVT::i32,   Custom);
390   }
391 
392   setOperationAction(ISD::EH_DWARF_CFA,         MVT::i32,   Custom);
393   if (Subtarget.isGP64bit())
394     setOperationAction(ISD::EH_DWARF_CFA,       MVT::i64,   Custom);
395 
396   setOperationAction(ISD::SDIV, MVT::i32, Expand);
397   setOperationAction(ISD::SREM, MVT::i32, Expand);
398   setOperationAction(ISD::UDIV, MVT::i32, Expand);
399   setOperationAction(ISD::UREM, MVT::i32, Expand);
400   setOperationAction(ISD::SDIV, MVT::i64, Expand);
401   setOperationAction(ISD::SREM, MVT::i64, Expand);
402   setOperationAction(ISD::UDIV, MVT::i64, Expand);
403   setOperationAction(ISD::UREM, MVT::i64, Expand);
404 
405   if (!(Subtarget.hasDSP() && Subtarget.hasMips32r2())) {
406     setOperationAction(ISD::ADDC, MVT::i32, Expand);
407     setOperationAction(ISD::ADDE, MVT::i32, Expand);
408   }
409 
410   setOperationAction(ISD::ADDC, MVT::i64, Expand);
411   setOperationAction(ISD::ADDE, MVT::i64, Expand);
412   setOperationAction(ISD::SUBC, MVT::i32, Expand);
413   setOperationAction(ISD::SUBE, MVT::i32, Expand);
414   setOperationAction(ISD::SUBC, MVT::i64, Expand);
415   setOperationAction(ISD::SUBE, MVT::i64, Expand);
416 
417   // Operations not directly supported by Mips.
418   setOperationAction(ISD::BR_CC,             MVT::f32,   Expand);
419   setOperationAction(ISD::BR_CC,             MVT::f64,   Expand);
420   setOperationAction(ISD::BR_CC,             MVT::i32,   Expand);
421   setOperationAction(ISD::BR_CC,             MVT::i64,   Expand);
422   setOperationAction(ISD::SELECT_CC,         MVT::i32,   Expand);
423   setOperationAction(ISD::SELECT_CC,         MVT::i64,   Expand);
424   setOperationAction(ISD::SELECT_CC,         MVT::f32,   Expand);
425   setOperationAction(ISD::SELECT_CC,         MVT::f64,   Expand);
426   setOperationAction(ISD::UINT_TO_FP,        MVT::i32,   Expand);
427   setOperationAction(ISD::UINT_TO_FP,        MVT::i64,   Expand);
428   setOperationAction(ISD::FP_TO_UINT,        MVT::i32,   Expand);
429   setOperationAction(ISD::FP_TO_UINT,        MVT::i64,   Expand);
430   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,    Expand);
431   if (Subtarget.hasCnMips()) {
432     setOperationAction(ISD::CTPOP,           MVT::i32,   Legal);
433     setOperationAction(ISD::CTPOP,           MVT::i64,   Legal);
434   } else {
435     setOperationAction(ISD::CTPOP,           MVT::i32,   Expand);
436     setOperationAction(ISD::CTPOP,           MVT::i64,   Expand);
437   }
438   setOperationAction(ISD::CTTZ,              MVT::i32,   Expand);
439   setOperationAction(ISD::CTTZ,              MVT::i64,   Expand);
440   setOperationAction(ISD::ROTL,              MVT::i32,   Expand);
441   setOperationAction(ISD::ROTL,              MVT::i64,   Expand);
442   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,  Expand);
443   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64,  Expand);
444 
445   if (!Subtarget.hasMips32r2())
446     setOperationAction(ISD::ROTR, MVT::i32,   Expand);
447 
448   if (!Subtarget.hasMips64r2())
449     setOperationAction(ISD::ROTR, MVT::i64,   Expand);
450 
451   setOperationAction(ISD::FSIN,              MVT::f32,   Expand);
452   setOperationAction(ISD::FSIN,              MVT::f64,   Expand);
453   setOperationAction(ISD::FCOS,              MVT::f32,   Expand);
454   setOperationAction(ISD::FCOS,              MVT::f64,   Expand);
455   setOperationAction(ISD::FSINCOS,           MVT::f32,   Expand);
456   setOperationAction(ISD::FSINCOS,           MVT::f64,   Expand);
457   setOperationAction(ISD::FPOW,              MVT::f32,   Expand);
458   setOperationAction(ISD::FPOW,              MVT::f64,   Expand);
459   setOperationAction(ISD::FLOG,              MVT::f32,   Expand);
460   setOperationAction(ISD::FLOG2,             MVT::f32,   Expand);
461   setOperationAction(ISD::FLOG10,            MVT::f32,   Expand);
462   setOperationAction(ISD::FEXP,              MVT::f32,   Expand);
463   setOperationAction(ISD::FMA,               MVT::f32,   Expand);
464   setOperationAction(ISD::FMA,               MVT::f64,   Expand);
465   setOperationAction(ISD::FREM,              MVT::f32,   Expand);
466   setOperationAction(ISD::FREM,              MVT::f64,   Expand);
467 
468   // Lower f16 conversion operations into library calls
469   setOperationAction(ISD::FP16_TO_FP,        MVT::f32,   Expand);
470   setOperationAction(ISD::FP_TO_FP16,        MVT::f32,   Expand);
471   setOperationAction(ISD::FP16_TO_FP,        MVT::f64,   Expand);
472   setOperationAction(ISD::FP_TO_FP16,        MVT::f64,   Expand);
473 
474   setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
475 
476   setOperationAction(ISD::VASTART,           MVT::Other, Custom);
477   setOperationAction(ISD::VAARG,             MVT::Other, Custom);
478   setOperationAction(ISD::VACOPY,            MVT::Other, Expand);
479   setOperationAction(ISD::VAEND,             MVT::Other, Expand);
480 
481   // Use the default for now
482   setOperationAction(ISD::STACKSAVE,         MVT::Other, Expand);
483   setOperationAction(ISD::STACKRESTORE,      MVT::Other, Expand);
484 
485   if (!Subtarget.isGP64bit()) {
486     setOperationAction(ISD::ATOMIC_LOAD,     MVT::i64,   Expand);
487     setOperationAction(ISD::ATOMIC_STORE,    MVT::i64,   Expand);
488   }
489 
490   if (!Subtarget.hasMips32r2()) {
491     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
492     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
493   }
494 
495   // MIPS16 lacks MIPS32's clz and clo instructions.
496   if (!Subtarget.hasMips32() || Subtarget.inMips16Mode())
497     setOperationAction(ISD::CTLZ, MVT::i32, Expand);
498   if (!Subtarget.hasMips64())
499     setOperationAction(ISD::CTLZ, MVT::i64, Expand);
500 
501   if (!Subtarget.hasMips32r2())
502     setOperationAction(ISD::BSWAP, MVT::i32, Expand);
503   if (!Subtarget.hasMips64r2())
504     setOperationAction(ISD::BSWAP, MVT::i64, Expand);
505 
506   if (Subtarget.isGP64bit()) {
507     setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);
508     setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
509     setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);
510     setTruncStoreAction(MVT::i64, MVT::i32, Custom);
511   }
512 
513   setOperationAction(ISD::TRAP, MVT::Other, Legal);
514 
515   setTargetDAGCombine(ISD::SDIVREM);
516   setTargetDAGCombine(ISD::UDIVREM);
517   setTargetDAGCombine(ISD::SELECT);
518   setTargetDAGCombine(ISD::AND);
519   setTargetDAGCombine(ISD::OR);
520   setTargetDAGCombine(ISD::ADD);
521   setTargetDAGCombine(ISD::SUB);
522   setTargetDAGCombine(ISD::AssertZext);
523   setTargetDAGCombine(ISD::SHL);
524 
525   if (ABI.IsO32()) {
526     // These libcalls are not available in 32-bit.
527     setLibcallName(RTLIB::SHL_I128, nullptr);
528     setLibcallName(RTLIB::SRL_I128, nullptr);
529     setLibcallName(RTLIB::SRA_I128, nullptr);
530   }
531 
532   setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
533 
534   // The arguments on the stack are defined in terms of 4-byte slots on O32
535   // and 8-byte slots on N32/N64.
536   setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4);
537 
538   setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
539 
540   MaxStoresPerMemcpy = 16;
541 
542   isMicroMips = Subtarget.inMicroMipsMode();
543 }
544 
545 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
546                                                      const MipsSubtarget &STI) {
547   if (STI.inMips16Mode())
548     return createMips16TargetLowering(TM, STI);
549 
550   return createMipsSETargetLowering(TM, STI);
551 }
552 
553 // Create a fast isel object.
554 FastISel *
555 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
556                                   const TargetLibraryInfo *libInfo) const {
557   const MipsTargetMachine &TM =
558       static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget());
559 
560   // We support only the standard encoding [MIPS32,MIPS32R5] ISAs.
561   bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() &&
562                      !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() &&
563                      !Subtarget.inMicroMipsMode();
564 
565   // Disable if either of the following is true:
566   // We do not generate PIC, the ABI is not O32, LargeGOT is being used.
567   if (!TM.isPositionIndependent() || !TM.getABI().IsO32() || LargeGOT)
568     UseFastISel = false;
569 
570   return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr;
571 }
572 
573 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
574                                            EVT VT) const {
575   if (!VT.isVector())
576     return MVT::i32;
577   return VT.changeVectorElementTypeToInteger();
578 }
579 
580 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
581                                     TargetLowering::DAGCombinerInfo &DCI,
582                                     const MipsSubtarget &Subtarget) {
583   if (DCI.isBeforeLegalizeOps())
584     return SDValue();
585 
586   EVT Ty = N->getValueType(0);
587   unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
588   unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
589   unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
590                                                   MipsISD::DivRemU16;
591   SDLoc DL(N);
592 
593   SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
594                                N->getOperand(0), N->getOperand(1));
595   SDValue InChain = DAG.getEntryNode();
596   SDValue InGlue = DivRem;
597 
598   // insert MFLO
599   if (N->hasAnyUseOfValue(0)) {
600     SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
601                                             InGlue);
602     DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
603     InChain = CopyFromLo.getValue(1);
604     InGlue = CopyFromLo.getValue(2);
605   }
606 
607   // insert MFHI
608   if (N->hasAnyUseOfValue(1)) {
609     SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
610                                             HI, Ty, InGlue);
611     DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
612   }
613 
614   return SDValue();
615 }
616 
617 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
618   switch (CC) {
619   default: llvm_unreachable("Unknown fp condition code!");
620   case ISD::SETEQ:
621   case ISD::SETOEQ: return Mips::FCOND_OEQ;
622   case ISD::SETUNE: return Mips::FCOND_UNE;
623   case ISD::SETLT:
624   case ISD::SETOLT: return Mips::FCOND_OLT;
625   case ISD::SETGT:
626   case ISD::SETOGT: return Mips::FCOND_OGT;
627   case ISD::SETLE:
628   case ISD::SETOLE: return Mips::FCOND_OLE;
629   case ISD::SETGE:
630   case ISD::SETOGE: return Mips::FCOND_OGE;
631   case ISD::SETULT: return Mips::FCOND_ULT;
632   case ISD::SETULE: return Mips::FCOND_ULE;
633   case ISD::SETUGT: return Mips::FCOND_UGT;
634   case ISD::SETUGE: return Mips::FCOND_UGE;
635   case ISD::SETUO:  return Mips::FCOND_UN;
636   case ISD::SETO:   return Mips::FCOND_OR;
637   case ISD::SETNE:
638   case ISD::SETONE: return Mips::FCOND_ONE;
639   case ISD::SETUEQ: return Mips::FCOND_UEQ;
640   }
641 }
642 
643 /// This function returns true if the floating point conditional branches and
644 /// conditional moves which use condition code CC should be inverted.
645 static bool invertFPCondCodeUser(Mips::CondCode CC) {
646   if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
647     return false;
648 
649   assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
650          "Illegal Condition Code");
651 
652   return true;
653 }
654 
655 // Creates and returns an FPCmp node from a setcc node.
656 // Returns Op if setcc is not a floating point comparison.
657 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
658   // must be a SETCC node
659   if (Op.getOpcode() != ISD::SETCC)
660     return Op;
661 
662   SDValue LHS = Op.getOperand(0);
663 
664   if (!LHS.getValueType().isFloatingPoint())
665     return Op;
666 
667   SDValue RHS = Op.getOperand(1);
668   SDLoc DL(Op);
669 
670   // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
671   // node if necessary.
672   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
673 
674   return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
675                      DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
676 }
677 
678 // Creates and returns a CMovFPT/F node.
679 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
680                             SDValue False, const SDLoc &DL) {
681   ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
682   bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
683   SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
684 
685   return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
686                      True.getValueType(), True, FCC0, False, Cond);
687 }
688 
689 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
690                                     TargetLowering::DAGCombinerInfo &DCI,
691                                     const MipsSubtarget &Subtarget) {
692   if (DCI.isBeforeLegalizeOps())
693     return SDValue();
694 
695   SDValue SetCC = N->getOperand(0);
696 
697   if ((SetCC.getOpcode() != ISD::SETCC) ||
698       !SetCC.getOperand(0).getValueType().isInteger())
699     return SDValue();
700 
701   SDValue False = N->getOperand(2);
702   EVT FalseTy = False.getValueType();
703 
704   if (!FalseTy.isInteger())
705     return SDValue();
706 
707   ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
708 
709   // If the RHS (False) is 0, we swap the order of the operands
710   // of ISD::SELECT (obviously also inverting the condition) so that we can
711   // take advantage of conditional moves using the $0 register.
712   // Example:
713   //   return (a != 0) ? x : 0;
714   //     load $reg, x
715   //     movz $reg, $0, a
716   if (!FalseC)
717     return SDValue();
718 
719   const SDLoc DL(N);
720 
721   if (!FalseC->getZExtValue()) {
722     ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
723     SDValue True = N->getOperand(1);
724 
725     SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
726                          SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
727 
728     return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
729   }
730 
731   // If both operands are integer constants there's a possibility that we
732   // can do some interesting optimizations.
733   SDValue True = N->getOperand(1);
734   ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
735 
736   if (!TrueC || !True.getValueType().isInteger())
737     return SDValue();
738 
739   // We'll also ignore MVT::i64 operands as this optimizations proves
740   // to be ineffective because of the required sign extensions as the result
741   // of a SETCC operator is always MVT::i32 for non-vector types.
742   if (True.getValueType() == MVT::i64)
743     return SDValue();
744 
745   int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
746 
747   // 1)  (a < x) ? y : y-1
748   //  slti $reg1, a, x
749   //  addiu $reg2, $reg1, y-1
750   if (Diff == 1)
751     return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
752 
753   // 2)  (a < x) ? y-1 : y
754   //  slti $reg1, a, x
755   //  xor $reg1, $reg1, 1
756   //  addiu $reg2, $reg1, y-1
757   if (Diff == -1) {
758     ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
759     SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
760                          SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
761     return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
762   }
763 
764   // Couldn't optimize.
765   return SDValue();
766 }
767 
768 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
769                                     TargetLowering::DAGCombinerInfo &DCI,
770                                     const MipsSubtarget &Subtarget) {
771   if (DCI.isBeforeLegalizeOps())
772     return SDValue();
773 
774   SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
775 
776   ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
777   if (!FalseC || FalseC->getZExtValue())
778     return SDValue();
779 
780   // Since RHS (False) is 0, we swap the order of the True/False operands
781   // (obviously also inverting the condition) so that we can
782   // take advantage of conditional moves using the $0 register.
783   // Example:
784   //   return (a != 0) ? x : 0;
785   //     load $reg, x
786   //     movz $reg, $0, a
787   unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
788                                                          MipsISD::CMovFP_T;
789 
790   SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
791   return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
792                      ValueIfFalse, FCC, ValueIfTrue, Glue);
793 }
794 
795 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
796                                  TargetLowering::DAGCombinerInfo &DCI,
797                                  const MipsSubtarget &Subtarget) {
798   if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
799     return SDValue();
800 
801   SDValue FirstOperand = N->getOperand(0);
802   unsigned FirstOperandOpc = FirstOperand.getOpcode();
803   SDValue Mask = N->getOperand(1);
804   EVT ValTy = N->getValueType(0);
805   SDLoc DL(N);
806 
807   uint64_t Pos = 0, SMPos, SMSize;
808   ConstantSDNode *CN;
809   SDValue NewOperand;
810   unsigned Opc;
811 
812   // Op's second operand must be a shifted mask.
813   if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
814       !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
815     return SDValue();
816 
817   if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) {
818     // Pattern match EXT.
819     //  $dst = and ((sra or srl) $src , pos), (2**size - 1)
820     //  => ext $dst, $src, pos, size
821 
822     // The second operand of the shift must be an immediate.
823     if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
824       return SDValue();
825 
826     Pos = CN->getZExtValue();
827 
828     // Return if the shifted mask does not start at bit 0 or the sum of its size
829     // and Pos exceeds the word's size.
830     if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
831       return SDValue();
832 
833     Opc = MipsISD::Ext;
834     NewOperand = FirstOperand.getOperand(0);
835   } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) {
836     // Pattern match CINS.
837     //  $dst = and (shl $src , pos), mask
838     //  => cins $dst, $src, pos, size
839     // mask is a shifted mask with consecutive 1's, pos = shift amount,
840     // size = population count.
841 
842     // The second operand of the shift must be an immediate.
843     if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
844       return SDValue();
845 
846     Pos = CN->getZExtValue();
847 
848     if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 ||
849         Pos + SMSize > ValTy.getSizeInBits())
850       return SDValue();
851 
852     NewOperand = FirstOperand.getOperand(0);
853     // SMSize is 'location' (position) in this case, not size.
854     SMSize--;
855     Opc = MipsISD::CIns;
856   } else {
857     // Pattern match EXT.
858     //  $dst = and $src, (2**size - 1) , if size > 16
859     //  => ext $dst, $src, pos, size , pos = 0
860 
861     // If the mask is <= 0xffff, andi can be used instead.
862     if (CN->getZExtValue() <= 0xffff)
863       return SDValue();
864 
865     // Return if the mask doesn't start at position 0.
866     if (SMPos)
867       return SDValue();
868 
869     Opc = MipsISD::Ext;
870     NewOperand = FirstOperand;
871   }
872   return DAG.getNode(Opc, DL, ValTy, NewOperand,
873                      DAG.getConstant(Pos, DL, MVT::i32),
874                      DAG.getConstant(SMSize, DL, MVT::i32));
875 }
876 
877 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
878                                 TargetLowering::DAGCombinerInfo &DCI,
879                                 const MipsSubtarget &Subtarget) {
880   // Pattern match INS.
881   //  $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
882   //  where mask1 = (2**size - 1) << pos, mask0 = ~mask1
883   //  => ins $dst, $src, size, pos, $src1
884   if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
885     return SDValue();
886 
887   SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
888   uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
889   ConstantSDNode *CN, *CN1;
890 
891   // See if Op's first operand matches (and $src1 , mask0).
892   if (And0.getOpcode() != ISD::AND)
893     return SDValue();
894 
895   if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
896       !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
897     return SDValue();
898 
899   // See if Op's second operand matches (and (shl $src, pos), mask1).
900   if (And1.getOpcode() == ISD::AND &&
901       And1.getOperand(0).getOpcode() == ISD::SHL) {
902 
903     if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
904         !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
905       return SDValue();
906 
907     // The shift masks must have the same position and size.
908     if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
909       return SDValue();
910 
911     SDValue Shl = And1.getOperand(0);
912 
913     if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
914       return SDValue();
915 
916     unsigned Shamt = CN->getZExtValue();
917 
918     // Return if the shift amount and the first bit position of mask are not the
919     // same.
920     EVT ValTy = N->getValueType(0);
921     if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
922       return SDValue();
923 
924     SDLoc DL(N);
925     return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
926                        DAG.getConstant(SMPos0, DL, MVT::i32),
927                        DAG.getConstant(SMSize0, DL, MVT::i32),
928                        And0.getOperand(0));
929   } else {
930     // Pattern match DINS.
931     //  $dst = or (and $src, mask0), mask1
932     //  where mask0 = ((1 << SMSize0) -1) << SMPos0
933     //  => dins $dst, $src, pos, size
934     if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) &&
935         ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) ||
936          (SMSize0 + SMPos0 <= 32))) {
937       // Check if AND instruction has constant as argument
938       bool isConstCase = And1.getOpcode() != ISD::AND;
939       if (And1.getOpcode() == ISD::AND) {
940         if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1))))
941           return SDValue();
942       } else {
943         if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1))))
944           return SDValue();
945       }
946       // Don't generate INS if constant OR operand doesn't fit into bits
947       // cleared by constant AND operand.
948       if (CN->getSExtValue() & CN1->getSExtValue())
949         return SDValue();
950 
951       SDLoc DL(N);
952       EVT ValTy = N->getOperand(0)->getValueType(0);
953       SDValue Const1;
954       SDValue SrlX;
955       if (!isConstCase) {
956         Const1 = DAG.getConstant(SMPos0, DL, MVT::i32);
957         SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1);
958       }
959       return DAG.getNode(
960           MipsISD::Ins, DL, N->getValueType(0),
961           isConstCase
962               ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy)
963               : SrlX,
964           DAG.getConstant(SMPos0, DL, MVT::i32),
965           DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31
966                                                         : SMSize0,
967                           DL, MVT::i32),
968           And0->getOperand(0));
969 
970     }
971     return SDValue();
972   }
973 }
974 
975 static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG,
976                                        const MipsSubtarget &Subtarget) {
977   // ROOTNode must have a multiplication as an operand for the match to be
978   // successful.
979   if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL &&
980       ROOTNode->getOperand(1).getOpcode() != ISD::MUL)
981     return SDValue();
982 
983   // We don't handle vector types here.
984   if (ROOTNode->getValueType(0).isVector())
985     return SDValue();
986 
987   // For MIPS64, madd / msub instructions are inefficent to use with 64 bit
988   // arithmetic. E.g.
989   // (add (mul a b) c) =>
990   //   let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in
991   //   MIPS64:   (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32)
992   //   or
993   //   MIPS64R2: (dins (mflo res) (mfhi res) 32 32)
994   //
995   // The overhead of setting up the Hi/Lo registers and reassembling the
996   // result makes this a dubious optimzation for MIPS64. The core of the
997   // problem is that Hi/Lo contain the upper and lower 32 bits of the
998   // operand and result.
999   //
1000   // It requires a chain of 4 add/mul for MIPS64R2 to get better code
1001   // density than doing it naively, 5 for MIPS64. Additionally, using
1002   // madd/msub on MIPS64 requires the operands actually be 32 bit sign
1003   // extended operands, not true 64 bit values.
1004   //
1005   // FIXME: For the moment, disable this completely for MIPS64.
1006   if (Subtarget.hasMips64())
1007     return SDValue();
1008 
1009   SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
1010                      ? ROOTNode->getOperand(0)
1011                      : ROOTNode->getOperand(1);
1012 
1013   SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
1014                      ? ROOTNode->getOperand(1)
1015                      : ROOTNode->getOperand(0);
1016 
1017   // Transform this to a MADD only if the user of this node is the add.
1018   // If there are other users of the mul, this function returns here.
1019   if (!Mult.hasOneUse())
1020     return SDValue();
1021 
1022   // maddu and madd are unusual instructions in that on MIPS64 bits 63..31
1023   // must be in canonical form, i.e. sign extended. For MIPS32, the operands
1024   // of the multiply must have 32 or more sign bits, otherwise we cannot
1025   // perform this optimization. We have to check this here as we're performing
1026   // this optimization pre-legalization.
1027   SDValue MultLHS = Mult->getOperand(0);
1028   SDValue MultRHS = Mult->getOperand(1);
1029 
1030   bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND &&
1031                   MultRHS->getOpcode() == ISD::SIGN_EXTEND;
1032   bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND &&
1033                     MultRHS->getOpcode() == ISD::ZERO_EXTEND;
1034 
1035   if (!IsSigned && !IsUnsigned)
1036     return SDValue();
1037 
1038   // Initialize accumulator.
1039   SDLoc DL(ROOTNode);
1040   SDValue TopHalf;
1041   SDValue BottomHalf;
1042   BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1043                               CurDAG.getIntPtrConstant(0, DL));
1044 
1045   TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1046                            CurDAG.getIntPtrConstant(1, DL));
1047   SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
1048                                   BottomHalf,
1049                                   TopHalf);
1050 
1051   // Create MipsMAdd(u) / MipsMSub(u) node.
1052   bool IsAdd = ROOTNode->getOpcode() == ISD::ADD;
1053   unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd)
1054                           : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub);
1055   SDValue MAddOps[3] = {
1056       CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)),
1057       CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn};
1058   EVT VTs[2] = {MVT::i32, MVT::i32};
1059   SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps);
1060 
1061   SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
1062   SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
1063   SDValue Combined =
1064       CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi);
1065   return Combined;
1066 }
1067 
1068 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG,
1069                                  TargetLowering::DAGCombinerInfo &DCI,
1070                                  const MipsSubtarget &Subtarget) {
1071   // (sub v0 (mul v1, v2)) => (msub v1, v2, v0)
1072   if (DCI.isBeforeLegalizeOps()) {
1073     if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1074         !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1075       return performMADD_MSUBCombine(N, DAG, Subtarget);
1076 
1077     return SDValue();
1078   }
1079 
1080   return SDValue();
1081 }
1082 
1083 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
1084                                  TargetLowering::DAGCombinerInfo &DCI,
1085                                  const MipsSubtarget &Subtarget) {
1086   // (add v0 (mul v1, v2)) => (madd v1, v2, v0)
1087   if (DCI.isBeforeLegalizeOps()) {
1088     if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1089         !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1090       return performMADD_MSUBCombine(N, DAG, Subtarget);
1091 
1092     return SDValue();
1093   }
1094 
1095   // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
1096   SDValue Add = N->getOperand(1);
1097 
1098   if (Add.getOpcode() != ISD::ADD)
1099     return SDValue();
1100 
1101   SDValue Lo = Add.getOperand(1);
1102 
1103   if ((Lo.getOpcode() != MipsISD::Lo) ||
1104       (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
1105     return SDValue();
1106 
1107   EVT ValTy = N->getValueType(0);
1108   SDLoc DL(N);
1109 
1110   SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
1111                              Add.getOperand(0));
1112   return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
1113 }
1114 
1115 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
1116                                  TargetLowering::DAGCombinerInfo &DCI,
1117                                  const MipsSubtarget &Subtarget) {
1118   // Pattern match CINS.
1119   //  $dst = shl (and $src , imm), pos
1120   //  => cins $dst, $src, pos, size
1121 
1122   if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips())
1123     return SDValue();
1124 
1125   SDValue FirstOperand = N->getOperand(0);
1126   unsigned FirstOperandOpc = FirstOperand.getOpcode();
1127   SDValue SecondOperand = N->getOperand(1);
1128   EVT ValTy = N->getValueType(0);
1129   SDLoc DL(N);
1130 
1131   uint64_t Pos = 0, SMPos, SMSize;
1132   ConstantSDNode *CN;
1133   SDValue NewOperand;
1134 
1135   // The second operand of the shift must be an immediate.
1136   if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)))
1137     return SDValue();
1138 
1139   Pos = CN->getZExtValue();
1140 
1141   if (Pos >= ValTy.getSizeInBits())
1142     return SDValue();
1143 
1144   if (FirstOperandOpc != ISD::AND)
1145     return SDValue();
1146 
1147   // AND's second operand must be a shifted mask.
1148   if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) ||
1149       !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
1150     return SDValue();
1151 
1152   // Return if the shifted mask does not start at bit 0 or the sum of its size
1153   // and Pos exceeds the word's size.
1154   if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits())
1155     return SDValue();
1156 
1157   NewOperand = FirstOperand.getOperand(0);
1158   // SMSize is 'location' (position) in this case, not size.
1159   SMSize--;
1160 
1161   return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand,
1162                      DAG.getConstant(Pos, DL, MVT::i32),
1163                      DAG.getConstant(SMSize, DL, MVT::i32));
1164 }
1165 
1166 SDValue  MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
1167   const {
1168   SelectionDAG &DAG = DCI.DAG;
1169   unsigned Opc = N->getOpcode();
1170 
1171   switch (Opc) {
1172   default: break;
1173   case ISD::SDIVREM:
1174   case ISD::UDIVREM:
1175     return performDivRemCombine(N, DAG, DCI, Subtarget);
1176   case ISD::SELECT:
1177     return performSELECTCombine(N, DAG, DCI, Subtarget);
1178   case MipsISD::CMovFP_F:
1179   case MipsISD::CMovFP_T:
1180     return performCMovFPCombine(N, DAG, DCI, Subtarget);
1181   case ISD::AND:
1182     return performANDCombine(N, DAG, DCI, Subtarget);
1183   case ISD::OR:
1184     return performORCombine(N, DAG, DCI, Subtarget);
1185   case ISD::ADD:
1186     return performADDCombine(N, DAG, DCI, Subtarget);
1187   case ISD::SHL:
1188     return performSHLCombine(N, DAG, DCI, Subtarget);
1189   case ISD::SUB:
1190     return performSUBCombine(N, DAG, DCI, Subtarget);
1191   }
1192 
1193   return SDValue();
1194 }
1195 
1196 bool MipsTargetLowering::isCheapToSpeculateCttz() const {
1197   return Subtarget.hasMips32();
1198 }
1199 
1200 bool MipsTargetLowering::isCheapToSpeculateCtlz() const {
1201   return Subtarget.hasMips32();
1202 }
1203 
1204 void
1205 MipsTargetLowering::LowerOperationWrapper(SDNode *N,
1206                                           SmallVectorImpl<SDValue> &Results,
1207                                           SelectionDAG &DAG) const {
1208   SDValue Res = LowerOperation(SDValue(N, 0), DAG);
1209 
1210   for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
1211     Results.push_back(Res.getValue(I));
1212 }
1213 
1214 void
1215 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
1216                                        SmallVectorImpl<SDValue> &Results,
1217                                        SelectionDAG &DAG) const {
1218   return LowerOperationWrapper(N, Results, DAG);
1219 }
1220 
1221 SDValue MipsTargetLowering::
1222 LowerOperation(SDValue Op, SelectionDAG &DAG) const
1223 {
1224   switch (Op.getOpcode())
1225   {
1226   case ISD::BRCOND:             return lowerBRCOND(Op, DAG);
1227   case ISD::ConstantPool:       return lowerConstantPool(Op, DAG);
1228   case ISD::GlobalAddress:      return lowerGlobalAddress(Op, DAG);
1229   case ISD::BlockAddress:       return lowerBlockAddress(Op, DAG);
1230   case ISD::GlobalTLSAddress:   return lowerGlobalTLSAddress(Op, DAG);
1231   case ISD::JumpTable:          return lowerJumpTable(Op, DAG);
1232   case ISD::SELECT:             return lowerSELECT(Op, DAG);
1233   case ISD::SETCC:              return lowerSETCC(Op, DAG);
1234   case ISD::VASTART:            return lowerVASTART(Op, DAG);
1235   case ISD::VAARG:              return lowerVAARG(Op, DAG);
1236   case ISD::FCOPYSIGN:          return lowerFCOPYSIGN(Op, DAG);
1237   case ISD::FRAMEADDR:          return lowerFRAMEADDR(Op, DAG);
1238   case ISD::RETURNADDR:         return lowerRETURNADDR(Op, DAG);
1239   case ISD::EH_RETURN:          return lowerEH_RETURN(Op, DAG);
1240   case ISD::ATOMIC_FENCE:       return lowerATOMIC_FENCE(Op, DAG);
1241   case ISD::SHL_PARTS:          return lowerShiftLeftParts(Op, DAG);
1242   case ISD::SRA_PARTS:          return lowerShiftRightParts(Op, DAG, true);
1243   case ISD::SRL_PARTS:          return lowerShiftRightParts(Op, DAG, false);
1244   case ISD::LOAD:               return lowerLOAD(Op, DAG);
1245   case ISD::STORE:              return lowerSTORE(Op, DAG);
1246   case ISD::EH_DWARF_CFA:       return lowerEH_DWARF_CFA(Op, DAG);
1247   case ISD::FP_TO_SINT:         return lowerFP_TO_SINT(Op, DAG);
1248   }
1249   return SDValue();
1250 }
1251 
1252 //===----------------------------------------------------------------------===//
1253 //  Lower helper functions
1254 //===----------------------------------------------------------------------===//
1255 
1256 // addLiveIn - This helper function adds the specified physical register to the
1257 // MachineFunction as a live in value.  It also creates a corresponding
1258 // virtual register for it.
1259 static unsigned
1260 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
1261 {
1262   unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1263   MF.getRegInfo().addLiveIn(PReg, VReg);
1264   return VReg;
1265 }
1266 
1267 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI,
1268                                               MachineBasicBlock &MBB,
1269                                               const TargetInstrInfo &TII,
1270                                               bool Is64Bit, bool IsMicroMips) {
1271   if (NoZeroDivCheck)
1272     return &MBB;
1273 
1274   // Insert instruction "teq $divisor_reg, $zero, 7".
1275   MachineBasicBlock::iterator I(MI);
1276   MachineInstrBuilder MIB;
1277   MachineOperand &Divisor = MI.getOperand(2);
1278   MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(),
1279                 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1280             .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
1281             .addReg(Mips::ZERO)
1282             .addImm(7);
1283 
1284   // Use the 32-bit sub-register if this is a 64-bit division.
1285   if (Is64Bit)
1286     MIB->getOperand(0).setSubReg(Mips::sub_32);
1287 
1288   // Clear Divisor's kill flag.
1289   Divisor.setIsKill(false);
1290 
1291   // We would normally delete the original instruction here but in this case
1292   // we only needed to inject an additional instruction rather than replace it.
1293 
1294   return &MBB;
1295 }
1296 
1297 MachineBasicBlock *
1298 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1299                                                 MachineBasicBlock *BB) const {
1300   switch (MI.getOpcode()) {
1301   default:
1302     llvm_unreachable("Unexpected instr type to insert");
1303   case Mips::ATOMIC_LOAD_ADD_I8:
1304     return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
1305   case Mips::ATOMIC_LOAD_ADD_I16:
1306     return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
1307   case Mips::ATOMIC_LOAD_ADD_I32:
1308     return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
1309   case Mips::ATOMIC_LOAD_ADD_I64:
1310     return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
1311 
1312   case Mips::ATOMIC_LOAD_AND_I8:
1313     return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
1314   case Mips::ATOMIC_LOAD_AND_I16:
1315     return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
1316   case Mips::ATOMIC_LOAD_AND_I32:
1317     return emitAtomicBinary(MI, BB, 4, Mips::AND);
1318   case Mips::ATOMIC_LOAD_AND_I64:
1319     return emitAtomicBinary(MI, BB, 8, Mips::AND64);
1320 
1321   case Mips::ATOMIC_LOAD_OR_I8:
1322     return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
1323   case Mips::ATOMIC_LOAD_OR_I16:
1324     return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
1325   case Mips::ATOMIC_LOAD_OR_I32:
1326     return emitAtomicBinary(MI, BB, 4, Mips::OR);
1327   case Mips::ATOMIC_LOAD_OR_I64:
1328     return emitAtomicBinary(MI, BB, 8, Mips::OR64);
1329 
1330   case Mips::ATOMIC_LOAD_XOR_I8:
1331     return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
1332   case Mips::ATOMIC_LOAD_XOR_I16:
1333     return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
1334   case Mips::ATOMIC_LOAD_XOR_I32:
1335     return emitAtomicBinary(MI, BB, 4, Mips::XOR);
1336   case Mips::ATOMIC_LOAD_XOR_I64:
1337     return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
1338 
1339   case Mips::ATOMIC_LOAD_NAND_I8:
1340     return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
1341   case Mips::ATOMIC_LOAD_NAND_I16:
1342     return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
1343   case Mips::ATOMIC_LOAD_NAND_I32:
1344     return emitAtomicBinary(MI, BB, 4, 0, true);
1345   case Mips::ATOMIC_LOAD_NAND_I64:
1346     return emitAtomicBinary(MI, BB, 8, 0, true);
1347 
1348   case Mips::ATOMIC_LOAD_SUB_I8:
1349     return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
1350   case Mips::ATOMIC_LOAD_SUB_I16:
1351     return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
1352   case Mips::ATOMIC_LOAD_SUB_I32:
1353     return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
1354   case Mips::ATOMIC_LOAD_SUB_I64:
1355     return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
1356 
1357   case Mips::ATOMIC_SWAP_I8:
1358     return emitAtomicBinaryPartword(MI, BB, 1, 0);
1359   case Mips::ATOMIC_SWAP_I16:
1360     return emitAtomicBinaryPartword(MI, BB, 2, 0);
1361   case Mips::ATOMIC_SWAP_I32:
1362     return emitAtomicBinary(MI, BB, 4, 0);
1363   case Mips::ATOMIC_SWAP_I64:
1364     return emitAtomicBinary(MI, BB, 8, 0);
1365 
1366   case Mips::ATOMIC_CMP_SWAP_I8:
1367     return emitAtomicCmpSwapPartword(MI, BB, 1);
1368   case Mips::ATOMIC_CMP_SWAP_I16:
1369     return emitAtomicCmpSwapPartword(MI, BB, 2);
1370   case Mips::ATOMIC_CMP_SWAP_I32:
1371     return emitAtomicCmpSwap(MI, BB, 4);
1372   case Mips::ATOMIC_CMP_SWAP_I64:
1373     return emitAtomicCmpSwap(MI, BB, 8);
1374   case Mips::PseudoSDIV:
1375   case Mips::PseudoUDIV:
1376   case Mips::DIV:
1377   case Mips::DIVU:
1378   case Mips::MOD:
1379   case Mips::MODU:
1380     return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false,
1381                                false);
1382   case Mips::SDIV_MM_Pseudo:
1383   case Mips::UDIV_MM_Pseudo:
1384   case Mips::SDIV_MM:
1385   case Mips::UDIV_MM:
1386   case Mips::DIV_MMR6:
1387   case Mips::DIVU_MMR6:
1388   case Mips::MOD_MMR6:
1389   case Mips::MODU_MMR6:
1390     return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true);
1391   case Mips::PseudoDSDIV:
1392   case Mips::PseudoDUDIV:
1393   case Mips::DDIV:
1394   case Mips::DDIVU:
1395   case Mips::DMOD:
1396   case Mips::DMODU:
1397     return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
1398 
1399   case Mips::PseudoSELECT_I:
1400   case Mips::PseudoSELECT_I64:
1401   case Mips::PseudoSELECT_S:
1402   case Mips::PseudoSELECT_D32:
1403   case Mips::PseudoSELECT_D64:
1404     return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1405   case Mips::PseudoSELECTFP_F_I:
1406   case Mips::PseudoSELECTFP_F_I64:
1407   case Mips::PseudoSELECTFP_F_S:
1408   case Mips::PseudoSELECTFP_F_D32:
1409   case Mips::PseudoSELECTFP_F_D64:
1410     return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1411   case Mips::PseudoSELECTFP_T_I:
1412   case Mips::PseudoSELECTFP_T_I64:
1413   case Mips::PseudoSELECTFP_T_S:
1414   case Mips::PseudoSELECTFP_T_D32:
1415   case Mips::PseudoSELECTFP_T_D64:
1416     return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1417   }
1418 }
1419 
1420 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1421 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1422 MachineBasicBlock *MipsTargetLowering::emitAtomicBinary(MachineInstr &MI,
1423                                                         MachineBasicBlock *BB,
1424                                                         unsigned Size,
1425                                                         unsigned BinOpcode,
1426                                                         bool Nand) const {
1427   assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
1428 
1429   MachineFunction *MF = BB->getParent();
1430   MachineRegisterInfo &RegInfo = MF->getRegInfo();
1431   const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1432   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1433   const bool ArePtrs64bit = ABI.ArePtrs64bit();
1434   DebugLoc DL = MI.getDebugLoc();
1435   unsigned LL, SC, AND, NOR, ZERO, BEQ;
1436 
1437   if (Size == 4) {
1438     if (isMicroMips) {
1439       LL = Mips::LL_MM;
1440       SC = Mips::SC_MM;
1441     } else {
1442       LL = Subtarget.hasMips32r6()
1443                ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1444                : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1445       SC = Subtarget.hasMips32r6()
1446                ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1447                : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1448     }
1449 
1450     AND = Mips::AND;
1451     NOR = Mips::NOR;
1452     ZERO = Mips::ZERO;
1453     BEQ = Mips::BEQ;
1454   } else {
1455     LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1456     SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1457     AND = Mips::AND64;
1458     NOR = Mips::NOR64;
1459     ZERO = Mips::ZERO_64;
1460     BEQ = Mips::BEQ64;
1461   }
1462 
1463   unsigned OldVal = MI.getOperand(0).getReg();
1464   unsigned Ptr = MI.getOperand(1).getReg();
1465   unsigned Incr = MI.getOperand(2).getReg();
1466 
1467   unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1468   unsigned AndRes = RegInfo.createVirtualRegister(RC);
1469   unsigned Success = RegInfo.createVirtualRegister(RC);
1470 
1471   // insert new blocks after the current block
1472   const BasicBlock *LLVM_BB = BB->getBasicBlock();
1473   MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1474   MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1475   MachineFunction::iterator It = ++BB->getIterator();
1476   MF->insert(It, loopMBB);
1477   MF->insert(It, exitMBB);
1478 
1479   // Transfer the remainder of BB and its successor edges to exitMBB.
1480   exitMBB->splice(exitMBB->begin(), BB,
1481                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
1482   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1483 
1484   //  thisMBB:
1485   //    ...
1486   //    fallthrough --> loopMBB
1487   BB->addSuccessor(loopMBB);
1488   loopMBB->addSuccessor(loopMBB);
1489   loopMBB->addSuccessor(exitMBB);
1490 
1491   //  loopMBB:
1492   //    ll oldval, 0(ptr)
1493   //    <binop> storeval, oldval, incr
1494   //    sc success, storeval, 0(ptr)
1495   //    beq success, $0, loopMBB
1496   BB = loopMBB;
1497   BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1498   if (Nand) {
1499     //  and andres, oldval, incr
1500     //  nor storeval, $0, andres
1501     BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1502     BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1503   } else if (BinOpcode) {
1504     //  <binop> storeval, oldval, incr
1505     BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1506   } else {
1507     StoreVal = Incr;
1508   }
1509   BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1510   BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1511 
1512   MI.eraseFromParent(); // The instruction is gone now.
1513 
1514   return exitMBB;
1515 }
1516 
1517 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1518     MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1519     unsigned SrcReg) const {
1520   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1521   const DebugLoc &DL = MI.getDebugLoc();
1522 
1523   if (Subtarget.hasMips32r2() && Size == 1) {
1524     BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1525     return BB;
1526   }
1527 
1528   if (Subtarget.hasMips32r2() && Size == 2) {
1529     BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1530     return BB;
1531   }
1532 
1533   MachineFunction *MF = BB->getParent();
1534   MachineRegisterInfo &RegInfo = MF->getRegInfo();
1535   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1536   unsigned ScrReg = RegInfo.createVirtualRegister(RC);
1537 
1538   assert(Size < 32);
1539   int64_t ShiftImm = 32 - (Size * 8);
1540 
1541   BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1542   BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1543 
1544   return BB;
1545 }
1546 
1547 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1548     MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
1549     bool Nand) const {
1550   assert((Size == 1 || Size == 2) &&
1551          "Unsupported size for EmitAtomicBinaryPartial.");
1552 
1553   MachineFunction *MF = BB->getParent();
1554   MachineRegisterInfo &RegInfo = MF->getRegInfo();
1555   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1556   const bool ArePtrs64bit = ABI.ArePtrs64bit();
1557   const TargetRegisterClass *RCp =
1558     getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1559   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1560   DebugLoc DL = MI.getDebugLoc();
1561 
1562   unsigned Dest = MI.getOperand(0).getReg();
1563   unsigned Ptr = MI.getOperand(1).getReg();
1564   unsigned Incr = MI.getOperand(2).getReg();
1565 
1566   unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1567   unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1568   unsigned Mask = RegInfo.createVirtualRegister(RC);
1569   unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1570   unsigned NewVal = RegInfo.createVirtualRegister(RC);
1571   unsigned OldVal = RegInfo.createVirtualRegister(RC);
1572   unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1573   unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1574   unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1575   unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1576   unsigned AndRes = RegInfo.createVirtualRegister(RC);
1577   unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1578   unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1579   unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1580   unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1581   unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1582   unsigned Success = RegInfo.createVirtualRegister(RC);
1583 
1584   unsigned LL, SC;
1585   if (isMicroMips) {
1586     LL = Mips::LL_MM;
1587     SC = Mips::SC_MM;
1588   } else {
1589     LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1590                                  : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1591     SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1592                                  : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1593   }
1594 
1595   // insert new blocks after the current block
1596   const BasicBlock *LLVM_BB = BB->getBasicBlock();
1597   MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1598   MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1599   MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1600   MachineFunction::iterator It = ++BB->getIterator();
1601   MF->insert(It, loopMBB);
1602   MF->insert(It, sinkMBB);
1603   MF->insert(It, exitMBB);
1604 
1605   // Transfer the remainder of BB and its successor edges to exitMBB.
1606   exitMBB->splice(exitMBB->begin(), BB,
1607                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
1608   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1609 
1610   BB->addSuccessor(loopMBB);
1611   loopMBB->addSuccessor(loopMBB);
1612   loopMBB->addSuccessor(sinkMBB);
1613   sinkMBB->addSuccessor(exitMBB);
1614 
1615   //  thisMBB:
1616   //    addiu   masklsb2,$0,-4                # 0xfffffffc
1617   //    and     alignedaddr,ptr,masklsb2
1618   //    andi    ptrlsb2,ptr,3
1619   //    sll     shiftamt,ptrlsb2,3
1620   //    ori     maskupper,$0,255               # 0xff
1621   //    sll     mask,maskupper,shiftamt
1622   //    nor     mask2,$0,mask
1623   //    sll     incr2,incr,shiftamt
1624 
1625   int64_t MaskImm = (Size == 1) ? 255 : 65535;
1626   BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2)
1627     .addReg(ABI.GetNullPtr()).addImm(-4);
1628   BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
1629     .addReg(Ptr).addReg(MaskLSB2);
1630   BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1631       .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1632   if (Subtarget.isLittle()) {
1633     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1634   } else {
1635     unsigned Off = RegInfo.createVirtualRegister(RC);
1636     BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1637       .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1638     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1639   }
1640   BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1641     .addReg(Mips::ZERO).addImm(MaskImm);
1642   BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1643     .addReg(MaskUpper).addReg(ShiftAmt);
1644   BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1645   BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1646 
1647   // atomic.load.binop
1648   // loopMBB:
1649   //   ll      oldval,0(alignedaddr)
1650   //   binop   binopres,oldval,incr2
1651   //   and     newval,binopres,mask
1652   //   and     maskedoldval0,oldval,mask2
1653   //   or      storeval,maskedoldval0,newval
1654   //   sc      success,storeval,0(alignedaddr)
1655   //   beq     success,$0,loopMBB
1656 
1657   // atomic.swap
1658   // loopMBB:
1659   //   ll      oldval,0(alignedaddr)
1660   //   and     newval,incr2,mask
1661   //   and     maskedoldval0,oldval,mask2
1662   //   or      storeval,maskedoldval0,newval
1663   //   sc      success,storeval,0(alignedaddr)
1664   //   beq     success,$0,loopMBB
1665 
1666   BB = loopMBB;
1667   BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1668   if (Nand) {
1669     //  and andres, oldval, incr2
1670     //  nor binopres, $0, andres
1671     //  and newval, binopres, mask
1672     BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1673     BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1674       .addReg(Mips::ZERO).addReg(AndRes);
1675     BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1676   } else if (BinOpcode) {
1677     //  <binop> binopres, oldval, incr2
1678     //  and newval, binopres, mask
1679     BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1680     BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1681   } else { // atomic.swap
1682     //  and newval, incr2, mask
1683     BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1684   }
1685 
1686   BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1687     .addReg(OldVal).addReg(Mask2);
1688   BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1689     .addReg(MaskedOldVal0).addReg(NewVal);
1690   BuildMI(BB, DL, TII->get(SC), Success)
1691     .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1692   BuildMI(BB, DL, TII->get(Mips::BEQ))
1693     .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1694 
1695   //  sinkMBB:
1696   //    and     maskedoldval1,oldval,mask
1697   //    srl     srlres,maskedoldval1,shiftamt
1698   //    sign_extend dest,srlres
1699   BB = sinkMBB;
1700 
1701   BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1702     .addReg(OldVal).addReg(Mask);
1703   BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1704       .addReg(MaskedOldVal1).addReg(ShiftAmt);
1705   BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1706 
1707   MI.eraseFromParent(); // The instruction is gone now.
1708 
1709   return exitMBB;
1710 }
1711 
1712 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI,
1713                                                          MachineBasicBlock *BB,
1714                                                          unsigned Size) const {
1715   assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1716 
1717   MachineFunction *MF = BB->getParent();
1718   MachineRegisterInfo &RegInfo = MF->getRegInfo();
1719   const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1720   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1721   const bool ArePtrs64bit = ABI.ArePtrs64bit();
1722   DebugLoc DL = MI.getDebugLoc();
1723   unsigned LL, SC, ZERO, BNE, BEQ;
1724 
1725   if (Size == 4) {
1726     if (isMicroMips) {
1727       LL = Mips::LL_MM;
1728       SC = Mips::SC_MM;
1729     } else {
1730       LL = Subtarget.hasMips32r6()
1731                ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1732                : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1733       SC = Subtarget.hasMips32r6()
1734                ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1735                : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1736     }
1737 
1738     ZERO = Mips::ZERO;
1739     BNE = Mips::BNE;
1740     BEQ = Mips::BEQ;
1741   } else {
1742     LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1743     SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1744     ZERO = Mips::ZERO_64;
1745     BNE = Mips::BNE64;
1746     BEQ = Mips::BEQ64;
1747   }
1748 
1749   unsigned Dest = MI.getOperand(0).getReg();
1750   unsigned Ptr = MI.getOperand(1).getReg();
1751   unsigned OldVal = MI.getOperand(2).getReg();
1752   unsigned NewVal = MI.getOperand(3).getReg();
1753 
1754   unsigned Success = RegInfo.createVirtualRegister(RC);
1755 
1756   // insert new blocks after the current block
1757   const BasicBlock *LLVM_BB = BB->getBasicBlock();
1758   MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1759   MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1760   MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1761   MachineFunction::iterator It = ++BB->getIterator();
1762   MF->insert(It, loop1MBB);
1763   MF->insert(It, loop2MBB);
1764   MF->insert(It, exitMBB);
1765 
1766   // Transfer the remainder of BB and its successor edges to exitMBB.
1767   exitMBB->splice(exitMBB->begin(), BB,
1768                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
1769   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1770 
1771   //  thisMBB:
1772   //    ...
1773   //    fallthrough --> loop1MBB
1774   BB->addSuccessor(loop1MBB);
1775   loop1MBB->addSuccessor(exitMBB);
1776   loop1MBB->addSuccessor(loop2MBB);
1777   loop2MBB->addSuccessor(loop1MBB);
1778   loop2MBB->addSuccessor(exitMBB);
1779 
1780   // loop1MBB:
1781   //   ll dest, 0(ptr)
1782   //   bne dest, oldval, exitMBB
1783   BB = loop1MBB;
1784   BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1785   BuildMI(BB, DL, TII->get(BNE))
1786     .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1787 
1788   // loop2MBB:
1789   //   sc success, newval, 0(ptr)
1790   //   beq success, $0, loop1MBB
1791   BB = loop2MBB;
1792   BuildMI(BB, DL, TII->get(SC), Success)
1793     .addReg(NewVal).addReg(Ptr).addImm(0);
1794   BuildMI(BB, DL, TII->get(BEQ))
1795     .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1796 
1797   MI.eraseFromParent(); // The instruction is gone now.
1798 
1799   return exitMBB;
1800 }
1801 
1802 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
1803     MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1804   assert((Size == 1 || Size == 2) &&
1805       "Unsupported size for EmitAtomicCmpSwapPartial.");
1806 
1807   MachineFunction *MF = BB->getParent();
1808   MachineRegisterInfo &RegInfo = MF->getRegInfo();
1809   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1810   const bool ArePtrs64bit = ABI.ArePtrs64bit();
1811   const TargetRegisterClass *RCp =
1812     getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1813   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1814   DebugLoc DL = MI.getDebugLoc();
1815 
1816   unsigned Dest = MI.getOperand(0).getReg();
1817   unsigned Ptr = MI.getOperand(1).getReg();
1818   unsigned CmpVal = MI.getOperand(2).getReg();
1819   unsigned NewVal = MI.getOperand(3).getReg();
1820 
1821   unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1822   unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1823   unsigned Mask = RegInfo.createVirtualRegister(RC);
1824   unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1825   unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1826   unsigned OldVal = RegInfo.createVirtualRegister(RC);
1827   unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1828   unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1829   unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1830   unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1831   unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1832   unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1833   unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1834   unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1835   unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1836   unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1837   unsigned Success = RegInfo.createVirtualRegister(RC);
1838   unsigned LL, SC;
1839 
1840   if (isMicroMips) {
1841     LL = Mips::LL_MM;
1842     SC = Mips::SC_MM;
1843   } else {
1844     LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1845                                  : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1846     SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1847                                  : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1848   }
1849 
1850   // insert new blocks after the current block
1851   const BasicBlock *LLVM_BB = BB->getBasicBlock();
1852   MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1853   MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1854   MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1855   MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1856   MachineFunction::iterator It = ++BB->getIterator();
1857   MF->insert(It, loop1MBB);
1858   MF->insert(It, loop2MBB);
1859   MF->insert(It, sinkMBB);
1860   MF->insert(It, exitMBB);
1861 
1862   // Transfer the remainder of BB and its successor edges to exitMBB.
1863   exitMBB->splice(exitMBB->begin(), BB,
1864                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
1865   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1866 
1867   BB->addSuccessor(loop1MBB);
1868   loop1MBB->addSuccessor(sinkMBB);
1869   loop1MBB->addSuccessor(loop2MBB);
1870   loop2MBB->addSuccessor(loop1MBB);
1871   loop2MBB->addSuccessor(sinkMBB);
1872   sinkMBB->addSuccessor(exitMBB);
1873 
1874   // FIXME: computation of newval2 can be moved to loop2MBB.
1875   //  thisMBB:
1876   //    addiu   masklsb2,$0,-4                # 0xfffffffc
1877   //    and     alignedaddr,ptr,masklsb2
1878   //    andi    ptrlsb2,ptr,3
1879   //    xori    ptrlsb2,ptrlsb2,3              # Only for BE
1880   //    sll     shiftamt,ptrlsb2,3
1881   //    ori     maskupper,$0,255               # 0xff
1882   //    sll     mask,maskupper,shiftamt
1883   //    nor     mask2,$0,mask
1884   //    andi    maskedcmpval,cmpval,255
1885   //    sll     shiftedcmpval,maskedcmpval,shiftamt
1886   //    andi    maskednewval,newval,255
1887   //    sll     shiftednewval,maskednewval,shiftamt
1888   int64_t MaskImm = (Size == 1) ? 255 : 65535;
1889   BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
1890     .addReg(ABI.GetNullPtr()).addImm(-4);
1891   BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
1892     .addReg(Ptr).addReg(MaskLSB2);
1893   BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1894       .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1895   if (Subtarget.isLittle()) {
1896     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1897   } else {
1898     unsigned Off = RegInfo.createVirtualRegister(RC);
1899     BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1900       .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1901     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1902   }
1903   BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1904     .addReg(Mips::ZERO).addImm(MaskImm);
1905   BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1906     .addReg(MaskUpper).addReg(ShiftAmt);
1907   BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1908   BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1909     .addReg(CmpVal).addImm(MaskImm);
1910   BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1911     .addReg(MaskedCmpVal).addReg(ShiftAmt);
1912   BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1913     .addReg(NewVal).addImm(MaskImm);
1914   BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1915     .addReg(MaskedNewVal).addReg(ShiftAmt);
1916 
1917   //  loop1MBB:
1918   //    ll      oldval,0(alginedaddr)
1919   //    and     maskedoldval0,oldval,mask
1920   //    bne     maskedoldval0,shiftedcmpval,sinkMBB
1921   BB = loop1MBB;
1922   BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1923   BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1924     .addReg(OldVal).addReg(Mask);
1925   BuildMI(BB, DL, TII->get(Mips::BNE))
1926     .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1927 
1928   //  loop2MBB:
1929   //    and     maskedoldval1,oldval,mask2
1930   //    or      storeval,maskedoldval1,shiftednewval
1931   //    sc      success,storeval,0(alignedaddr)
1932   //    beq     success,$0,loop1MBB
1933   BB = loop2MBB;
1934   BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1935     .addReg(OldVal).addReg(Mask2);
1936   BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1937     .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1938   BuildMI(BB, DL, TII->get(SC), Success)
1939       .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1940   BuildMI(BB, DL, TII->get(Mips::BEQ))
1941       .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1942 
1943   //  sinkMBB:
1944   //    srl     srlres,maskedoldval0,shiftamt
1945   //    sign_extend dest,srlres
1946   BB = sinkMBB;
1947 
1948   BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1949       .addReg(MaskedOldVal0).addReg(ShiftAmt);
1950   BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1951 
1952   MI.eraseFromParent(); // The instruction is gone now.
1953 
1954   return exitMBB;
1955 }
1956 
1957 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1958   // The first operand is the chain, the second is the condition, the third is
1959   // the block to branch to if the condition is true.
1960   SDValue Chain = Op.getOperand(0);
1961   SDValue Dest = Op.getOperand(2);
1962   SDLoc DL(Op);
1963 
1964   assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1965   SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1966 
1967   // Return if flag is not set by a floating point comparison.
1968   if (CondRes.getOpcode() != MipsISD::FPCmp)
1969     return Op;
1970 
1971   SDValue CCNode  = CondRes.getOperand(2);
1972   Mips::CondCode CC =
1973     (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1974   unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1975   SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
1976   SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1977   return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1978                      FCC0, Dest, CondRes);
1979 }
1980 
1981 SDValue MipsTargetLowering::
1982 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1983 {
1984   assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1985   SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1986 
1987   // Return if flag is not set by a floating point comparison.
1988   if (Cond.getOpcode() != MipsISD::FPCmp)
1989     return Op;
1990 
1991   return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1992                       SDLoc(Op));
1993 }
1994 
1995 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1996   assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1997   SDValue Cond = createFPCmp(DAG, Op);
1998 
1999   assert(Cond.getOpcode() == MipsISD::FPCmp &&
2000          "Floating point operand expected.");
2001 
2002   SDLoc DL(Op);
2003   SDValue True  = DAG.getConstant(1, DL, MVT::i32);
2004   SDValue False = DAG.getConstant(0, DL, MVT::i32);
2005 
2006   return createCMovFP(DAG, Cond, True, False, DL);
2007 }
2008 
2009 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
2010                                                SelectionDAG &DAG) const {
2011   EVT Ty = Op.getValueType();
2012   GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
2013   const GlobalValue *GV = N->getGlobal();
2014 
2015   if (!isPositionIndependent()) {
2016     const MipsTargetObjectFile *TLOF =
2017         static_cast<const MipsTargetObjectFile *>(
2018             getTargetMachine().getObjFileLowering());
2019     const GlobalObject *GO = GV->getBaseObject();
2020     if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine()))
2021       // %gp_rel relocation
2022       return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
2023 
2024                                  // %hi/%lo relocation
2025     return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2026                                  // %highest/%higher/%hi/%lo relocation
2027                                  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2028   }
2029 
2030   // Every other architecture would use shouldAssumeDSOLocal in here, but
2031   // mips is special.
2032   // * In PIC code mips requires got loads even for local statics!
2033   // * To save on got entries, for local statics the got entry contains the
2034   //   page and an additional add instruction takes care of the low bits.
2035   // * It is legal to access a hidden symbol with a non hidden undefined,
2036   //   so one cannot guarantee that all access to a hidden symbol will know
2037   //   it is hidden.
2038   // * Mips linkers don't support creating a page and a full got entry for
2039   //   the same symbol.
2040   // * Given all that, we have to use a full got entry for hidden symbols :-(
2041   if (GV->hasLocalLinkage())
2042     return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2043 
2044   if (LargeGOT)
2045     return getAddrGlobalLargeGOT(
2046         N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16,
2047         DAG.getEntryNode(),
2048         MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2049 
2050   return getAddrGlobal(
2051       N, SDLoc(N), Ty, DAG,
2052       (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT,
2053       DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2054 }
2055 
2056 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
2057                                               SelectionDAG &DAG) const {
2058   BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
2059   EVT Ty = Op.getValueType();
2060 
2061   if (!isPositionIndependent())
2062     return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2063                                 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2064 
2065   return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2066 }
2067 
2068 SDValue MipsTargetLowering::
2069 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
2070 {
2071   // If the relocation model is PIC, use the General Dynamic TLS Model or
2072   // Local Dynamic TLS model, otherwise use the Initial Exec or
2073   // Local Exec TLS Model.
2074 
2075   GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2076   if (DAG.getTarget().Options.EmulatedTLS)
2077     return LowerToTLSEmulatedModel(GA, DAG);
2078 
2079   SDLoc DL(GA);
2080   const GlobalValue *GV = GA->getGlobal();
2081   EVT PtrVT = getPointerTy(DAG.getDataLayout());
2082 
2083   TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2084 
2085   if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2086     // General Dynamic and Local Dynamic TLS Model.
2087     unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
2088                                                       : MipsII::MO_TLSGD;
2089 
2090     SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
2091     SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
2092                                    getGlobalReg(DAG, PtrVT), TGA);
2093     unsigned PtrSize = PtrVT.getSizeInBits();
2094     IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
2095 
2096     SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
2097 
2098     ArgListTy Args;
2099     ArgListEntry Entry;
2100     Entry.Node = Argument;
2101     Entry.Ty = PtrTy;
2102     Args.push_back(Entry);
2103 
2104     TargetLowering::CallLoweringInfo CLI(DAG);
2105     CLI.setDebugLoc(DL)
2106         .setChain(DAG.getEntryNode())
2107         .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
2108     std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2109 
2110     SDValue Ret = CallResult.first;
2111 
2112     if (model != TLSModel::LocalDynamic)
2113       return Ret;
2114 
2115     SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2116                                                MipsII::MO_DTPREL_HI);
2117     SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
2118     SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2119                                                MipsII::MO_DTPREL_LO);
2120     SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2121     SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
2122     return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
2123   }
2124 
2125   SDValue Offset;
2126   if (model == TLSModel::InitialExec) {
2127     // Initial Exec TLS Model
2128     SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2129                                              MipsII::MO_GOTTPREL);
2130     TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
2131                       TGA);
2132     Offset =
2133         DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo());
2134   } else {
2135     // Local Exec TLS Model
2136     assert(model == TLSModel::LocalExec);
2137     SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2138                                                MipsII::MO_TPREL_HI);
2139     SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2140                                                MipsII::MO_TPREL_LO);
2141     SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
2142     SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2143     Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2144   }
2145 
2146   SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
2147   return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
2148 }
2149 
2150 SDValue MipsTargetLowering::
2151 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
2152 {
2153   JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
2154   EVT Ty = Op.getValueType();
2155 
2156   if (!isPositionIndependent())
2157     return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2158                                 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2159 
2160   return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2161 }
2162 
2163 SDValue MipsTargetLowering::
2164 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
2165 {
2166   ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
2167   EVT Ty = Op.getValueType();
2168 
2169   if (!isPositionIndependent()) {
2170     const MipsTargetObjectFile *TLOF =
2171         static_cast<const MipsTargetObjectFile *>(
2172             getTargetMachine().getObjFileLowering());
2173 
2174     if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
2175                                        getTargetMachine()))
2176       // %gp_rel relocation
2177       return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
2178 
2179     return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2180                                 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2181   }
2182 
2183  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2184 }
2185 
2186 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2187   MachineFunction &MF = DAG.getMachineFunction();
2188   MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2189 
2190   SDLoc DL(Op);
2191   SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2192                                  getPointerTy(MF.getDataLayout()));
2193 
2194   // vastart just stores the address of the VarArgsFrameIndex slot into the
2195   // memory location argument.
2196   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2197   return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
2198                       MachinePointerInfo(SV));
2199 }
2200 
2201 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2202   SDNode *Node = Op.getNode();
2203   EVT VT = Node->getValueType(0);
2204   SDValue Chain = Node->getOperand(0);
2205   SDValue VAListPtr = Node->getOperand(1);
2206   unsigned Align = Node->getConstantOperandVal(3);
2207   const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2208   SDLoc DL(Node);
2209   unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
2210 
2211   SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain,
2212                                    VAListPtr, MachinePointerInfo(SV));
2213   SDValue VAList = VAListLoad;
2214 
2215   // Re-align the pointer if necessary.
2216   // It should only ever be necessary for 64-bit types on O32 since the minimum
2217   // argument alignment is the same as the maximum type alignment for N32/N64.
2218   //
2219   // FIXME: We currently align too often. The code generator doesn't notice
2220   //        when the pointer is still aligned from the last va_arg (or pair of
2221   //        va_args for the i64 on O32 case).
2222   if (Align > getMinStackArgumentAlignment()) {
2223     assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2224 
2225     VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2226                          DAG.getConstant(Align - 1, DL, VAList.getValueType()));
2227 
2228     VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
2229                          DAG.getConstant(-(int64_t)Align, DL,
2230                                          VAList.getValueType()));
2231   }
2232 
2233   // Increment the pointer, VAList, to the next vaarg.
2234   auto &TD = DAG.getDataLayout();
2235   unsigned ArgSizeInBytes =
2236       TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
2237   SDValue Tmp3 =
2238       DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2239                   DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes),
2240                                   DL, VAList.getValueType()));
2241   // Store the incremented VAList to the legalized pointer
2242   Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
2243                        MachinePointerInfo(SV));
2244 
2245   // In big-endian mode we must adjust the pointer when the load size is smaller
2246   // than the argument slot size. We must also reduce the known alignment to
2247   // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
2248   // the correct half of the slot, and reduce the alignment from 8 (slot
2249   // alignment) down to 4 (type alignment).
2250   if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
2251     unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
2252     VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
2253                          DAG.getIntPtrConstant(Adjustment, DL));
2254   }
2255   // Load the actual argument out of the pointer VAList
2256   return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo());
2257 }
2258 
2259 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
2260                                 bool HasExtractInsert) {
2261   EVT TyX = Op.getOperand(0).getValueType();
2262   EVT TyY = Op.getOperand(1).getValueType();
2263   SDLoc DL(Op);
2264   SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2265   SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
2266   SDValue Res;
2267 
2268   // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2269   // to i32.
2270   SDValue X = (TyX == MVT::f32) ?
2271     DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2272     DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2273                 Const1);
2274   SDValue Y = (TyY == MVT::f32) ?
2275     DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2276     DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
2277                 Const1);
2278 
2279   if (HasExtractInsert) {
2280     // ext  E, Y, 31, 1  ; extract bit31 of Y
2281     // ins  X, E, 31, 1  ; insert extracted bit at bit31 of X
2282     SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2283     Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2284   } else {
2285     // sll SllX, X, 1
2286     // srl SrlX, SllX, 1
2287     // srl SrlY, Y, 31
2288     // sll SllY, SrlX, 31
2289     // or  Or, SrlX, SllY
2290     SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2291     SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2292     SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2293     SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2294     Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2295   }
2296 
2297   if (TyX == MVT::f32)
2298     return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2299 
2300   SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2301                              Op.getOperand(0),
2302                              DAG.getConstant(0, DL, MVT::i32));
2303   return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2304 }
2305 
2306 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
2307                                 bool HasExtractInsert) {
2308   unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2309   unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2310   EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2311   SDLoc DL(Op);
2312   SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2313 
2314   // Bitcast to integer nodes.
2315   SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2316   SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2317 
2318   if (HasExtractInsert) {
2319     // ext  E, Y, width(Y) - 1, 1  ; extract bit width(Y)-1 of Y
2320     // ins  X, E, width(X) - 1, 1  ; insert extracted bit at bit width(X)-1 of X
2321     SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2322                             DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
2323 
2324     if (WidthX > WidthY)
2325       E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2326     else if (WidthY > WidthX)
2327       E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2328 
2329     SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2330                             DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
2331                             X);
2332     return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2333   }
2334 
2335   // (d)sll SllX, X, 1
2336   // (d)srl SrlX, SllX, 1
2337   // (d)srl SrlY, Y, width(Y)-1
2338   // (d)sll SllY, SrlX, width(Y)-1
2339   // or     Or, SrlX, SllY
2340   SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2341   SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2342   SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2343                              DAG.getConstant(WidthY - 1, DL, MVT::i32));
2344 
2345   if (WidthX > WidthY)
2346     SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2347   else if (WidthY > WidthX)
2348     SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2349 
2350   SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2351                              DAG.getConstant(WidthX - 1, DL, MVT::i32));
2352   SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2353   return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2354 }
2355 
2356 SDValue
2357 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2358   if (Subtarget.isGP64bit())
2359     return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
2360 
2361   return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
2362 }
2363 
2364 SDValue MipsTargetLowering::
2365 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2366   // check the depth
2367   assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2368          "Frame address can only be determined for current frame.");
2369 
2370   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2371   MFI.setFrameAddressIsTaken(true);
2372   EVT VT = Op.getValueType();
2373   SDLoc DL(Op);
2374   SDValue FrameAddr = DAG.getCopyFromReg(
2375       DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
2376   return FrameAddr;
2377 }
2378 
2379 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2380                                             SelectionDAG &DAG) const {
2381   if (verifyReturnAddressArgumentIsConstant(Op, DAG))
2382     return SDValue();
2383 
2384   // check the depth
2385   assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2386          "Return address can be determined only for current frame.");
2387 
2388   MachineFunction &MF = DAG.getMachineFunction();
2389   MachineFrameInfo &MFI = MF.getFrameInfo();
2390   MVT VT = Op.getSimpleValueType();
2391   unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2392   MFI.setReturnAddressIsTaken(true);
2393 
2394   // Return RA, which contains the return address. Mark it an implicit live-in.
2395   unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2396   return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2397 }
2398 
2399 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2400 // generated from __builtin_eh_return (offset, handler)
2401 // The effect of this is to adjust the stack pointer by "offset"
2402 // and then branch to "handler".
2403 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2404                                                                      const {
2405   MachineFunction &MF = DAG.getMachineFunction();
2406   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2407 
2408   MipsFI->setCallsEhReturn();
2409   SDValue Chain     = Op.getOperand(0);
2410   SDValue Offset    = Op.getOperand(1);
2411   SDValue Handler   = Op.getOperand(2);
2412   SDLoc DL(Op);
2413   EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2414 
2415   // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2416   // EH_RETURN nodes, so that instructions are emitted back-to-back.
2417   unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2418   unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2419   Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2420   Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2421   return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2422                      DAG.getRegister(OffsetReg, Ty),
2423                      DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
2424                      Chain.getValue(1));
2425 }
2426 
2427 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2428                                               SelectionDAG &DAG) const {
2429   // FIXME: Need pseudo-fence for 'singlethread' fences
2430   // FIXME: Set SType for weaker fences where supported/appropriate.
2431   unsigned SType = 0;
2432   SDLoc DL(Op);
2433   return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2434                      DAG.getConstant(SType, DL, MVT::i32));
2435 }
2436 
2437 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2438                                                 SelectionDAG &DAG) const {
2439   SDLoc DL(Op);
2440   MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2441 
2442   SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2443   SDValue Shamt = Op.getOperand(2);
2444   // if shamt < (VT.bits):
2445   //  lo = (shl lo, shamt)
2446   //  hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2447   // else:
2448   //  lo = 0
2449   //  hi = (shl lo, shamt[4:0])
2450   SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2451                             DAG.getConstant(-1, DL, MVT::i32));
2452   SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2453                                       DAG.getConstant(1, DL, VT));
2454   SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2455   SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2456   SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2457   SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2458   SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2459                              DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2460   Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2461                    DAG.getConstant(0, DL, VT), ShiftLeftLo);
2462   Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2463 
2464   SDValue Ops[2] = {Lo, Hi};
2465   return DAG.getMergeValues(Ops, DL);
2466 }
2467 
2468 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2469                                                  bool IsSRA) const {
2470   SDLoc DL(Op);
2471   SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2472   SDValue Shamt = Op.getOperand(2);
2473   MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2474 
2475   // if shamt < (VT.bits):
2476   //  lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2477   //  if isSRA:
2478   //    hi = (sra hi, shamt)
2479   //  else:
2480   //    hi = (srl hi, shamt)
2481   // else:
2482   //  if isSRA:
2483   //   lo = (sra hi, shamt[4:0])
2484   //   hi = (sra hi, 31)
2485   //  else:
2486   //   lo = (srl hi, shamt[4:0])
2487   //   hi = 0
2488   SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2489                             DAG.getConstant(-1, DL, MVT::i32));
2490   SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2491                                      DAG.getConstant(1, DL, VT));
2492   SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2493   SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2494   SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2495   SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2496                                      DL, VT, Hi, Shamt);
2497   SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2498                              DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2499   SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2500                             DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
2501   Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2502   Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2503                    IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
2504 
2505   SDValue Ops[2] = {Lo, Hi};
2506   return DAG.getMergeValues(Ops, DL);
2507 }
2508 
2509 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2510                             SDValue Chain, SDValue Src, unsigned Offset) {
2511   SDValue Ptr = LD->getBasePtr();
2512   EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2513   EVT BasePtrVT = Ptr.getValueType();
2514   SDLoc DL(LD);
2515   SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2516 
2517   if (Offset)
2518     Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2519                       DAG.getConstant(Offset, DL, BasePtrVT));
2520 
2521   SDValue Ops[] = { Chain, Ptr, Src };
2522   return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2523                                  LD->getMemOperand());
2524 }
2525 
2526 // Expand an unaligned 32 or 64-bit integer load node.
2527 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2528   LoadSDNode *LD = cast<LoadSDNode>(Op);
2529   EVT MemVT = LD->getMemoryVT();
2530 
2531   if (Subtarget.systemSupportsUnalignedAccess())
2532     return Op;
2533 
2534   // Return if load is aligned or if MemVT is neither i32 nor i64.
2535   if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2536       ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2537     return SDValue();
2538 
2539   bool IsLittle = Subtarget.isLittle();
2540   EVT VT = Op.getValueType();
2541   ISD::LoadExtType ExtType = LD->getExtensionType();
2542   SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2543 
2544   assert((VT == MVT::i32) || (VT == MVT::i64));
2545 
2546   // Expand
2547   //  (set dst, (i64 (load baseptr)))
2548   // to
2549   //  (set tmp, (ldl (add baseptr, 7), undef))
2550   //  (set dst, (ldr baseptr, tmp))
2551   if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2552     SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2553                                IsLittle ? 7 : 0);
2554     return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2555                         IsLittle ? 0 : 7);
2556   }
2557 
2558   SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2559                              IsLittle ? 3 : 0);
2560   SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2561                              IsLittle ? 0 : 3);
2562 
2563   // Expand
2564   //  (set dst, (i32 (load baseptr))) or
2565   //  (set dst, (i64 (sextload baseptr))) or
2566   //  (set dst, (i64 (extload baseptr)))
2567   // to
2568   //  (set tmp, (lwl (add baseptr, 3), undef))
2569   //  (set dst, (lwr baseptr, tmp))
2570   if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2571       (ExtType == ISD::EXTLOAD))
2572     return LWR;
2573 
2574   assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2575 
2576   // Expand
2577   //  (set dst, (i64 (zextload baseptr)))
2578   // to
2579   //  (set tmp0, (lwl (add baseptr, 3), undef))
2580   //  (set tmp1, (lwr baseptr, tmp0))
2581   //  (set tmp2, (shl tmp1, 32))
2582   //  (set dst, (srl tmp2, 32))
2583   SDLoc DL(LD);
2584   SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
2585   SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2586   SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2587   SDValue Ops[] = { SRL, LWR.getValue(1) };
2588   return DAG.getMergeValues(Ops, DL);
2589 }
2590 
2591 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2592                              SDValue Chain, unsigned Offset) {
2593   SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2594   EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2595   SDLoc DL(SD);
2596   SDVTList VTList = DAG.getVTList(MVT::Other);
2597 
2598   if (Offset)
2599     Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2600                       DAG.getConstant(Offset, DL, BasePtrVT));
2601 
2602   SDValue Ops[] = { Chain, Value, Ptr };
2603   return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2604                                  SD->getMemOperand());
2605 }
2606 
2607 // Expand an unaligned 32 or 64-bit integer store node.
2608 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2609                                       bool IsLittle) {
2610   SDValue Value = SD->getValue(), Chain = SD->getChain();
2611   EVT VT = Value.getValueType();
2612 
2613   // Expand
2614   //  (store val, baseptr) or
2615   //  (truncstore val, baseptr)
2616   // to
2617   //  (swl val, (add baseptr, 3))
2618   //  (swr val, baseptr)
2619   if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2620     SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2621                                 IsLittle ? 3 : 0);
2622     return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2623   }
2624 
2625   assert(VT == MVT::i64);
2626 
2627   // Expand
2628   //  (store val, baseptr)
2629   // to
2630   //  (sdl val, (add baseptr, 7))
2631   //  (sdr val, baseptr)
2632   SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2633   return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2634 }
2635 
2636 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2637 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
2638   SDValue Val = SD->getValue();
2639 
2640   if (Val.getOpcode() != ISD::FP_TO_SINT)
2641     return SDValue();
2642 
2643   EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2644   SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2645                            Val.getOperand(0));
2646   return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2647                       SD->getPointerInfo(), SD->getAlignment(),
2648                       SD->getMemOperand()->getFlags());
2649 }
2650 
2651 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2652   StoreSDNode *SD = cast<StoreSDNode>(Op);
2653   EVT MemVT = SD->getMemoryVT();
2654 
2655   // Lower unaligned integer stores.
2656   if (!Subtarget.systemSupportsUnalignedAccess() &&
2657       (SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2658       ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2659     return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2660 
2661   return lowerFP_TO_SINT_STORE(SD, DAG);
2662 }
2663 
2664 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
2665                                               SelectionDAG &DAG) const {
2666 
2667   // Return a fixed StackObject with offset 0 which points to the old stack
2668   // pointer.
2669   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2670   EVT ValTy = Op->getValueType(0);
2671   int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2672   return DAG.getFrameIndex(FI, ValTy);
2673 }
2674 
2675 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2676                                             SelectionDAG &DAG) const {
2677   EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2678   SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2679                               Op.getOperand(0));
2680   return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2681 }
2682 
2683 //===----------------------------------------------------------------------===//
2684 //                      Calling Convention Implementation
2685 //===----------------------------------------------------------------------===//
2686 
2687 //===----------------------------------------------------------------------===//
2688 // TODO: Implement a generic logic using tblgen that can support this.
2689 // Mips O32 ABI rules:
2690 // ---
2691 // i32 - Passed in A0, A1, A2, A3 and stack
2692 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2693 //       an argument. Otherwise, passed in A1, A2, A3 and stack.
2694 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2695 //       yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2696 //       not used, it must be shadowed. If only A3 is available, shadow it and
2697 //       go to stack.
2698 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack.
2699 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3}
2700 //         with the remainder spilled to the stack.
2701 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases
2702 //         spilling the remainder to the stack.
2703 //
2704 //  For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2705 //===----------------------------------------------------------------------===//
2706 
2707 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2708                        CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2709                        CCState &State, ArrayRef<MCPhysReg> F64Regs) {
2710   const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
2711       State.getMachineFunction().getSubtarget());
2712 
2713   static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2714 
2715   const MipsCCState * MipsState = static_cast<MipsCCState *>(&State);
2716 
2717   static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2718 
2719   static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
2720 
2721   // Do not process byval args here.
2722   if (ArgFlags.isByVal())
2723     return true;
2724 
2725   // Promote i8 and i16
2726   if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2727     if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2728       LocVT = MVT::i32;
2729       if (ArgFlags.isSExt())
2730         LocInfo = CCValAssign::SExtUpper;
2731       else if (ArgFlags.isZExt())
2732         LocInfo = CCValAssign::ZExtUpper;
2733       else
2734         LocInfo = CCValAssign::AExtUpper;
2735     }
2736   }
2737 
2738   // Promote i8 and i16
2739   if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2740     LocVT = MVT::i32;
2741     if (ArgFlags.isSExt())
2742       LocInfo = CCValAssign::SExt;
2743     else if (ArgFlags.isZExt())
2744       LocInfo = CCValAssign::ZExt;
2745     else
2746       LocInfo = CCValAssign::AExt;
2747   }
2748 
2749   unsigned Reg;
2750 
2751   // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2752   // is true: function is vararg, argument is 3rd or higher, there is previous
2753   // argument which is not f32 or f64.
2754   bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 ||
2755                                 State.getFirstUnallocated(F32Regs) != ValNo;
2756   unsigned OrigAlign = ArgFlags.getOrigAlign();
2757   bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2758   bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo);
2759 
2760   // The MIPS vector ABI for floats passes them in a pair of registers
2761   if (ValVT == MVT::i32 && isVectorFloat) {
2762     // This is the start of an vector that was scalarized into an unknown number
2763     // of components. It doesn't matter how many there are. Allocate one of the
2764     // notional 8 byte aligned registers which map onto the argument stack, and
2765     // shadow the register lost to alignment requirements.
2766     if (ArgFlags.isSplit()) {
2767       Reg = State.AllocateReg(FloatVectorIntRegs);
2768       if (Reg == Mips::A2)
2769         State.AllocateReg(Mips::A1);
2770       else if (Reg == 0)
2771         State.AllocateReg(Mips::A3);
2772     } else {
2773       // If we're an intermediate component of the split, we can just attempt to
2774       // allocate a register directly.
2775       Reg = State.AllocateReg(IntRegs);
2776     }
2777   } else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2778     Reg = State.AllocateReg(IntRegs);
2779     // If this is the first part of an i64 arg,
2780     // the allocated register must be either A0 or A2.
2781     if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2782       Reg = State.AllocateReg(IntRegs);
2783     LocVT = MVT::i32;
2784   } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2785     // Allocate int register and shadow next int register. If first
2786     // available register is Mips::A1 or Mips::A3, shadow it too.
2787     Reg = State.AllocateReg(IntRegs);
2788     if (Reg == Mips::A1 || Reg == Mips::A3)
2789       Reg = State.AllocateReg(IntRegs);
2790     State.AllocateReg(IntRegs);
2791     LocVT = MVT::i32;
2792   } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2793     // we are guaranteed to find an available float register
2794     if (ValVT == MVT::f32) {
2795       Reg = State.AllocateReg(F32Regs);
2796       // Shadow int register
2797       State.AllocateReg(IntRegs);
2798     } else {
2799       Reg = State.AllocateReg(F64Regs);
2800       // Shadow int registers
2801       unsigned Reg2 = State.AllocateReg(IntRegs);
2802       if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2803         State.AllocateReg(IntRegs);
2804       State.AllocateReg(IntRegs);
2805     }
2806   } else
2807     llvm_unreachable("Cannot handle this ValVT.");
2808 
2809   if (!Reg) {
2810     unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign);
2811     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2812   } else
2813     State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2814 
2815   return false;
2816 }
2817 
2818 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2819                             MVT LocVT, CCValAssign::LocInfo LocInfo,
2820                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
2821   static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2822 
2823   return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2824 }
2825 
2826 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2827                             MVT LocVT, CCValAssign::LocInfo LocInfo,
2828                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
2829   static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2830 
2831   return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2832 }
2833 
2834 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2835                        CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2836                        CCState &State) LLVM_ATTRIBUTE_UNUSED;
2837 
2838 #include "MipsGenCallingConv.inc"
2839 
2840 //===----------------------------------------------------------------------===//
2841 //                  Call Calling Convention Implementation
2842 //===----------------------------------------------------------------------===//
2843 
2844 // Return next O32 integer argument register.
2845 static unsigned getNextIntArgReg(unsigned Reg) {
2846   assert((Reg == Mips::A0) || (Reg == Mips::A2));
2847   return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2848 }
2849 
2850 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2851                                            SDValue Chain, SDValue Arg,
2852                                            const SDLoc &DL, bool IsTailCall,
2853                                            SelectionDAG &DAG) const {
2854   if (!IsTailCall) {
2855     SDValue PtrOff =
2856         DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
2857                     DAG.getIntPtrConstant(Offset, DL));
2858     return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo());
2859   }
2860 
2861   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2862   int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2863   SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2864   return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2865                       /* Alignment = */ 0, MachineMemOperand::MOVolatile);
2866 }
2867 
2868 void MipsTargetLowering::
2869 getOpndList(SmallVectorImpl<SDValue> &Ops,
2870             std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
2871             bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2872             bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
2873             SDValue Chain) const {
2874   // Insert node "GP copy globalreg" before call to function.
2875   //
2876   // R_MIPS_CALL* operators (emitted when non-internal functions are called
2877   // in PIC mode) allow symbols to be resolved via lazy binding.
2878   // The lazy binding stub requires GP to point to the GOT.
2879   // Note that we don't need GP to point to the GOT for indirect calls
2880   // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
2881   // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
2882   // used for the function (that is, Mips linker doesn't generate lazy binding
2883   // stub for a function whose address is taken in the program).
2884   if (IsPICCall && !InternalLinkage && IsCallReloc) {
2885     unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
2886     EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2887     RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2888   }
2889 
2890   // Build a sequence of copy-to-reg nodes chained together with token
2891   // chain and flag operands which copy the outgoing args into registers.
2892   // The InFlag in necessary since all emitted instructions must be
2893   // stuck together.
2894   SDValue InFlag;
2895 
2896   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2897     Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2898                                  RegsToPass[i].second, InFlag);
2899     InFlag = Chain.getValue(1);
2900   }
2901 
2902   // Add argument registers to the end of the list so that they are
2903   // known live into the call.
2904   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2905     Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2906                                       RegsToPass[i].second.getValueType()));
2907 
2908   // Add a register mask operand representing the call-preserved registers.
2909   const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2910   const uint32_t *Mask =
2911       TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv);
2912   assert(Mask && "Missing call preserved mask for calling convention");
2913   if (Subtarget.inMips16HardFloat()) {
2914     if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2915       StringRef Sym = G->getGlobal()->getName();
2916       Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2917       if (F && F->hasFnAttribute("__Mips16RetHelper")) {
2918         Mask = MipsRegisterInfo::getMips16RetHelperMask();
2919       }
2920     }
2921   }
2922   Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2923 
2924   if (InFlag.getNode())
2925     Ops.push_back(InFlag);
2926 }
2927 
2928 /// LowerCall - functions arguments are copied from virtual regs to
2929 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2930 SDValue
2931 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2932                               SmallVectorImpl<SDValue> &InVals) const {
2933   SelectionDAG &DAG                     = CLI.DAG;
2934   SDLoc DL                              = CLI.DL;
2935   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2936   SmallVectorImpl<SDValue> &OutVals     = CLI.OutVals;
2937   SmallVectorImpl<ISD::InputArg> &Ins   = CLI.Ins;
2938   SDValue Chain                         = CLI.Chain;
2939   SDValue Callee                        = CLI.Callee;
2940   bool &IsTailCall                      = CLI.IsTailCall;
2941   CallingConv::ID CallConv              = CLI.CallConv;
2942   bool IsVarArg                         = CLI.IsVarArg;
2943 
2944   MachineFunction &MF = DAG.getMachineFunction();
2945   MachineFrameInfo &MFI = MF.getFrameInfo();
2946   const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
2947   MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2948   bool IsPIC = isPositionIndependent();
2949 
2950   // Analyze operands of the call, assigning locations to each operand.
2951   SmallVector<CCValAssign, 16> ArgLocs;
2952   MipsCCState CCInfo(
2953       CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
2954       MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget));
2955 
2956   // Allocate the reserved argument area. It seems strange to do this from the
2957   // caller side but removing it breaks the frame size calculation.
2958   CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
2959 
2960   const ExternalSymbolSDNode *ES =
2961       dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode());
2962   CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(),
2963                              ES ? ES->getSymbol() : nullptr);
2964 
2965   // Get a count of how many bytes are to be pushed on the stack.
2966   unsigned NextStackOffset = CCInfo.getNextStackOffset();
2967 
2968   // Check if it's really possible to do a tail call. Restrict it to functions
2969   // that are part of this compilation unit.
2970   bool InternalLinkage = false;
2971   if (IsTailCall) {
2972     IsTailCall = isEligibleForTailCallOptimization(
2973         CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
2974      if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2975       InternalLinkage = G->getGlobal()->hasInternalLinkage();
2976       IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() ||
2977                      G->getGlobal()->hasPrivateLinkage() ||
2978                      G->getGlobal()->hasHiddenVisibility() ||
2979                      G->getGlobal()->hasProtectedVisibility());
2980      }
2981   }
2982   if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall())
2983     report_fatal_error("failed to perform tail call elimination on a call "
2984                        "site marked musttail");
2985 
2986   if (IsTailCall)
2987     ++NumTailCalls;
2988 
2989   // Chain is the output chain of the last Load/Store or CopyToReg node.
2990   // ByValChain is the output chain of the last Memcpy node created for copying
2991   // byval arguments to the stack.
2992   unsigned StackAlignment = TFL->getStackAlignment();
2993   NextStackOffset = alignTo(NextStackOffset, StackAlignment);
2994   SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
2995 
2996   if (!IsTailCall)
2997     Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
2998 
2999   SDValue StackPtr =
3000       DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
3001                          getPointerTy(DAG.getDataLayout()));
3002 
3003   std::deque<std::pair<unsigned, SDValue>> RegsToPass;
3004   SmallVector<SDValue, 8> MemOpChains;
3005 
3006   CCInfo.rewindByValRegsInfo();
3007 
3008   // Walk the register/memloc assignments, inserting copies/loads.
3009   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3010     SDValue Arg = OutVals[i];
3011     CCValAssign &VA = ArgLocs[i];
3012     MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
3013     ISD::ArgFlagsTy Flags = Outs[i].Flags;
3014     bool UseUpperBits = false;
3015 
3016     // ByVal Arg.
3017     if (Flags.isByVal()) {
3018       unsigned FirstByValReg, LastByValReg;
3019       unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3020       CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3021 
3022       assert(Flags.getByValSize() &&
3023              "ByVal args of size 0 should have been ignored by front-end.");
3024       assert(ByValIdx < CCInfo.getInRegsParamsCount());
3025       assert(!IsTailCall &&
3026              "Do not tail-call optimize if there is a byval argument.");
3027       passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3028                    FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
3029                    VA);
3030       CCInfo.nextInRegsParam();
3031       continue;
3032     }
3033 
3034     // Promote the value if needed.
3035     switch (VA.getLocInfo()) {
3036     default:
3037       llvm_unreachable("Unknown loc info!");
3038     case CCValAssign::Full:
3039       if (VA.isRegLoc()) {
3040         if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3041             (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3042             (ValVT == MVT::i64 && LocVT == MVT::f64))
3043           Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3044         else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3045           SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
3046                                    Arg, DAG.getConstant(0, DL, MVT::i32));
3047           SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
3048                                    Arg, DAG.getConstant(1, DL, MVT::i32));
3049           if (!Subtarget.isLittle())
3050             std::swap(Lo, Hi);
3051           unsigned LocRegLo = VA.getLocReg();
3052           unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
3053           RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
3054           RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
3055           continue;
3056         }
3057       }
3058       break;
3059     case CCValAssign::BCvt:
3060       Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3061       break;
3062     case CCValAssign::SExtUpper:
3063       UseUpperBits = true;
3064       LLVM_FALLTHROUGH;
3065     case CCValAssign::SExt:
3066       Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
3067       break;
3068     case CCValAssign::ZExtUpper:
3069       UseUpperBits = true;
3070       LLVM_FALLTHROUGH;
3071     case CCValAssign::ZExt:
3072       Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
3073       break;
3074     case CCValAssign::AExtUpper:
3075       UseUpperBits = true;
3076       LLVM_FALLTHROUGH;
3077     case CCValAssign::AExt:
3078       Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
3079       break;
3080     }
3081 
3082     if (UseUpperBits) {
3083       unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3084       unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3085       Arg = DAG.getNode(
3086           ISD::SHL, DL, VA.getLocVT(), Arg,
3087           DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3088     }
3089 
3090     // Arguments that can be passed on register must be kept at
3091     // RegsToPass vector
3092     if (VA.isRegLoc()) {
3093       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3094       continue;
3095     }
3096 
3097     // Register can't get to this point...
3098     assert(VA.isMemLoc());
3099 
3100     // emit ISD::STORE whichs stores the
3101     // parameter value to a stack Location
3102     MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
3103                                          Chain, Arg, DL, IsTailCall, DAG));
3104   }
3105 
3106   // Transform all store nodes into one single node because all store
3107   // nodes are independent of each other.
3108   if (!MemOpChains.empty())
3109     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3110 
3111   // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3112   // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3113   // node so that legalize doesn't hack it.
3114 
3115   EVT Ty = Callee.getValueType();
3116   bool GlobalOrExternal = false, IsCallReloc = false;
3117 
3118   // The long-calls feature is ignored in case of PIC.
3119   // While we do not support -mshared / -mno-shared properly,
3120   // ignore long-calls in case of -mabicalls too.
3121   if (!Subtarget.isABICalls() && !IsPIC) {
3122     // If the function should be called using "long call",
3123     // get its address into a register to prevent using
3124     // of the `jal` instruction for the direct call.
3125     if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3126       if (Subtarget.useLongCalls())
3127         Callee = Subtarget.hasSym32()
3128                      ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3129                      : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3130     } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) {
3131       bool UseLongCalls = Subtarget.useLongCalls();
3132       // If the function has long-call/far/near attribute
3133       // it overrides command line switch pased to the backend.
3134       if (auto *F = dyn_cast<Function>(N->getGlobal())) {
3135         if (F->hasFnAttribute("long-call"))
3136           UseLongCalls = true;
3137         else if (F->hasFnAttribute("short-call"))
3138           UseLongCalls = false;
3139       }
3140       if (UseLongCalls)
3141         Callee = Subtarget.hasSym32()
3142                      ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3143                      : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3144     }
3145   }
3146 
3147   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3148     if (IsPIC) {
3149       const GlobalValue *Val = G->getGlobal();
3150       InternalLinkage = Val->hasInternalLinkage();
3151 
3152       if (InternalLinkage)
3153         Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64());
3154       else if (LargeGOT) {
3155         Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16,
3156                                        MipsII::MO_CALL_LO16, Chain,
3157                                        FuncInfo->callPtrInfo(Val));
3158         IsCallReloc = true;
3159       } else {
3160         Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3161                                FuncInfo->callPtrInfo(Val));
3162         IsCallReloc = true;
3163       }
3164     } else
3165       Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
3166                                           getPointerTy(DAG.getDataLayout()), 0,
3167                                           MipsII::MO_NO_FLAG);
3168     GlobalOrExternal = true;
3169   }
3170   else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3171     const char *Sym = S->getSymbol();
3172 
3173     if (!IsPIC) // static
3174       Callee = DAG.getTargetExternalSymbol(
3175           Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG);
3176     else if (LargeGOT) {
3177       Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
3178                                      MipsII::MO_CALL_LO16, Chain,
3179                                      FuncInfo->callPtrInfo(Sym));
3180       IsCallReloc = true;
3181     } else { // PIC
3182       Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3183                              FuncInfo->callPtrInfo(Sym));
3184       IsCallReloc = true;
3185     }
3186 
3187     GlobalOrExternal = true;
3188   }
3189 
3190   SmallVector<SDValue, 8> Ops(1, Chain);
3191   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3192 
3193   getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage,
3194               IsCallReloc, CLI, Callee, Chain);
3195 
3196   if (IsTailCall) {
3197     MF.getFrameInfo().setHasTailCall();
3198     return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
3199   }
3200 
3201   Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
3202   SDValue InFlag = Chain.getValue(1);
3203 
3204   // Create the CALLSEQ_END node.
3205   Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
3206                              DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
3207   InFlag = Chain.getValue(1);
3208 
3209   // Handle result values, copying them out of physregs into vregs that we
3210   // return.
3211   return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3212                          InVals, CLI);
3213 }
3214 
3215 /// LowerCallResult - Lower the result values of a call into the
3216 /// appropriate copies out of appropriate physical registers.
3217 SDValue MipsTargetLowering::LowerCallResult(
3218     SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
3219     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3220     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
3221     TargetLowering::CallLoweringInfo &CLI) const {
3222   // Assign locations to each value returned by this call.
3223   SmallVector<CCValAssign, 16> RVLocs;
3224   MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
3225                      *DAG.getContext());
3226 
3227   const ExternalSymbolSDNode *ES =
3228       dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode());
3229   CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy,
3230                            ES ? ES->getSymbol() : nullptr);
3231 
3232   // Copy all of the result registers out of their specified physreg.
3233   for (unsigned i = 0; i != RVLocs.size(); ++i) {
3234     CCValAssign &VA = RVLocs[i];
3235     assert(VA.isRegLoc() && "Can only return in registers!");
3236 
3237     SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
3238                                      RVLocs[i].getLocVT(), InFlag);
3239     Chain = Val.getValue(1);
3240     InFlag = Val.getValue(2);
3241 
3242     if (VA.isUpperBitsInLoc()) {
3243       unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
3244       unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3245       unsigned Shift =
3246           VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
3247       Val = DAG.getNode(
3248           Shift, DL, VA.getLocVT(), Val,
3249           DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3250     }
3251 
3252     switch (VA.getLocInfo()) {
3253     default:
3254       llvm_unreachable("Unknown loc info!");
3255     case CCValAssign::Full:
3256       break;
3257     case CCValAssign::BCvt:
3258       Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
3259       break;
3260     case CCValAssign::AExt:
3261     case CCValAssign::AExtUpper:
3262       Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3263       break;
3264     case CCValAssign::ZExt:
3265     case CCValAssign::ZExtUpper:
3266       Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
3267                         DAG.getValueType(VA.getValVT()));
3268       Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3269       break;
3270     case CCValAssign::SExt:
3271     case CCValAssign::SExtUpper:
3272       Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
3273                         DAG.getValueType(VA.getValVT()));
3274       Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3275       break;
3276     }
3277 
3278     InVals.push_back(Val);
3279   }
3280 
3281   return Chain;
3282 }
3283 
3284 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
3285                                       EVT ArgVT, const SDLoc &DL,
3286                                       SelectionDAG &DAG) {
3287   MVT LocVT = VA.getLocVT();
3288   EVT ValVT = VA.getValVT();
3289 
3290   // Shift into the upper bits if necessary.
3291   switch (VA.getLocInfo()) {
3292   default:
3293     break;
3294   case CCValAssign::AExtUpper:
3295   case CCValAssign::SExtUpper:
3296   case CCValAssign::ZExtUpper: {
3297     unsigned ValSizeInBits = ArgVT.getSizeInBits();
3298     unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3299     unsigned Opcode =
3300         VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
3301     Val = DAG.getNode(
3302         Opcode, DL, VA.getLocVT(), Val,
3303         DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3304     break;
3305   }
3306   }
3307 
3308   // If this is an value smaller than the argument slot size (32-bit for O32,
3309   // 64-bit for N32/N64), it has been promoted in some way to the argument slot
3310   // size. Extract the value and insert any appropriate assertions regarding
3311   // sign/zero extension.
3312   switch (VA.getLocInfo()) {
3313   default:
3314     llvm_unreachable("Unknown loc info!");
3315   case CCValAssign::Full:
3316     break;
3317   case CCValAssign::AExtUpper:
3318   case CCValAssign::AExt:
3319     Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3320     break;
3321   case CCValAssign::SExtUpper:
3322   case CCValAssign::SExt:
3323     Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
3324     Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3325     break;
3326   case CCValAssign::ZExtUpper:
3327   case CCValAssign::ZExt:
3328     Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
3329     Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3330     break;
3331   case CCValAssign::BCvt:
3332     Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
3333     break;
3334   }
3335 
3336   return Val;
3337 }
3338 
3339 //===----------------------------------------------------------------------===//
3340 //             Formal Arguments Calling Convention Implementation
3341 //===----------------------------------------------------------------------===//
3342 /// LowerFormalArguments - transform physical registers into virtual registers
3343 /// and generate load operations for arguments places on the stack.
3344 SDValue MipsTargetLowering::LowerFormalArguments(
3345     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
3346     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3347     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3348   MachineFunction &MF = DAG.getMachineFunction();
3349   MachineFrameInfo &MFI = MF.getFrameInfo();
3350   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3351 
3352   MipsFI->setVarArgsFrameIndex(0);
3353 
3354   // Used with vargs to acumulate store chains.
3355   std::vector<SDValue> OutChains;
3356 
3357   // Assign locations to all of the incoming arguments.
3358   SmallVector<CCValAssign, 16> ArgLocs;
3359   MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
3360                      *DAG.getContext());
3361   CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
3362   const Function &Func = DAG.getMachineFunction().getFunction();
3363   Function::const_arg_iterator FuncArg = Func.arg_begin();
3364 
3365   if (Func.hasFnAttribute("interrupt") && !Func.arg_empty())
3366     report_fatal_error(
3367         "Functions with the interrupt attribute cannot have arguments!");
3368 
3369   CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3370   MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
3371                            CCInfo.getInRegsParamsCount() > 0);
3372 
3373   unsigned CurArgIdx = 0;
3374   CCInfo.rewindByValRegsInfo();
3375 
3376   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3377     CCValAssign &VA = ArgLocs[i];
3378     if (Ins[i].isOrigArg()) {
3379       std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
3380       CurArgIdx = Ins[i].getOrigArgIndex();
3381     }
3382     EVT ValVT = VA.getValVT();
3383     ISD::ArgFlagsTy Flags = Ins[i].Flags;
3384     bool IsRegLoc = VA.isRegLoc();
3385 
3386     if (Flags.isByVal()) {
3387       assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit");
3388       unsigned FirstByValReg, LastByValReg;
3389       unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3390       CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3391 
3392       assert(Flags.getByValSize() &&
3393              "ByVal args of size 0 should have been ignored by front-end.");
3394       assert(ByValIdx < CCInfo.getInRegsParamsCount());
3395       copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3396                     FirstByValReg, LastByValReg, VA, CCInfo);
3397       CCInfo.nextInRegsParam();
3398       continue;
3399     }
3400 
3401     // Arguments stored on registers
3402     if (IsRegLoc) {
3403       MVT RegVT = VA.getLocVT();
3404       unsigned ArgReg = VA.getLocReg();
3405       const TargetRegisterClass *RC = getRegClassFor(RegVT);
3406 
3407       // Transform the arguments stored on
3408       // physical registers into virtual ones
3409       unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3410       SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3411 
3412       ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3413 
3414       // Handle floating point arguments passed in integer registers and
3415       // long double arguments passed in floating point registers.
3416       if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3417           (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3418           (RegVT == MVT::f64 && ValVT == MVT::i64))
3419         ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
3420       else if (ABI.IsO32() && RegVT == MVT::i32 &&
3421                ValVT == MVT::f64) {
3422         unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
3423                                   getNextIntArgReg(ArgReg), RC);
3424         SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3425         if (!Subtarget.isLittle())
3426           std::swap(ArgValue, ArgValue2);
3427         ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
3428                                ArgValue, ArgValue2);
3429       }
3430 
3431       InVals.push_back(ArgValue);
3432     } else { // VA.isRegLoc()
3433       MVT LocVT = VA.getLocVT();
3434 
3435       if (ABI.IsO32()) {
3436         // We ought to be able to use LocVT directly but O32 sets it to i32
3437         // when allocating floating point values to integer registers.
3438         // This shouldn't influence how we load the value into registers unless
3439         // we are targeting softfloat.
3440         if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat())
3441           LocVT = VA.getValVT();
3442       }
3443 
3444       // sanity check
3445       assert(VA.isMemLoc());
3446 
3447       // The stack pointer offset is relative to the caller stack frame.
3448       int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
3449                                      VA.getLocMemOffset(), true);
3450 
3451       // Create load nodes to retrieve arguments from the stack
3452       SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3453       SDValue ArgValue = DAG.getLoad(
3454           LocVT, DL, Chain, FIN,
3455           MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3456       OutChains.push_back(ArgValue.getValue(1));
3457 
3458       ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3459 
3460       InVals.push_back(ArgValue);
3461     }
3462   }
3463 
3464   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3465     // The mips ABIs for returning structs by value requires that we copy
3466     // the sret argument into $v0 for the return. Save the argument into
3467     // a virtual register so that we can access it from the return points.
3468     if (Ins[i].Flags.isSRet()) {
3469       unsigned Reg = MipsFI->getSRetReturnReg();
3470       if (!Reg) {
3471         Reg = MF.getRegInfo().createVirtualRegister(
3472             getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));
3473         MipsFI->setSRetReturnReg(Reg);
3474       }
3475       SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3476       Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3477       break;
3478     }
3479   }
3480 
3481   if (IsVarArg)
3482     writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3483 
3484   // All stores are grouped in one node to allow the matching between
3485   // the size of Ins and InVals. This only happens when on varg functions
3486   if (!OutChains.empty()) {
3487     OutChains.push_back(Chain);
3488     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3489   }
3490 
3491   return Chain;
3492 }
3493 
3494 //===----------------------------------------------------------------------===//
3495 //               Return Value Calling Convention Implementation
3496 //===----------------------------------------------------------------------===//
3497 
3498 bool
3499 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3500                                    MachineFunction &MF, bool IsVarArg,
3501                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
3502                                    LLVMContext &Context) const {
3503   SmallVector<CCValAssign, 16> RVLocs;
3504   MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3505   return CCInfo.CheckReturn(Outs, RetCC_Mips);
3506 }
3507 
3508 bool
3509 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
3510   if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32)
3511       return true;
3512 
3513   return IsSigned;
3514 }
3515 
3516 SDValue
3517 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3518                                          const SDLoc &DL,
3519                                          SelectionDAG &DAG) const {
3520   MachineFunction &MF = DAG.getMachineFunction();
3521   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3522 
3523   MipsFI->setISR();
3524 
3525   return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps);
3526 }
3527 
3528 SDValue
3529 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3530                                 bool IsVarArg,
3531                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
3532                                 const SmallVectorImpl<SDValue> &OutVals,
3533                                 const SDLoc &DL, SelectionDAG &DAG) const {
3534   // CCValAssign - represent the assignment of
3535   // the return value to a location
3536   SmallVector<CCValAssign, 16> RVLocs;
3537   MachineFunction &MF = DAG.getMachineFunction();
3538 
3539   // CCState - Info about the registers and stack slot.
3540   MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3541 
3542   // Analyze return values.
3543   CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3544 
3545   SDValue Flag;
3546   SmallVector<SDValue, 4> RetOps(1, Chain);
3547 
3548   // Copy the result values into the output registers.
3549   for (unsigned i = 0; i != RVLocs.size(); ++i) {
3550     SDValue Val = OutVals[i];
3551     CCValAssign &VA = RVLocs[i];
3552     assert(VA.isRegLoc() && "Can only return in registers!");
3553     bool UseUpperBits = false;
3554 
3555     switch (VA.getLocInfo()) {
3556     default:
3557       llvm_unreachable("Unknown loc info!");
3558     case CCValAssign::Full:
3559       break;
3560     case CCValAssign::BCvt:
3561       Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3562       break;
3563     case CCValAssign::AExtUpper:
3564       UseUpperBits = true;
3565       LLVM_FALLTHROUGH;
3566     case CCValAssign::AExt:
3567       Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3568       break;
3569     case CCValAssign::ZExtUpper:
3570       UseUpperBits = true;
3571       LLVM_FALLTHROUGH;
3572     case CCValAssign::ZExt:
3573       Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3574       break;
3575     case CCValAssign::SExtUpper:
3576       UseUpperBits = true;
3577       LLVM_FALLTHROUGH;
3578     case CCValAssign::SExt:
3579       Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3580       break;
3581     }
3582 
3583     if (UseUpperBits) {
3584       unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3585       unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3586       Val = DAG.getNode(
3587           ISD::SHL, DL, VA.getLocVT(), Val,
3588           DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3589     }
3590 
3591     Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
3592 
3593     // Guarantee that all emitted copies are stuck together with flags.
3594     Flag = Chain.getValue(1);
3595     RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3596   }
3597 
3598   // The mips ABIs for returning structs by value requires that we copy
3599   // the sret argument into $v0 for the return. We saved the argument into
3600   // a virtual register in the entry block, so now we copy the value out
3601   // and into $v0.
3602   if (MF.getFunction().hasStructRetAttr()) {
3603     MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3604     unsigned Reg = MipsFI->getSRetReturnReg();
3605 
3606     if (!Reg)
3607       llvm_unreachable("sret virtual register not created in the entry block");
3608     SDValue Val =
3609         DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
3610     unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3611 
3612     Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3613     Flag = Chain.getValue(1);
3614     RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
3615   }
3616 
3617   RetOps[0] = Chain;  // Update chain.
3618 
3619   // Add the flag if we have it.
3620   if (Flag.getNode())
3621     RetOps.push_back(Flag);
3622 
3623   // ISRs must use "eret".
3624   if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt"))
3625     return LowerInterruptReturn(RetOps, DL, DAG);
3626 
3627   // Standard return on Mips is a "jr $ra"
3628   return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3629 }
3630 
3631 //===----------------------------------------------------------------------===//
3632 //                           Mips Inline Assembly Support
3633 //===----------------------------------------------------------------------===//
3634 
3635 /// getConstraintType - Given a constraint letter, return the type of
3636 /// constraint it is for this target.
3637 MipsTargetLowering::ConstraintType
3638 MipsTargetLowering::getConstraintType(StringRef Constraint) const {
3639   // Mips specific constraints
3640   // GCC config/mips/constraints.md
3641   //
3642   // 'd' : An address register. Equivalent to r
3643   //       unless generating MIPS16 code.
3644   // 'y' : Equivalent to r; retained for
3645   //       backwards compatibility.
3646   // 'c' : A register suitable for use in an indirect
3647   //       jump. This will always be $25 for -mabicalls.
3648   // 'l' : The lo register. 1 word storage.
3649   // 'x' : The hilo register pair. Double word storage.
3650   if (Constraint.size() == 1) {
3651     switch (Constraint[0]) {
3652       default : break;
3653       case 'd':
3654       case 'y':
3655       case 'f':
3656       case 'c':
3657       case 'l':
3658       case 'x':
3659         return C_RegisterClass;
3660       case 'R':
3661         return C_Memory;
3662     }
3663   }
3664 
3665   if (Constraint == "ZC")
3666     return C_Memory;
3667 
3668   return TargetLowering::getConstraintType(Constraint);
3669 }
3670 
3671 /// Examine constraint type and operand type and determine a weight value.
3672 /// This object must already have been set up with the operand type
3673 /// and the current alternative constraint selected.
3674 TargetLowering::ConstraintWeight
3675 MipsTargetLowering::getSingleConstraintMatchWeight(
3676     AsmOperandInfo &info, const char *constraint) const {
3677   ConstraintWeight weight = CW_Invalid;
3678   Value *CallOperandVal = info.CallOperandVal;
3679     // If we don't have a value, we can't do a match,
3680     // but allow it at the lowest weight.
3681   if (!CallOperandVal)
3682     return CW_Default;
3683   Type *type = CallOperandVal->getType();
3684   // Look at the constraint type.
3685   switch (*constraint) {
3686   default:
3687     weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3688     break;
3689   case 'd':
3690   case 'y':
3691     if (type->isIntegerTy())
3692       weight = CW_Register;
3693     break;
3694   case 'f': // FPU or MSA register
3695     if (Subtarget.hasMSA() && type->isVectorTy() &&
3696         cast<VectorType>(type)->getBitWidth() == 128)
3697       weight = CW_Register;
3698     else if (type->isFloatTy())
3699       weight = CW_Register;
3700     break;
3701   case 'c': // $25 for indirect jumps
3702   case 'l': // lo register
3703   case 'x': // hilo register pair
3704     if (type->isIntegerTy())
3705       weight = CW_SpecificReg;
3706     break;
3707   case 'I': // signed 16 bit immediate
3708   case 'J': // integer zero
3709   case 'K': // unsigned 16 bit immediate
3710   case 'L': // signed 32 bit immediate where lower 16 bits are 0
3711   case 'N': // immediate in the range of -65535 to -1 (inclusive)
3712   case 'O': // signed 15 bit immediate (+- 16383)
3713   case 'P': // immediate in the range of 65535 to 1 (inclusive)
3714     if (isa<ConstantInt>(CallOperandVal))
3715       weight = CW_Constant;
3716     break;
3717   case 'R':
3718     weight = CW_Memory;
3719     break;
3720   }
3721   return weight;
3722 }
3723 
3724 /// This is a helper function to parse a physical register string and split it
3725 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
3726 /// that is returned indicates whether parsing was successful. The second flag
3727 /// is true if the numeric part exists.
3728 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
3729                                               unsigned long long &Reg) {
3730   if (C.front() != '{' || C.back() != '}')
3731     return std::make_pair(false, false);
3732 
3733   // Search for the first numeric character.
3734   StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
3735   I = std::find_if(B, E, isdigit);
3736 
3737   Prefix = StringRef(B, I - B);
3738 
3739   // The second flag is set to false if no numeric characters were found.
3740   if (I == E)
3741     return std::make_pair(true, false);
3742 
3743   // Parse the numeric characters.
3744   return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
3745                         true);
3746 }
3747 
3748 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
3749 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
3750   const TargetRegisterInfo *TRI =
3751       Subtarget.getRegisterInfo();
3752   const TargetRegisterClass *RC;
3753   StringRef Prefix;
3754   unsigned long long Reg;
3755 
3756   std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
3757 
3758   if (!R.first)
3759     return std::make_pair(0U, nullptr);
3760 
3761   if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
3762     // No numeric characters follow "hi" or "lo".
3763     if (R.second)
3764       return std::make_pair(0U, nullptr);
3765 
3766     RC = TRI->getRegClass(Prefix == "hi" ?
3767                           Mips::HI32RegClassID : Mips::LO32RegClassID);
3768     return std::make_pair(*(RC->begin()), RC);
3769   } else if (Prefix.startswith("$msa")) {
3770     // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
3771 
3772     // No numeric characters follow the name.
3773     if (R.second)
3774       return std::make_pair(0U, nullptr);
3775 
3776     Reg = StringSwitch<unsigned long long>(Prefix)
3777               .Case("$msair", Mips::MSAIR)
3778               .Case("$msacsr", Mips::MSACSR)
3779               .Case("$msaaccess", Mips::MSAAccess)
3780               .Case("$msasave", Mips::MSASave)
3781               .Case("$msamodify", Mips::MSAModify)
3782               .Case("$msarequest", Mips::MSARequest)
3783               .Case("$msamap", Mips::MSAMap)
3784               .Case("$msaunmap", Mips::MSAUnmap)
3785               .Default(0);
3786 
3787     if (!Reg)
3788       return std::make_pair(0U, nullptr);
3789 
3790     RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
3791     return std::make_pair(Reg, RC);
3792   }
3793 
3794   if (!R.second)
3795     return std::make_pair(0U, nullptr);
3796 
3797   if (Prefix == "$f") { // Parse $f0-$f31.
3798     // If the size of FP registers is 64-bit or Reg is an even number, select
3799     // the 64-bit register class. Otherwise, select the 32-bit register class.
3800     if (VT == MVT::Other)
3801       VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
3802 
3803     RC = getRegClassFor(VT);
3804 
3805     if (RC == &Mips::AFGR64RegClass) {
3806       assert(Reg % 2 == 0);
3807       Reg >>= 1;
3808     }
3809   } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
3810     RC = TRI->getRegClass(Mips::FCCRegClassID);
3811   else if (Prefix == "$w") { // Parse $w0-$w31.
3812     RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
3813   } else { // Parse $0-$31.
3814     assert(Prefix == "$");
3815     RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
3816   }
3817 
3818   assert(Reg < RC->getNumRegs());
3819   return std::make_pair(*(RC->begin() + Reg), RC);
3820 }
3821 
3822 /// Given a register class constraint, like 'r', if this corresponds directly
3823 /// to an LLVM register class, return a register of 0 and the register class
3824 /// pointer.
3825 std::pair<unsigned, const TargetRegisterClass *>
3826 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3827                                                  StringRef Constraint,
3828                                                  MVT VT) const {
3829   if (Constraint.size() == 1) {
3830     switch (Constraint[0]) {
3831     case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3832     case 'y': // Same as 'r'. Exists for compatibility.
3833     case 'r':
3834       if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3835         if (Subtarget.inMips16Mode())
3836           return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3837         return std::make_pair(0U, &Mips::GPR32RegClass);
3838       }
3839       if (VT == MVT::i64 && !Subtarget.isGP64bit())
3840         return std::make_pair(0U, &Mips::GPR32RegClass);
3841       if (VT == MVT::i64 && Subtarget.isGP64bit())
3842         return std::make_pair(0U, &Mips::GPR64RegClass);
3843       // This will generate an error message
3844       return std::make_pair(0U, nullptr);
3845     case 'f': // FPU or MSA register
3846       if (VT == MVT::v16i8)
3847         return std::make_pair(0U, &Mips::MSA128BRegClass);
3848       else if (VT == MVT::v8i16 || VT == MVT::v8f16)
3849         return std::make_pair(0U, &Mips::MSA128HRegClass);
3850       else if (VT == MVT::v4i32 || VT == MVT::v4f32)
3851         return std::make_pair(0U, &Mips::MSA128WRegClass);
3852       else if (VT == MVT::v2i64 || VT == MVT::v2f64)
3853         return std::make_pair(0U, &Mips::MSA128DRegClass);
3854       else if (VT == MVT::f32)
3855         return std::make_pair(0U, &Mips::FGR32RegClass);
3856       else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
3857         if (Subtarget.isFP64bit())
3858           return std::make_pair(0U, &Mips::FGR64RegClass);
3859         return std::make_pair(0U, &Mips::AFGR64RegClass);
3860       }
3861       break;
3862     case 'c': // register suitable for indirect jump
3863       if (VT == MVT::i32)
3864         return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
3865       if (VT == MVT::i64)
3866         return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
3867       // This will generate an error message
3868       return std::make_pair(0U, nullptr);
3869     case 'l': // use the `lo` register to store values
3870               // that are no bigger than a word
3871       if (VT == MVT::i32)
3872         return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
3873       return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
3874     case 'x': // use the concatenated `hi` and `lo` registers
3875               // to store doubleword values
3876       // Fixme: Not triggering the use of both hi and low
3877       // This will generate an error message
3878       return std::make_pair(0U, nullptr);
3879     }
3880   }
3881 
3882   std::pair<unsigned, const TargetRegisterClass *> R;
3883   R = parseRegForInlineAsmConstraint(Constraint, VT);
3884 
3885   if (R.second)
3886     return R;
3887 
3888   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3889 }
3890 
3891 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3892 /// vector.  If it is invalid, don't add anything to Ops.
3893 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3894                                                      std::string &Constraint,
3895                                                      std::vector<SDValue>&Ops,
3896                                                      SelectionDAG &DAG) const {
3897   SDLoc DL(Op);
3898   SDValue Result;
3899 
3900   // Only support length 1 constraints for now.
3901   if (Constraint.length() > 1) return;
3902 
3903   char ConstraintLetter = Constraint[0];
3904   switch (ConstraintLetter) {
3905   default: break; // This will fall through to the generic implementation
3906   case 'I': // Signed 16 bit constant
3907     // If this fails, the parent routine will give an error
3908     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3909       EVT Type = Op.getValueType();
3910       int64_t Val = C->getSExtValue();
3911       if (isInt<16>(Val)) {
3912         Result = DAG.getTargetConstant(Val, DL, Type);
3913         break;
3914       }
3915     }
3916     return;
3917   case 'J': // integer zero
3918     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3919       EVT Type = Op.getValueType();
3920       int64_t Val = C->getZExtValue();
3921       if (Val == 0) {
3922         Result = DAG.getTargetConstant(0, DL, Type);
3923         break;
3924       }
3925     }
3926     return;
3927   case 'K': // unsigned 16 bit immediate
3928     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3929       EVT Type = Op.getValueType();
3930       uint64_t Val = (uint64_t)C->getZExtValue();
3931       if (isUInt<16>(Val)) {
3932         Result = DAG.getTargetConstant(Val, DL, Type);
3933         break;
3934       }
3935     }
3936     return;
3937   case 'L': // signed 32 bit immediate where lower 16 bits are 0
3938     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3939       EVT Type = Op.getValueType();
3940       int64_t Val = C->getSExtValue();
3941       if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3942         Result = DAG.getTargetConstant(Val, DL, Type);
3943         break;
3944       }
3945     }
3946     return;
3947   case 'N': // immediate in the range of -65535 to -1 (inclusive)
3948     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3949       EVT Type = Op.getValueType();
3950       int64_t Val = C->getSExtValue();
3951       if ((Val >= -65535) && (Val <= -1)) {
3952         Result = DAG.getTargetConstant(Val, DL, Type);
3953         break;
3954       }
3955     }
3956     return;
3957   case 'O': // signed 15 bit immediate
3958     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3959       EVT Type = Op.getValueType();
3960       int64_t Val = C->getSExtValue();
3961       if ((isInt<15>(Val))) {
3962         Result = DAG.getTargetConstant(Val, DL, Type);
3963         break;
3964       }
3965     }
3966     return;
3967   case 'P': // immediate in the range of 1 to 65535 (inclusive)
3968     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3969       EVT Type = Op.getValueType();
3970       int64_t Val = C->getSExtValue();
3971       if ((Val <= 65535) && (Val >= 1)) {
3972         Result = DAG.getTargetConstant(Val, DL, Type);
3973         break;
3974       }
3975     }
3976     return;
3977   }
3978 
3979   if (Result.getNode()) {
3980     Ops.push_back(Result);
3981     return;
3982   }
3983 
3984   TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3985 }
3986 
3987 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3988                                                const AddrMode &AM, Type *Ty,
3989                                                unsigned AS, Instruction *I) const {
3990   // No global is ever allowed as a base.
3991   if (AM.BaseGV)
3992     return false;
3993 
3994   switch (AM.Scale) {
3995   case 0: // "r+i" or just "i", depending on HasBaseReg.
3996     break;
3997   case 1:
3998     if (!AM.HasBaseReg) // allow "r+i".
3999       break;
4000     return false; // disallow "r+r" or "r+r+i".
4001   default:
4002     return false;
4003   }
4004 
4005   return true;
4006 }
4007 
4008 bool
4009 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4010   // The Mips target isn't yet aware of offsets.
4011   return false;
4012 }
4013 
4014 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
4015                                             unsigned SrcAlign,
4016                                             bool IsMemset, bool ZeroMemset,
4017                                             bool MemcpyStrSrc,
4018                                             MachineFunction &MF) const {
4019   if (Subtarget.hasMips64())
4020     return MVT::i64;
4021 
4022   return MVT::i32;
4023 }
4024 
4025 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4026   if (VT != MVT::f32 && VT != MVT::f64)
4027     return false;
4028   if (Imm.isNegZero())
4029     return false;
4030   return Imm.isZero();
4031 }
4032 
4033 unsigned MipsTargetLowering::getJumpTableEncoding() const {
4034 
4035   // FIXME: For space reasons this should be: EK_GPRel32BlockAddress.
4036   if (ABI.IsN64() && isPositionIndependent())
4037     return MachineJumpTableInfo::EK_GPRel64BlockAddress;
4038 
4039   return TargetLowering::getJumpTableEncoding();
4040 }
4041 
4042 bool MipsTargetLowering::useSoftFloat() const {
4043   return Subtarget.useSoftFloat();
4044 }
4045 
4046 void MipsTargetLowering::copyByValRegs(
4047     SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains,
4048     SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
4049     SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
4050     unsigned FirstReg, unsigned LastReg, const CCValAssign &VA,
4051     MipsCCState &State) const {
4052   MachineFunction &MF = DAG.getMachineFunction();
4053   MachineFrameInfo &MFI = MF.getFrameInfo();
4054   unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
4055   unsigned NumRegs = LastReg - FirstReg;
4056   unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
4057   unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
4058   int FrameObjOffset;
4059   ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
4060 
4061   if (RegAreaSize)
4062     FrameObjOffset =
4063         (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
4064         (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
4065   else
4066     FrameObjOffset = VA.getLocMemOffset();
4067 
4068   // Create frame object.
4069   EVT PtrTy = getPointerTy(DAG.getDataLayout());
4070   int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, true);
4071   SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4072   InVals.push_back(FIN);
4073 
4074   if (!NumRegs)
4075     return;
4076 
4077   // Copy arg registers.
4078   MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
4079   const TargetRegisterClass *RC = getRegClassFor(RegTy);
4080 
4081   for (unsigned I = 0; I < NumRegs; ++I) {
4082     unsigned ArgReg = ByValArgRegs[FirstReg + I];
4083     unsigned VReg = addLiveIn(MF, ArgReg, RC);
4084     unsigned Offset = I * GPRSizeInBytes;
4085     SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
4086                                    DAG.getConstant(Offset, DL, PtrTy));
4087     SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
4088                                  StorePtr, MachinePointerInfo(FuncArg, Offset));
4089     OutChains.push_back(Store);
4090   }
4091 }
4092 
4093 // Copy byVal arg to registers and stack.
4094 void MipsTargetLowering::passByValArg(
4095     SDValue Chain, const SDLoc &DL,
4096     std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
4097     SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
4098     MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
4099     unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
4100     const CCValAssign &VA) const {
4101   unsigned ByValSizeInBytes = Flags.getByValSize();
4102   unsigned OffsetInBytes = 0; // From beginning of struct
4103   unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4104   unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
4105   EVT PtrTy = getPointerTy(DAG.getDataLayout()),
4106       RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4107   unsigned NumRegs = LastReg - FirstReg;
4108 
4109   if (NumRegs) {
4110     ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs();
4111     bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
4112     unsigned I = 0;
4113 
4114     // Copy words to registers.
4115     for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
4116       SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4117                                     DAG.getConstant(OffsetInBytes, DL, PtrTy));
4118       SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
4119                                     MachinePointerInfo(), Alignment);
4120       MemOpChains.push_back(LoadVal.getValue(1));
4121       unsigned ArgReg = ArgRegs[FirstReg + I];
4122       RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
4123     }
4124 
4125     // Return if the struct has been fully copied.
4126     if (ByValSizeInBytes == OffsetInBytes)
4127       return;
4128 
4129     // Copy the remainder of the byval argument with sub-word loads and shifts.
4130     if (LeftoverBytes) {
4131       SDValue Val;
4132 
4133       for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
4134            OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
4135         unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
4136 
4137         if (RemainingSizeInBytes < LoadSizeInBytes)
4138           continue;
4139 
4140         // Load subword.
4141         SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4142                                       DAG.getConstant(OffsetInBytes, DL,
4143                                                       PtrTy));
4144         SDValue LoadVal = DAG.getExtLoad(
4145             ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
4146             MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment);
4147         MemOpChains.push_back(LoadVal.getValue(1));
4148 
4149         // Shift the loaded value.
4150         unsigned Shamt;
4151 
4152         if (isLittle)
4153           Shamt = TotalBytesLoaded * 8;
4154         else
4155           Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
4156 
4157         SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
4158                                     DAG.getConstant(Shamt, DL, MVT::i32));
4159 
4160         if (Val.getNode())
4161           Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
4162         else
4163           Val = Shift;
4164 
4165         OffsetInBytes += LoadSizeInBytes;
4166         TotalBytesLoaded += LoadSizeInBytes;
4167         Alignment = std::min(Alignment, LoadSizeInBytes);
4168       }
4169 
4170       unsigned ArgReg = ArgRegs[FirstReg + I];
4171       RegsToPass.push_back(std::make_pair(ArgReg, Val));
4172       return;
4173     }
4174   }
4175 
4176   // Copy remainder of byval arg to it with memcpy.
4177   unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
4178   SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4179                             DAG.getConstant(OffsetInBytes, DL, PtrTy));
4180   SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
4181                             DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
4182   Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
4183                         DAG.getConstant(MemCpySize, DL, PtrTy),
4184                         Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
4185                         /*isTailCall=*/false,
4186                         MachinePointerInfo(), MachinePointerInfo());
4187   MemOpChains.push_back(Chain);
4188 }
4189 
4190 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4191                                          SDValue Chain, const SDLoc &DL,
4192                                          SelectionDAG &DAG,
4193                                          CCState &State) const {
4194   ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
4195   unsigned Idx = State.getFirstUnallocated(ArgRegs);
4196   unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4197   MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4198   const TargetRegisterClass *RC = getRegClassFor(RegTy);
4199   MachineFunction &MF = DAG.getMachineFunction();
4200   MachineFrameInfo &MFI = MF.getFrameInfo();
4201   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
4202 
4203   // Offset of the first variable argument from stack pointer.
4204   int VaArgOffset;
4205 
4206   if (ArgRegs.size() == Idx)
4207     VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes);
4208   else {
4209     VaArgOffset =
4210         (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
4211         (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
4212   }
4213 
4214   // Record the frame index of the first variable argument
4215   // which is a value necessary to VASTART.
4216   int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4217   MipsFI->setVarArgsFrameIndex(FI);
4218 
4219   // Copy the integer registers that have not been used for argument passing
4220   // to the argument register save area. For O32, the save area is allocated
4221   // in the caller's stack frame, while for N32/64, it is allocated in the
4222   // callee's stack frame.
4223   for (unsigned I = Idx; I < ArgRegs.size();
4224        ++I, VaArgOffset += RegSizeInBytes) {
4225     unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
4226     SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
4227     FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4228     SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4229     SDValue Store =
4230         DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo());
4231     cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
4232         (Value *)nullptr);
4233     OutChains.push_back(Store);
4234   }
4235 }
4236 
4237 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
4238                                      unsigned Align) const {
4239   const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
4240 
4241   assert(Size && "Byval argument's size shouldn't be 0.");
4242 
4243   Align = std::min(Align, TFL->getStackAlignment());
4244 
4245   unsigned FirstReg = 0;
4246   unsigned NumRegs = 0;
4247 
4248   if (State->getCallingConv() != CallingConv::Fast) {
4249     unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4250     ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
4251     // FIXME: The O32 case actually describes no shadow registers.
4252     const MCPhysReg *ShadowRegs =
4253         ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs;
4254 
4255     // We used to check the size as well but we can't do that anymore since
4256     // CCState::HandleByVal() rounds up the size after calling this function.
4257     assert(!(Align % RegSizeInBytes) &&
4258            "Byval argument's alignment should be a multiple of"
4259            "RegSizeInBytes.");
4260 
4261     FirstReg = State->getFirstUnallocated(IntArgRegs);
4262 
4263     // If Align > RegSizeInBytes, the first arg register must be even.
4264     // FIXME: This condition happens to do the right thing but it's not the
4265     //        right way to test it. We want to check that the stack frame offset
4266     //        of the register is aligned.
4267     if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
4268       State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
4269       ++FirstReg;
4270     }
4271 
4272     // Mark the registers allocated.
4273     Size = alignTo(Size, RegSizeInBytes);
4274     for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
4275          Size -= RegSizeInBytes, ++I, ++NumRegs)
4276       State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
4277   }
4278 
4279   State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
4280 }
4281 
4282 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
4283                                                         MachineBasicBlock *BB,
4284                                                         bool isFPCmp,
4285                                                         unsigned Opc) const {
4286   assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
4287          "Subtarget already supports SELECT nodes with the use of"
4288          "conditional-move instructions.");
4289 
4290   const TargetInstrInfo *TII =
4291       Subtarget.getInstrInfo();
4292   DebugLoc DL = MI.getDebugLoc();
4293 
4294   // To "insert" a SELECT instruction, we actually have to insert the
4295   // diamond control-flow pattern.  The incoming instruction knows the
4296   // destination vreg to set, the condition code register to branch on, the
4297   // true/false values to select between, and a branch opcode to use.
4298   const BasicBlock *LLVM_BB = BB->getBasicBlock();
4299   MachineFunction::iterator It = ++BB->getIterator();
4300 
4301   //  thisMBB:
4302   //  ...
4303   //   TrueVal = ...
4304   //   setcc r1, r2, r3
4305   //   bNE   r1, r0, copy1MBB
4306   //   fallthrough --> copy0MBB
4307   MachineBasicBlock *thisMBB  = BB;
4308   MachineFunction *F = BB->getParent();
4309   MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4310   MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
4311   F->insert(It, copy0MBB);
4312   F->insert(It, sinkMBB);
4313 
4314   // Transfer the remainder of BB and its successor edges to sinkMBB.
4315   sinkMBB->splice(sinkMBB->begin(), BB,
4316                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
4317   sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4318 
4319   // Next, add the true and fallthrough blocks as its successors.
4320   BB->addSuccessor(copy0MBB);
4321   BB->addSuccessor(sinkMBB);
4322 
4323   if (isFPCmp) {
4324     // bc1[tf] cc, sinkMBB
4325     BuildMI(BB, DL, TII->get(Opc))
4326         .addReg(MI.getOperand(1).getReg())
4327         .addMBB(sinkMBB);
4328   } else {
4329     // bne rs, $0, sinkMBB
4330     BuildMI(BB, DL, TII->get(Opc))
4331         .addReg(MI.getOperand(1).getReg())
4332         .addReg(Mips::ZERO)
4333         .addMBB(sinkMBB);
4334   }
4335 
4336   //  copy0MBB:
4337   //   %FalseValue = ...
4338   //   # fallthrough to sinkMBB
4339   BB = copy0MBB;
4340 
4341   // Update machine-CFG edges
4342   BB->addSuccessor(sinkMBB);
4343 
4344   //  sinkMBB:
4345   //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
4346   //  ...
4347   BB = sinkMBB;
4348 
4349   BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4350       .addReg(MI.getOperand(2).getReg())
4351       .addMBB(thisMBB)
4352       .addReg(MI.getOperand(3).getReg())
4353       .addMBB(copy0MBB);
4354 
4355   MI.eraseFromParent(); // The pseudo instruction is gone now.
4356 
4357   return BB;
4358 }
4359 
4360 // FIXME? Maybe this could be a TableGen attribute on some registers and
4361 // this table could be generated automatically from RegInfo.
4362 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
4363                                                SelectionDAG &DAG) const {
4364   // Named registers is expected to be fairly rare. For now, just support $28
4365   // since the linux kernel uses it.
4366   if (Subtarget.isGP64bit()) {
4367     unsigned Reg = StringSwitch<unsigned>(RegName)
4368                          .Case("$28", Mips::GP_64)
4369                          .Default(0);
4370     if (Reg)
4371       return Reg;
4372   } else {
4373     unsigned Reg = StringSwitch<unsigned>(RegName)
4374                          .Case("$28", Mips::GP)
4375                          .Default(0);
4376     if (Reg)
4377       return Reg;
4378   }
4379   report_fatal_error("Invalid register name global variable");
4380 }
4381