1//===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// This describes the calling conventions for Mips architecture. 10//===----------------------------------------------------------------------===// 11 12/// CCIfSubtarget - Match if the current subtarget has a feature F. 13class CCIfSubtarget<string F, CCAction A, string Invert = ""> 14 : CCIf<!strconcat(Invert, 15 "State.getMachineFunction().getTarget()." 16 "getSubtarget<const MipsSubtarget>().", 17 F), 18 A>; 19 20// The inverse of CCIfSubtarget 21class CCIfSubtargetNot<string F, CCAction A> : CCIfSubtarget<F, A, "!">; 22 23// For soft-float, f128 values are returned in A0_64 rather than V1_64. 24def RetCC_F128SoftFloat : CallingConv<[ 25 CCAssignToReg<[V0_64, A0_64]> 26]>; 27 28// For hard-float, f128 values are returned as a pair of f64's rather than a 29// pair of i64's. 30def RetCC_F128HardFloat : CallingConv<[ 31 CCBitConvertToType<f64>, 32 33 // Contrary to the ABI documentation, a struct containing a long double is 34 // returned in $f0, and $f1 instead of the usual $f0, and $f2. This is to 35 // match the de facto ABI as implemented by GCC. 36 CCIfInReg<CCAssignToReg<[D0_64, D1_64]>>, 37 38 CCAssignToReg<[D0_64, D2_64]> 39]>; 40 41// Handle F128 specially since we can't identify the original type during the 42// tablegen-erated code. 43def RetCC_F128 : CallingConv<[ 44 CCIfSubtarget<"abiUsesSoftFloat()", 45 CCIfType<[i64], CCDelegateTo<RetCC_F128SoftFloat>>>, 46 CCIfSubtargetNot<"abiUsesSoftFloat()", 47 CCIfType<[i64], CCDelegateTo<RetCC_F128HardFloat>>> 48]>; 49 50//===----------------------------------------------------------------------===// 51// Mips O32 Calling Convention 52//===----------------------------------------------------------------------===// 53 54// Only the return rules are defined here for O32. The rules for argument 55// passing are defined in MipsISelLowering.cpp. 56def RetCC_MipsO32 : CallingConv<[ 57 // i32 are returned in registers V0, V1, A0, A1 58 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>, 59 60 // f32 are returned in registers F0, F2 61 CCIfType<[f32], CCAssignToReg<[F0, F2]>>, 62 63 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or 64 // in D0 and D1 in FP32bit mode. 65 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>, 66 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", CCAssignToReg<[D0, D1]>>> 67]>; 68 69def CC_MipsO32_FP32 : CustomCallingConv; 70def CC_MipsO32_FP64 : CustomCallingConv; 71 72def CC_MipsO32_FP : CallingConv<[ 73 CCIfSubtargetNot<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP32>>, 74 CCIfSubtarget<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP64>> 75]>; 76 77//===----------------------------------------------------------------------===// 78// Mips N32/64 Calling Convention 79//===----------------------------------------------------------------------===// 80 81def CC_MipsN_SoftFloat : CallingConv<[ 82 CCAssignToRegWithShadow<[A0, A1, A2, A3, 83 T0, T1, T2, T3], 84 [D12_64, D13_64, D14_64, D15_64, 85 D16_64, D17_64, D18_64, D19_64]>, 86 CCAssignToStack<4, 8> 87]>; 88 89def CC_MipsN : CallingConv<[ 90 CCIfType<[i8, i16, i32], 91 CCIfSubtargetNot<"isLittle()", 92 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>, 93 94 // All integers (except soft-float integers) are promoted to 64-bit. 95 CCIfType<[i8, i16, i32], 96 CCIf<"!static_cast<MipsCCState *>(&State)->WasOriginalArgFloat(ValNo)", 97 CCPromoteToType<i64>>>, 98 99 // The only i32's we have left are soft-float arguments. 100 CCIfSubtarget<"abiUsesSoftFloat()", CCIfType<[i32], CCDelegateTo<CC_MipsN_SoftFloat>>>, 101 102 // Integer arguments are passed in integer registers. 103 CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64, 104 T0_64, T1_64, T2_64, T3_64], 105 [D12_64, D13_64, D14_64, D15_64, 106 D16_64, D17_64, D18_64, D19_64]>>, 107 108 // f32 arguments are passed in single precision FP registers. 109 CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15, 110 F16, F17, F18, F19], 111 [A0_64, A1_64, A2_64, A3_64, 112 T0_64, T1_64, T2_64, T3_64]>>, 113 114 // f64 arguments are passed in double precision FP registers. 115 CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64, 116 D16_64, D17_64, D18_64, D19_64], 117 [A0_64, A1_64, A2_64, A3_64, 118 T0_64, T1_64, T2_64, T3_64]>>, 119 120 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned. 121 CCIfType<[f32], CCAssignToStack<4, 8>>, 122 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 123]>; 124 125// N32/64 variable arguments. 126// All arguments are passed in integer registers. 127def CC_MipsN_VarArg : CallingConv<[ 128 // All integers are promoted to 64-bit. 129 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 130 131 CCIfType<[f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>, 132 133 CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, 134 T0_64, T1_64, T2_64, T3_64]>>, 135 136 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned. 137 CCIfType<[f32], CCAssignToStack<4, 8>>, 138 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 139]>; 140 141def RetCC_MipsN : CallingConv<[ 142 // f128 needs to be handled similarly to f32 and f64. However, f128 is not 143 // legal and is lowered to i128 which is further lowered to a pair of i64's. 144 // This presents us with a problem for the calling convention since hard-float 145 // still needs to pass them in FPU registers, and soft-float needs to use $v0, 146 // and $a0 instead of the usual $v0, and $v1. We therefore resort to a 147 // pre-analyze (see PreAnalyzeReturnForF128()) step to pass information on 148 // whether the result was originally an f128 into the tablegen-erated code. 149 // 150 // f128 should only occur for the N64 ABI where long double is 128-bit. On 151 // N32, long double is equivalent to double. 152 CCIfType<[i64], 153 CCIf<"static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)", 154 CCDelegateTo<RetCC_F128>>>, 155 156 // Aggregate returns are positioned at the lowest address in the slot for 157 // both little and big-endian targets. When passing in registers, this 158 // requires that big-endian targets shift the value into the upper bits. 159 CCIfSubtarget<"isLittle()", 160 CCIfType<[i8, i16, i32, i64], CCIfInReg<CCPromoteToType<i64>>>>, 161 CCIfSubtargetNot<"isLittle()", 162 CCIfType<[i8, i16, i32, i64], 163 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>, 164 165 // i64 are returned in registers V0_64, V1_64 166 CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>, 167 168 // f32 are returned in registers F0, F2 169 CCIfType<[f32], CCAssignToReg<[F0, F2]>>, 170 171 // f64 are returned in registers D0, D2 172 CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>> 173]>; 174 175//===----------------------------------------------------------------------===// 176// Mips EABI Calling Convention 177//===----------------------------------------------------------------------===// 178 179def CC_MipsEABI : CallingConv<[ 180 // Promote i8/i16 arguments to i32. 181 CCIfType<[i8, i16], CCPromoteToType<i32>>, 182 183 // Integer arguments are passed in integer registers. 184 CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>, 185 186 // Single fp arguments are passed in pairs within 32-bit mode 187 CCIfType<[f32], CCIfSubtarget<"isSingleFloat()", 188 CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>, 189 190 CCIfType<[f32], CCIfSubtargetNot<"isSingleFloat()", 191 CCAssignToReg<[F12, F14, F16, F18]>>>, 192 193 // The first 4 double fp arguments are passed in single fp registers. 194 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", 195 CCAssignToReg<[D6, D7, D8, D9]>>>, 196 197 // Integer values get stored in stack slots that are 4 bytes in 198 // size and 4-byte aligned. 199 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 200 201 // Integer values get stored in stack slots that are 8 bytes in 202 // size and 8-byte aligned. 203 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToStack<8, 8>>> 204]>; 205 206def RetCC_MipsEABI : CallingConv<[ 207 // i32 are returned in registers V0, V1 208 CCIfType<[i32], CCAssignToReg<[V0, V1]>>, 209 210 // f32 are returned in registers F0, F1 211 CCIfType<[f32], CCAssignToReg<[F0, F1]>>, 212 213 // f64 are returned in register D0 214 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToReg<[D0]>>> 215]>; 216 217//===----------------------------------------------------------------------===// 218// Mips FastCC Calling Convention 219//===----------------------------------------------------------------------===// 220def CC_MipsO32_FastCC : CallingConv<[ 221 // f64 arguments are passed in double-precision floating pointer registers. 222 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", 223 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, 224 D7, D8, D9]>>>, 225 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"useOddSPReg()", 226 CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, 227 D4_64, D5_64, D6_64, D7_64, 228 D8_64, D9_64, D10_64, D11_64, 229 D12_64, D13_64, D14_64, D15_64, 230 D16_64, D17_64, D18_64, 231 D19_64]>>>>, 232 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"noOddSPReg()", 233 CCAssignToReg<[D0_64, D2_64, D4_64, D6_64, 234 D8_64, D10_64, D12_64, D14_64, 235 D16_64, D18_64]>>>>, 236 237 // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned. 238 CCIfType<[f64], CCAssignToStack<8, 8>> 239]>; 240 241def CC_MipsN_FastCC : CallingConv<[ 242 // Integer arguments are passed in integer registers. 243 CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64, 244 T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 245 T8_64, V1_64]>>, 246 247 // f64 arguments are passed in double-precision floating pointer registers. 248 CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64, 249 D6_64, D7_64, D8_64, D9_64, D10_64, D11_64, 250 D12_64, D13_64, D14_64, D15_64, D16_64, D17_64, 251 D18_64, D19_64]>>, 252 253 // Stack parameter slots for i64 and f64 are 64-bit doublewords and 254 // 8-byte aligned. 255 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 256]>; 257 258def CC_Mips_FastCC : CallingConv<[ 259 // Handles byval parameters. 260 CCIfByVal<CCPassByVal<4, 4>>, 261 262 // Promote i8/i16 arguments to i32. 263 CCIfType<[i8, i16], CCPromoteToType<i32>>, 264 265 // Integer arguments are passed in integer registers. All scratch registers, 266 // except for AT, V0 and T9, are available to be used as argument registers. 267 CCIfType<[i32], CCIfSubtargetNot<"isTargetNaCl()", 268 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>>, 269 270 // In NaCl, T6, T7 and T8 are reserved and not available as argument 271 // registers for fastcc. T6 contains the mask for sandboxing control flow 272 // (indirect jumps and calls). T7 contains the mask for sandboxing memory 273 // accesses (loads and stores). T8 contains the thread pointer. 274 CCIfType<[i32], CCIfSubtarget<"isTargetNaCl()", 275 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>, 276 277 // f32 arguments are passed in single-precision floating pointer registers. 278 CCIfType<[f32], CCIfSubtarget<"useOddSPReg()", 279 CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, 280 F14, F15, F16, F17, F18, F19]>>>, 281 282 // Don't use odd numbered single-precision registers for -mno-odd-spreg. 283 CCIfType<[f32], CCIfSubtarget<"noOddSPReg()", 284 CCAssignToReg<[F0, F2, F4, F6, F8, F10, F12, F14, F16, F18]>>>, 285 286 // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned. 287 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 288 289 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>, 290 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>, 291 CCDelegateTo<CC_MipsN_FastCC> 292]>; 293 294//===----------------------------------------------------------------------===// 295// Mips Calling Convention Dispatch 296//===----------------------------------------------------------------------===// 297 298def RetCC_Mips : CallingConv<[ 299 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>, 300 CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>, 301 CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>, 302 CCDelegateTo<RetCC_MipsO32> 303]>; 304 305def CC_Mips_ByVal : CallingConv<[ 306 CCIfSubtarget<"isABI_O32()", CCIfByVal<CCPassByVal<4, 4>>>, 307 CCIfByVal<CCPassByVal<8, 8>> 308]>; 309 310def CC_Mips16RetHelper : CallingConv<[ 311 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>, 312 313 // Integer arguments are passed in integer registers. 314 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>> 315]>; 316 317def CC_Mips_FixedArg : CallingConv<[ 318 // Mips16 needs special handling on some functions. 319 CCIf<"State.getCallingConv() != CallingConv::Fast", 320 CCIf<"static_cast<MipsCCState *>(&State)->getSpecialCallingConv() == " 321 "MipsCCState::Mips16RetHelperConv", 322 CCDelegateTo<CC_Mips16RetHelper>>>, 323 324 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>, 325 326 // f128 needs to be handled similarly to f32 and f64 on hard-float. However, 327 // f128 is not legal and is lowered to i128 which is further lowered to a pair 328 // of i64's. 329 // This presents us with a problem for the calling convention since hard-float 330 // still needs to pass them in FPU registers. We therefore resort to a 331 // pre-analyze (see PreAnalyzeFormalArgsForF128()) step to pass information on 332 // whether the argument was originally an f128 into the tablegen-erated code. 333 // 334 // f128 should only occur for the N64 ABI where long double is 128-bit. On 335 // N32, long double is equivalent to double. 336 CCIfType<[i64], 337 CCIfSubtargetNot<"abiUsesSoftFloat()", 338 CCIf<"static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)", 339 CCBitConvertToType<f64>>>>, 340 341 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_Mips_FastCC>>, 342 343 // FIXME: There wasn't an EABI case in the original code and it seems unlikely 344 // that it's the same as CC_MipsN 345 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>, 346 CCDelegateTo<CC_MipsN> 347]>; 348 349def CC_Mips_VarArg : CallingConv<[ 350 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>, 351 352 // FIXME: There wasn't an EABI case in the original code and it seems unlikely 353 // that it's the same as CC_MipsN_VarArg 354 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>, 355 CCDelegateTo<CC_MipsN_VarArg> 356]>; 357 358def CC_Mips : CallingConv<[ 359 CCIfVarArg< 360 CCIf<"!static_cast<MipsCCState *>(&State)->IsCallOperandFixed(ValNo)", 361 CCDelegateTo<CC_Mips_VarArg>>>, 362 CCDelegateTo<CC_Mips_FixedArg> 363]>; 364 365//===----------------------------------------------------------------------===// 366// Callee-saved register lists. 367//===----------------------------------------------------------------------===// 368 369def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP, 370 (sequence "S%u", 7, 0))>; 371 372def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP, 373 (sequence "S%u", 7, 0))> { 374 let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2)); 375} 376 377def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP, 378 (sequence "S%u", 7, 0))>; 379 380def CSR_O32_FP64 : 381 CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP, 382 (sequence "S%u", 7, 0))>; 383 384def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64, 385 D30_64, RA_64, FP_64, GP_64, 386 (sequence "S%u_64", 7, 0))>; 387 388def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64, 389 GP_64, (sequence "S%u_64", 7, 0))>; 390 391def CSR_Mips16RetHelper : 392 CalleeSavedRegs<(add V0, V1, FP, 393 (sequence "A%u", 3, 0), (sequence "S%u", 7, 0), 394 (sequence "D%u", 15, 10))>; 395