1 //===-- Mips16ISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips16 ----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Subclass of MipsDAGToDAGISel specialized for mips16.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Mips16ISelDAGToDAG.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "Mips.h"
17 #include "MipsAnalyzeImmediate.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsRegisterInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/IR/CFG.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetMachine.h"
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "mips-isel"
38 
39 bool Mips16DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
40   Subtarget = &TM.getSubtarget<MipsSubtarget>();
41   if (!Subtarget->inMips16Mode())
42     return false;
43   return MipsDAGToDAGISel::runOnMachineFunction(MF);
44 }
45 /// Select multiply instructions.
46 std::pair<SDNode*, SDNode*>
47 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, SDLoc DL, EVT Ty,
48                                bool HasLo, bool HasHi) {
49   SDNode *Lo = nullptr, *Hi = nullptr;
50   SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
51                                        N->getOperand(1));
52   SDValue InFlag = SDValue(Mul, 0);
53 
54   if (HasLo) {
55     unsigned Opcode = Mips::Mflo16;
56     Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
57     InFlag = SDValue(Lo, 1);
58   }
59   if (HasHi) {
60     unsigned Opcode = Mips::Mfhi16;
61     Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag);
62   }
63   return std::make_pair(Lo, Hi);
64 }
65 
66 void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
67   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
68 
69   if (!MipsFI->globalBaseRegSet())
70     return;
71 
72   MachineBasicBlock &MBB = MF.front();
73   MachineBasicBlock::iterator I = MBB.begin();
74   MachineRegisterInfo &RegInfo = MF.getRegInfo();
75   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
76   DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
77   unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
78   const TargetRegisterClass *RC =
79     (const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
80 
81   V0 = RegInfo.createVirtualRegister(RC);
82   V1 = RegInfo.createVirtualRegister(RC);
83   V2 = RegInfo.createVirtualRegister(RC);
84 
85   BuildMI(MBB, I, DL, TII.get(Mips::GotPrologue16), V0).
86     addReg(V1, RegState::Define).
87     addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI).
88     addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
89 
90   BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
91   BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
92     .addReg(V1).addReg(V2);
93 }
94 
95 // Insert instructions to initialize the Mips16 SP Alias register in the
96 // first MBB of the function.
97 //
98 void Mips16DAGToDAGISel::initMips16SPAliasReg(MachineFunction &MF) {
99   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
100 
101   if (!MipsFI->mips16SPAliasRegSet())
102     return;
103 
104   MachineBasicBlock &MBB = MF.front();
105   MachineBasicBlock::iterator I = MBB.begin();
106   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
107   DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
108   unsigned Mips16SPAliasReg = MipsFI->getMips16SPAliasReg();
109 
110   BuildMI(MBB, I, DL, TII.get(Mips::MoveR3216), Mips16SPAliasReg)
111     .addReg(Mips::SP);
112 }
113 
114 void Mips16DAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
115   initGlobalBaseReg(MF);
116   initMips16SPAliasReg(MF);
117 }
118 
119 /// getMips16SPAliasReg - Output the instructions required to put the
120 /// SP into a Mips16 accessible aliased register.
121 SDValue Mips16DAGToDAGISel::getMips16SPAliasReg() {
122   unsigned Mips16SPAliasReg =
123     MF->getInfo<MipsFunctionInfo>()->getMips16SPAliasReg();
124   return CurDAG->getRegister(Mips16SPAliasReg,
125                              getTargetLowering()->getPointerTy());
126 }
127 
128 void Mips16DAGToDAGISel::getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg) {
129   SDValue AliasFPReg = CurDAG->getRegister(Mips::S0,
130                                            getTargetLowering()->getPointerTy());
131   if (Parent) {
132     switch (Parent->getOpcode()) {
133       case ISD::LOAD: {
134         LoadSDNode *SD = dyn_cast<LoadSDNode>(Parent);
135         switch (SD->getMemoryVT().getSizeInBits()) {
136         case 8:
137         case 16:
138           AliasReg = TM.getFrameLowering()->hasFP(*MF)?
139             AliasFPReg: getMips16SPAliasReg();
140           return;
141         }
142         break;
143       }
144       case ISD::STORE: {
145         StoreSDNode *SD = dyn_cast<StoreSDNode>(Parent);
146         switch (SD->getMemoryVT().getSizeInBits()) {
147         case 8:
148         case 16:
149           AliasReg = TM.getFrameLowering()->hasFP(*MF)?
150             AliasFPReg: getMips16SPAliasReg();
151           return;
152         }
153         break;
154       }
155     }
156   }
157   AliasReg = CurDAG->getRegister(Mips::SP, getTargetLowering()->getPointerTy());
158   return;
159 
160 }
161 
162 bool Mips16DAGToDAGISel::selectAddr16(
163   SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset,
164   SDValue &Alias) {
165   EVT ValTy = Addr.getValueType();
166 
167   Alias = CurDAG->getTargetConstant(0, ValTy);
168 
169   // if Address is FI, get the TargetFrameIndex.
170   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
171     Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
172     Offset = CurDAG->getTargetConstant(0, ValTy);
173     getMips16SPRefReg(Parent, Alias);
174     return true;
175   }
176   // on PIC code Load GA
177   if (Addr.getOpcode() == MipsISD::Wrapper) {
178     Base   = Addr.getOperand(0);
179     Offset = Addr.getOperand(1);
180     return true;
181   }
182   if (TM.getRelocationModel() != Reloc::PIC_) {
183     if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
184         Addr.getOpcode() == ISD::TargetGlobalAddress))
185       return false;
186   }
187   // Addresses of the form FI+const or FI|const
188   if (CurDAG->isBaseWithConstantOffset(Addr)) {
189     ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
190     if (isInt<16>(CN->getSExtValue())) {
191 
192       // If the first operand is a FI, get the TargetFI Node
193       if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
194                                   (Addr.getOperand(0))) {
195         Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
196         getMips16SPRefReg(Parent, Alias);
197       }
198       else
199         Base = Addr.getOperand(0);
200 
201       Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
202       return true;
203     }
204   }
205   // Operand is a result from an ADD.
206   if (Addr.getOpcode() == ISD::ADD) {
207     // When loading from constant pools, load the lower address part in
208     // the instruction itself. Example, instead of:
209     //  lui $2, %hi($CPI1_0)
210     //  addiu $2, $2, %lo($CPI1_0)
211     //  lwc1 $f0, 0($2)
212     // Generate:
213     //  lui $2, %hi($CPI1_0)
214     //  lwc1 $f0, %lo($CPI1_0)($2)
215     if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
216         Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
217       SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
218       if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
219           isa<JumpTableSDNode>(Opnd0)) {
220         Base = Addr.getOperand(0);
221         Offset = Opnd0;
222         return true;
223       }
224     }
225 
226     // If an indexed floating point load/store can be emitted, return false.
227     const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent);
228 
229     if (LS) {
230       if (LS->getMemoryVT() == MVT::f32 && Subtarget->hasMips4_32r2())
231         return false;
232       if (LS->getMemoryVT() == MVT::f64 && Subtarget->hasMips4_32r2())
233         return false;
234     }
235   }
236   Base   = Addr;
237   Offset = CurDAG->getTargetConstant(0, ValTy);
238   return true;
239 }
240 
241 /// Select instructions not customized! Used for
242 /// expanded, promoted and normal instructions
243 std::pair<bool, SDNode*> Mips16DAGToDAGISel::selectNode(SDNode *Node) {
244   unsigned Opcode = Node->getOpcode();
245   SDLoc DL(Node);
246 
247   ///
248   // Instruction Selection not handled by the auto-generated
249   // tablegen selection should be handled here.
250   ///
251   EVT NodeTy = Node->getValueType(0);
252   unsigned MultOpc;
253 
254   switch(Opcode) {
255   default: break;
256 
257   case ISD::SUBE:
258   case ISD::ADDE: {
259     SDValue InFlag = Node->getOperand(2), CmpLHS;
260     unsigned Opc = InFlag.getOpcode(); (void)Opc;
261     assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
262             (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
263            "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
264 
265     unsigned MOp;
266     if (Opcode == ISD::ADDE) {
267       CmpLHS = InFlag.getValue(0);
268       MOp = Mips::AdduRxRyRz16;
269     } else {
270       CmpLHS = InFlag.getOperand(0);
271       MOp = Mips::SubuRxRyRz16;
272     }
273 
274     SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
275 
276     SDValue LHS = Node->getOperand(0);
277     SDValue RHS = Node->getOperand(1);
278 
279     EVT VT = LHS.getValueType();
280 
281     unsigned Sltu_op = Mips::SltuRxRyRz16;
282     SDNode *Carry = CurDAG->getMachineNode(Sltu_op, DL, VT, Ops);
283     unsigned Addu_op = Mips::AdduRxRyRz16;
284     SDNode *AddCarry = CurDAG->getMachineNode(Addu_op, DL, VT,
285                                               SDValue(Carry,0), RHS);
286 
287     SDNode *Result = CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
288                                           SDValue(AddCarry,0));
289     return std::make_pair(true, Result);
290   }
291 
292   /// Mul with two results
293   case ISD::SMUL_LOHI:
294   case ISD::UMUL_LOHI: {
295     MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MultuRxRy16 : Mips::MultRxRy16);
296     std::pair<SDNode*, SDNode*> LoHi = selectMULT(Node, MultOpc, DL, NodeTy,
297                                                   true, true);
298     if (!SDValue(Node, 0).use_empty())
299       ReplaceUses(SDValue(Node, 0), SDValue(LoHi.first, 0));
300 
301     if (!SDValue(Node, 1).use_empty())
302       ReplaceUses(SDValue(Node, 1), SDValue(LoHi.second, 0));
303 
304     return std::make_pair(true, nullptr);
305   }
306 
307   case ISD::MULHS:
308   case ISD::MULHU: {
309     MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16);
310     SDNode *Result = selectMULT(Node, MultOpc, DL, NodeTy, false, true).second;
311     return std::make_pair(true, Result);
312   }
313   }
314 
315   return std::make_pair(false, nullptr);
316 }
317 
318 FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM) {
319   return new Mips16DAGToDAGISel(TM);
320 }
321