1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the MipsMCCodeEmitter class. 11 // 12 //===----------------------------------------------------------------------===// 13 // 14 15 #include "MipsMCCodeEmitter.h" 16 #include "MCTargetDesc/MipsFixupKinds.h" 17 #include "MCTargetDesc/MipsMCExpr.h" 18 #include "MCTargetDesc/MipsMCTargetDesc.h" 19 #include "llvm/ADT/APFloat.h" 20 #include "llvm/ADT/SmallVector.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCExpr.h" 23 #include "llvm/MC/MCFixup.h" 24 #include "llvm/MC/MCInst.h" 25 #include "llvm/MC/MCInstrInfo.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 #define DEBUG_TYPE "mccodeemitter" 30 31 #define GET_INSTRMAP_INFO 32 #include "MipsGenInstrInfo.inc" 33 #undef GET_INSTRMAP_INFO 34 35 namespace llvm { 36 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, 37 const MCRegisterInfo &MRI, 38 const MCSubtargetInfo &STI, 39 MCContext &Ctx) { 40 return new MipsMCCodeEmitter(MCII, Ctx, false); 41 } 42 43 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, 44 const MCRegisterInfo &MRI, 45 const MCSubtargetInfo &STI, 46 MCContext &Ctx) { 47 return new MipsMCCodeEmitter(MCII, Ctx, true); 48 } 49 } // End of namespace llvm. 50 51 // If the D<shift> instruction has a shift amount that is greater 52 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction 53 static void LowerLargeShift(MCInst& Inst) { 54 55 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!"); 56 assert(Inst.getOperand(2).isImm()); 57 58 int64_t Shift = Inst.getOperand(2).getImm(); 59 if (Shift <= 31) 60 return; // Do nothing 61 Shift -= 32; 62 63 // saminus32 64 Inst.getOperand(2).setImm(Shift); 65 66 switch (Inst.getOpcode()) { 67 default: 68 // Calling function is not synchronized 69 llvm_unreachable("Unexpected shift instruction"); 70 case Mips::DSLL: 71 Inst.setOpcode(Mips::DSLL32); 72 return; 73 case Mips::DSRL: 74 Inst.setOpcode(Mips::DSRL32); 75 return; 76 case Mips::DSRA: 77 Inst.setOpcode(Mips::DSRA32); 78 return; 79 case Mips::DROTR: 80 Inst.setOpcode(Mips::DROTR32); 81 return; 82 } 83 } 84 85 // Pick a DEXT or DINS instruction variant based on the pos and size operands 86 static void LowerDextDins(MCInst& InstIn) { 87 int Opcode = InstIn.getOpcode(); 88 89 if (Opcode == Mips::DEXT) 90 assert(InstIn.getNumOperands() == 4 && 91 "Invalid no. of machine operands for DEXT!"); 92 else // Only DEXT and DINS are possible 93 assert(InstIn.getNumOperands() == 5 && 94 "Invalid no. of machine operands for DINS!"); 95 96 assert(InstIn.getOperand(2).isImm()); 97 int64_t pos = InstIn.getOperand(2).getImm(); 98 assert(InstIn.getOperand(3).isImm()); 99 int64_t size = InstIn.getOperand(3).getImm(); 100 101 if (size <= 32) { 102 if (pos < 32) // DEXT/DINS, do nothing 103 return; 104 // DEXTU/DINSU 105 InstIn.getOperand(2).setImm(pos - 32); 106 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU); 107 return; 108 } 109 // DEXTM/DINSM 110 assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32"); 111 InstIn.getOperand(3).setImm(size - 32); 112 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM); 113 return; 114 } 115 116 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const { 117 return STI.getFeatureBits() & Mips::FeatureMicroMips; 118 } 119 120 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const { 121 OS << (char)C; 122 } 123 124 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size, 125 const MCSubtargetInfo &STI, 126 raw_ostream &OS) const { 127 // Output the instruction encoding in little endian byte order. 128 // Little-endian byte ordering: 129 // mips32r2: 4 | 3 | 2 | 1 130 // microMIPS: 2 | 1 | 4 | 3 131 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) { 132 EmitInstruction(Val >> 16, 2, STI, OS); 133 EmitInstruction(Val, 2, STI, OS); 134 } else { 135 for (unsigned i = 0; i < Size; ++i) { 136 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8; 137 EmitByte((Val >> Shift) & 0xff, OS); 138 } 139 } 140 } 141 142 /// EncodeInstruction - Emit the instruction. 143 /// Size the instruction with Desc.getSize(). 144 void MipsMCCodeEmitter:: 145 EncodeInstruction(const MCInst &MI, raw_ostream &OS, 146 SmallVectorImpl<MCFixup> &Fixups, 147 const MCSubtargetInfo &STI) const 148 { 149 150 // Non-pseudo instructions that get changed for direct object 151 // only based on operand values. 152 // If this list of instructions get much longer we will move 153 // the check to a function call. Until then, this is more efficient. 154 MCInst TmpInst = MI; 155 switch (MI.getOpcode()) { 156 // If shift amount is >= 32 it the inst needs to be lowered further 157 case Mips::DSLL: 158 case Mips::DSRL: 159 case Mips::DSRA: 160 case Mips::DROTR: 161 LowerLargeShift(TmpInst); 162 break; 163 // Double extract instruction is chosen by pos and size operands 164 case Mips::DEXT: 165 case Mips::DINS: 166 LowerDextDins(TmpInst); 167 } 168 169 unsigned long N = Fixups.size(); 170 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 171 172 // Check for unimplemented opcodes. 173 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0 174 // so we have to special check for them. 175 unsigned Opcode = TmpInst.getOpcode(); 176 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && 177 (Opcode != Mips::SLL_MM) && !Binary) 178 llvm_unreachable("unimplemented opcode in EncodeInstruction()"); 179 180 if (STI.getFeatureBits() & Mips::FeatureMicroMips) { 181 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips); 182 if (NewOpcode != -1) { 183 if (Fixups.size() > N) 184 Fixups.pop_back(); 185 Opcode = NewOpcode; 186 TmpInst.setOpcode (NewOpcode); 187 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); 188 } 189 } 190 191 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode()); 192 193 // Get byte count of instruction 194 unsigned Size = Desc.getSize(); 195 if (!Size) 196 llvm_unreachable("Desc.getSize() returns 0"); 197 198 EmitInstruction(Binary, Size, STI, OS); 199 } 200 201 /// getBranchTargetOpValue - Return binary encoding of the branch 202 /// target operand. If the machine operand requires relocation, 203 /// record the relocation and return zero. 204 unsigned MipsMCCodeEmitter:: 205 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, 206 SmallVectorImpl<MCFixup> &Fixups, 207 const MCSubtargetInfo &STI) const { 208 209 const MCOperand &MO = MI.getOperand(OpNo); 210 211 // If the destination is an immediate, divide by 4. 212 if (MO.isImm()) return MO.getImm() >> 2; 213 214 assert(MO.isExpr() && 215 "getBranchTargetOpValue expects only expressions or immediates"); 216 217 const MCExpr *Expr = MO.getExpr(); 218 Fixups.push_back(MCFixup::Create(0, Expr, 219 MCFixupKind(Mips::fixup_Mips_PC16))); 220 return 0; 221 } 222 223 /// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch 224 /// target operand. If the machine operand requires relocation, 225 /// record the relocation and return zero. 226 unsigned MipsMCCodeEmitter:: 227 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo, 228 SmallVectorImpl<MCFixup> &Fixups, 229 const MCSubtargetInfo &STI) const { 230 231 const MCOperand &MO = MI.getOperand(OpNo); 232 233 // If the destination is an immediate, divide by 2. 234 if (MO.isImm()) return MO.getImm() >> 1; 235 236 assert(MO.isExpr() && 237 "getBranchTargetOpValueMM expects only expressions or immediates"); 238 239 const MCExpr *Expr = MO.getExpr(); 240 Fixups.push_back(MCFixup::Create(0, Expr, 241 MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1))); 242 return 0; 243 } 244 245 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch 246 /// target operand. If the machine operand requires relocation, 247 /// record the relocation and return zero. 248 unsigned MipsMCCodeEmitter:: 249 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, 250 SmallVectorImpl<MCFixup> &Fixups, 251 const MCSubtargetInfo &STI) const { 252 253 const MCOperand &MO = MI.getOperand(OpNo); 254 255 // If the destination is an immediate, divide by 2. 256 if (MO.isImm()) return MO.getImm() >> 1; 257 258 assert(MO.isExpr() && 259 "getBranchTargetOpValueMM expects only expressions or immediates"); 260 261 const MCExpr *Expr = MO.getExpr(); 262 Fixups.push_back(MCFixup::Create(0, Expr, 263 MCFixupKind(Mips:: 264 fixup_MICROMIPS_PC16_S1))); 265 return 0; 266 } 267 268 /// getBranchTarget21OpValue - Return binary encoding of the branch 269 /// target operand. If the machine operand requires relocation, 270 /// record the relocation and return zero. 271 unsigned MipsMCCodeEmitter:: 272 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo, 273 SmallVectorImpl<MCFixup> &Fixups, 274 const MCSubtargetInfo &STI) const { 275 276 const MCOperand &MO = MI.getOperand(OpNo); 277 278 // If the destination is an immediate, divide by 4. 279 if (MO.isImm()) return MO.getImm() >> 2; 280 281 assert(MO.isExpr() && 282 "getBranchTarget21OpValue expects only expressions or immediates"); 283 284 const MCExpr *Expr = MO.getExpr(); 285 Fixups.push_back(MCFixup::Create(0, Expr, 286 MCFixupKind(Mips::fixup_MIPS_PC21_S2))); 287 return 0; 288 } 289 290 /// getBranchTarget26OpValue - Return binary encoding of the branch 291 /// target operand. If the machine operand requires relocation, 292 /// record the relocation and return zero. 293 unsigned MipsMCCodeEmitter:: 294 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo, 295 SmallVectorImpl<MCFixup> &Fixups, 296 const MCSubtargetInfo &STI) const { 297 298 const MCOperand &MO = MI.getOperand(OpNo); 299 300 // If the destination is an immediate, divide by 4. 301 if (MO.isImm()) return MO.getImm() >> 2; 302 303 assert(MO.isExpr() && 304 "getBranchTarget26OpValue expects only expressions or immediates"); 305 306 const MCExpr *Expr = MO.getExpr(); 307 Fixups.push_back(MCFixup::Create(0, Expr, 308 MCFixupKind(Mips::fixup_MIPS_PC26_S2))); 309 return 0; 310 } 311 312 /// getJumpOffset16OpValue - Return binary encoding of the jump 313 /// target operand. If the machine operand requires relocation, 314 /// record the relocation and return zero. 315 unsigned MipsMCCodeEmitter:: 316 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo, 317 SmallVectorImpl<MCFixup> &Fixups, 318 const MCSubtargetInfo &STI) const { 319 320 const MCOperand &MO = MI.getOperand(OpNo); 321 322 if (MO.isImm()) return MO.getImm(); 323 324 assert(MO.isExpr() && 325 "getJumpOffset16OpValue expects only expressions or an immediate"); 326 327 // TODO: Push fixup. 328 return 0; 329 } 330 331 /// getJumpTargetOpValue - Return binary encoding of the jump 332 /// target operand. If the machine operand requires relocation, 333 /// record the relocation and return zero. 334 unsigned MipsMCCodeEmitter:: 335 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, 336 SmallVectorImpl<MCFixup> &Fixups, 337 const MCSubtargetInfo &STI) const { 338 339 const MCOperand &MO = MI.getOperand(OpNo); 340 // If the destination is an immediate, divide by 4. 341 if (MO.isImm()) return MO.getImm()>>2; 342 343 assert(MO.isExpr() && 344 "getJumpTargetOpValue expects only expressions or an immediate"); 345 346 const MCExpr *Expr = MO.getExpr(); 347 Fixups.push_back(MCFixup::Create(0, Expr, 348 MCFixupKind(Mips::fixup_Mips_26))); 349 return 0; 350 } 351 352 unsigned MipsMCCodeEmitter:: 353 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, 354 SmallVectorImpl<MCFixup> &Fixups, 355 const MCSubtargetInfo &STI) const { 356 357 const MCOperand &MO = MI.getOperand(OpNo); 358 // If the destination is an immediate, divide by 2. 359 if (MO.isImm()) return MO.getImm() >> 1; 360 361 assert(MO.isExpr() && 362 "getJumpTargetOpValueMM expects only expressions or an immediate"); 363 364 const MCExpr *Expr = MO.getExpr(); 365 Fixups.push_back(MCFixup::Create(0, Expr, 366 MCFixupKind(Mips::fixup_MICROMIPS_26_S1))); 367 return 0; 368 } 369 370 unsigned MipsMCCodeEmitter:: 371 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo, 372 SmallVectorImpl<MCFixup> &Fixups, 373 const MCSubtargetInfo &STI) const { 374 375 const MCOperand &MO = MI.getOperand(OpNo); 376 if (MO.isImm()) { 377 // The immediate is encoded as 'immediate << 2'. 378 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI); 379 assert((Res & 3) == 0); 380 return Res >> 2; 381 } 382 383 assert(MO.isExpr() && 384 "getUImm5Lsl2Encoding expects only expressions or an immediate"); 385 386 return 0; 387 } 388 389 unsigned MipsMCCodeEmitter:: 390 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo, 391 SmallVectorImpl<MCFixup> &Fixups, 392 const MCSubtargetInfo &STI) const { 393 394 const MCOperand &MO = MI.getOperand(OpNo); 395 if (MO.isImm()) { 396 int Value = MO.getImm(); 397 return Value >> 2; 398 } 399 400 return 0; 401 } 402 403 unsigned MipsMCCodeEmitter:: 404 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo, 405 SmallVectorImpl<MCFixup> &Fixups, 406 const MCSubtargetInfo &STI) const { 407 408 const MCOperand &MO = MI.getOperand(OpNo); 409 if (MO.isImm()) { 410 unsigned Value = MO.getImm(); 411 return Value >> 2; 412 } 413 414 return 0; 415 } 416 417 unsigned MipsMCCodeEmitter:: 418 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo, 419 SmallVectorImpl<MCFixup> &Fixups, 420 const MCSubtargetInfo &STI) const { 421 422 const MCOperand &MO = MI.getOperand(OpNo); 423 if (MO.isImm()) { 424 unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff; 425 return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff)); 426 } 427 428 return 0; 429 } 430 431 unsigned MipsMCCodeEmitter:: 432 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups, 433 const MCSubtargetInfo &STI) const { 434 int64_t Res; 435 436 if (Expr->EvaluateAsAbsolute(Res)) 437 return Res; 438 439 MCExpr::ExprKind Kind = Expr->getKind(); 440 if (Kind == MCExpr::Constant) { 441 return cast<MCConstantExpr>(Expr)->getValue(); 442 } 443 444 if (Kind == MCExpr::Binary) { 445 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI); 446 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI); 447 return Res; 448 } 449 450 if (Kind == MCExpr::Target) { 451 const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr); 452 453 Mips::Fixups FixupKind = Mips::Fixups(0); 454 switch (MipsExpr->getKind()) { 455 default: llvm_unreachable("Unsupported fixup kind for target expression!"); 456 case MipsMCExpr::VK_Mips_HIGHEST: 457 FixupKind = Mips::fixup_Mips_HIGHEST; 458 break; 459 case MipsMCExpr::VK_Mips_HIGHER: 460 FixupKind = Mips::fixup_Mips_HIGHER; 461 break; 462 case MipsMCExpr::VK_Mips_HI: 463 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16 464 : Mips::fixup_Mips_HI16; 465 break; 466 case MipsMCExpr::VK_Mips_LO: 467 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16 468 : Mips::fixup_Mips_LO16; 469 break; 470 } 471 Fixups.push_back(MCFixup::Create(0, MipsExpr, MCFixupKind(FixupKind))); 472 return 0; 473 } 474 475 if (Kind == MCExpr::SymbolRef) { 476 Mips::Fixups FixupKind = Mips::Fixups(0); 477 478 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) { 479 default: llvm_unreachable("Unknown fixup kind!"); 480 break; 481 case MCSymbolRefExpr::VK_Mips_GPOFF_HI : 482 FixupKind = Mips::fixup_Mips_GPOFF_HI; 483 break; 484 case MCSymbolRefExpr::VK_Mips_GPOFF_LO : 485 FixupKind = Mips::fixup_Mips_GPOFF_LO; 486 break; 487 case MCSymbolRefExpr::VK_Mips_GOT_PAGE : 488 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE 489 : Mips::fixup_Mips_GOT_PAGE; 490 break; 491 case MCSymbolRefExpr::VK_Mips_GOT_OFST : 492 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST 493 : Mips::fixup_Mips_GOT_OFST; 494 break; 495 case MCSymbolRefExpr::VK_Mips_GOT_DISP : 496 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP 497 : Mips::fixup_Mips_GOT_DISP; 498 break; 499 case MCSymbolRefExpr::VK_Mips_GPREL: 500 FixupKind = Mips::fixup_Mips_GPREL16; 501 break; 502 case MCSymbolRefExpr::VK_Mips_GOT_CALL: 503 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16 504 : Mips::fixup_Mips_CALL16; 505 break; 506 case MCSymbolRefExpr::VK_Mips_GOT16: 507 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16 508 : Mips::fixup_Mips_GOT_Global; 509 break; 510 case MCSymbolRefExpr::VK_Mips_GOT: 511 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16 512 : Mips::fixup_Mips_GOT_Local; 513 break; 514 case MCSymbolRefExpr::VK_Mips_ABS_HI: 515 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16 516 : Mips::fixup_Mips_HI16; 517 break; 518 case MCSymbolRefExpr::VK_Mips_ABS_LO: 519 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16 520 : Mips::fixup_Mips_LO16; 521 break; 522 case MCSymbolRefExpr::VK_Mips_TLSGD: 523 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD 524 : Mips::fixup_Mips_TLSGD; 525 break; 526 case MCSymbolRefExpr::VK_Mips_TLSLDM: 527 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM 528 : Mips::fixup_Mips_TLSLDM; 529 break; 530 case MCSymbolRefExpr::VK_Mips_DTPREL_HI: 531 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16 532 : Mips::fixup_Mips_DTPREL_HI; 533 break; 534 case MCSymbolRefExpr::VK_Mips_DTPREL_LO: 535 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16 536 : Mips::fixup_Mips_DTPREL_LO; 537 break; 538 case MCSymbolRefExpr::VK_Mips_GOTTPREL: 539 FixupKind = Mips::fixup_Mips_GOTTPREL; 540 break; 541 case MCSymbolRefExpr::VK_Mips_TPREL_HI: 542 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16 543 : Mips::fixup_Mips_TPREL_HI; 544 break; 545 case MCSymbolRefExpr::VK_Mips_TPREL_LO: 546 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16 547 : Mips::fixup_Mips_TPREL_LO; 548 break; 549 case MCSymbolRefExpr::VK_Mips_HIGHER: 550 FixupKind = Mips::fixup_Mips_HIGHER; 551 break; 552 case MCSymbolRefExpr::VK_Mips_HIGHEST: 553 FixupKind = Mips::fixup_Mips_HIGHEST; 554 break; 555 case MCSymbolRefExpr::VK_Mips_GOT_HI16: 556 FixupKind = Mips::fixup_Mips_GOT_HI16; 557 break; 558 case MCSymbolRefExpr::VK_Mips_GOT_LO16: 559 FixupKind = Mips::fixup_Mips_GOT_LO16; 560 break; 561 case MCSymbolRefExpr::VK_Mips_CALL_HI16: 562 FixupKind = Mips::fixup_Mips_CALL_HI16; 563 break; 564 case MCSymbolRefExpr::VK_Mips_CALL_LO16: 565 FixupKind = Mips::fixup_Mips_CALL_LO16; 566 break; 567 case MCSymbolRefExpr::VK_Mips_PCREL_HI16: 568 FixupKind = Mips::fixup_MIPS_PCHI16; 569 break; 570 case MCSymbolRefExpr::VK_Mips_PCREL_LO16: 571 FixupKind = Mips::fixup_MIPS_PCLO16; 572 break; 573 } // switch 574 575 Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind))); 576 return 0; 577 } 578 return 0; 579 } 580 581 /// getMachineOpValue - Return binary encoding of operand. If the machine 582 /// operand requires relocation, record the relocation and return zero. 583 unsigned MipsMCCodeEmitter:: 584 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 585 SmallVectorImpl<MCFixup> &Fixups, 586 const MCSubtargetInfo &STI) const { 587 if (MO.isReg()) { 588 unsigned Reg = MO.getReg(); 589 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg); 590 return RegNo; 591 } else if (MO.isImm()) { 592 return static_cast<unsigned>(MO.getImm()); 593 } else if (MO.isFPImm()) { 594 return static_cast<unsigned>(APFloat(MO.getFPImm()) 595 .bitcastToAPInt().getHiBits(32).getLimitedValue()); 596 } 597 // MO must be an Expr. 598 assert(MO.isExpr()); 599 return getExprOpValue(MO.getExpr(),Fixups, STI); 600 } 601 602 /// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST 603 /// instructions. 604 unsigned 605 MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo, 606 SmallVectorImpl<MCFixup> &Fixups, 607 const MCSubtargetInfo &STI) const { 608 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0. 609 assert(MI.getOperand(OpNo).isReg()); 610 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16; 611 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); 612 613 // The immediate field of an LD/ST instruction is scaled which means it must 614 // be divided (when encoding) by the size (in bytes) of the instructions' 615 // data format. 616 // .b - 1 byte 617 // .h - 2 bytes 618 // .w - 4 bytes 619 // .d - 8 bytes 620 switch(MI.getOpcode()) 621 { 622 default: 623 assert (0 && "Unexpected instruction"); 624 break; 625 case Mips::LD_B: 626 case Mips::ST_B: 627 // We don't need to scale the offset in this case 628 break; 629 case Mips::LD_H: 630 case Mips::ST_H: 631 OffBits >>= 1; 632 break; 633 case Mips::LD_W: 634 case Mips::ST_W: 635 OffBits >>= 2; 636 break; 637 case Mips::LD_D: 638 case Mips::ST_D: 639 OffBits >>= 3; 640 break; 641 } 642 643 return (OffBits & 0xFFFF) | RegBits; 644 } 645 646 /// getMemEncoding - Return binary encoding of memory related operand. 647 /// If the offset operand requires relocation, record the relocation. 648 unsigned 649 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo, 650 SmallVectorImpl<MCFixup> &Fixups, 651 const MCSubtargetInfo &STI) const { 652 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0. 653 assert(MI.getOperand(OpNo).isReg()); 654 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16; 655 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); 656 657 return (OffBits & 0xFFFF) | RegBits; 658 } 659 660 unsigned MipsMCCodeEmitter:: 661 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo, 662 SmallVectorImpl<MCFixup> &Fixups, 663 const MCSubtargetInfo &STI) const { 664 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0. 665 assert(MI.getOperand(OpNo).isReg()); 666 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), 667 Fixups, STI) << 4; 668 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), 669 Fixups, STI); 670 671 return (OffBits & 0xF) | RegBits; 672 } 673 674 unsigned MipsMCCodeEmitter:: 675 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo, 676 SmallVectorImpl<MCFixup> &Fixups, 677 const MCSubtargetInfo &STI) const { 678 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0. 679 assert(MI.getOperand(OpNo).isReg()); 680 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), 681 Fixups, STI) << 4; 682 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), 683 Fixups, STI) >> 1; 684 685 return (OffBits & 0xF) | RegBits; 686 } 687 688 unsigned MipsMCCodeEmitter:: 689 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo, 690 SmallVectorImpl<MCFixup> &Fixups, 691 const MCSubtargetInfo &STI) const { 692 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0. 693 assert(MI.getOperand(OpNo).isReg()); 694 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), 695 Fixups, STI) << 4; 696 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), 697 Fixups, STI) >> 2; 698 699 return (OffBits & 0xF) | RegBits; 700 } 701 702 unsigned MipsMCCodeEmitter:: 703 getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo, 704 SmallVectorImpl<MCFixup> &Fixups, 705 const MCSubtargetInfo &STI) const { 706 // Register is encoded in bits 9-5, offset is encoded in bits 4-0. 707 assert(MI.getOperand(OpNo).isReg() && 708 MI.getOperand(OpNo).getReg() == Mips::SP && 709 "Unexpected base register!"); 710 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), 711 Fixups, STI) >> 2; 712 713 return OffBits & 0x1F; 714 } 715 716 unsigned MipsMCCodeEmitter:: 717 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, 718 SmallVectorImpl<MCFixup> &Fixups, 719 const MCSubtargetInfo &STI) const { 720 // opNum can be invalid if instruction had reglist as operand. 721 // MemOperand is always last operand of instruction (base + offset). 722 switch (MI.getOpcode()) { 723 default: 724 break; 725 case Mips::SWM32_MM: 726 case Mips::LWM32_MM: 727 OpNo = MI.getNumOperands() - 2; 728 break; 729 } 730 731 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0. 732 assert(MI.getOperand(OpNo).isReg()); 733 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16; 734 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); 735 736 return (OffBits & 0x0FFF) | RegBits; 737 } 738 739 unsigned MipsMCCodeEmitter:: 740 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, 741 SmallVectorImpl<MCFixup> &Fixups, 742 const MCSubtargetInfo &STI) const { 743 // opNum can be invalid if instruction had reglist as operand 744 // MemOperand is always last operand of instruction (base + offset) 745 switch (MI.getOpcode()) { 746 default: 747 break; 748 case Mips::SWM16_MM: 749 case Mips::LWM16_MM: 750 OpNo = MI.getNumOperands() - 2; 751 break; 752 } 753 754 // Offset is encoded in bits 4-0. 755 assert(MI.getOperand(OpNo).isReg()); 756 // Base register is always SP - thus it is not encoded. 757 assert(MI.getOperand(OpNo+1).isImm()); 758 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); 759 760 return ((OffBits >> 2) & 0x0F); 761 } 762 763 unsigned 764 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo, 765 SmallVectorImpl<MCFixup> &Fixups, 766 const MCSubtargetInfo &STI) const { 767 assert(MI.getOperand(OpNo).isImm()); 768 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); 769 return SizeEncoding - 1; 770 } 771 772 // FIXME: should be called getMSBEncoding 773 // 774 unsigned 775 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo, 776 SmallVectorImpl<MCFixup> &Fixups, 777 const MCSubtargetInfo &STI) const { 778 assert(MI.getOperand(OpNo-1).isImm()); 779 assert(MI.getOperand(OpNo).isImm()); 780 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI); 781 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); 782 783 return Position + Size - 1; 784 } 785 786 unsigned 787 MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo, 788 SmallVectorImpl<MCFixup> &Fixups, 789 const MCSubtargetInfo &STI) const { 790 assert(MI.getOperand(OpNo).isImm()); 791 // The immediate is encoded as 'immediate - 1'. 792 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1; 793 } 794 795 unsigned 796 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo, 797 SmallVectorImpl<MCFixup> &Fixups, 798 const MCSubtargetInfo &STI) const { 799 const MCOperand &MO = MI.getOperand(OpNo); 800 if (MO.isImm()) { 801 // The immediate is encoded as 'immediate << 2'. 802 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI); 803 assert((Res & 3) == 0); 804 return Res >> 2; 805 } 806 807 assert(MO.isExpr() && 808 "getSimm19Lsl2Encoding expects only expressions or an immediate"); 809 810 const MCExpr *Expr = MO.getExpr(); 811 Fixups.push_back(MCFixup::Create(0, Expr, 812 MCFixupKind(Mips::fixup_MIPS_PC19_S2))); 813 return 0; 814 } 815 816 unsigned 817 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo, 818 SmallVectorImpl<MCFixup> &Fixups, 819 const MCSubtargetInfo &STI) const { 820 const MCOperand &MO = MI.getOperand(OpNo); 821 if (MO.isImm()) { 822 // The immediate is encoded as 'immediate << 3'. 823 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); 824 assert((Res & 7) == 0); 825 return Res >> 3; 826 } 827 828 assert(MO.isExpr() && 829 "getSimm18Lsl2Encoding expects only expressions or an immediate"); 830 831 const MCExpr *Expr = MO.getExpr(); 832 Fixups.push_back(MCFixup::Create(0, Expr, 833 MCFixupKind(Mips::fixup_MIPS_PC18_S3))); 834 return 0; 835 } 836 837 unsigned 838 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo, 839 SmallVectorImpl<MCFixup> &Fixups, 840 const MCSubtargetInfo &STI) const { 841 assert(MI.getOperand(OpNo).isImm()); 842 const MCOperand &MO = MI.getOperand(OpNo); 843 return MO.getImm() % 8; 844 } 845 846 unsigned 847 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo, 848 SmallVectorImpl<MCFixup> &Fixups, 849 const MCSubtargetInfo &STI) const { 850 assert(MI.getOperand(OpNo).isImm()); 851 const MCOperand &MO = MI.getOperand(OpNo); 852 unsigned Value = MO.getImm(); 853 switch (Value) { 854 case 128: return 0x0; 855 case 1: return 0x1; 856 case 2: return 0x2; 857 case 3: return 0x3; 858 case 4: return 0x4; 859 case 7: return 0x5; 860 case 8: return 0x6; 861 case 15: return 0x7; 862 case 16: return 0x8; 863 case 31: return 0x9; 864 case 32: return 0xa; 865 case 63: return 0xb; 866 case 64: return 0xc; 867 case 255: return 0xd; 868 case 32768: return 0xe; 869 case 65535: return 0xf; 870 } 871 llvm_unreachable("Unexpected value"); 872 } 873 874 unsigned 875 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo, 876 SmallVectorImpl<MCFixup> &Fixups, 877 const MCSubtargetInfo &STI) const { 878 unsigned res = 0; 879 880 // Register list operand is always first operand of instruction and it is 881 // placed before memory operand (register + imm). 882 883 for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) { 884 unsigned Reg = MI.getOperand(I).getReg(); 885 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg); 886 if (RegNo != 31) 887 res++; 888 else 889 res |= 0x10; 890 } 891 return res; 892 } 893 894 unsigned 895 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo, 896 SmallVectorImpl<MCFixup> &Fixups, 897 const MCSubtargetInfo &STI) const { 898 return (MI.getNumOperands() - 4); 899 } 900 901 unsigned 902 MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo, 903 SmallVectorImpl<MCFixup> &Fixups, 904 const MCSubtargetInfo &STI) const { 905 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); 906 } 907 908 #include "MipsGenMCCodeEmitter.inc" 909