1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the MipsMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsMCCodeEmitter.h"
15 #include "MCTargetDesc/MipsFixupKinds.h"
16 #include "MCTargetDesc/MipsMCExpr.h"
17 #include "MCTargetDesc/MipsMCTargetDesc.h"
18 #include "llvm/ADT/APFloat.h"
19 #include "llvm/ADT/APInt.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCFixup.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/MC/MCInstrInfo.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/Support/Casting.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include <cassert>
33 #include <cstdint>
34 
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "mccodeemitter"
38 
39 #define GET_INSTRMAP_INFO
40 #include "MipsGenInstrInfo.inc"
41 #undef GET_INSTRMAP_INFO
42 
43 namespace llvm {
44 
45 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
46                                          const MCRegisterInfo &MRI,
47                                          MCContext &Ctx) {
48   return new MipsMCCodeEmitter(MCII, Ctx, false);
49 }
50 
51 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
52                                          const MCRegisterInfo &MRI,
53                                          MCContext &Ctx) {
54   return new MipsMCCodeEmitter(MCII, Ctx, true);
55 }
56 
57 } // end namespace llvm
58 
59 // If the D<shift> instruction has a shift amount that is greater
60 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
61 static void LowerLargeShift(MCInst& Inst) {
62   assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
63   assert(Inst.getOperand(2).isImm());
64 
65   int64_t Shift = Inst.getOperand(2).getImm();
66   if (Shift <= 31)
67     return; // Do nothing
68   Shift -= 32;
69 
70   // saminus32
71   Inst.getOperand(2).setImm(Shift);
72 
73   switch (Inst.getOpcode()) {
74   default:
75     // Calling function is not synchronized
76     llvm_unreachable("Unexpected shift instruction");
77   case Mips::DSLL:
78     Inst.setOpcode(Mips::DSLL32);
79     return;
80   case Mips::DSRL:
81     Inst.setOpcode(Mips::DSRL32);
82     return;
83   case Mips::DSRA:
84     Inst.setOpcode(Mips::DSRA32);
85     return;
86   case Mips::DROTR:
87     Inst.setOpcode(Mips::DROTR32);
88     return;
89   }
90 }
91 
92 // Fix a bad compact branch encoding for beqc/bnec.
93 void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {
94   // Encoding may be illegal !(rs < rt), but this situation is
95   // easily fixed.
96   unsigned RegOp0 = Inst.getOperand(0).getReg();
97   unsigned RegOp1 = Inst.getOperand(1).getReg();
98 
99   unsigned Reg0 =  Ctx.getRegisterInfo()->getEncodingValue(RegOp0);
100   unsigned Reg1 =  Ctx.getRegisterInfo()->getEncodingValue(RegOp1);
101 
102   if (Inst.getOpcode() == Mips::BNEC || Inst.getOpcode() == Mips::BEQC ||
103       Inst.getOpcode() == Mips::BNEC64 || Inst.getOpcode() == Mips::BEQC64) {
104     assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!");
105     if (Reg0 < Reg1)
106       return;
107   } else if (Inst.getOpcode() == Mips::BNVC || Inst.getOpcode() == Mips::BOVC) {
108     if (Reg0 >= Reg1)
109       return;
110   } else if (Inst.getOpcode() == Mips::BNVC_MMR6 ||
111              Inst.getOpcode() == Mips::BOVC_MMR6) {
112     if (Reg1 >= Reg0)
113       return;
114   } else
115     llvm_unreachable("Cannot rewrite unknown branch!");
116 
117   Inst.getOperand(0).setReg(RegOp1);
118   Inst.getOperand(1).setReg(RegOp0);
119 }
120 
121 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
122   return STI.getFeatureBits()[Mips::FeatureMicroMips];
123 }
124 
125 bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const {
126   return STI.getFeatureBits()[Mips::FeatureMips32r6];
127 }
128 
129 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
130   OS << (char)C;
131 }
132 
133 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
134                                         const MCSubtargetInfo &STI,
135                                         raw_ostream &OS) const {
136   // Output the instruction encoding in little endian byte order.
137   // Little-endian byte ordering:
138   //   mips32r2:   4 | 3 | 2 | 1
139   //   microMIPS:  2 | 1 | 4 | 3
140   if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
141     EmitInstruction(Val >> 16, 2, STI, OS);
142     EmitInstruction(Val, 2, STI, OS);
143   } else {
144     for (unsigned i = 0; i < Size; ++i) {
145       unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
146       EmitByte((Val >> Shift) & 0xff, OS);
147     }
148   }
149 }
150 
151 /// encodeInstruction - Emit the instruction.
152 /// Size the instruction with Desc.getSize().
153 void MipsMCCodeEmitter::
154 encodeInstruction(const MCInst &MI, raw_ostream &OS,
155                   SmallVectorImpl<MCFixup> &Fixups,
156                   const MCSubtargetInfo &STI) const
157 {
158   // Non-pseudo instructions that get changed for direct object
159   // only based on operand values.
160   // If this list of instructions get much longer we will move
161   // the check to a function call. Until then, this is more efficient.
162   MCInst TmpInst = MI;
163   switch (MI.getOpcode()) {
164   // If shift amount is >= 32 it the inst needs to be lowered further
165   case Mips::DSLL:
166   case Mips::DSRL:
167   case Mips::DSRA:
168   case Mips::DROTR:
169     LowerLargeShift(TmpInst);
170     break;
171   // Compact branches, enforce encoding restrictions.
172   case Mips::BEQC:
173   case Mips::BNEC:
174   case Mips::BEQC64:
175   case Mips::BNEC64:
176   case Mips::BOVC:
177   case Mips::BOVC_MMR6:
178   case Mips::BNVC:
179   case Mips::BNVC_MMR6:
180     LowerCompactBranch(TmpInst);
181   }
182 
183   unsigned long N = Fixups.size();
184   uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
185 
186   // Check for unimplemented opcodes.
187   // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
188   // so we have to special check for them.
189   unsigned Opcode = TmpInst.getOpcode();
190   if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
191       (Opcode != Mips::SLL_MM) && (Opcode != Mips::SLL_MMR6) && !Binary)
192     llvm_unreachable("unimplemented opcode in encodeInstruction()");
193 
194   int NewOpcode = -1;
195   if (isMicroMips(STI)) {
196     if (isMips32r6(STI)) {
197       NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
198       if (NewOpcode == -1)
199         NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
200     }
201     else
202       NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
203 
204     // Check whether it is Dsp instruction.
205     if (NewOpcode == -1)
206       NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp);
207 
208     if (NewOpcode != -1) {
209       if (Fixups.size() > N)
210         Fixups.pop_back();
211 
212       Opcode = NewOpcode;
213       TmpInst.setOpcode (NewOpcode);
214       Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
215     }
216 
217     if (((MI.getOpcode() == Mips::MOVEP_MM) ||
218          (MI.getOpcode() == Mips::MOVEP_MMR6))) {
219       unsigned RegPair = getMovePRegPairOpValue(MI, 0, Fixups, STI);
220       Binary = (Binary & 0xFFFFFC7F) | (RegPair << 7);
221     }
222   }
223 
224   const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
225 
226   // Get byte count of instruction
227   unsigned Size = Desc.getSize();
228   if (!Size)
229     llvm_unreachable("Desc.getSize() returns 0");
230 
231   EmitInstruction(Binary, Size, STI, OS);
232 }
233 
234 /// getBranchTargetOpValue - Return binary encoding of the branch
235 /// target operand. If the machine operand requires relocation,
236 /// record the relocation and return zero.
237 unsigned MipsMCCodeEmitter::
238 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
239                        SmallVectorImpl<MCFixup> &Fixups,
240                        const MCSubtargetInfo &STI) const {
241   const MCOperand &MO = MI.getOperand(OpNo);
242 
243   // If the destination is an immediate, divide by 4.
244   if (MO.isImm()) return MO.getImm() >> 2;
245 
246   assert(MO.isExpr() &&
247          "getBranchTargetOpValue expects only expressions or immediates");
248 
249   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
250       MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
251   Fixups.push_back(MCFixup::create(0, FixupExpression,
252                                    MCFixupKind(Mips::fixup_Mips_PC16)));
253   return 0;
254 }
255 
256 /// getBranchTargetOpValue1SImm16 - Return binary encoding of the branch
257 /// target operand. If the machine operand requires relocation,
258 /// record the relocation and return zero.
259 unsigned MipsMCCodeEmitter::
260 getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo,
261                               SmallVectorImpl<MCFixup> &Fixups,
262                               const MCSubtargetInfo &STI) const {
263   const MCOperand &MO = MI.getOperand(OpNo);
264 
265   // If the destination is an immediate, divide by 2.
266   if (MO.isImm()) return MO.getImm() >> 1;
267 
268   assert(MO.isExpr() &&
269          "getBranchTargetOpValue expects only expressions or immediates");
270 
271   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
272       MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
273   Fixups.push_back(MCFixup::create(0, FixupExpression,
274                                    MCFixupKind(Mips::fixup_Mips_PC16)));
275   return 0;
276 }
277 
278 /// getBranchTargetOpValueMMR6 - Return binary encoding of the branch
279 /// target operand. If the machine operand requires relocation,
280 /// record the relocation and return zero.
281 unsigned MipsMCCodeEmitter::
282 getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo,
283                            SmallVectorImpl<MCFixup> &Fixups,
284                            const MCSubtargetInfo &STI) const {
285   const MCOperand &MO = MI.getOperand(OpNo);
286 
287   // If the destination is an immediate, divide by 2.
288   if (MO.isImm())
289     return MO.getImm() >> 1;
290 
291   assert(MO.isExpr() &&
292          "getBranchTargetOpValueMMR6 expects only expressions or immediates");
293 
294   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
295       MO.getExpr(), MCConstantExpr::create(-2, Ctx), Ctx);
296   Fixups.push_back(MCFixup::create(0, FixupExpression,
297                                    MCFixupKind(Mips::fixup_Mips_PC16)));
298   return 0;
299 }
300 
301 /// getBranchTargetOpValueLsl2MMR6 - Return binary encoding of the branch
302 /// target operand. If the machine operand requires relocation,
303 /// record the relocation and return zero.
304 unsigned MipsMCCodeEmitter::
305 getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo,
306                                SmallVectorImpl<MCFixup> &Fixups,
307                                const MCSubtargetInfo &STI) const {
308   const MCOperand &MO = MI.getOperand(OpNo);
309 
310   // If the destination is an immediate, divide by 4.
311   if (MO.isImm())
312     return MO.getImm() >> 2;
313 
314   assert(MO.isExpr() &&
315          "getBranchTargetOpValueLsl2MMR6 expects only expressions or immediates");
316 
317   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
318       MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
319   Fixups.push_back(MCFixup::create(0, FixupExpression,
320                                    MCFixupKind(Mips::fixup_Mips_PC16)));
321   return 0;
322 }
323 
324 /// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch
325 /// target operand. If the machine operand requires relocation,
326 /// record the relocation and return zero.
327 unsigned MipsMCCodeEmitter::
328 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
329                           SmallVectorImpl<MCFixup> &Fixups,
330                           const MCSubtargetInfo &STI) const {
331   const MCOperand &MO = MI.getOperand(OpNo);
332 
333   // If the destination is an immediate, divide by 2.
334   if (MO.isImm()) return MO.getImm() >> 1;
335 
336   assert(MO.isExpr() &&
337          "getBranchTargetOpValueMM expects only expressions or immediates");
338 
339   const MCExpr *Expr = MO.getExpr();
340   Fixups.push_back(MCFixup::create(0, Expr,
341                                    MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1)));
342   return 0;
343 }
344 
345 /// getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS
346 /// 10-bit branch target operand. If the machine operand requires relocation,
347 /// record the relocation and return zero.
348 unsigned MipsMCCodeEmitter::
349 getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
350                              SmallVectorImpl<MCFixup> &Fixups,
351                              const MCSubtargetInfo &STI) const {
352   const MCOperand &MO = MI.getOperand(OpNo);
353 
354   // If the destination is an immediate, divide by 2.
355   if (MO.isImm()) return MO.getImm() >> 1;
356 
357   assert(MO.isExpr() &&
358          "getBranchTargetOpValuePC10 expects only expressions or immediates");
359 
360   const MCExpr *Expr = MO.getExpr();
361   Fixups.push_back(MCFixup::create(0, Expr,
362                    MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1)));
363   return 0;
364 }
365 
366 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
367 /// target operand. If the machine operand requires relocation,
368 /// record the relocation and return zero.
369 unsigned MipsMCCodeEmitter::
370 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
371                          SmallVectorImpl<MCFixup> &Fixups,
372                          const MCSubtargetInfo &STI) const {
373   const MCOperand &MO = MI.getOperand(OpNo);
374 
375   // If the destination is an immediate, divide by 2.
376   if (MO.isImm()) return MO.getImm() >> 1;
377 
378   assert(MO.isExpr() &&
379          "getBranchTargetOpValueMM expects only expressions or immediates");
380 
381   const MCExpr *Expr = MO.getExpr();
382   Fixups.push_back(MCFixup::create(0, Expr,
383                    MCFixupKind(Mips::
384                                fixup_MICROMIPS_PC16_S1)));
385   return 0;
386 }
387 
388 /// getBranchTarget21OpValue - Return binary encoding of the branch
389 /// target operand. If the machine operand requires relocation,
390 /// record the relocation and return zero.
391 unsigned MipsMCCodeEmitter::
392 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
393                          SmallVectorImpl<MCFixup> &Fixups,
394                          const MCSubtargetInfo &STI) const {
395   const MCOperand &MO = MI.getOperand(OpNo);
396 
397   // If the destination is an immediate, divide by 4.
398   if (MO.isImm()) return MO.getImm() >> 2;
399 
400   assert(MO.isExpr() &&
401          "getBranchTarget21OpValue expects only expressions or immediates");
402 
403   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
404       MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
405   Fixups.push_back(MCFixup::create(0, FixupExpression,
406                                    MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
407   return 0;
408 }
409 
410 /// getBranchTarget21OpValueMM - Return binary encoding of the branch
411 /// target operand for microMIPS. If the machine operand requires
412 /// relocation, record the relocation and return zero.
413 unsigned MipsMCCodeEmitter::
414 getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo,
415                            SmallVectorImpl<MCFixup> &Fixups,
416                            const MCSubtargetInfo &STI) const {
417   const MCOperand &MO = MI.getOperand(OpNo);
418 
419   // If the destination is an immediate, divide by 4.
420   if (MO.isImm()) return MO.getImm() >> 2;
421 
422   assert(MO.isExpr() &&
423     "getBranchTarget21OpValueMM expects only expressions or immediates");
424 
425   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
426       MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
427   Fixups.push_back(MCFixup::create(0, FixupExpression,
428                                    MCFixupKind(Mips::fixup_MICROMIPS_PC21_S1)));
429   return 0;
430 }
431 
432 /// getBranchTarget26OpValue - Return binary encoding of the branch
433 /// target operand. If the machine operand requires relocation,
434 /// record the relocation and return zero.
435 unsigned MipsMCCodeEmitter::
436 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
437                          SmallVectorImpl<MCFixup> &Fixups,
438                          const MCSubtargetInfo &STI) const {
439   const MCOperand &MO = MI.getOperand(OpNo);
440 
441   // If the destination is an immediate, divide by 4.
442   if (MO.isImm()) return MO.getImm() >> 2;
443 
444   assert(MO.isExpr() &&
445          "getBranchTarget26OpValue expects only expressions or immediates");
446 
447   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
448       MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
449   Fixups.push_back(MCFixup::create(0, FixupExpression,
450                                    MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
451   return 0;
452 }
453 
454 /// getBranchTarget26OpValueMM - Return binary encoding of the branch
455 /// target operand. If the machine operand requires relocation,
456 /// record the relocation and return zero.
457 unsigned MipsMCCodeEmitter::getBranchTarget26OpValueMM(
458     const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
459     const MCSubtargetInfo &STI) const {
460   const MCOperand &MO = MI.getOperand(OpNo);
461 
462   // If the destination is an immediate, divide by 2.
463   if (MO.isImm())
464     return MO.getImm() >> 1;
465 
466   assert(MO.isExpr() &&
467          "getBranchTarget26OpValueMM expects only expressions or immediates");
468 
469   const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
470       MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
471   Fixups.push_back(MCFixup::create(0, FixupExpression,
472                                    MCFixupKind(Mips::fixup_MICROMIPS_PC26_S1)));
473   return 0;
474 }
475 
476 /// getJumpOffset16OpValue - Return binary encoding of the jump
477 /// target operand. If the machine operand requires relocation,
478 /// record the relocation and return zero.
479 unsigned MipsMCCodeEmitter::
480 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
481                        SmallVectorImpl<MCFixup> &Fixups,
482                        const MCSubtargetInfo &STI) const {
483   const MCOperand &MO = MI.getOperand(OpNo);
484 
485   if (MO.isImm()) return MO.getImm();
486 
487   assert(MO.isExpr() &&
488          "getJumpOffset16OpValue expects only expressions or an immediate");
489 
490    // TODO: Push fixup.
491    return 0;
492 }
493 
494 /// getJumpTargetOpValue - Return binary encoding of the jump
495 /// target operand. If the machine operand requires relocation,
496 /// record the relocation and return zero.
497 unsigned MipsMCCodeEmitter::
498 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
499                      SmallVectorImpl<MCFixup> &Fixups,
500                      const MCSubtargetInfo &STI) const {
501   const MCOperand &MO = MI.getOperand(OpNo);
502   // If the destination is an immediate, divide by 4.
503   if (MO.isImm()) return MO.getImm()>>2;
504 
505   assert(MO.isExpr() &&
506          "getJumpTargetOpValue expects only expressions or an immediate");
507 
508   const MCExpr *Expr = MO.getExpr();
509   Fixups.push_back(MCFixup::create(0, Expr,
510                                    MCFixupKind(Mips::fixup_Mips_26)));
511   return 0;
512 }
513 
514 unsigned MipsMCCodeEmitter::
515 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
516                        SmallVectorImpl<MCFixup> &Fixups,
517                        const MCSubtargetInfo &STI) const {
518   const MCOperand &MO = MI.getOperand(OpNo);
519   // If the destination is an immediate, divide by 2.
520   if (MO.isImm()) return MO.getImm() >> 1;
521 
522   assert(MO.isExpr() &&
523          "getJumpTargetOpValueMM expects only expressions or an immediate");
524 
525   const MCExpr *Expr = MO.getExpr();
526   Fixups.push_back(MCFixup::create(0, Expr,
527                                    MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
528   return 0;
529 }
530 
531 unsigned MipsMCCodeEmitter::
532 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
533                      SmallVectorImpl<MCFixup> &Fixups,
534                      const MCSubtargetInfo &STI) const {
535   const MCOperand &MO = MI.getOperand(OpNo);
536   if (MO.isImm()) {
537     // The immediate is encoded as 'immediate << 2'.
538     unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
539     assert((Res & 3) == 0);
540     return Res >> 2;
541   }
542 
543   assert(MO.isExpr() &&
544          "getUImm5Lsl2Encoding expects only expressions or an immediate");
545 
546   return 0;
547 }
548 
549 unsigned MipsMCCodeEmitter::
550 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
551                   SmallVectorImpl<MCFixup> &Fixups,
552                   const MCSubtargetInfo &STI) const {
553   const MCOperand &MO = MI.getOperand(OpNo);
554   if (MO.isImm()) {
555     int Value = MO.getImm();
556     return Value >> 2;
557   }
558 
559   return 0;
560 }
561 
562 unsigned MipsMCCodeEmitter::
563 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
564                      SmallVectorImpl<MCFixup> &Fixups,
565                      const MCSubtargetInfo &STI) const {
566   const MCOperand &MO = MI.getOperand(OpNo);
567   if (MO.isImm()) {
568     unsigned Value = MO.getImm();
569     return Value >> 2;
570   }
571 
572   return 0;
573 }
574 
575 unsigned MipsMCCodeEmitter::
576 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
577                      SmallVectorImpl<MCFixup> &Fixups,
578                      const MCSubtargetInfo &STI) const {
579   const MCOperand &MO = MI.getOperand(OpNo);
580   if (MO.isImm()) {
581     unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff;
582     return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
583   }
584 
585   return 0;
586 }
587 
588 unsigned MipsMCCodeEmitter::
589 getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
590                const MCSubtargetInfo &STI) const {
591   int64_t Res;
592 
593   if (Expr->evaluateAsAbsolute(Res))
594     return Res;
595 
596   MCExpr::ExprKind Kind = Expr->getKind();
597   if (Kind == MCExpr::Constant) {
598     return cast<MCConstantExpr>(Expr)->getValue();
599   }
600 
601   if (Kind == MCExpr::Binary) {
602     unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
603     Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
604     return Res;
605   }
606 
607   if (Kind == MCExpr::Target) {
608     const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
609 
610     Mips::Fixups FixupKind = Mips::Fixups(0);
611     switch (MipsExpr->getKind()) {
612     case MipsMCExpr::MEK_None:
613     case MipsMCExpr::MEK_Special:
614       llvm_unreachable("Unhandled fixup kind!");
615       break;
616     case MipsMCExpr::MEK_DTPREL:
617       // MEK_DTPREL is used for marking TLS DIEExpr only
618       // and contains a regular sub-expression.
619       return getExprOpValue(MipsExpr->getSubExpr(), Fixups, STI);
620     case MipsMCExpr::MEK_CALL_HI16:
621       FixupKind = Mips::fixup_Mips_CALL_HI16;
622       break;
623     case MipsMCExpr::MEK_CALL_LO16:
624       FixupKind = Mips::fixup_Mips_CALL_LO16;
625       break;
626     case MipsMCExpr::MEK_DTPREL_HI:
627       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
628                                    : Mips::fixup_Mips_DTPREL_HI;
629       break;
630     case MipsMCExpr::MEK_DTPREL_LO:
631       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
632                                    : Mips::fixup_Mips_DTPREL_LO;
633       break;
634     case MipsMCExpr::MEK_GOTTPREL:
635       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOTTPREL
636                                    : Mips::fixup_Mips_GOTTPREL;
637       break;
638     case MipsMCExpr::MEK_GOT:
639       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
640                                    : Mips::fixup_Mips_GOT;
641       break;
642     case MipsMCExpr::MEK_GOT_CALL:
643       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
644                                    : Mips::fixup_Mips_CALL16;
645       break;
646     case MipsMCExpr::MEK_GOT_DISP:
647       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
648                                    : Mips::fixup_Mips_GOT_DISP;
649       break;
650     case MipsMCExpr::MEK_GOT_HI16:
651       FixupKind = Mips::fixup_Mips_GOT_HI16;
652       break;
653     case MipsMCExpr::MEK_GOT_LO16:
654       FixupKind = Mips::fixup_Mips_GOT_LO16;
655       break;
656     case MipsMCExpr::MEK_GOT_PAGE:
657       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
658                                    : Mips::fixup_Mips_GOT_PAGE;
659       break;
660     case MipsMCExpr::MEK_GOT_OFST:
661       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
662                                    : Mips::fixup_Mips_GOT_OFST;
663       break;
664     case MipsMCExpr::MEK_GPREL:
665       FixupKind = Mips::fixup_Mips_GPREL16;
666       break;
667     case MipsMCExpr::MEK_LO:
668       // Check for %lo(%neg(%gp_rel(X)))
669       if (MipsExpr->isGpOff())
670         FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GPOFF_LO
671                                      : Mips::fixup_Mips_GPOFF_LO;
672       else
673         FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
674                                      : Mips::fixup_Mips_LO16;
675       break;
676     case MipsMCExpr::MEK_HIGHEST:
677       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HIGHEST
678                                    : Mips::fixup_Mips_HIGHEST;
679       break;
680     case MipsMCExpr::MEK_HIGHER:
681       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HIGHER
682                                    : Mips::fixup_Mips_HIGHER;
683       break;
684     case MipsMCExpr::MEK_HI:
685       // Check for %hi(%neg(%gp_rel(X)))
686       if (MipsExpr->isGpOff())
687         FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GPOFF_HI
688                                      : Mips::fixup_Mips_GPOFF_HI;
689       else
690         FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
691                                      : Mips::fixup_Mips_HI16;
692       break;
693     case MipsMCExpr::MEK_PCREL_HI16:
694       FixupKind = Mips::fixup_MIPS_PCHI16;
695       break;
696     case MipsMCExpr::MEK_PCREL_LO16:
697       FixupKind = Mips::fixup_MIPS_PCLO16;
698       break;
699     case MipsMCExpr::MEK_TLSGD:
700       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
701                                    : Mips::fixup_Mips_TLSGD;
702       break;
703     case MipsMCExpr::MEK_TLSLDM:
704       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
705                                    : Mips::fixup_Mips_TLSLDM;
706       break;
707     case MipsMCExpr::MEK_TPREL_HI:
708       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
709                                    : Mips::fixup_Mips_TPREL_HI;
710       break;
711     case MipsMCExpr::MEK_TPREL_LO:
712       FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
713                                    : Mips::fixup_Mips_TPREL_LO;
714       break;
715     case MipsMCExpr::MEK_NEG:
716       FixupKind =
717           isMicroMips(STI) ? Mips::fixup_MICROMIPS_SUB : Mips::fixup_Mips_SUB;
718       break;
719     }
720     Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind)));
721     return 0;
722   }
723 
724   if (Kind == MCExpr::SymbolRef) {
725     Mips::Fixups FixupKind = Mips::Fixups(0);
726 
727     switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
728     default: llvm_unreachable("Unknown fixup kind!");
729       break;
730     case MCSymbolRefExpr::VK_None:
731       FixupKind = Mips::fixup_Mips_32; // FIXME: This is ok for O32/N32 but not N64.
732       break;
733     } // switch
734 
735     Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
736     return 0;
737   }
738   return 0;
739 }
740 
741 /// getMachineOpValue - Return binary encoding of operand. If the machine
742 /// operand requires relocation, record the relocation and return zero.
743 unsigned MipsMCCodeEmitter::
744 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
745                   SmallVectorImpl<MCFixup> &Fixups,
746                   const MCSubtargetInfo &STI) const {
747   if (MO.isReg()) {
748     unsigned Reg = MO.getReg();
749     unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
750     return RegNo;
751   } else if (MO.isImm()) {
752     return static_cast<unsigned>(MO.getImm());
753   } else if (MO.isFPImm()) {
754     return static_cast<unsigned>(APFloat(MO.getFPImm())
755         .bitcastToAPInt().getHiBits(32).getLimitedValue());
756   }
757   // MO must be an Expr.
758   assert(MO.isExpr());
759   return getExprOpValue(MO.getExpr(),Fixups, STI);
760 }
761 
762 /// Return binary encoding of memory related operand.
763 /// If the offset operand requires relocation, record the relocation.
764 template <unsigned ShiftAmount>
765 unsigned MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
766                                            SmallVectorImpl<MCFixup> &Fixups,
767                                            const MCSubtargetInfo &STI) const {
768   // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
769   assert(MI.getOperand(OpNo).isReg());
770   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
771   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
772 
773   // Apply the scale factor if there is one.
774   OffBits >>= ShiftAmount;
775 
776   return (OffBits & 0xFFFF) | RegBits;
777 }
778 
779 unsigned MipsMCCodeEmitter::
780 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
781                      SmallVectorImpl<MCFixup> &Fixups,
782                      const MCSubtargetInfo &STI) const {
783   // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
784   assert(MI.getOperand(OpNo).isReg());
785   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
786                                        Fixups, STI) << 4;
787   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
788                                        Fixups, STI);
789 
790   return (OffBits & 0xF) | RegBits;
791 }
792 
793 unsigned MipsMCCodeEmitter::
794 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
795                          SmallVectorImpl<MCFixup> &Fixups,
796                          const MCSubtargetInfo &STI) const {
797   // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
798   assert(MI.getOperand(OpNo).isReg());
799   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
800                                        Fixups, STI) << 4;
801   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
802                                        Fixups, STI) >> 1;
803 
804   return (OffBits & 0xF) | RegBits;
805 }
806 
807 unsigned MipsMCCodeEmitter::
808 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
809                          SmallVectorImpl<MCFixup> &Fixups,
810                          const MCSubtargetInfo &STI) const {
811   // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
812   assert(MI.getOperand(OpNo).isReg());
813   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
814                                        Fixups, STI) << 4;
815   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
816                                        Fixups, STI) >> 2;
817 
818   return (OffBits & 0xF) | RegBits;
819 }
820 
821 unsigned MipsMCCodeEmitter::
822 getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
823                            SmallVectorImpl<MCFixup> &Fixups,
824                            const MCSubtargetInfo &STI) const {
825   // Register is encoded in bits 9-5, offset is encoded in bits 4-0.
826   assert(MI.getOperand(OpNo).isReg() &&
827          (MI.getOperand(OpNo).getReg() == Mips::SP ||
828          MI.getOperand(OpNo).getReg() == Mips::SP_64) &&
829          "Unexpected base register!");
830   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
831                                        Fixups, STI) >> 2;
832 
833   return OffBits & 0x1F;
834 }
835 
836 unsigned MipsMCCodeEmitter::
837 getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
838                            SmallVectorImpl<MCFixup> &Fixups,
839                            const MCSubtargetInfo &STI) const {
840   // Register is encoded in bits 9-7, offset is encoded in bits 6-0.
841   assert(MI.getOperand(OpNo).isReg() &&
842          MI.getOperand(OpNo).getReg() == Mips::GP &&
843          "Unexpected base register!");
844 
845   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
846                                        Fixups, STI) >> 2;
847 
848   return OffBits & 0x7F;
849 }
850 
851 unsigned MipsMCCodeEmitter::
852 getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
853                      SmallVectorImpl<MCFixup> &Fixups,
854                      const MCSubtargetInfo &STI) const {
855   // Base register is encoded in bits 20-16, offset is encoded in bits 8-0.
856   assert(MI.getOperand(OpNo).isReg());
857   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
858                                        STI) << 16;
859   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI);
860 
861   return (OffBits & 0x1FF) | RegBits;
862 }
863 
864 unsigned MipsMCCodeEmitter::
865 getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo,
866                       SmallVectorImpl<MCFixup> &Fixups,
867                       const MCSubtargetInfo &STI) const {
868   // Base register is encoded in bits 20-16, offset is encoded in bits 10-0.
869   assert(MI.getOperand(OpNo).isReg());
870   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
871                                        STI) << 16;
872   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
873 
874   return (OffBits & 0x07FF) | RegBits;
875 }
876 
877 unsigned MipsMCCodeEmitter::
878 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
879                       SmallVectorImpl<MCFixup> &Fixups,
880                       const MCSubtargetInfo &STI) const {
881   // opNum can be invalid if instruction had reglist as operand.
882   // MemOperand is always last operand of instruction (base + offset).
883   switch (MI.getOpcode()) {
884   default:
885     break;
886   case Mips::SWM32_MM:
887   case Mips::LWM32_MM:
888     OpNo = MI.getNumOperands() - 2;
889     break;
890   }
891 
892   // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
893   assert(MI.getOperand(OpNo).isReg());
894   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
895   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
896 
897   return (OffBits & 0x0FFF) | RegBits;
898 }
899 
900 unsigned MipsMCCodeEmitter::
901 getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo,
902                       SmallVectorImpl<MCFixup> &Fixups,
903                       const MCSubtargetInfo &STI) const {
904   // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
905   assert(MI.getOperand(OpNo).isReg());
906   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
907                                        STI) << 16;
908   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
909 
910   return (OffBits & 0xFFFF) | RegBits;
911 }
912 
913 unsigned MipsMCCodeEmitter::
914 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
915                        SmallVectorImpl<MCFixup> &Fixups,
916                        const MCSubtargetInfo &STI) const {
917   // opNum can be invalid if instruction had reglist as operand
918   // MemOperand is always last operand of instruction (base + offset)
919   switch (MI.getOpcode()) {
920   default:
921     break;
922   case Mips::SWM16_MM:
923   case Mips::SWM16_MMR6:
924   case Mips::LWM16_MM:
925   case Mips::LWM16_MMR6:
926     OpNo = MI.getNumOperands() - 2;
927     break;
928   }
929 
930   // Offset is encoded in bits 4-0.
931   assert(MI.getOperand(OpNo).isReg());
932   // Base register is always SP - thus it is not encoded.
933   assert(MI.getOperand(OpNo+1).isImm());
934   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
935 
936   return ((OffBits >> 2) & 0x0F);
937 }
938 
939 // FIXME: should be called getMSBEncoding
940 //
941 unsigned
942 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
943                                       SmallVectorImpl<MCFixup> &Fixups,
944                                       const MCSubtargetInfo &STI) const {
945   assert(MI.getOperand(OpNo-1).isImm());
946   assert(MI.getOperand(OpNo).isImm());
947   unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
948   unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
949 
950   return Position + Size - 1;
951 }
952 
953 template <unsigned Bits, int Offset>
954 unsigned
955 MipsMCCodeEmitter::getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo,
956                                              SmallVectorImpl<MCFixup> &Fixups,
957                                              const MCSubtargetInfo &STI) const {
958   assert(MI.getOperand(OpNo).isImm());
959   unsigned Value = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
960   Value -= Offset;
961   return Value;
962 }
963 
964 unsigned
965 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
966                                          SmallVectorImpl<MCFixup> &Fixups,
967                                          const MCSubtargetInfo &STI) const {
968   const MCOperand &MO = MI.getOperand(OpNo);
969   if (MO.isImm()) {
970     // The immediate is encoded as 'immediate << 2'.
971     unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
972     assert((Res & 3) == 0);
973     return Res >> 2;
974   }
975 
976   assert(MO.isExpr() &&
977          "getSimm19Lsl2Encoding expects only expressions or an immediate");
978 
979   const MCExpr *Expr = MO.getExpr();
980   Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC19_S2
981                                             : Mips::fixup_MIPS_PC19_S2;
982   Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
983   return 0;
984 }
985 
986 unsigned
987 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
988                                          SmallVectorImpl<MCFixup> &Fixups,
989                                          const MCSubtargetInfo &STI) const {
990   const MCOperand &MO = MI.getOperand(OpNo);
991   if (MO.isImm()) {
992     // The immediate is encoded as 'immediate << 3'.
993     unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
994     assert((Res & 7) == 0);
995     return Res >> 3;
996   }
997 
998   assert(MO.isExpr() &&
999          "getSimm18Lsl2Encoding expects only expressions or an immediate");
1000 
1001   const MCExpr *Expr = MO.getExpr();
1002   Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC18_S3
1003                                             : Mips::fixup_MIPS_PC18_S3;
1004   Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
1005   return 0;
1006 }
1007 
1008 unsigned
1009 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
1010                                         SmallVectorImpl<MCFixup> &Fixups,
1011                                         const MCSubtargetInfo &STI) const {
1012   assert(MI.getOperand(OpNo).isImm());
1013   const MCOperand &MO = MI.getOperand(OpNo);
1014   return MO.getImm() % 8;
1015 }
1016 
1017 unsigned
1018 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
1019                                     SmallVectorImpl<MCFixup> &Fixups,
1020                                     const MCSubtargetInfo &STI) const {
1021   assert(MI.getOperand(OpNo).isImm());
1022   const MCOperand &MO = MI.getOperand(OpNo);
1023   unsigned Value = MO.getImm();
1024   switch (Value) {
1025     case 128:   return 0x0;
1026     case 1:     return 0x1;
1027     case 2:     return 0x2;
1028     case 3:     return 0x3;
1029     case 4:     return 0x4;
1030     case 7:     return 0x5;
1031     case 8:     return 0x6;
1032     case 15:    return 0x7;
1033     case 16:    return 0x8;
1034     case 31:    return 0x9;
1035     case 32:    return 0xa;
1036     case 63:    return 0xb;
1037     case 64:    return 0xc;
1038     case 255:   return 0xd;
1039     case 32768: return 0xe;
1040     case 65535: return 0xf;
1041   }
1042   llvm_unreachable("Unexpected value");
1043 }
1044 
1045 unsigned
1046 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
1047                                           SmallVectorImpl<MCFixup> &Fixups,
1048                                           const MCSubtargetInfo &STI) const {
1049   unsigned res = 0;
1050 
1051   // Register list operand is always first operand of instruction and it is
1052   // placed before memory operand (register + imm).
1053 
1054   for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
1055     unsigned Reg = MI.getOperand(I).getReg();
1056     unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
1057     if (RegNo != 31)
1058       res++;
1059     else
1060       res |= 0x10;
1061   }
1062   return res;
1063 }
1064 
1065 unsigned
1066 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
1067                                             SmallVectorImpl<MCFixup> &Fixups,
1068                                             const MCSubtargetInfo &STI) const {
1069   return (MI.getNumOperands() - 4);
1070 }
1071 
1072 unsigned
1073 MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
1074                                           SmallVectorImpl<MCFixup> &Fixups,
1075                                           const MCSubtargetInfo &STI) const {
1076   unsigned res = 0;
1077 
1078   if (MI.getOperand(0).getReg() == Mips::A1 &&
1079       MI.getOperand(1).getReg() == Mips::A2)
1080     res = 0;
1081   else if (MI.getOperand(0).getReg() == Mips::A1 &&
1082            MI.getOperand(1).getReg() == Mips::A3)
1083     res = 1;
1084   else if (MI.getOperand(0).getReg() == Mips::A2 &&
1085            MI.getOperand(1).getReg() == Mips::A3)
1086     res = 2;
1087   else if (MI.getOperand(0).getReg() == Mips::A0 &&
1088            MI.getOperand(1).getReg() == Mips::S5)
1089     res = 3;
1090   else if (MI.getOperand(0).getReg() == Mips::A0 &&
1091            MI.getOperand(1).getReg() == Mips::S6)
1092     res = 4;
1093   else if (MI.getOperand(0).getReg() == Mips::A0 &&
1094            MI.getOperand(1).getReg() == Mips::A1)
1095     res = 5;
1096   else if (MI.getOperand(0).getReg() == Mips::A0 &&
1097            MI.getOperand(1).getReg() == Mips::A2)
1098     res = 6;
1099   else if (MI.getOperand(0).getReg() == Mips::A0 &&
1100            MI.getOperand(1).getReg() == Mips::A3)
1101     res = 7;
1102 
1103   return res;
1104 }
1105 
1106 unsigned
1107 MipsMCCodeEmitter::getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo,
1108                                             SmallVectorImpl<MCFixup> &Fixups,
1109                                             const MCSubtargetInfo &STI) const {
1110   assert(((OpNo == 2) || (OpNo == 3)) &&
1111          "Unexpected OpNo for movep operand encoding!");
1112 
1113   MCOperand Op = MI.getOperand(OpNo);
1114   assert(Op.isReg() && "Operand of movep is not a register!");
1115   switch (Op.getReg()) {
1116   default:
1117     llvm_unreachable("Unknown register for movep!");
1118   case Mips::ZERO:  return 0;
1119   case Mips::S1:    return 1;
1120   case Mips::V0:    return 2;
1121   case Mips::V1:    return 3;
1122   case Mips::S0:    return 4;
1123   case Mips::S2:    return 5;
1124   case Mips::S3:    return 6;
1125   case Mips::S4:    return 7;
1126   }
1127 }
1128 
1129 unsigned
1130 MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
1131                                          SmallVectorImpl<MCFixup> &Fixups,
1132                                          const MCSubtargetInfo &STI) const {
1133   const MCOperand &MO = MI.getOperand(OpNo);
1134   assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate");
1135   // The immediate is encoded as 'immediate >> 2'.
1136   unsigned Res = static_cast<unsigned>(MO.getImm());
1137   assert((Res & 3) == 0);
1138   return Res >> 2;
1139 }
1140 
1141 #include "MipsGenMCCodeEmitter.inc"
1142