1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Mips Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsSubtarget.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 /// A disasembler class for Mips. 34 class MipsDisassemblerBase : public MCDisassembler { 35 public: 36 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx, 37 bool IsBigEndian) 38 : MCDisassembler(STI, Ctx), 39 IsGP64Bit(STI.getFeatureBits() & Mips::FeatureGP64Bit), 40 IsBigEndian(IsBigEndian) {} 41 42 virtual ~MipsDisassemblerBase() {} 43 44 bool isGP64Bit() const { return IsGP64Bit; } 45 46 private: 47 bool IsGP64Bit; 48 protected: 49 bool IsBigEndian; 50 }; 51 52 /// A disasembler class for Mips32. 53 class MipsDisassembler : public MipsDisassemblerBase { 54 bool IsMicroMips; 55 public: 56 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian) 57 : MipsDisassemblerBase(STI, Ctx, bigEndian) { 58 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips; 59 } 60 61 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; } 62 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; } 63 bool hasMips32r6() const { 64 return STI.getFeatureBits() & Mips::FeatureMips32r6; 65 } 66 67 bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; } 68 69 bool hasCOP3() const { 70 // Only present in MIPS-I and MIPS-II 71 return !hasMips32() && !hasMips3(); 72 } 73 74 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 75 ArrayRef<uint8_t> Bytes, uint64_t Address, 76 raw_ostream &VStream, 77 raw_ostream &CStream) const override; 78 }; 79 80 /// A disasembler class for Mips64. 81 class Mips64Disassembler : public MipsDisassemblerBase { 82 public: 83 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 84 bool bigEndian) : 85 MipsDisassemblerBase(STI, Ctx, bigEndian) {} 86 87 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 88 ArrayRef<uint8_t> Bytes, uint64_t Address, 89 raw_ostream &VStream, 90 raw_ostream &CStream) const override; 91 }; 92 93 } // end anonymous namespace 94 95 // Forward declare these because the autogenerated code will reference them. 96 // Definitions are further down. 97 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 98 unsigned RegNo, 99 uint64_t Address, 100 const void *Decoder); 101 102 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 103 unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 107 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 108 unsigned RegNo, 109 uint64_t Address, 110 const void *Decoder); 111 112 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 113 unsigned RegNo, 114 uint64_t Address, 115 const void *Decoder); 116 117 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 118 unsigned RegNo, 119 uint64_t Address, 120 const void *Decoder); 121 122 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 123 unsigned Insn, 124 uint64_t Address, 125 const void *Decoder); 126 127 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 128 unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder); 131 132 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 133 unsigned RegNo, 134 uint64_t Address, 135 const void *Decoder); 136 137 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 138 unsigned RegNo, 139 uint64_t Address, 140 const void *Decoder); 141 142 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 143 unsigned RegNo, 144 uint64_t Address, 145 const void *Decoder); 146 147 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 148 unsigned RegNo, 149 uint64_t Address, 150 const void *Decoder); 151 152 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 153 uint64_t Address, 154 const void *Decoder); 155 156 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 157 unsigned Insn, 158 uint64_t Address, 159 const void *Decoder); 160 161 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 162 unsigned RegNo, 163 uint64_t Address, 164 const void *Decoder); 165 166 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 167 unsigned RegNo, 168 uint64_t Address, 169 const void *Decoder); 170 171 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 172 unsigned RegNo, 173 uint64_t Address, 174 const void *Decoder); 175 176 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 181 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 182 unsigned RegNo, 183 uint64_t Address, 184 const void *Decoder); 185 186 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 187 unsigned RegNo, 188 uint64_t Address, 189 const void *Decoder); 190 191 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 192 unsigned RegNo, 193 uint64_t Address, 194 const void *Decoder); 195 196 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 197 unsigned RegNo, 198 uint64_t Address, 199 const void *Decoder); 200 201 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 202 unsigned RegNo, 203 uint64_t Address, 204 const void *Decoder); 205 206 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 207 unsigned RegNo, 208 uint64_t Address, 209 const void *Decoder); 210 211 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 212 unsigned Offset, 213 uint64_t Address, 214 const void *Decoder); 215 216 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 217 unsigned Insn, 218 uint64_t Address, 219 const void *Decoder); 220 221 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 222 unsigned Offset, 223 uint64_t Address, 224 const void *Decoder); 225 226 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 227 unsigned Offset, 228 uint64_t Address, 229 const void *Decoder); 230 231 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 232 // shifted left by 1 bit. 233 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 234 unsigned Offset, 235 uint64_t Address, 236 const void *Decoder); 237 238 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 239 // shifted left by 1 bit. 240 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 241 unsigned Offset, 242 uint64_t Address, 243 const void *Decoder); 244 245 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 246 // shifted left by 1 bit. 247 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 248 unsigned Insn, 249 uint64_t Address, 250 const void *Decoder); 251 252 static DecodeStatus DecodeMem(MCInst &Inst, 253 unsigned Insn, 254 uint64_t Address, 255 const void *Decoder); 256 257 static DecodeStatus DecodeCacheOp(MCInst &Inst, 258 unsigned Insn, 259 uint64_t Address, 260 const void *Decoder); 261 262 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 263 unsigned Insn, 264 uint64_t Address, 265 const void *Decoder); 266 267 static DecodeStatus DecodeSyncI(MCInst &Inst, 268 unsigned Insn, 269 uint64_t Address, 270 const void *Decoder); 271 272 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 273 uint64_t Address, const void *Decoder); 274 275 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 276 unsigned Insn, 277 uint64_t Address, 278 const void *Decoder); 279 280 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 281 unsigned Insn, 282 uint64_t Address, 283 const void *Decoder); 284 285 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 286 unsigned Insn, 287 uint64_t Address, 288 const void *Decoder); 289 290 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 291 unsigned Insn, 292 uint64_t Address, 293 const void *Decoder); 294 295 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 296 uint64_t Address, 297 const void *Decoder); 298 299 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, 300 uint64_t Address, 301 const void *Decoder); 302 303 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, 304 uint64_t Address, 305 const void *Decoder); 306 307 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 308 unsigned Insn, 309 uint64_t Address, 310 const void *Decoder); 311 312 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 313 unsigned Value, 314 uint64_t Address, 315 const void *Decoder); 316 317 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, 318 unsigned Value, 319 uint64_t Address, 320 const void *Decoder); 321 322 static DecodeStatus DecodeLiSimm7(MCInst &Inst, 323 unsigned Value, 324 uint64_t Address, 325 const void *Decoder); 326 327 static DecodeStatus DecodeSimm4(MCInst &Inst, 328 unsigned Value, 329 uint64_t Address, 330 const void *Decoder); 331 332 static DecodeStatus DecodeSimm16(MCInst &Inst, 333 unsigned Insn, 334 uint64_t Address, 335 const void *Decoder); 336 337 // Decode the immediate field of an LSA instruction which 338 // is off by one. 339 static DecodeStatus DecodeLSAImm(MCInst &Inst, 340 unsigned Insn, 341 uint64_t Address, 342 const void *Decoder); 343 344 static DecodeStatus DecodeInsSize(MCInst &Inst, 345 unsigned Insn, 346 uint64_t Address, 347 const void *Decoder); 348 349 static DecodeStatus DecodeExtSize(MCInst &Inst, 350 unsigned Insn, 351 uint64_t Address, 352 const void *Decoder); 353 354 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 355 uint64_t Address, const void *Decoder); 356 357 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 358 uint64_t Address, const void *Decoder); 359 360 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 361 uint64_t Address, const void *Decoder); 362 363 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 364 uint64_t Address, const void *Decoder); 365 366 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, 367 uint64_t Address, const void *Decoder); 368 369 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 370 /// handle. 371 template <typename InsnType> 372 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 373 const void *Decoder); 374 375 template <typename InsnType> 376 static DecodeStatus 377 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 378 const void *Decoder); 379 380 template <typename InsnType> 381 static DecodeStatus 382 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 383 const void *Decoder); 384 385 template <typename InsnType> 386 static DecodeStatus 387 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 388 const void *Decoder); 389 390 template <typename InsnType> 391 static DecodeStatus 392 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 393 const void *Decoder); 394 395 template <typename InsnType> 396 static DecodeStatus 397 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 398 const void *Decoder); 399 400 template <typename InsnType> 401 static DecodeStatus 402 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 403 const void *Decoder); 404 405 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 406 uint64_t Address, 407 const void *Decoder); 408 409 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 410 uint64_t Address, 411 const void *Decoder); 412 413 namespace llvm { 414 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, 415 TheMips64elTarget; 416 } 417 418 static MCDisassembler *createMipsDisassembler( 419 const Target &T, 420 const MCSubtargetInfo &STI, 421 MCContext &Ctx) { 422 return new MipsDisassembler(STI, Ctx, true); 423 } 424 425 static MCDisassembler *createMipselDisassembler( 426 const Target &T, 427 const MCSubtargetInfo &STI, 428 MCContext &Ctx) { 429 return new MipsDisassembler(STI, Ctx, false); 430 } 431 432 static MCDisassembler *createMips64Disassembler( 433 const Target &T, 434 const MCSubtargetInfo &STI, 435 MCContext &Ctx) { 436 return new Mips64Disassembler(STI, Ctx, true); 437 } 438 439 static MCDisassembler *createMips64elDisassembler( 440 const Target &T, 441 const MCSubtargetInfo &STI, 442 MCContext &Ctx) { 443 return new Mips64Disassembler(STI, Ctx, false); 444 } 445 446 extern "C" void LLVMInitializeMipsDisassembler() { 447 // Register the disassembler. 448 TargetRegistry::RegisterMCDisassembler(TheMipsTarget, 449 createMipsDisassembler); 450 TargetRegistry::RegisterMCDisassembler(TheMipselTarget, 451 createMipselDisassembler); 452 TargetRegistry::RegisterMCDisassembler(TheMips64Target, 453 createMips64Disassembler); 454 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, 455 createMips64elDisassembler); 456 } 457 458 #include "MipsGenDisassemblerTables.inc" 459 460 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 461 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D); 462 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 463 return *(RegInfo->getRegClass(RC).begin() + RegNo); 464 } 465 466 template <typename InsnType> 467 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 468 const void *Decoder) { 469 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *); 470 // The size of the n field depends on the element size 471 // The register class also depends on this. 472 InsnType tmp = fieldFromInstruction(insn, 17, 5); 473 unsigned NSize = 0; 474 DecodeFN RegDecoder = nullptr; 475 if ((tmp & 0x18) == 0x00) { // INSVE_B 476 NSize = 4; 477 RegDecoder = DecodeMSA128BRegisterClass; 478 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 479 NSize = 3; 480 RegDecoder = DecodeMSA128HRegisterClass; 481 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 482 NSize = 2; 483 RegDecoder = DecodeMSA128WRegisterClass; 484 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 485 NSize = 1; 486 RegDecoder = DecodeMSA128DRegisterClass; 487 } else 488 llvm_unreachable("Invalid encoding"); 489 490 assert(NSize != 0 && RegDecoder != nullptr); 491 492 // $wd 493 tmp = fieldFromInstruction(insn, 6, 5); 494 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 495 return MCDisassembler::Fail; 496 // $wd_in 497 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 498 return MCDisassembler::Fail; 499 // $n 500 tmp = fieldFromInstruction(insn, 16, NSize); 501 MI.addOperand(MCOperand::CreateImm(tmp)); 502 // $ws 503 tmp = fieldFromInstruction(insn, 11, 5); 504 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 505 return MCDisassembler::Fail; 506 // $n2 507 MI.addOperand(MCOperand::CreateImm(0)); 508 509 return MCDisassembler::Success; 510 } 511 512 template <typename InsnType> 513 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 514 uint64_t Address, 515 const void *Decoder) { 516 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 517 // (otherwise we would have matched the ADDI instruction from the earlier 518 // ISA's instead). 519 // 520 // We have: 521 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 522 // BOVC if rs >= rt 523 // BEQZALC if rs == 0 && rt != 0 524 // BEQC if rs < rt && rs != 0 525 526 InsnType Rs = fieldFromInstruction(insn, 21, 5); 527 InsnType Rt = fieldFromInstruction(insn, 16, 5); 528 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 529 bool HasRs = false; 530 531 if (Rs >= Rt) { 532 MI.setOpcode(Mips::BOVC); 533 HasRs = true; 534 } else if (Rs != 0 && Rs < Rt) { 535 MI.setOpcode(Mips::BEQC); 536 HasRs = true; 537 } else 538 MI.setOpcode(Mips::BEQZALC); 539 540 if (HasRs) 541 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 542 Rs))); 543 544 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 545 Rt))); 546 MI.addOperand(MCOperand::CreateImm(Imm)); 547 548 return MCDisassembler::Success; 549 } 550 551 template <typename InsnType> 552 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 553 uint64_t Address, 554 const void *Decoder) { 555 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 556 // (otherwise we would have matched the ADDI instruction from the earlier 557 // ISA's instead). 558 // 559 // We have: 560 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 561 // BNVC if rs >= rt 562 // BNEZALC if rs == 0 && rt != 0 563 // BNEC if rs < rt && rs != 0 564 565 InsnType Rs = fieldFromInstruction(insn, 21, 5); 566 InsnType Rt = fieldFromInstruction(insn, 16, 5); 567 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 568 bool HasRs = false; 569 570 if (Rs >= Rt) { 571 MI.setOpcode(Mips::BNVC); 572 HasRs = true; 573 } else if (Rs != 0 && Rs < Rt) { 574 MI.setOpcode(Mips::BNEC); 575 HasRs = true; 576 } else 577 MI.setOpcode(Mips::BNEZALC); 578 579 if (HasRs) 580 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 581 Rs))); 582 583 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 584 Rt))); 585 MI.addOperand(MCOperand::CreateImm(Imm)); 586 587 return MCDisassembler::Success; 588 } 589 590 template <typename InsnType> 591 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 592 uint64_t Address, 593 const void *Decoder) { 594 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 595 // (otherwise we would have matched the BLEZL instruction from the earlier 596 // ISA's instead). 597 // 598 // We have: 599 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 600 // Invalid if rs == 0 601 // BLEZC if rs == 0 && rt != 0 602 // BGEZC if rs == rt && rt != 0 603 // BGEC if rs != rt && rs != 0 && rt != 0 604 605 InsnType Rs = fieldFromInstruction(insn, 21, 5); 606 InsnType Rt = fieldFromInstruction(insn, 16, 5); 607 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 608 bool HasRs = false; 609 610 if (Rt == 0) 611 return MCDisassembler::Fail; 612 else if (Rs == 0) 613 MI.setOpcode(Mips::BLEZC); 614 else if (Rs == Rt) 615 MI.setOpcode(Mips::BGEZC); 616 else { 617 HasRs = true; 618 MI.setOpcode(Mips::BGEC); 619 } 620 621 if (HasRs) 622 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 623 Rs))); 624 625 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 626 Rt))); 627 628 MI.addOperand(MCOperand::CreateImm(Imm)); 629 630 return MCDisassembler::Success; 631 } 632 633 template <typename InsnType> 634 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 635 uint64_t Address, 636 const void *Decoder) { 637 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 638 // (otherwise we would have matched the BGTZL instruction from the earlier 639 // ISA's instead). 640 // 641 // We have: 642 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 643 // Invalid if rs == 0 644 // BGTZC if rs == 0 && rt != 0 645 // BLTZC if rs == rt && rt != 0 646 // BLTC if rs != rt && rs != 0 && rt != 0 647 648 bool HasRs = false; 649 650 InsnType Rs = fieldFromInstruction(insn, 21, 5); 651 InsnType Rt = fieldFromInstruction(insn, 16, 5); 652 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 653 654 if (Rt == 0) 655 return MCDisassembler::Fail; 656 else if (Rs == 0) 657 MI.setOpcode(Mips::BGTZC); 658 else if (Rs == Rt) 659 MI.setOpcode(Mips::BLTZC); 660 else { 661 MI.setOpcode(Mips::BLTC); 662 HasRs = true; 663 } 664 665 if (HasRs) 666 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 667 Rs))); 668 669 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 670 Rt))); 671 672 MI.addOperand(MCOperand::CreateImm(Imm)); 673 674 return MCDisassembler::Success; 675 } 676 677 template <typename InsnType> 678 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 679 uint64_t Address, 680 const void *Decoder) { 681 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 682 // (otherwise we would have matched the BGTZ instruction from the earlier 683 // ISA's instead). 684 // 685 // We have: 686 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 687 // BGTZ if rt == 0 688 // BGTZALC if rs == 0 && rt != 0 689 // BLTZALC if rs != 0 && rs == rt 690 // BLTUC if rs != 0 && rs != rt 691 692 InsnType Rs = fieldFromInstruction(insn, 21, 5); 693 InsnType Rt = fieldFromInstruction(insn, 16, 5); 694 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 695 bool HasRs = false; 696 bool HasRt = false; 697 698 if (Rt == 0) { 699 MI.setOpcode(Mips::BGTZ); 700 HasRs = true; 701 } else if (Rs == 0) { 702 MI.setOpcode(Mips::BGTZALC); 703 HasRt = true; 704 } else if (Rs == Rt) { 705 MI.setOpcode(Mips::BLTZALC); 706 HasRs = true; 707 } else { 708 MI.setOpcode(Mips::BLTUC); 709 HasRs = true; 710 HasRt = true; 711 } 712 713 if (HasRs) 714 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 715 Rs))); 716 717 if (HasRt) 718 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 719 Rt))); 720 721 MI.addOperand(MCOperand::CreateImm(Imm)); 722 723 return MCDisassembler::Success; 724 } 725 726 template <typename InsnType> 727 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 728 uint64_t Address, 729 const void *Decoder) { 730 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 731 // (otherwise we would have matched the BLEZL instruction from the earlier 732 // ISA's instead). 733 // 734 // We have: 735 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 736 // Invalid if rs == 0 737 // BLEZALC if rs == 0 && rt != 0 738 // BGEZALC if rs == rt && rt != 0 739 // BGEUC if rs != rt && rs != 0 && rt != 0 740 741 InsnType Rs = fieldFromInstruction(insn, 21, 5); 742 InsnType Rt = fieldFromInstruction(insn, 16, 5); 743 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; 744 bool HasRs = false; 745 746 if (Rt == 0) 747 return MCDisassembler::Fail; 748 else if (Rs == 0) 749 MI.setOpcode(Mips::BLEZALC); 750 else if (Rs == Rt) 751 MI.setOpcode(Mips::BGEZALC); 752 else { 753 HasRs = true; 754 MI.setOpcode(Mips::BGEUC); 755 } 756 757 if (HasRs) 758 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 759 Rs))); 760 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID, 761 Rt))); 762 763 MI.addOperand(MCOperand::CreateImm(Imm)); 764 765 return MCDisassembler::Success; 766 } 767 768 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 769 /// according to the given endianess. 770 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 771 uint64_t &Size, uint32_t &Insn, 772 bool IsBigEndian) { 773 // We want to read exactly 2 Bytes of data. 774 if (Bytes.size() < 2) { 775 Size = 0; 776 return MCDisassembler::Fail; 777 } 778 779 if (IsBigEndian) { 780 Insn = (Bytes[0] << 8) | Bytes[1]; 781 } else { 782 Insn = (Bytes[1] << 8) | Bytes[0]; 783 } 784 785 return MCDisassembler::Success; 786 } 787 788 /// Read four bytes from the ArrayRef and return 32 bit word sorted 789 /// according to the given endianess 790 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 791 uint64_t &Size, uint32_t &Insn, 792 bool IsBigEndian, bool IsMicroMips) { 793 // We want to read exactly 4 Bytes of data. 794 if (Bytes.size() < 4) { 795 Size = 0; 796 return MCDisassembler::Fail; 797 } 798 799 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 800 // always precede the low 16 bits in the instruction stream (that is, they 801 // are placed at lower addresses in the instruction stream). 802 // 803 // microMIPS byte ordering: 804 // Big-endian: 0 | 1 | 2 | 3 805 // Little-endian: 1 | 0 | 3 | 2 806 807 if (IsBigEndian) { 808 // Encoded as a big-endian 32-bit word in the stream. 809 Insn = 810 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 811 } else { 812 if (IsMicroMips) { 813 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 814 (Bytes[1] << 24); 815 } else { 816 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 817 (Bytes[3] << 24); 818 } 819 } 820 821 return MCDisassembler::Success; 822 } 823 824 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 825 ArrayRef<uint8_t> Bytes, 826 uint64_t Address, 827 raw_ostream &VStream, 828 raw_ostream &CStream) const { 829 uint32_t Insn; 830 DecodeStatus Result; 831 832 if (IsMicroMips) { 833 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 834 835 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 836 // Calling the auto-generated decoder function. 837 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 838 this, STI); 839 if (Result != MCDisassembler::Fail) { 840 Size = 2; 841 return Result; 842 } 843 844 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 845 if (Result == MCDisassembler::Fail) 846 return MCDisassembler::Fail; 847 848 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 849 // Calling the auto-generated decoder function. 850 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 851 this, STI); 852 if (Result != MCDisassembler::Fail) { 853 Size = 4; 854 return Result; 855 } 856 return MCDisassembler::Fail; 857 } 858 859 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 860 if (Result == MCDisassembler::Fail) 861 return MCDisassembler::Fail; 862 863 if (hasCOP3()) { 864 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 865 Result = 866 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 867 if (Result != MCDisassembler::Fail) { 868 Size = 4; 869 return Result; 870 } 871 } 872 873 if (hasMips32r6() && isGP64()) { 874 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 875 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 876 Address, this, STI); 877 if (Result != MCDisassembler::Fail) { 878 Size = 4; 879 return Result; 880 } 881 } 882 883 if (hasMips32r6()) { 884 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 885 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 886 Address, this, STI); 887 if (Result != MCDisassembler::Fail) { 888 Size = 4; 889 return Result; 890 } 891 } 892 893 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 894 // Calling the auto-generated decoder function. 895 Result = 896 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 897 if (Result != MCDisassembler::Fail) { 898 Size = 4; 899 return Result; 900 } 901 902 return MCDisassembler::Fail; 903 } 904 905 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size, 906 ArrayRef<uint8_t> Bytes, 907 uint64_t Address, 908 raw_ostream &VStream, 909 raw_ostream &CStream) const { 910 uint32_t Insn; 911 912 DecodeStatus Result = 913 readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 914 if (Result == MCDisassembler::Fail) 915 return MCDisassembler::Fail; 916 917 // Calling the auto-generated decoder function. 918 Result = 919 decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI); 920 if (Result != MCDisassembler::Fail) { 921 Size = 4; 922 return Result; 923 } 924 // If we fail to decode in Mips64 decoder space we can try in Mips32 925 Result = 926 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 927 if (Result != MCDisassembler::Fail) { 928 Size = 4; 929 return Result; 930 } 931 932 return MCDisassembler::Fail; 933 } 934 935 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 936 unsigned RegNo, 937 uint64_t Address, 938 const void *Decoder) { 939 940 return MCDisassembler::Fail; 941 942 } 943 944 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 945 unsigned RegNo, 946 uint64_t Address, 947 const void *Decoder) { 948 949 if (RegNo > 31) 950 return MCDisassembler::Fail; 951 952 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 953 Inst.addOperand(MCOperand::CreateReg(Reg)); 954 return MCDisassembler::Success; 955 } 956 957 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 958 unsigned RegNo, 959 uint64_t Address, 960 const void *Decoder) { 961 if (RegNo > 7) 962 return MCDisassembler::Fail; 963 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 964 Inst.addOperand(MCOperand::CreateReg(Reg)); 965 return MCDisassembler::Success; 966 } 967 968 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 969 unsigned RegNo, 970 uint64_t Address, 971 const void *Decoder) { 972 if (RegNo > 7) 973 return MCDisassembler::Fail; 974 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 975 Inst.addOperand(MCOperand::CreateReg(Reg)); 976 return MCDisassembler::Success; 977 } 978 979 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 980 unsigned RegNo, 981 uint64_t Address, 982 const void *Decoder) { 983 if (RegNo > 31) 984 return MCDisassembler::Fail; 985 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 986 Inst.addOperand(MCOperand::CreateReg(Reg)); 987 return MCDisassembler::Success; 988 } 989 990 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 991 unsigned RegNo, 992 uint64_t Address, 993 const void *Decoder) { 994 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64Bit()) 995 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 996 997 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 998 } 999 1000 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1001 unsigned RegNo, 1002 uint64_t Address, 1003 const void *Decoder) { 1004 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1005 } 1006 1007 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1008 unsigned RegNo, 1009 uint64_t Address, 1010 const void *Decoder) { 1011 if (RegNo > 31) 1012 return MCDisassembler::Fail; 1013 1014 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1015 Inst.addOperand(MCOperand::CreateReg(Reg)); 1016 return MCDisassembler::Success; 1017 } 1018 1019 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1020 unsigned RegNo, 1021 uint64_t Address, 1022 const void *Decoder) { 1023 if (RegNo > 31) 1024 return MCDisassembler::Fail; 1025 1026 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1027 Inst.addOperand(MCOperand::CreateReg(Reg)); 1028 return MCDisassembler::Success; 1029 } 1030 1031 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1032 unsigned RegNo, 1033 uint64_t Address, 1034 const void *Decoder) { 1035 if (RegNo > 31) 1036 return MCDisassembler::Fail; 1037 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1038 Inst.addOperand(MCOperand::CreateReg(Reg)); 1039 return MCDisassembler::Success; 1040 } 1041 1042 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1043 unsigned RegNo, 1044 uint64_t Address, 1045 const void *Decoder) { 1046 if (RegNo > 7) 1047 return MCDisassembler::Fail; 1048 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1049 Inst.addOperand(MCOperand::CreateReg(Reg)); 1050 return MCDisassembler::Success; 1051 } 1052 1053 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1054 uint64_t Address, 1055 const void *Decoder) { 1056 if (RegNo > 31) 1057 return MCDisassembler::Fail; 1058 1059 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1060 Inst.addOperand(MCOperand::CreateReg(Reg)); 1061 return MCDisassembler::Success; 1062 } 1063 1064 static DecodeStatus DecodeMem(MCInst &Inst, 1065 unsigned Insn, 1066 uint64_t Address, 1067 const void *Decoder) { 1068 int Offset = SignExtend32<16>(Insn & 0xffff); 1069 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1070 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1071 1072 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1073 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1074 1075 if(Inst.getOpcode() == Mips::SC || 1076 Inst.getOpcode() == Mips::SCD){ 1077 Inst.addOperand(MCOperand::CreateReg(Reg)); 1078 } 1079 1080 Inst.addOperand(MCOperand::CreateReg(Reg)); 1081 Inst.addOperand(MCOperand::CreateReg(Base)); 1082 Inst.addOperand(MCOperand::CreateImm(Offset)); 1083 1084 return MCDisassembler::Success; 1085 } 1086 1087 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1088 unsigned Insn, 1089 uint64_t Address, 1090 const void *Decoder) { 1091 int Offset = SignExtend32<16>(Insn & 0xffff); 1092 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1093 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1094 1095 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1096 1097 Inst.addOperand(MCOperand::CreateReg(Base)); 1098 Inst.addOperand(MCOperand::CreateImm(Offset)); 1099 Inst.addOperand(MCOperand::CreateImm(Hint)); 1100 1101 return MCDisassembler::Success; 1102 } 1103 1104 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1105 unsigned Insn, 1106 uint64_t Address, 1107 const void *Decoder) { 1108 int Offset = SignExtend32<12>(Insn & 0xfff); 1109 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1110 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1111 1112 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1113 1114 Inst.addOperand(MCOperand::CreateReg(Base)); 1115 Inst.addOperand(MCOperand::CreateImm(Offset)); 1116 Inst.addOperand(MCOperand::CreateImm(Hint)); 1117 1118 return MCDisassembler::Success; 1119 } 1120 1121 static DecodeStatus DecodeSyncI(MCInst &Inst, 1122 unsigned Insn, 1123 uint64_t Address, 1124 const void *Decoder) { 1125 int Offset = SignExtend32<16>(Insn & 0xffff); 1126 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1127 1128 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1129 1130 Inst.addOperand(MCOperand::CreateReg(Base)); 1131 Inst.addOperand(MCOperand::CreateImm(Offset)); 1132 1133 return MCDisassembler::Success; 1134 } 1135 1136 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1137 uint64_t Address, const void *Decoder) { 1138 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1139 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1140 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1141 1142 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1143 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1144 1145 Inst.addOperand(MCOperand::CreateReg(Reg)); 1146 Inst.addOperand(MCOperand::CreateReg(Base)); 1147 1148 // The immediate field of an LD/ST instruction is scaled which means it must 1149 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1150 // data format. 1151 // .b - 1 byte 1152 // .h - 2 bytes 1153 // .w - 4 bytes 1154 // .d - 8 bytes 1155 switch(Inst.getOpcode()) 1156 { 1157 default: 1158 assert (0 && "Unexpected instruction"); 1159 return MCDisassembler::Fail; 1160 break; 1161 case Mips::LD_B: 1162 case Mips::ST_B: 1163 Inst.addOperand(MCOperand::CreateImm(Offset)); 1164 break; 1165 case Mips::LD_H: 1166 case Mips::ST_H: 1167 Inst.addOperand(MCOperand::CreateImm(Offset * 2)); 1168 break; 1169 case Mips::LD_W: 1170 case Mips::ST_W: 1171 Inst.addOperand(MCOperand::CreateImm(Offset * 4)); 1172 break; 1173 case Mips::LD_D: 1174 case Mips::ST_D: 1175 Inst.addOperand(MCOperand::CreateImm(Offset * 8)); 1176 break; 1177 } 1178 1179 return MCDisassembler::Success; 1180 } 1181 1182 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1183 unsigned Insn, 1184 uint64_t Address, 1185 const void *Decoder) { 1186 unsigned Offset = Insn & 0xf; 1187 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1188 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1189 1190 switch (Inst.getOpcode()) { 1191 case Mips::LBU16_MM: 1192 case Mips::LHU16_MM: 1193 case Mips::LW16_MM: 1194 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1195 == MCDisassembler::Fail) 1196 return MCDisassembler::Fail; 1197 break; 1198 case Mips::SB16_MM: 1199 case Mips::SH16_MM: 1200 case Mips::SW16_MM: 1201 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1202 == MCDisassembler::Fail) 1203 return MCDisassembler::Fail; 1204 break; 1205 } 1206 1207 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1208 == MCDisassembler::Fail) 1209 return MCDisassembler::Fail; 1210 1211 switch (Inst.getOpcode()) { 1212 case Mips::LBU16_MM: 1213 if (Offset == 0xf) 1214 Inst.addOperand(MCOperand::CreateImm(-1)); 1215 else 1216 Inst.addOperand(MCOperand::CreateImm(Offset)); 1217 break; 1218 case Mips::SB16_MM: 1219 Inst.addOperand(MCOperand::CreateImm(Offset)); 1220 break; 1221 case Mips::LHU16_MM: 1222 case Mips::SH16_MM: 1223 Inst.addOperand(MCOperand::CreateImm(Offset << 1)); 1224 break; 1225 case Mips::LW16_MM: 1226 case Mips::SW16_MM: 1227 Inst.addOperand(MCOperand::CreateImm(Offset << 2)); 1228 break; 1229 } 1230 1231 return MCDisassembler::Success; 1232 } 1233 1234 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1235 unsigned Insn, 1236 uint64_t Address, 1237 const void *Decoder) { 1238 unsigned Offset = Insn & 0x1F; 1239 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1240 1241 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1242 1243 Inst.addOperand(MCOperand::CreateReg(Reg)); 1244 Inst.addOperand(MCOperand::CreateReg(Mips::SP)); 1245 Inst.addOperand(MCOperand::CreateImm(Offset << 2)); 1246 1247 return MCDisassembler::Success; 1248 } 1249 1250 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1251 unsigned Insn, 1252 uint64_t Address, 1253 const void *Decoder) { 1254 int Offset = SignExtend32<12>(Insn & 0x0fff); 1255 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1256 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1257 1258 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1259 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1260 1261 switch (Inst.getOpcode()) { 1262 case Mips::SWM32_MM: 1263 case Mips::LWM32_MM: 1264 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1265 == MCDisassembler::Fail) 1266 return MCDisassembler::Fail; 1267 Inst.addOperand(MCOperand::CreateReg(Base)); 1268 Inst.addOperand(MCOperand::CreateImm(Offset)); 1269 break; 1270 case Mips::SC_MM: 1271 Inst.addOperand(MCOperand::CreateReg(Reg)); 1272 // fallthrough 1273 default: 1274 Inst.addOperand(MCOperand::CreateReg(Reg)); 1275 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1276 Inst.addOperand(MCOperand::CreateReg(Reg+1)); 1277 1278 Inst.addOperand(MCOperand::CreateReg(Base)); 1279 Inst.addOperand(MCOperand::CreateImm(Offset)); 1280 } 1281 1282 return MCDisassembler::Success; 1283 } 1284 1285 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1286 unsigned Insn, 1287 uint64_t Address, 1288 const void *Decoder) { 1289 int Offset = SignExtend32<16>(Insn & 0xffff); 1290 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1291 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1292 1293 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1294 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1295 1296 Inst.addOperand(MCOperand::CreateReg(Reg)); 1297 Inst.addOperand(MCOperand::CreateReg(Base)); 1298 Inst.addOperand(MCOperand::CreateImm(Offset)); 1299 1300 return MCDisassembler::Success; 1301 } 1302 1303 static DecodeStatus DecodeFMem(MCInst &Inst, 1304 unsigned Insn, 1305 uint64_t Address, 1306 const void *Decoder) { 1307 int Offset = SignExtend32<16>(Insn & 0xffff); 1308 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1309 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1310 1311 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1312 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1313 1314 Inst.addOperand(MCOperand::CreateReg(Reg)); 1315 Inst.addOperand(MCOperand::CreateReg(Base)); 1316 Inst.addOperand(MCOperand::CreateImm(Offset)); 1317 1318 return MCDisassembler::Success; 1319 } 1320 1321 static DecodeStatus DecodeFMem2(MCInst &Inst, 1322 unsigned Insn, 1323 uint64_t Address, 1324 const void *Decoder) { 1325 int Offset = SignExtend32<16>(Insn & 0xffff); 1326 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1327 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1328 1329 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1330 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1331 1332 Inst.addOperand(MCOperand::CreateReg(Reg)); 1333 Inst.addOperand(MCOperand::CreateReg(Base)); 1334 Inst.addOperand(MCOperand::CreateImm(Offset)); 1335 1336 return MCDisassembler::Success; 1337 } 1338 1339 static DecodeStatus DecodeFMem3(MCInst &Inst, 1340 unsigned Insn, 1341 uint64_t Address, 1342 const void *Decoder) { 1343 int Offset = SignExtend32<16>(Insn & 0xffff); 1344 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1345 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1346 1347 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 1348 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1349 1350 Inst.addOperand(MCOperand::CreateReg(Reg)); 1351 Inst.addOperand(MCOperand::CreateReg(Base)); 1352 Inst.addOperand(MCOperand::CreateImm(Offset)); 1353 1354 return MCDisassembler::Success; 1355 } 1356 1357 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 1358 unsigned Insn, 1359 uint64_t Address, 1360 const void *Decoder) { 1361 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 1362 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 1363 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1364 1365 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 1366 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1367 1368 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 1369 Inst.addOperand(MCOperand::CreateReg(Rt)); 1370 } 1371 1372 Inst.addOperand(MCOperand::CreateReg(Rt)); 1373 Inst.addOperand(MCOperand::CreateReg(Base)); 1374 Inst.addOperand(MCOperand::CreateImm(Offset)); 1375 1376 return MCDisassembler::Success; 1377 } 1378 1379 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 1380 unsigned RegNo, 1381 uint64_t Address, 1382 const void *Decoder) { 1383 // Currently only hardware register 29 is supported. 1384 if (RegNo != 29) 1385 return MCDisassembler::Fail; 1386 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29)); 1387 return MCDisassembler::Success; 1388 } 1389 1390 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 1391 unsigned RegNo, 1392 uint64_t Address, 1393 const void *Decoder) { 1394 if (RegNo > 30 || RegNo %2) 1395 return MCDisassembler::Fail; 1396 1397 ; 1398 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 1399 Inst.addOperand(MCOperand::CreateReg(Reg)); 1400 return MCDisassembler::Success; 1401 } 1402 1403 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 1404 unsigned RegNo, 1405 uint64_t Address, 1406 const void *Decoder) { 1407 if (RegNo >= 4) 1408 return MCDisassembler::Fail; 1409 1410 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 1411 Inst.addOperand(MCOperand::CreateReg(Reg)); 1412 return MCDisassembler::Success; 1413 } 1414 1415 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 1416 unsigned RegNo, 1417 uint64_t Address, 1418 const void *Decoder) { 1419 if (RegNo >= 4) 1420 return MCDisassembler::Fail; 1421 1422 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 1423 Inst.addOperand(MCOperand::CreateReg(Reg)); 1424 return MCDisassembler::Success; 1425 } 1426 1427 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 1428 unsigned RegNo, 1429 uint64_t Address, 1430 const void *Decoder) { 1431 if (RegNo >= 4) 1432 return MCDisassembler::Fail; 1433 1434 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 1435 Inst.addOperand(MCOperand::CreateReg(Reg)); 1436 return MCDisassembler::Success; 1437 } 1438 1439 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 1440 unsigned RegNo, 1441 uint64_t Address, 1442 const void *Decoder) { 1443 if (RegNo > 31) 1444 return MCDisassembler::Fail; 1445 1446 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 1447 Inst.addOperand(MCOperand::CreateReg(Reg)); 1448 return MCDisassembler::Success; 1449 } 1450 1451 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 1452 unsigned RegNo, 1453 uint64_t Address, 1454 const void *Decoder) { 1455 if (RegNo > 31) 1456 return MCDisassembler::Fail; 1457 1458 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 1459 Inst.addOperand(MCOperand::CreateReg(Reg)); 1460 return MCDisassembler::Success; 1461 } 1462 1463 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 1464 unsigned RegNo, 1465 uint64_t Address, 1466 const void *Decoder) { 1467 if (RegNo > 31) 1468 return MCDisassembler::Fail; 1469 1470 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 1471 Inst.addOperand(MCOperand::CreateReg(Reg)); 1472 return MCDisassembler::Success; 1473 } 1474 1475 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 1476 unsigned RegNo, 1477 uint64_t Address, 1478 const void *Decoder) { 1479 if (RegNo > 31) 1480 return MCDisassembler::Fail; 1481 1482 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 1483 Inst.addOperand(MCOperand::CreateReg(Reg)); 1484 return MCDisassembler::Success; 1485 } 1486 1487 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 1488 unsigned RegNo, 1489 uint64_t Address, 1490 const void *Decoder) { 1491 if (RegNo > 7) 1492 return MCDisassembler::Fail; 1493 1494 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 1495 Inst.addOperand(MCOperand::CreateReg(Reg)); 1496 return MCDisassembler::Success; 1497 } 1498 1499 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 1500 unsigned RegNo, 1501 uint64_t Address, 1502 const void *Decoder) { 1503 if (RegNo > 31) 1504 return MCDisassembler::Fail; 1505 1506 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 1507 Inst.addOperand(MCOperand::CreateReg(Reg)); 1508 return MCDisassembler::Success; 1509 } 1510 1511 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 1512 unsigned Offset, 1513 uint64_t Address, 1514 const void *Decoder) { 1515 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 1516 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1517 return MCDisassembler::Success; 1518 } 1519 1520 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 1521 unsigned Insn, 1522 uint64_t Address, 1523 const void *Decoder) { 1524 1525 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 1526 Inst.addOperand(MCOperand::CreateImm(JumpOffset)); 1527 return MCDisassembler::Success; 1528 } 1529 1530 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 1531 unsigned Offset, 1532 uint64_t Address, 1533 const void *Decoder) { 1534 int32_t BranchOffset = SignExtend32<21>(Offset) * 4; 1535 1536 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1537 return MCDisassembler::Success; 1538 } 1539 1540 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 1541 unsigned Offset, 1542 uint64_t Address, 1543 const void *Decoder) { 1544 int32_t BranchOffset = SignExtend32<26>(Offset) * 4; 1545 1546 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1547 return MCDisassembler::Success; 1548 } 1549 1550 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 1551 unsigned Offset, 1552 uint64_t Address, 1553 const void *Decoder) { 1554 int32_t BranchOffset = SignExtend32<7>(Offset) << 1; 1555 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1556 return MCDisassembler::Success; 1557 } 1558 1559 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 1560 unsigned Offset, 1561 uint64_t Address, 1562 const void *Decoder) { 1563 int32_t BranchOffset = SignExtend32<16>(Offset) * 2; 1564 Inst.addOperand(MCOperand::CreateImm(BranchOffset)); 1565 return MCDisassembler::Success; 1566 } 1567 1568 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 1569 unsigned Insn, 1570 uint64_t Address, 1571 const void *Decoder) { 1572 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 1573 Inst.addOperand(MCOperand::CreateImm(JumpOffset)); 1574 return MCDisassembler::Success; 1575 } 1576 1577 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 1578 unsigned Value, 1579 uint64_t Address, 1580 const void *Decoder) { 1581 if (Value == 0) 1582 Inst.addOperand(MCOperand::CreateImm(1)); 1583 else if (Value == 0x7) 1584 Inst.addOperand(MCOperand::CreateImm(-1)); 1585 else 1586 Inst.addOperand(MCOperand::CreateImm(Value << 2)); 1587 return MCDisassembler::Success; 1588 } 1589 1590 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst, 1591 unsigned Value, 1592 uint64_t Address, 1593 const void *Decoder) { 1594 Inst.addOperand(MCOperand::CreateImm(Value << 2)); 1595 return MCDisassembler::Success; 1596 } 1597 1598 static DecodeStatus DecodeLiSimm7(MCInst &Inst, 1599 unsigned Value, 1600 uint64_t Address, 1601 const void *Decoder) { 1602 if (Value == 0x7F) 1603 Inst.addOperand(MCOperand::CreateImm(-1)); 1604 else 1605 Inst.addOperand(MCOperand::CreateImm(Value)); 1606 return MCDisassembler::Success; 1607 } 1608 1609 static DecodeStatus DecodeSimm4(MCInst &Inst, 1610 unsigned Value, 1611 uint64_t Address, 1612 const void *Decoder) { 1613 Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value))); 1614 return MCDisassembler::Success; 1615 } 1616 1617 static DecodeStatus DecodeSimm16(MCInst &Inst, 1618 unsigned Insn, 1619 uint64_t Address, 1620 const void *Decoder) { 1621 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn))); 1622 return MCDisassembler::Success; 1623 } 1624 1625 static DecodeStatus DecodeLSAImm(MCInst &Inst, 1626 unsigned Insn, 1627 uint64_t Address, 1628 const void *Decoder) { 1629 // We add one to the immediate field as it was encoded as 'imm - 1'. 1630 Inst.addOperand(MCOperand::CreateImm(Insn + 1)); 1631 return MCDisassembler::Success; 1632 } 1633 1634 static DecodeStatus DecodeInsSize(MCInst &Inst, 1635 unsigned Insn, 1636 uint64_t Address, 1637 const void *Decoder) { 1638 // First we need to grab the pos(lsb) from MCInst. 1639 int Pos = Inst.getOperand(2).getImm(); 1640 int Size = (int) Insn - Pos + 1; 1641 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size))); 1642 return MCDisassembler::Success; 1643 } 1644 1645 static DecodeStatus DecodeExtSize(MCInst &Inst, 1646 unsigned Insn, 1647 uint64_t Address, 1648 const void *Decoder) { 1649 int Size = (int) Insn + 1; 1650 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size))); 1651 return MCDisassembler::Success; 1652 } 1653 1654 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 1655 uint64_t Address, const void *Decoder) { 1656 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4)); 1657 return MCDisassembler::Success; 1658 } 1659 1660 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 1661 uint64_t Address, const void *Decoder) { 1662 Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8)); 1663 return MCDisassembler::Success; 1664 } 1665 1666 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 1667 uint64_t Address, const void *Decoder) { 1668 int32_t DecodedValue; 1669 switch (Insn) { 1670 case 0: DecodedValue = 256; break; 1671 case 1: DecodedValue = 257; break; 1672 case 510: DecodedValue = -258; break; 1673 case 511: DecodedValue = -257; break; 1674 default: DecodedValue = SignExtend32<9>(Insn); break; 1675 } 1676 Inst.addOperand(MCOperand::CreateImm(DecodedValue * 4)); 1677 return MCDisassembler::Success; 1678 } 1679 1680 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 1681 uint64_t Address, const void *Decoder) { 1682 // Insn must be >= 0, since it is unsigned that condition is always true. 1683 assert(Insn < 16); 1684 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 1685 255, 32768, 65535}; 1686 Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn])); 1687 return MCDisassembler::Success; 1688 } 1689 1690 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, 1691 uint64_t Address, const void *Decoder) { 1692 Inst.addOperand(MCOperand::CreateImm(Insn << 2)); 1693 return MCDisassembler::Success; 1694 } 1695 1696 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 1697 unsigned Insn, 1698 uint64_t Address, 1699 const void *Decoder) { 1700 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 1701 Mips::S6, Mips::FP}; 1702 unsigned RegNum; 1703 1704 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 1705 // Empty register lists are not allowed. 1706 if (RegLst == 0) 1707 return MCDisassembler::Fail; 1708 1709 RegNum = RegLst & 0xf; 1710 for (unsigned i = 0; i < RegNum; i++) 1711 Inst.addOperand(MCOperand::CreateReg(Regs[i])); 1712 1713 if (RegLst & 0x10) 1714 Inst.addOperand(MCOperand::CreateReg(Mips::RA)); 1715 1716 return MCDisassembler::Success; 1717 } 1718 1719 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 1720 uint64_t Address, 1721 const void *Decoder) { 1722 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 1723 unsigned RegNum; 1724 1725 unsigned RegLst = fieldFromInstruction(Insn, 4, 2); 1726 // Empty register lists are not allowed. 1727 if (RegLst == 0) 1728 return MCDisassembler::Fail; 1729 1730 RegNum = RegLst & 0x3; 1731 for (unsigned i = 0; i < RegNum - 1; i++) 1732 Inst.addOperand(MCOperand::CreateReg(Regs[i])); 1733 1734 Inst.addOperand(MCOperand::CreateReg(Mips::RA)); 1735 1736 return MCDisassembler::Success; 1737 } 1738