1 //===- MSP430RegisterInfo.cpp - MSP430 Register Information ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MSP430 implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "msp430-reg-info"
15 
16 #include "MSP430.h"
17 #include "MSP430MachineFunctionInfo.h"
18 #include "MSP430RegisterInfo.h"
19 #include "MSP430TargetMachine.h"
20 #include "llvm/Function.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/Support/ErrorHandling.h"
28 
29 using namespace llvm;
30 
31 // FIXME: Provide proper call frame setup / destroy opcodes.
32 MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
33                                        const TargetInstrInfo &tii)
34   : MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
35     TM(tm), TII(tii) {
36   StackAlign = TM.getFrameInfo()->getStackAlignment();
37 }
38 
39 const unsigned*
40 MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
41   const Function* F = MF->getFunction();
42   static const unsigned CalleeSavedRegs[] = {
43     MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
44     MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
45     0
46   };
47   static const unsigned CalleeSavedRegsFP[] = {
48     MSP430::R5W, MSP430::R6W, MSP430::R7W,
49     MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
50     0
51   };
52   static const unsigned CalleeSavedRegsIntr[] = {
53     MSP430::FPW,  MSP430::R5W,  MSP430::R6W,  MSP430::R7W,
54     MSP430::R8W,  MSP430::R9W,  MSP430::R10W, MSP430::R11W,
55     MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
56     0
57   };
58   static const unsigned CalleeSavedRegsIntrFP[] = {
59     MSP430::R5W,  MSP430::R6W,  MSP430::R7W,
60     MSP430::R8W,  MSP430::R9W,  MSP430::R10W, MSP430::R11W,
61     MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
62     0
63   };
64 
65   if (hasFP(*MF))
66     return (F->getCallingConv() == CallingConv::MSP430_INTR ?
67             CalleeSavedRegsIntrFP : CalleeSavedRegsFP);
68   else
69     return (F->getCallingConv() == CallingConv::MSP430_INTR ?
70             CalleeSavedRegsIntr : CalleeSavedRegs);
71 
72 }
73 
74 BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
75   BitVector Reserved(getNumRegs());
76 
77   // Mark 4 special registers as reserved.
78   Reserved.set(MSP430::PCW);
79   Reserved.set(MSP430::SPW);
80   Reserved.set(MSP430::SRW);
81   Reserved.set(MSP430::CGW);
82 
83   // Mark frame pointer as reserved if needed.
84   if (hasFP(MF))
85     Reserved.set(MSP430::FPW);
86 
87   return Reserved;
88 }
89 
90 const TargetRegisterClass *
91 MSP430RegisterInfo::getPointerRegClass(unsigned Kind) const {
92   return &MSP430::GR16RegClass;
93 }
94 
95 
96 bool MSP430RegisterInfo::hasFP(const MachineFunction &MF) const {
97   const MachineFrameInfo *MFI = MF.getFrameInfo();
98 
99   return (DisableFramePointerElim(MF) ||
100           MF.getFrameInfo()->hasVarSizedObjects() ||
101           MFI->isFrameAddressTaken());
102 }
103 
104 bool MSP430RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
105   return !MF.getFrameInfo()->hasVarSizedObjects();
106 }
107 
108 void MSP430RegisterInfo::
109 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
110                               MachineBasicBlock::iterator I) const {
111   if (!hasReservedCallFrame(MF)) {
112     // If the stack pointer can be changed after prologue, turn the
113     // adjcallstackup instruction into a 'sub SPW, <amt>' and the
114     // adjcallstackdown instruction into 'add SPW, <amt>'
115     // TODO: consider using push / pop instead of sub + store / add
116     MachineInstr *Old = I;
117     uint64_t Amount = Old->getOperand(0).getImm();
118     if (Amount != 0) {
119       // We need to keep the stack aligned properly.  To do this, we round the
120       // amount of space needed for the outgoing arguments up to the next
121       // alignment boundary.
122       Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
123 
124       MachineInstr *New = 0;
125       if (Old->getOpcode() == getCallFrameSetupOpcode()) {
126         New = BuildMI(MF, Old->getDebugLoc(),
127                       TII.get(MSP430::SUB16ri), MSP430::SPW)
128           .addReg(MSP430::SPW).addImm(Amount);
129       } else {
130         assert(Old->getOpcode() == getCallFrameDestroyOpcode());
131         // factor out the amount the callee already popped.
132         uint64_t CalleeAmt = Old->getOperand(1).getImm();
133         Amount -= CalleeAmt;
134         if (Amount)
135           New = BuildMI(MF, Old->getDebugLoc(),
136                         TII.get(MSP430::ADD16ri), MSP430::SPW)
137             .addReg(MSP430::SPW).addImm(Amount);
138       }
139 
140       if (New) {
141         // The SRW implicit def is dead.
142         New->getOperand(3).setIsDead();
143 
144         // Replace the pseudo instruction with a new instruction...
145         MBB.insert(I, New);
146       }
147     }
148   } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
149     // If we are performing frame pointer elimination and if the callee pops
150     // something off the stack pointer, add it back.
151     if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
152       MachineInstr *Old = I;
153       MachineInstr *New =
154         BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
155                 MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt);
156       // The SRW implicit def is dead.
157       New->getOperand(3).setIsDead();
158 
159       MBB.insert(I, New);
160     }
161   }
162 
163   MBB.erase(I);
164 }
165 
166 unsigned
167 MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
168                                         int SPAdj, FrameIndexValue *Value,
169                                         RegScavenger *RS) const {
170   assert(SPAdj == 0 && "Unexpected");
171 
172   unsigned i = 0;
173   MachineInstr &MI = *II;
174   MachineBasicBlock &MBB = *MI.getParent();
175   MachineFunction &MF = *MBB.getParent();
176   DebugLoc dl = MI.getDebugLoc();
177   while (!MI.getOperand(i).isFI()) {
178     ++i;
179     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
180   }
181 
182   int FrameIndex = MI.getOperand(i).getIndex();
183 
184   unsigned BasePtr = (hasFP(MF) ? MSP430::FPW : MSP430::SPW);
185   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
186 
187   // Skip the saved PC
188   Offset += 2;
189 
190   if (!hasFP(MF))
191     Offset += MF.getFrameInfo()->getStackSize();
192   else
193     Offset += 2; // Skip the saved FPW
194 
195   // Fold imm into offset
196   Offset += MI.getOperand(i+1).getImm();
197 
198   if (MI.getOpcode() == MSP430::ADD16ri) {
199     // This is actually "load effective address" of the stack slot
200     // instruction. We have only two-address instructions, thus we need to
201     // expand it into mov + add
202 
203     MI.setDesc(TII.get(MSP430::MOV16rr));
204     MI.getOperand(i).ChangeToRegister(BasePtr, false);
205 
206     if (Offset == 0)
207       return 0;
208 
209     // We need to materialize the offset via add instruction.
210     unsigned DstReg = MI.getOperand(0).getReg();
211     if (Offset < 0)
212       BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
213         .addReg(DstReg).addImm(-Offset);
214     else
215       BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
216         .addReg(DstReg).addImm(Offset);
217 
218     return 0;
219   }
220 
221   MI.getOperand(i).ChangeToRegister(BasePtr, false);
222   MI.getOperand(i+1).ChangeToImmediate(Offset);
223   return 0;
224 }
225 
226 void
227 MSP430RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
228                                                                          const {
229   // Create a frame entry for the FPW register that must be saved.
230   if (hasFP(MF)) {
231     int FrameIdx = MF.getFrameInfo()->CreateFixedObject(2, -4, true);
232     (void)FrameIdx;
233     assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
234            "Slot for FPW register must be last in order to be found!");
235   }
236 }
237 
238 
239 void MSP430RegisterInfo::emitPrologue(MachineFunction &MF) const {
240   MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
241   MachineFrameInfo *MFI = MF.getFrameInfo();
242   MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
243   MachineBasicBlock::iterator MBBI = MBB.begin();
244   DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
245 
246   // Get the number of bytes to allocate from the FrameInfo.
247   uint64_t StackSize = MFI->getStackSize();
248 
249   uint64_t NumBytes = 0;
250   if (hasFP(MF)) {
251     // Calculate required stack adjustment
252     uint64_t FrameSize = StackSize - 2;
253     NumBytes = FrameSize - MSP430FI->getCalleeSavedFrameSize();
254 
255     // Get the offset of the stack slot for the EBP register... which is
256     // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
257     // Update the frame offset adjustment.
258     MFI->setOffsetAdjustment(-NumBytes);
259 
260     // Save FPW into the appropriate stack slot...
261     BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
262       .addReg(MSP430::FPW, RegState::Kill);
263 
264     // Update FPW with the new base value...
265     BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
266       .addReg(MSP430::SPW);
267 
268     // Mark the FramePtr as live-in in every block except the entry.
269     for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
270          I != E; ++I)
271       I->addLiveIn(MSP430::FPW);
272 
273   } else
274     NumBytes = StackSize - MSP430FI->getCalleeSavedFrameSize();
275 
276   // Skip the callee-saved push instructions.
277   while (MBBI != MBB.end() && (MBBI->getOpcode() == MSP430::PUSH16r))
278     ++MBBI;
279 
280   if (MBBI != MBB.end())
281     DL = MBBI->getDebugLoc();
282 
283   if (NumBytes) { // adjust stack pointer: SPW -= numbytes
284     // If there is an SUB16ri of SPW immediately before this instruction, merge
285     // the two.
286     //NumBytes -= mergeSPUpdates(MBB, MBBI, true);
287     // If there is an ADD16ri or SUB16ri of SPW immediately after this
288     // instruction, merge the two instructions.
289     // mergeSPUpdatesDown(MBB, MBBI, &NumBytes);
290 
291     if (NumBytes) {
292       MachineInstr *MI =
293         BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
294         .addReg(MSP430::SPW).addImm(NumBytes);
295       // The SRW implicit def is dead.
296       MI->getOperand(3).setIsDead();
297     }
298   }
299 }
300 
301 void MSP430RegisterInfo::emitEpilogue(MachineFunction &MF,
302                                       MachineBasicBlock &MBB) const {
303   const MachineFrameInfo *MFI = MF.getFrameInfo();
304   MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
305   MachineBasicBlock::iterator MBBI = prior(MBB.end());
306   unsigned RetOpcode = MBBI->getOpcode();
307   DebugLoc DL = MBBI->getDebugLoc();
308 
309   switch (RetOpcode) {
310   case MSP430::RET:
311   case MSP430::RETI: break;  // These are ok
312   default:
313     llvm_unreachable("Can only insert epilog into returning blocks");
314   }
315 
316   // Get the number of bytes to allocate from the FrameInfo
317   uint64_t StackSize = MFI->getStackSize();
318   unsigned CSSize = MSP430FI->getCalleeSavedFrameSize();
319   uint64_t NumBytes = 0;
320 
321   if (hasFP(MF)) {
322     // Calculate required stack adjustment
323     uint64_t FrameSize = StackSize - 2;
324     NumBytes = FrameSize - CSSize;
325 
326     // pop FPW.
327     BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
328   } else
329     NumBytes = StackSize - CSSize;
330 
331   // Skip the callee-saved pop instructions.
332   while (MBBI != MBB.begin()) {
333     MachineBasicBlock::iterator PI = prior(MBBI);
334     unsigned Opc = PI->getOpcode();
335     if (Opc != MSP430::POP16r && !PI->getDesc().isTerminator())
336       break;
337     --MBBI;
338   }
339 
340   DL = MBBI->getDebugLoc();
341 
342   // If there is an ADD16ri or SUB16ri of SPW immediately before this
343   // instruction, merge the two instructions.
344   //if (NumBytes || MFI->hasVarSizedObjects())
345   //  mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
346 
347   if (MFI->hasVarSizedObjects()) {
348     BuildMI(MBB, MBBI, DL,
349             TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW);
350     if (CSSize) {
351       MachineInstr *MI =
352         BuildMI(MBB, MBBI, DL,
353                 TII.get(MSP430::SUB16ri), MSP430::SPW)
354         .addReg(MSP430::SPW).addImm(CSSize);
355       // The SRW implicit def is dead.
356       MI->getOperand(3).setIsDead();
357     }
358   } else {
359     // adjust stack pointer back: SPW += numbytes
360     if (NumBytes) {
361       MachineInstr *MI =
362         BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
363         .addReg(MSP430::SPW).addImm(NumBytes);
364       // The SRW implicit def is dead.
365       MI->getOperand(3).setIsDead();
366     }
367   }
368 }
369 
370 unsigned MSP430RegisterInfo::getRARegister() const {
371   return MSP430::PCW;
372 }
373 
374 unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
375   return hasFP(MF) ? MSP430::FPW : MSP430::SPW;
376 }
377 
378 int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
379   llvm_unreachable("Not implemented yet!");
380   return 0;
381 }
382 
383 #include "MSP430GenRegisterInfo.inc"
384