1 //===- MSP430InstrInfo.cpp - MSP430 Instruction Information ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the MSP430 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MSP430.h" 15 #include "MSP430InstrInfo.h" 16 #include "MSP430MachineFunctionInfo.h" 17 #include "MSP430TargetMachine.h" 18 #include "MSP430GenInstrInfo.inc" 19 #include "llvm/Function.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/CodeGen/PseudoSourceValue.h" 24 #include "llvm/Support/ErrorHandling.h" 25 26 using namespace llvm; 27 28 MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm) 29 : TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts)), 30 RI(tm, *this), TM(tm) {} 31 32 void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 33 MachineBasicBlock::iterator MI, 34 unsigned SrcReg, bool isKill, int FrameIdx, 35 const TargetRegisterClass *RC, 36 const TargetRegisterInfo *TRI) const { 37 DebugLoc DL; 38 if (MI != MBB.end()) DL = MI->getDebugLoc(); 39 MachineFunction &MF = *MBB.getParent(); 40 MachineFrameInfo &MFI = *MF.getFrameInfo(); 41 42 MachineMemOperand *MMO = 43 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx), 44 MachineMemOperand::MOStore, 0, 45 MFI.getObjectSize(FrameIdx), 46 MFI.getObjectAlignment(FrameIdx)); 47 48 if (RC == &MSP430::GR16RegClass) 49 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr)) 50 .addFrameIndex(FrameIdx).addImm(0) 51 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 52 else if (RC == &MSP430::GR8RegClass) 53 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr)) 54 .addFrameIndex(FrameIdx).addImm(0) 55 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 56 else 57 llvm_unreachable("Cannot store this register to stack slot!"); 58 } 59 60 void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 61 MachineBasicBlock::iterator MI, 62 unsigned DestReg, int FrameIdx, 63 const TargetRegisterClass *RC, 64 const TargetRegisterInfo *TRI) const{ 65 DebugLoc DL; 66 if (MI != MBB.end()) DL = MI->getDebugLoc(); 67 MachineFunction &MF = *MBB.getParent(); 68 MachineFrameInfo &MFI = *MF.getFrameInfo(); 69 70 MachineMemOperand *MMO = 71 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx), 72 MachineMemOperand::MOLoad, 0, 73 MFI.getObjectSize(FrameIdx), 74 MFI.getObjectAlignment(FrameIdx)); 75 76 if (RC == &MSP430::GR16RegClass) 77 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm)) 78 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO); 79 else if (RC == &MSP430::GR8RegClass) 80 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm)) 81 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO); 82 else 83 llvm_unreachable("Cannot store this register to stack slot!"); 84 } 85 86 void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 87 MachineBasicBlock::iterator I, DebugLoc DL, 88 unsigned DestReg, unsigned SrcReg, 89 bool KillSrc) const { 90 unsigned Opc; 91 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) 92 Opc = MSP430::MOV16rr; 93 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) 94 Opc = MSP430::MOV8rr; 95 else 96 llvm_unreachable("Impossible reg-to-reg copy"); 97 98 BuildMI(MBB, I, DL, get(Opc), DestReg) 99 .addReg(SrcReg, getKillRegState(KillSrc)); 100 } 101 102 bool 103 MSP430InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 104 MachineBasicBlock::iterator MI, 105 const std::vector<CalleeSavedInfo> &CSI, 106 const TargetRegisterInfo *TRI) const { 107 if (CSI.empty()) 108 return false; 109 110 DebugLoc DL; 111 if (MI != MBB.end()) DL = MI->getDebugLoc(); 112 113 MachineFunction &MF = *MBB.getParent(); 114 MSP430MachineFunctionInfo *MFI = MF.getInfo<MSP430MachineFunctionInfo>(); 115 MFI->setCalleeSavedFrameSize(CSI.size() * 2); 116 117 for (unsigned i = CSI.size(); i != 0; --i) { 118 unsigned Reg = CSI[i-1].getReg(); 119 // Add the callee-saved register as live-in. It's killed at the spill. 120 MBB.addLiveIn(Reg); 121 BuildMI(MBB, MI, DL, get(MSP430::PUSH16r)) 122 .addReg(Reg, RegState::Kill); 123 } 124 return true; 125 } 126 127 bool 128 MSP430InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 129 MachineBasicBlock::iterator MI, 130 const std::vector<CalleeSavedInfo> &CSI, 131 const TargetRegisterInfo *TRI) const { 132 if (CSI.empty()) 133 return false; 134 135 DebugLoc DL; 136 if (MI != MBB.end()) DL = MI->getDebugLoc(); 137 138 for (unsigned i = 0, e = CSI.size(); i != e; ++i) 139 BuildMI(MBB, MI, DL, get(MSP430::POP16r), CSI[i].getReg()); 140 141 return true; 142 } 143 144 unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 145 MachineBasicBlock::iterator I = MBB.end(); 146 unsigned Count = 0; 147 148 while (I != MBB.begin()) { 149 --I; 150 if (I->isDebugValue()) 151 continue; 152 if (I->getOpcode() != MSP430::JMP && 153 I->getOpcode() != MSP430::JCC && 154 I->getOpcode() != MSP430::Br && 155 I->getOpcode() != MSP430::Bm) 156 break; 157 // Remove the branch. 158 I->eraseFromParent(); 159 I = MBB.end(); 160 ++Count; 161 } 162 163 return Count; 164 } 165 166 bool MSP430InstrInfo:: 167 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 168 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); 169 170 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); 171 172 switch (CC) { 173 default: 174 assert(0 && "Invalid branch condition!"); 175 break; 176 case MSP430CC::COND_E: 177 CC = MSP430CC::COND_NE; 178 break; 179 case MSP430CC::COND_NE: 180 CC = MSP430CC::COND_E; 181 break; 182 case MSP430CC::COND_L: 183 CC = MSP430CC::COND_GE; 184 break; 185 case MSP430CC::COND_GE: 186 CC = MSP430CC::COND_L; 187 break; 188 case MSP430CC::COND_HS: 189 CC = MSP430CC::COND_LO; 190 break; 191 case MSP430CC::COND_LO: 192 CC = MSP430CC::COND_HS; 193 break; 194 } 195 196 Cond[0].setImm(CC); 197 return false; 198 } 199 200 bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 201 const TargetInstrDesc &TID = MI->getDesc(); 202 if (!TID.isTerminator()) return false; 203 204 // Conditional branch is a special case. 205 if (TID.isBranch() && !TID.isBarrier()) 206 return true; 207 if (!TID.isPredicable()) 208 return true; 209 return !isPredicated(MI); 210 } 211 212 bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 213 MachineBasicBlock *&TBB, 214 MachineBasicBlock *&FBB, 215 SmallVectorImpl<MachineOperand> &Cond, 216 bool AllowModify) const { 217 // Start from the bottom of the block and work up, examining the 218 // terminator instructions. 219 MachineBasicBlock::iterator I = MBB.end(); 220 while (I != MBB.begin()) { 221 --I; 222 if (I->isDebugValue()) 223 continue; 224 225 // Working from the bottom, when we see a non-terminator 226 // instruction, we're done. 227 if (!isUnpredicatedTerminator(I)) 228 break; 229 230 // A terminator that isn't a branch can't easily be handled 231 // by this analysis. 232 if (!I->getDesc().isBranch()) 233 return true; 234 235 // Cannot handle indirect branches. 236 if (I->getOpcode() == MSP430::Br || 237 I->getOpcode() == MSP430::Bm) 238 return true; 239 240 // Handle unconditional branches. 241 if (I->getOpcode() == MSP430::JMP) { 242 if (!AllowModify) { 243 TBB = I->getOperand(0).getMBB(); 244 continue; 245 } 246 247 // If the block has any instructions after a JMP, delete them. 248 while (llvm::next(I) != MBB.end()) 249 llvm::next(I)->eraseFromParent(); 250 Cond.clear(); 251 FBB = 0; 252 253 // Delete the JMP if it's equivalent to a fall-through. 254 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 255 TBB = 0; 256 I->eraseFromParent(); 257 I = MBB.end(); 258 continue; 259 } 260 261 // TBB is used to indicate the unconditinal destination. 262 TBB = I->getOperand(0).getMBB(); 263 continue; 264 } 265 266 // Handle conditional branches. 267 assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch"); 268 MSP430CC::CondCodes BranchCode = 269 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm()); 270 if (BranchCode == MSP430CC::COND_INVALID) 271 return true; // Can't handle weird stuff. 272 273 // Working from the bottom, handle the first conditional branch. 274 if (Cond.empty()) { 275 FBB = TBB; 276 TBB = I->getOperand(0).getMBB(); 277 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 278 continue; 279 } 280 281 // Handle subsequent conditional branches. Only handle the case where all 282 // conditional branches branch to the same destination. 283 assert(Cond.size() == 1); 284 assert(TBB); 285 286 // Only handle the case where all conditional branches branch to 287 // the same destination. 288 if (TBB != I->getOperand(0).getMBB()) 289 return true; 290 291 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); 292 // If the conditions are the same, we can leave them alone. 293 if (OldBranchCode == BranchCode) 294 continue; 295 296 return true; 297 } 298 299 return false; 300 } 301 302 unsigned 303 MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 304 MachineBasicBlock *FBB, 305 const SmallVectorImpl<MachineOperand> &Cond, 306 DebugLoc DL) const { 307 // Shouldn't be a fall through. 308 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 309 assert((Cond.size() == 1 || Cond.size() == 0) && 310 "MSP430 branch conditions have one component!"); 311 312 if (Cond.empty()) { 313 // Unconditional branch? 314 assert(!FBB && "Unconditional branch with multiple successors!"); 315 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB); 316 return 1; 317 } 318 319 // Conditional branch. 320 unsigned Count = 0; 321 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm()); 322 ++Count; 323 324 if (FBB) { 325 // Two-way Conditional branch. Insert the second branch. 326 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB); 327 ++Count; 328 } 329 return Count; 330 } 331 332 /// GetInstSize - Return the number of bytes of code the specified 333 /// instruction may be. This returns the maximum number of bytes. 334 /// 335 unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 336 const TargetInstrDesc &Desc = MI->getDesc(); 337 338 switch (Desc.TSFlags & MSP430II::SizeMask) { 339 default: 340 switch (Desc.getOpcode()) { 341 default: 342 assert(0 && "Unknown instruction size!"); 343 case TargetOpcode::PROLOG_LABEL: 344 case TargetOpcode::EH_LABEL: 345 case TargetOpcode::IMPLICIT_DEF: 346 case TargetOpcode::KILL: 347 case TargetOpcode::DBG_VALUE: 348 return 0; 349 case TargetOpcode::INLINEASM: { 350 const MachineFunction *MF = MI->getParent()->getParent(); 351 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 352 return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(), 353 *MF->getTarget().getMCAsmInfo()); 354 } 355 } 356 case MSP430II::SizeSpecial: 357 switch (MI->getOpcode()) { 358 default: 359 assert(0 && "Unknown instruction size!"); 360 case MSP430::SAR8r1c: 361 case MSP430::SAR16r1c: 362 return 4; 363 } 364 case MSP430II::Size2Bytes: 365 return 2; 366 case MSP430II::Size4Bytes: 367 return 4; 368 case MSP430II::Size6Bytes: 369 return 6; 370 } 371 372 return 6; 373 } 374