1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the MSP430TargetLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MSP430ISelLowering.h" 15 #include "MSP430.h" 16 #include "MSP430MachineFunctionInfo.h" 17 #include "MSP430Subtarget.h" 18 #include "MSP430TargetMachine.h" 19 #include "llvm/CodeGen/CallingConvLower.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/SelectionDAGISel.h" 25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/IR/CallingConv.h" 28 #include "llvm/IR/DerivedTypes.h" 29 #include "llvm/IR/Function.h" 30 #include "llvm/IR/GlobalAlias.h" 31 #include "llvm/IR/GlobalVariable.h" 32 #include "llvm/IR/Intrinsics.h" 33 #include "llvm/Support/CommandLine.h" 34 #include "llvm/Support/Debug.h" 35 #include "llvm/Support/ErrorHandling.h" 36 #include "llvm/Support/raw_ostream.h" 37 using namespace llvm; 38 39 #define DEBUG_TYPE "msp430-lower" 40 41 typedef enum { 42 NoHWMult, 43 HWMultIntr, 44 HWMultNoIntr 45 } HWMultUseMode; 46 47 static cl::opt<HWMultUseMode> 48 HWMultMode("msp430-hwmult-mode", cl::Hidden, 49 cl::desc("Hardware multiplier use mode"), 50 cl::init(HWMultNoIntr), 51 cl::values( 52 clEnumValN(NoHWMult, "no", 53 "Do not use hardware multiplier"), 54 clEnumValN(HWMultIntr, "interrupts", 55 "Assume hardware multiplier can be used inside interrupts"), 56 clEnumValN(HWMultNoIntr, "use", 57 "Assume hardware multiplier cannot be used inside interrupts"), 58 clEnumValEnd)); 59 60 MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM) 61 : TargetLowering(TM) { 62 63 // Set up the register classes. 64 addRegisterClass(MVT::i8, &MSP430::GR8RegClass); 65 addRegisterClass(MVT::i16, &MSP430::GR16RegClass); 66 67 // Compute derived properties from the register classes 68 computeRegisterProperties(); 69 70 // Provide all sorts of operation actions 71 72 // Division is expensive 73 setIntDivIsCheap(false); 74 75 setStackPointerRegisterToSaveRestore(MSP430::SP); 76 setBooleanContents(ZeroOrOneBooleanContent); 77 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 78 79 // We have post-incremented loads / stores. 80 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); 81 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); 82 83 for (MVT VT : MVT::integer_valuetypes()) { 84 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 85 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 86 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 87 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); 88 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); 89 } 90 91 // We don't have any truncstores 92 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 93 94 setOperationAction(ISD::SRA, MVT::i8, Custom); 95 setOperationAction(ISD::SHL, MVT::i8, Custom); 96 setOperationAction(ISD::SRL, MVT::i8, Custom); 97 setOperationAction(ISD::SRA, MVT::i16, Custom); 98 setOperationAction(ISD::SHL, MVT::i16, Custom); 99 setOperationAction(ISD::SRL, MVT::i16, Custom); 100 setOperationAction(ISD::ROTL, MVT::i8, Expand); 101 setOperationAction(ISD::ROTR, MVT::i8, Expand); 102 setOperationAction(ISD::ROTL, MVT::i16, Expand); 103 setOperationAction(ISD::ROTR, MVT::i16, Expand); 104 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); 105 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom); 106 setOperationAction(ISD::BlockAddress, MVT::i16, Custom); 107 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 108 setOperationAction(ISD::BR_CC, MVT::i8, Custom); 109 setOperationAction(ISD::BR_CC, MVT::i16, Custom); 110 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 111 setOperationAction(ISD::SETCC, MVT::i8, Custom); 112 setOperationAction(ISD::SETCC, MVT::i16, Custom); 113 setOperationAction(ISD::SELECT, MVT::i8, Expand); 114 setOperationAction(ISD::SELECT, MVT::i16, Expand); 115 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); 116 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); 117 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom); 118 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand); 119 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand); 120 121 setOperationAction(ISD::CTTZ, MVT::i8, Expand); 122 setOperationAction(ISD::CTTZ, MVT::i16, Expand); 123 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i8, Expand); 124 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand); 125 setOperationAction(ISD::CTLZ, MVT::i8, Expand); 126 setOperationAction(ISD::CTLZ, MVT::i16, Expand); 127 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8, Expand); 128 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Expand); 129 setOperationAction(ISD::CTPOP, MVT::i8, Expand); 130 setOperationAction(ISD::CTPOP, MVT::i16, Expand); 131 132 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand); 133 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand); 134 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand); 135 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand); 136 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand); 137 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand); 138 139 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 140 141 // FIXME: Implement efficiently multiplication by a constant 142 setOperationAction(ISD::MUL, MVT::i8, Expand); 143 setOperationAction(ISD::MULHS, MVT::i8, Expand); 144 setOperationAction(ISD::MULHU, MVT::i8, Expand); 145 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand); 146 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand); 147 setOperationAction(ISD::MUL, MVT::i16, Expand); 148 setOperationAction(ISD::MULHS, MVT::i16, Expand); 149 setOperationAction(ISD::MULHU, MVT::i16, Expand); 150 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand); 151 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand); 152 153 setOperationAction(ISD::UDIV, MVT::i8, Expand); 154 setOperationAction(ISD::UDIVREM, MVT::i8, Expand); 155 setOperationAction(ISD::UREM, MVT::i8, Expand); 156 setOperationAction(ISD::SDIV, MVT::i8, Expand); 157 setOperationAction(ISD::SDIVREM, MVT::i8, Expand); 158 setOperationAction(ISD::SREM, MVT::i8, Expand); 159 setOperationAction(ISD::UDIV, MVT::i16, Expand); 160 setOperationAction(ISD::UDIVREM, MVT::i16, Expand); 161 setOperationAction(ISD::UREM, MVT::i16, Expand); 162 setOperationAction(ISD::SDIV, MVT::i16, Expand); 163 setOperationAction(ISD::SDIVREM, MVT::i16, Expand); 164 setOperationAction(ISD::SREM, MVT::i16, Expand); 165 166 // varargs support 167 setOperationAction(ISD::VASTART, MVT::Other, Custom); 168 setOperationAction(ISD::VAARG, MVT::Other, Expand); 169 setOperationAction(ISD::VAEND, MVT::Other, Expand); 170 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 171 setOperationAction(ISD::JumpTable, MVT::i16, Custom); 172 173 // Libcalls names. 174 if (HWMultMode == HWMultIntr) { 175 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw"); 176 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw"); 177 } else if (HWMultMode == HWMultNoIntr) { 178 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw_noint"); 179 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint"); 180 } 181 182 setMinFunctionAlignment(1); 183 setPrefFunctionAlignment(2); 184 } 185 186 SDValue MSP430TargetLowering::LowerOperation(SDValue Op, 187 SelectionDAG &DAG) const { 188 switch (Op.getOpcode()) { 189 case ISD::SHL: // FALLTHROUGH 190 case ISD::SRL: 191 case ISD::SRA: return LowerShifts(Op, DAG); 192 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 193 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 194 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 195 case ISD::SETCC: return LowerSETCC(Op, DAG); 196 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 197 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 198 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); 199 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 200 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 201 case ISD::VASTART: return LowerVASTART(Op, DAG); 202 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 203 default: 204 llvm_unreachable("unimplemented operand"); 205 } 206 } 207 208 //===----------------------------------------------------------------------===// 209 // MSP430 Inline Assembly Support 210 //===----------------------------------------------------------------------===// 211 212 /// getConstraintType - Given a constraint letter, return the type of 213 /// constraint it is for this target. 214 TargetLowering::ConstraintType 215 MSP430TargetLowering::getConstraintType(const std::string &Constraint) const { 216 if (Constraint.size() == 1) { 217 switch (Constraint[0]) { 218 case 'r': 219 return C_RegisterClass; 220 default: 221 break; 222 } 223 } 224 return TargetLowering::getConstraintType(Constraint); 225 } 226 227 std::pair<unsigned, const TargetRegisterClass*> 228 MSP430TargetLowering:: 229 getRegForInlineAsmConstraint(const std::string &Constraint, 230 MVT VT) const { 231 if (Constraint.size() == 1) { 232 // GCC Constraint Letters 233 switch (Constraint[0]) { 234 default: break; 235 case 'r': // GENERAL_REGS 236 if (VT == MVT::i8) 237 return std::make_pair(0U, &MSP430::GR8RegClass); 238 239 return std::make_pair(0U, &MSP430::GR16RegClass); 240 } 241 } 242 243 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 244 } 245 246 //===----------------------------------------------------------------------===// 247 // Calling Convention Implementation 248 //===----------------------------------------------------------------------===// 249 250 #include "MSP430GenCallingConv.inc" 251 252 /// For each argument in a function store the number of pieces it is composed 253 /// of. 254 template<typename ArgT> 255 static void ParseFunctionArgs(const SmallVectorImpl<ArgT> &Args, 256 SmallVectorImpl<unsigned> &Out) { 257 unsigned CurrentArgIndex = ~0U; 258 for (unsigned i = 0, e = Args.size(); i != e; i++) { 259 if (CurrentArgIndex == Args[i].OrigArgIndex) { 260 Out.back()++; 261 } else { 262 Out.push_back(1); 263 CurrentArgIndex++; 264 } 265 } 266 } 267 268 static void AnalyzeVarArgs(CCState &State, 269 const SmallVectorImpl<ISD::OutputArg> &Outs) { 270 State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack); 271 } 272 273 static void AnalyzeVarArgs(CCState &State, 274 const SmallVectorImpl<ISD::InputArg> &Ins) { 275 State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack); 276 } 277 278 /// Analyze incoming and outgoing function arguments. We need custom C++ code 279 /// to handle special constraints in the ABI like reversing the order of the 280 /// pieces of splitted arguments. In addition, all pieces of a certain argument 281 /// have to be passed either using registers or the stack but never mixing both. 282 template<typename ArgT> 283 static void AnalyzeArguments(CCState &State, 284 SmallVectorImpl<CCValAssign> &ArgLocs, 285 const SmallVectorImpl<ArgT> &Args) { 286 static const MCPhysReg RegList[] = { 287 MSP430::R15, MSP430::R14, MSP430::R13, MSP430::R12 288 }; 289 static const unsigned NbRegs = array_lengthof(RegList); 290 291 if (State.isVarArg()) { 292 AnalyzeVarArgs(State, Args); 293 return; 294 } 295 296 SmallVector<unsigned, 4> ArgsParts; 297 ParseFunctionArgs(Args, ArgsParts); 298 299 unsigned RegsLeft = NbRegs; 300 bool UseStack = false; 301 unsigned ValNo = 0; 302 303 for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) { 304 MVT ArgVT = Args[ValNo].VT; 305 ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags; 306 MVT LocVT = ArgVT; 307 CCValAssign::LocInfo LocInfo = CCValAssign::Full; 308 309 // Promote i8 to i16 310 if (LocVT == MVT::i8) { 311 LocVT = MVT::i16; 312 if (ArgFlags.isSExt()) 313 LocInfo = CCValAssign::SExt; 314 else if (ArgFlags.isZExt()) 315 LocInfo = CCValAssign::ZExt; 316 else 317 LocInfo = CCValAssign::AExt; 318 } 319 320 // Handle byval arguments 321 if (ArgFlags.isByVal()) { 322 State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags); 323 continue; 324 } 325 326 unsigned Parts = ArgsParts[i]; 327 328 if (!UseStack && Parts <= RegsLeft) { 329 unsigned FirstVal = ValNo; 330 for (unsigned j = 0; j < Parts; j++) { 331 unsigned Reg = State.AllocateReg(RegList, NbRegs); 332 State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo)); 333 RegsLeft--; 334 } 335 336 // Reverse the order of the pieces to agree with the "big endian" format 337 // required in the calling convention ABI. 338 SmallVectorImpl<CCValAssign>::iterator B = ArgLocs.begin() + FirstVal; 339 std::reverse(B, B + Parts); 340 } else { 341 UseStack = true; 342 for (unsigned j = 0; j < Parts; j++) 343 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State); 344 } 345 } 346 } 347 348 static void AnalyzeRetResult(CCState &State, 349 const SmallVectorImpl<ISD::InputArg> &Ins) { 350 State.AnalyzeCallResult(Ins, RetCC_MSP430); 351 } 352 353 static void AnalyzeRetResult(CCState &State, 354 const SmallVectorImpl<ISD::OutputArg> &Outs) { 355 State.AnalyzeReturn(Outs, RetCC_MSP430); 356 } 357 358 template<typename ArgT> 359 static void AnalyzeReturnValues(CCState &State, 360 SmallVectorImpl<CCValAssign> &RVLocs, 361 const SmallVectorImpl<ArgT> &Args) { 362 AnalyzeRetResult(State, Args); 363 364 // Reverse splitted return values to get the "big endian" format required 365 // to agree with the calling convention ABI. 366 std::reverse(RVLocs.begin(), RVLocs.end()); 367 } 368 369 SDValue 370 MSP430TargetLowering::LowerFormalArguments(SDValue Chain, 371 CallingConv::ID CallConv, 372 bool isVarArg, 373 const SmallVectorImpl<ISD::InputArg> 374 &Ins, 375 SDLoc dl, 376 SelectionDAG &DAG, 377 SmallVectorImpl<SDValue> &InVals) 378 const { 379 380 switch (CallConv) { 381 default: 382 llvm_unreachable("Unsupported calling convention"); 383 case CallingConv::C: 384 case CallingConv::Fast: 385 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals); 386 case CallingConv::MSP430_INTR: 387 if (Ins.empty()) 388 return Chain; 389 report_fatal_error("ISRs cannot have arguments"); 390 } 391 } 392 393 SDValue 394 MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 395 SmallVectorImpl<SDValue> &InVals) const { 396 SelectionDAG &DAG = CLI.DAG; 397 SDLoc &dl = CLI.DL; 398 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 399 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 400 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 401 SDValue Chain = CLI.Chain; 402 SDValue Callee = CLI.Callee; 403 bool &isTailCall = CLI.IsTailCall; 404 CallingConv::ID CallConv = CLI.CallConv; 405 bool isVarArg = CLI.IsVarArg; 406 407 // MSP430 target does not yet support tail call optimization. 408 isTailCall = false; 409 410 switch (CallConv) { 411 default: 412 llvm_unreachable("Unsupported calling convention"); 413 case CallingConv::Fast: 414 case CallingConv::C: 415 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall, 416 Outs, OutVals, Ins, dl, DAG, InVals); 417 case CallingConv::MSP430_INTR: 418 report_fatal_error("ISRs cannot be called directly"); 419 } 420 } 421 422 /// LowerCCCArguments - transform physical registers into virtual registers and 423 /// generate load operations for arguments places on the stack. 424 // FIXME: struct return stuff 425 SDValue 426 MSP430TargetLowering::LowerCCCArguments(SDValue Chain, 427 CallingConv::ID CallConv, 428 bool isVarArg, 429 const SmallVectorImpl<ISD::InputArg> 430 &Ins, 431 SDLoc dl, 432 SelectionDAG &DAG, 433 SmallVectorImpl<SDValue> &InVals) 434 const { 435 MachineFunction &MF = DAG.getMachineFunction(); 436 MachineFrameInfo *MFI = MF.getFrameInfo(); 437 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 438 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>(); 439 440 // Assign locations to all of the incoming arguments. 441 SmallVector<CCValAssign, 16> ArgLocs; 442 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 443 *DAG.getContext()); 444 AnalyzeArguments(CCInfo, ArgLocs, Ins); 445 446 // Create frame index for the start of the first vararg value 447 if (isVarArg) { 448 unsigned Offset = CCInfo.getNextStackOffset(); 449 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, Offset, true)); 450 } 451 452 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 453 CCValAssign &VA = ArgLocs[i]; 454 if (VA.isRegLoc()) { 455 // Arguments passed in registers 456 EVT RegVT = VA.getLocVT(); 457 switch (RegVT.getSimpleVT().SimpleTy) { 458 default: 459 { 460 #ifndef NDEBUG 461 errs() << "LowerFormalArguments Unhandled argument type: " 462 << RegVT.getSimpleVT().SimpleTy << "\n"; 463 #endif 464 llvm_unreachable(nullptr); 465 } 466 case MVT::i16: 467 unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass); 468 RegInfo.addLiveIn(VA.getLocReg(), VReg); 469 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); 470 471 // If this is an 8-bit value, it is really passed promoted to 16 472 // bits. Insert an assert[sz]ext to capture this, then truncate to the 473 // right size. 474 if (VA.getLocInfo() == CCValAssign::SExt) 475 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 476 DAG.getValueType(VA.getValVT())); 477 else if (VA.getLocInfo() == CCValAssign::ZExt) 478 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 479 DAG.getValueType(VA.getValVT())); 480 481 if (VA.getLocInfo() != CCValAssign::Full) 482 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 483 484 InVals.push_back(ArgValue); 485 } 486 } else { 487 // Sanity check 488 assert(VA.isMemLoc()); 489 490 SDValue InVal; 491 ISD::ArgFlagsTy Flags = Ins[i].Flags; 492 493 if (Flags.isByVal()) { 494 int FI = MFI->CreateFixedObject(Flags.getByValSize(), 495 VA.getLocMemOffset(), true); 496 InVal = DAG.getFrameIndex(FI, getPointerTy()); 497 } else { 498 // Load the argument to a virtual register 499 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; 500 if (ObjSize > 2) { 501 errs() << "LowerFormalArguments Unhandled argument type: " 502 << EVT(VA.getLocVT()).getEVTString() 503 << "\n"; 504 } 505 // Create the frame index object for this incoming parameter... 506 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true); 507 508 // Create the SelectionDAG nodes corresponding to a load 509 //from this parameter 510 SDValue FIN = DAG.getFrameIndex(FI, MVT::i16); 511 InVal = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, 512 MachinePointerInfo::getFixedStack(FI), 513 false, false, false, 0); 514 } 515 516 InVals.push_back(InVal); 517 } 518 } 519 520 return Chain; 521 } 522 523 SDValue 524 MSP430TargetLowering::LowerReturn(SDValue Chain, 525 CallingConv::ID CallConv, bool isVarArg, 526 const SmallVectorImpl<ISD::OutputArg> &Outs, 527 const SmallVectorImpl<SDValue> &OutVals, 528 SDLoc dl, SelectionDAG &DAG) const { 529 530 // CCValAssign - represent the assignment of the return value to a location 531 SmallVector<CCValAssign, 16> RVLocs; 532 533 // ISRs cannot return any value. 534 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) 535 report_fatal_error("ISRs cannot return any value"); 536 537 // CCState - Info about the registers and stack slot. 538 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 539 *DAG.getContext()); 540 541 // Analize return values. 542 AnalyzeReturnValues(CCInfo, RVLocs, Outs); 543 544 SDValue Flag; 545 SmallVector<SDValue, 4> RetOps(1, Chain); 546 547 // Copy the result values into the output registers. 548 for (unsigned i = 0; i != RVLocs.size(); ++i) { 549 CCValAssign &VA = RVLocs[i]; 550 assert(VA.isRegLoc() && "Can only return in registers!"); 551 552 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 553 OutVals[i], Flag); 554 555 // Guarantee that all emitted copies are stuck together, 556 // avoiding something bad. 557 Flag = Chain.getValue(1); 558 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 559 } 560 561 unsigned Opc = (CallConv == CallingConv::MSP430_INTR ? 562 MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG); 563 564 RetOps[0] = Chain; // Update chain. 565 566 // Add the flag if we have it. 567 if (Flag.getNode()) 568 RetOps.push_back(Flag); 569 570 return DAG.getNode(Opc, dl, MVT::Other, RetOps); 571 } 572 573 /// LowerCCCCallTo - functions arguments are copied from virtual regs to 574 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 575 // TODO: sret. 576 SDValue 577 MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, 578 CallingConv::ID CallConv, bool isVarArg, 579 bool isTailCall, 580 const SmallVectorImpl<ISD::OutputArg> 581 &Outs, 582 const SmallVectorImpl<SDValue> &OutVals, 583 const SmallVectorImpl<ISD::InputArg> &Ins, 584 SDLoc dl, SelectionDAG &DAG, 585 SmallVectorImpl<SDValue> &InVals) const { 586 // Analyze operands of the call, assigning locations to each operand. 587 SmallVector<CCValAssign, 16> ArgLocs; 588 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 589 *DAG.getContext()); 590 AnalyzeArguments(CCInfo, ArgLocs, Outs); 591 592 // Get a count of how many bytes are to be pushed on the stack. 593 unsigned NumBytes = CCInfo.getNextStackOffset(); 594 595 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes, 596 getPointerTy(), true), 597 dl); 598 599 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; 600 SmallVector<SDValue, 12> MemOpChains; 601 SDValue StackPtr; 602 603 // Walk the register/memloc assignments, inserting copies/loads. 604 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 605 CCValAssign &VA = ArgLocs[i]; 606 607 SDValue Arg = OutVals[i]; 608 609 // Promote the value if needed. 610 switch (VA.getLocInfo()) { 611 default: llvm_unreachable("Unknown loc info!"); 612 case CCValAssign::Full: break; 613 case CCValAssign::SExt: 614 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 615 break; 616 case CCValAssign::ZExt: 617 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 618 break; 619 case CCValAssign::AExt: 620 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 621 break; 622 } 623 624 // Arguments that can be passed on register must be kept at RegsToPass 625 // vector 626 if (VA.isRegLoc()) { 627 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 628 } else { 629 assert(VA.isMemLoc()); 630 631 if (!StackPtr.getNode()) 632 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, getPointerTy()); 633 634 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), 635 StackPtr, 636 DAG.getIntPtrConstant(VA.getLocMemOffset())); 637 638 SDValue MemOp; 639 ISD::ArgFlagsTy Flags = Outs[i].Flags; 640 641 if (Flags.isByVal()) { 642 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i16); 643 MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode, 644 Flags.getByValAlign(), 645 /*isVolatile*/false, 646 /*AlwaysInline=*/true, 647 MachinePointerInfo(), 648 MachinePointerInfo()); 649 } else { 650 MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(), 651 false, false, 0); 652 } 653 654 MemOpChains.push_back(MemOp); 655 } 656 } 657 658 // Transform all store nodes into one single node because all store nodes are 659 // independent of each other. 660 if (!MemOpChains.empty()) 661 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); 662 663 // Build a sequence of copy-to-reg nodes chained together with token chain and 664 // flag operands which copy the outgoing args into registers. The InFlag in 665 // necessary since all emitted instructions must be stuck together. 666 SDValue InFlag; 667 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 668 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 669 RegsToPass[i].second, InFlag); 670 InFlag = Chain.getValue(1); 671 } 672 673 // If the callee is a GlobalAddress node (quite common, every direct call is) 674 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 675 // Likewise ExternalSymbol -> TargetExternalSymbol. 676 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 677 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16); 678 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 679 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16); 680 681 // Returns a chain & a flag for retval copy to use. 682 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 683 SmallVector<SDValue, 8> Ops; 684 Ops.push_back(Chain); 685 Ops.push_back(Callee); 686 687 // Add argument registers to the end of the list so that they are 688 // known live into the call. 689 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 690 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 691 RegsToPass[i].second.getValueType())); 692 693 if (InFlag.getNode()) 694 Ops.push_back(InFlag); 695 696 Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops); 697 InFlag = Chain.getValue(1); 698 699 // Create the CALLSEQ_END node. 700 Chain = DAG.getCALLSEQ_END(Chain, 701 DAG.getConstant(NumBytes, getPointerTy(), true), 702 DAG.getConstant(0, getPointerTy(), true), 703 InFlag, dl); 704 InFlag = Chain.getValue(1); 705 706 // Handle result values, copying them out of physregs into vregs that we 707 // return. 708 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, 709 DAG, InVals); 710 } 711 712 /// LowerCallResult - Lower the result values of a call into the 713 /// appropriate copies out of appropriate physical registers. 714 /// 715 SDValue 716 MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 717 CallingConv::ID CallConv, bool isVarArg, 718 const SmallVectorImpl<ISD::InputArg> &Ins, 719 SDLoc dl, SelectionDAG &DAG, 720 SmallVectorImpl<SDValue> &InVals) const { 721 722 // Assign locations to each value returned by this call. 723 SmallVector<CCValAssign, 16> RVLocs; 724 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 725 *DAG.getContext()); 726 727 AnalyzeReturnValues(CCInfo, RVLocs, Ins); 728 729 // Copy all of the result registers out of their specified physreg. 730 for (unsigned i = 0; i != RVLocs.size(); ++i) { 731 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 732 RVLocs[i].getValVT(), InFlag).getValue(1); 733 InFlag = Chain.getValue(2); 734 InVals.push_back(Chain.getValue(0)); 735 } 736 737 return Chain; 738 } 739 740 SDValue MSP430TargetLowering::LowerShifts(SDValue Op, 741 SelectionDAG &DAG) const { 742 unsigned Opc = Op.getOpcode(); 743 SDNode* N = Op.getNode(); 744 EVT VT = Op.getValueType(); 745 SDLoc dl(N); 746 747 // Expand non-constant shifts to loops: 748 if (!isa<ConstantSDNode>(N->getOperand(1))) 749 switch (Opc) { 750 default: llvm_unreachable("Invalid shift opcode!"); 751 case ISD::SHL: 752 return DAG.getNode(MSP430ISD::SHL, dl, 753 VT, N->getOperand(0), N->getOperand(1)); 754 case ISD::SRA: 755 return DAG.getNode(MSP430ISD::SRA, dl, 756 VT, N->getOperand(0), N->getOperand(1)); 757 case ISD::SRL: 758 return DAG.getNode(MSP430ISD::SRL, dl, 759 VT, N->getOperand(0), N->getOperand(1)); 760 } 761 762 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 763 764 // Expand the stuff into sequence of shifts. 765 // FIXME: for some shift amounts this might be done better! 766 // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N 767 SDValue Victim = N->getOperand(0); 768 769 if (Opc == ISD::SRL && ShiftAmount) { 770 // Emit a special goodness here: 771 // srl A, 1 => clrc; rrc A 772 Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim); 773 ShiftAmount -= 1; 774 } 775 776 while (ShiftAmount--) 777 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA), 778 dl, VT, Victim); 779 780 return Victim; 781 } 782 783 SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, 784 SelectionDAG &DAG) const { 785 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 786 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 787 788 // Create the TargetGlobalAddress node, folding in the constant offset. 789 SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op), 790 getPointerTy(), Offset); 791 return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op), 792 getPointerTy(), Result); 793 } 794 795 SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op, 796 SelectionDAG &DAG) const { 797 SDLoc dl(Op); 798 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 799 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 800 801 return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result); 802 } 803 804 SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op, 805 SelectionDAG &DAG) const { 806 SDLoc dl(Op); 807 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 808 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy()); 809 810 return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result); 811 } 812 813 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, 814 ISD::CondCode CC, 815 SDLoc dl, SelectionDAG &DAG) { 816 // FIXME: Handle bittests someday 817 assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet"); 818 819 // FIXME: Handle jump negative someday 820 MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID; 821 switch (CC) { 822 default: llvm_unreachable("Invalid integer condition!"); 823 case ISD::SETEQ: 824 TCC = MSP430CC::COND_E; // aka COND_Z 825 // Minor optimization: if LHS is a constant, swap operands, then the 826 // constant can be folded into comparison. 827 if (LHS.getOpcode() == ISD::Constant) 828 std::swap(LHS, RHS); 829 break; 830 case ISD::SETNE: 831 TCC = MSP430CC::COND_NE; // aka COND_NZ 832 // Minor optimization: if LHS is a constant, swap operands, then the 833 // constant can be folded into comparison. 834 if (LHS.getOpcode() == ISD::Constant) 835 std::swap(LHS, RHS); 836 break; 837 case ISD::SETULE: 838 std::swap(LHS, RHS); // FALLTHROUGH 839 case ISD::SETUGE: 840 // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to 841 // fold constant into instruction. 842 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 843 LHS = RHS; 844 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0)); 845 TCC = MSP430CC::COND_LO; 846 break; 847 } 848 TCC = MSP430CC::COND_HS; // aka COND_C 849 break; 850 case ISD::SETUGT: 851 std::swap(LHS, RHS); // FALLTHROUGH 852 case ISD::SETULT: 853 // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to 854 // fold constant into instruction. 855 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 856 LHS = RHS; 857 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0)); 858 TCC = MSP430CC::COND_HS; 859 break; 860 } 861 TCC = MSP430CC::COND_LO; // aka COND_NC 862 break; 863 case ISD::SETLE: 864 std::swap(LHS, RHS); // FALLTHROUGH 865 case ISD::SETGE: 866 // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to 867 // fold constant into instruction. 868 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 869 LHS = RHS; 870 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0)); 871 TCC = MSP430CC::COND_L; 872 break; 873 } 874 TCC = MSP430CC::COND_GE; 875 break; 876 case ISD::SETGT: 877 std::swap(LHS, RHS); // FALLTHROUGH 878 case ISD::SETLT: 879 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to 880 // fold constant into instruction. 881 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 882 LHS = RHS; 883 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0)); 884 TCC = MSP430CC::COND_GE; 885 break; 886 } 887 TCC = MSP430CC::COND_L; 888 break; 889 } 890 891 TargetCC = DAG.getConstant(TCC, MVT::i8); 892 return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS); 893 } 894 895 896 SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 897 SDValue Chain = Op.getOperand(0); 898 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 899 SDValue LHS = Op.getOperand(2); 900 SDValue RHS = Op.getOperand(3); 901 SDValue Dest = Op.getOperand(4); 902 SDLoc dl (Op); 903 904 SDValue TargetCC; 905 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); 906 907 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(), 908 Chain, Dest, TargetCC, Flag); 909 } 910 911 SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 912 SDValue LHS = Op.getOperand(0); 913 SDValue RHS = Op.getOperand(1); 914 SDLoc dl (Op); 915 916 // If we are doing an AND and testing against zero, then the CMP 917 // will not be generated. The AND (or BIT) will generate the condition codes, 918 // but they are different from CMP. 919 // FIXME: since we're doing a post-processing, use a pseudoinstr here, so 920 // lowering & isel wouldn't diverge. 921 bool andCC = false; 922 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 923 if (RHSC->isNullValue() && LHS.hasOneUse() && 924 (LHS.getOpcode() == ISD::AND || 925 (LHS.getOpcode() == ISD::TRUNCATE && 926 LHS.getOperand(0).getOpcode() == ISD::AND))) { 927 andCC = true; 928 } 929 } 930 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 931 SDValue TargetCC; 932 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); 933 934 // Get the condition codes directly from the status register, if its easy. 935 // Otherwise a branch will be generated. Note that the AND and BIT 936 // instructions generate different flags than CMP, the carry bit can be used 937 // for NE/EQ. 938 bool Invert = false; 939 bool Shift = false; 940 bool Convert = true; 941 switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) { 942 default: 943 Convert = false; 944 break; 945 case MSP430CC::COND_HS: 946 // Res = SR & 1, no processing is required 947 break; 948 case MSP430CC::COND_LO: 949 // Res = ~(SR & 1) 950 Invert = true; 951 break; 952 case MSP430CC::COND_NE: 953 if (andCC) { 954 // C = ~Z, thus Res = SR & 1, no processing is required 955 } else { 956 // Res = ~((SR >> 1) & 1) 957 Shift = true; 958 Invert = true; 959 } 960 break; 961 case MSP430CC::COND_E: 962 Shift = true; 963 // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however, 964 // Res = (SR >> 1) & 1 is 1 word shorter. 965 break; 966 } 967 EVT VT = Op.getValueType(); 968 SDValue One = DAG.getConstant(1, VT); 969 if (Convert) { 970 SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR, 971 MVT::i16, Flag); 972 if (Shift) 973 // FIXME: somewhere this is turned into a SRL, lower it MSP specific? 974 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); 975 SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One); 976 if (Invert) 977 SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One); 978 return SR; 979 } else { 980 SDValue Zero = DAG.getConstant(0, VT); 981 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 982 SmallVector<SDValue, 4> Ops; 983 Ops.push_back(One); 984 Ops.push_back(Zero); 985 Ops.push_back(TargetCC); 986 Ops.push_back(Flag); 987 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); 988 } 989 } 990 991 SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, 992 SelectionDAG &DAG) const { 993 SDValue LHS = Op.getOperand(0); 994 SDValue RHS = Op.getOperand(1); 995 SDValue TrueV = Op.getOperand(2); 996 SDValue FalseV = Op.getOperand(3); 997 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 998 SDLoc dl (Op); 999 1000 SDValue TargetCC; 1001 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); 1002 1003 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 1004 SmallVector<SDValue, 4> Ops; 1005 Ops.push_back(TrueV); 1006 Ops.push_back(FalseV); 1007 Ops.push_back(TargetCC); 1008 Ops.push_back(Flag); 1009 1010 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); 1011 } 1012 1013 SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op, 1014 SelectionDAG &DAG) const { 1015 SDValue Val = Op.getOperand(0); 1016 EVT VT = Op.getValueType(); 1017 SDLoc dl(Op); 1018 1019 assert(VT == MVT::i16 && "Only support i16 for now!"); 1020 1021 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, 1022 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val), 1023 DAG.getValueType(Val.getValueType())); 1024 } 1025 1026 SDValue 1027 MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 1028 MachineFunction &MF = DAG.getMachineFunction(); 1029 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>(); 1030 int ReturnAddrIndex = FuncInfo->getRAIndex(); 1031 1032 if (ReturnAddrIndex == 0) { 1033 // Set up a frame object for the return address. 1034 uint64_t SlotSize = getDataLayout()->getPointerSize(); 1035 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 1036 true); 1037 FuncInfo->setRAIndex(ReturnAddrIndex); 1038 } 1039 1040 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 1041 } 1042 1043 SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op, 1044 SelectionDAG &DAG) const { 1045 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1046 MFI->setReturnAddressIsTaken(true); 1047 1048 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 1049 return SDValue(); 1050 1051 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 1052 SDLoc dl(Op); 1053 1054 if (Depth > 0) { 1055 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 1056 SDValue Offset = 1057 DAG.getConstant(getDataLayout()->getPointerSize(), MVT::i16); 1058 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 1059 DAG.getNode(ISD::ADD, dl, getPointerTy(), 1060 FrameAddr, Offset), 1061 MachinePointerInfo(), false, false, false, 0); 1062 } 1063 1064 // Just load the return address. 1065 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 1066 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 1067 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 1068 } 1069 1070 SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op, 1071 SelectionDAG &DAG) const { 1072 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1073 MFI->setFrameAddressIsTaken(true); 1074 1075 EVT VT = Op.getValueType(); 1076 SDLoc dl(Op); // FIXME probably not meaningful 1077 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 1078 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 1079 MSP430::FP, VT); 1080 while (Depth--) 1081 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 1082 MachinePointerInfo(), 1083 false, false, false, 0); 1084 return FrameAddr; 1085 } 1086 1087 SDValue MSP430TargetLowering::LowerVASTART(SDValue Op, 1088 SelectionDAG &DAG) const { 1089 MachineFunction &MF = DAG.getMachineFunction(); 1090 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>(); 1091 1092 // Frame index of first vararg argument 1093 SDValue FrameIndex = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1094 getPointerTy()); 1095 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1096 1097 // Create a store of the frame index to the location operand 1098 return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex, 1099 Op.getOperand(1), MachinePointerInfo(SV), 1100 false, false, 0); 1101 } 1102 1103 SDValue MSP430TargetLowering::LowerJumpTable(SDValue Op, 1104 SelectionDAG &DAG) const { 1105 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1106 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); 1107 return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT), 1108 getPointerTy(), Result); 1109 } 1110 1111 /// getPostIndexedAddressParts - returns true by value, base pointer and 1112 /// offset pointer and addressing mode by reference if this node can be 1113 /// combined with a load / store to form a post-indexed load / store. 1114 bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 1115 SDValue &Base, 1116 SDValue &Offset, 1117 ISD::MemIndexedMode &AM, 1118 SelectionDAG &DAG) const { 1119 1120 LoadSDNode *LD = cast<LoadSDNode>(N); 1121 if (LD->getExtensionType() != ISD::NON_EXTLOAD) 1122 return false; 1123 1124 EVT VT = LD->getMemoryVT(); 1125 if (VT != MVT::i8 && VT != MVT::i16) 1126 return false; 1127 1128 if (Op->getOpcode() != ISD::ADD) 1129 return false; 1130 1131 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { 1132 uint64_t RHSC = RHS->getZExtValue(); 1133 if ((VT == MVT::i16 && RHSC != 2) || 1134 (VT == MVT::i8 && RHSC != 1)) 1135 return false; 1136 1137 Base = Op->getOperand(0); 1138 Offset = DAG.getConstant(RHSC, VT); 1139 AM = ISD::POST_INC; 1140 return true; 1141 } 1142 1143 return false; 1144 } 1145 1146 1147 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const { 1148 switch (Opcode) { 1149 default: return nullptr; 1150 case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG"; 1151 case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG"; 1152 case MSP430ISD::RRA: return "MSP430ISD::RRA"; 1153 case MSP430ISD::RLA: return "MSP430ISD::RLA"; 1154 case MSP430ISD::RRC: return "MSP430ISD::RRC"; 1155 case MSP430ISD::CALL: return "MSP430ISD::CALL"; 1156 case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper"; 1157 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC"; 1158 case MSP430ISD::CMP: return "MSP430ISD::CMP"; 1159 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC"; 1160 case MSP430ISD::SHL: return "MSP430ISD::SHL"; 1161 case MSP430ISD::SRA: return "MSP430ISD::SRA"; 1162 } 1163 } 1164 1165 bool MSP430TargetLowering::isTruncateFree(Type *Ty1, 1166 Type *Ty2) const { 1167 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 1168 return false; 1169 1170 return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits()); 1171 } 1172 1173 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 1174 if (!VT1.isInteger() || !VT2.isInteger()) 1175 return false; 1176 1177 return (VT1.getSizeInBits() > VT2.getSizeInBits()); 1178 } 1179 1180 bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 1181 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers. 1182 return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16); 1183 } 1184 1185 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 1186 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers. 1187 return 0 && VT1 == MVT::i8 && VT2 == MVT::i16; 1188 } 1189 1190 bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { 1191 return isZExtFree(Val.getValueType(), VT2); 1192 } 1193 1194 //===----------------------------------------------------------------------===// 1195 // Other Lowering Code 1196 //===----------------------------------------------------------------------===// 1197 1198 MachineBasicBlock* 1199 MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI, 1200 MachineBasicBlock *BB) const { 1201 MachineFunction *F = BB->getParent(); 1202 MachineRegisterInfo &RI = F->getRegInfo(); 1203 DebugLoc dl = MI->getDebugLoc(); 1204 const TargetInstrInfo &TII = 1205 *getTargetMachine().getSubtargetImpl()->getInstrInfo(); 1206 1207 unsigned Opc; 1208 const TargetRegisterClass * RC; 1209 switch (MI->getOpcode()) { 1210 default: llvm_unreachable("Invalid shift opcode!"); 1211 case MSP430::Shl8: 1212 Opc = MSP430::SHL8r1; 1213 RC = &MSP430::GR8RegClass; 1214 break; 1215 case MSP430::Shl16: 1216 Opc = MSP430::SHL16r1; 1217 RC = &MSP430::GR16RegClass; 1218 break; 1219 case MSP430::Sra8: 1220 Opc = MSP430::SAR8r1; 1221 RC = &MSP430::GR8RegClass; 1222 break; 1223 case MSP430::Sra16: 1224 Opc = MSP430::SAR16r1; 1225 RC = &MSP430::GR16RegClass; 1226 break; 1227 case MSP430::Srl8: 1228 Opc = MSP430::SAR8r1c; 1229 RC = &MSP430::GR8RegClass; 1230 break; 1231 case MSP430::Srl16: 1232 Opc = MSP430::SAR16r1c; 1233 RC = &MSP430::GR16RegClass; 1234 break; 1235 } 1236 1237 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1238 MachineFunction::iterator I = BB; 1239 ++I; 1240 1241 // Create loop block 1242 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB); 1243 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB); 1244 1245 F->insert(I, LoopBB); 1246 F->insert(I, RemBB); 1247 1248 // Update machine-CFG edges by transferring all successors of the current 1249 // block to the block containing instructions after shift. 1250 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)), 1251 BB->end()); 1252 RemBB->transferSuccessorsAndUpdatePHIs(BB); 1253 1254 // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB 1255 BB->addSuccessor(LoopBB); 1256 BB->addSuccessor(RemBB); 1257 LoopBB->addSuccessor(RemBB); 1258 LoopBB->addSuccessor(LoopBB); 1259 1260 unsigned ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass); 1261 unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass); 1262 unsigned ShiftReg = RI.createVirtualRegister(RC); 1263 unsigned ShiftReg2 = RI.createVirtualRegister(RC); 1264 unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg(); 1265 unsigned SrcReg = MI->getOperand(1).getReg(); 1266 unsigned DstReg = MI->getOperand(0).getReg(); 1267 1268 // BB: 1269 // cmp 0, N 1270 // je RemBB 1271 BuildMI(BB, dl, TII.get(MSP430::CMP8ri)) 1272 .addReg(ShiftAmtSrcReg).addImm(0); 1273 BuildMI(BB, dl, TII.get(MSP430::JCC)) 1274 .addMBB(RemBB) 1275 .addImm(MSP430CC::COND_E); 1276 1277 // LoopBB: 1278 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB] 1279 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB] 1280 // ShiftReg2 = shift ShiftReg 1281 // ShiftAmt2 = ShiftAmt - 1; 1282 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg) 1283 .addReg(SrcReg).addMBB(BB) 1284 .addReg(ShiftReg2).addMBB(LoopBB); 1285 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg) 1286 .addReg(ShiftAmtSrcReg).addMBB(BB) 1287 .addReg(ShiftAmtReg2).addMBB(LoopBB); 1288 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2) 1289 .addReg(ShiftReg); 1290 BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2) 1291 .addReg(ShiftAmtReg).addImm(1); 1292 BuildMI(LoopBB, dl, TII.get(MSP430::JCC)) 1293 .addMBB(LoopBB) 1294 .addImm(MSP430CC::COND_NE); 1295 1296 // RemBB: 1297 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB] 1298 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg) 1299 .addReg(SrcReg).addMBB(BB) 1300 .addReg(ShiftReg2).addMBB(LoopBB); 1301 1302 MI->eraseFromParent(); // The pseudo instruction is gone now. 1303 return RemBB; 1304 } 1305 1306 MachineBasicBlock* 1307 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1308 MachineBasicBlock *BB) const { 1309 unsigned Opc = MI->getOpcode(); 1310 1311 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 || 1312 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 || 1313 Opc == MSP430::Srl8 || Opc == MSP430::Srl16) 1314 return EmitShiftInstr(MI, BB); 1315 1316 const TargetInstrInfo &TII = 1317 *getTargetMachine().getSubtargetImpl()->getInstrInfo(); 1318 DebugLoc dl = MI->getDebugLoc(); 1319 1320 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) && 1321 "Unexpected instr type to insert"); 1322 1323 // To "insert" a SELECT instruction, we actually have to insert the diamond 1324 // control-flow pattern. The incoming instruction knows the destination vreg 1325 // to set, the condition code register to branch on, the true/false values to 1326 // select between, and a branch opcode to use. 1327 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1328 MachineFunction::iterator I = BB; 1329 ++I; 1330 1331 // thisMBB: 1332 // ... 1333 // TrueVal = ... 1334 // cmpTY ccX, r1, r2 1335 // jCC copy1MBB 1336 // fallthrough --> copy0MBB 1337 MachineBasicBlock *thisMBB = BB; 1338 MachineFunction *F = BB->getParent(); 1339 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1340 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); 1341 F->insert(I, copy0MBB); 1342 F->insert(I, copy1MBB); 1343 // Update machine-CFG edges by transferring all successors of the current 1344 // block to the new block which will contain the Phi node for the select. 1345 copy1MBB->splice(copy1MBB->begin(), BB, 1346 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1347 copy1MBB->transferSuccessorsAndUpdatePHIs(BB); 1348 // Next, add the true and fallthrough blocks as its successors. 1349 BB->addSuccessor(copy0MBB); 1350 BB->addSuccessor(copy1MBB); 1351 1352 BuildMI(BB, dl, TII.get(MSP430::JCC)) 1353 .addMBB(copy1MBB) 1354 .addImm(MI->getOperand(3).getImm()); 1355 1356 // copy0MBB: 1357 // %FalseValue = ... 1358 // # fallthrough to copy1MBB 1359 BB = copy0MBB; 1360 1361 // Update machine-CFG edges 1362 BB->addSuccessor(copy1MBB); 1363 1364 // copy1MBB: 1365 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1366 // ... 1367 BB = copy1MBB; 1368 BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), 1369 MI->getOperand(0).getReg()) 1370 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 1371 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 1372 1373 MI->eraseFromParent(); // The pseudo instruction is gone now. 1374 return BB; 1375 } 1376