1 //===-- LanaiTargetMachine.cpp - Define TargetMachine for Lanai ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Implements the info about Lanai target spec. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "LanaiTargetMachine.h" 15 16 #include "Lanai.h" 17 #include "LanaiTargetObjectFile.h" 18 #include "LanaiTargetTransformInfo.h" 19 #include "llvm/Analysis/TargetTransformInfo.h" 20 #include "llvm/CodeGen/Passes.h" 21 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 22 #include "llvm/CodeGen/TargetPassConfig.h" 23 #include "llvm/Support/FormattedStream.h" 24 #include "llvm/Support/TargetRegistry.h" 25 #include "llvm/Target/TargetOptions.h" 26 27 using namespace llvm; 28 29 namespace llvm { 30 void initializeLanaiMemAluCombinerPass(PassRegistry &); 31 } // namespace llvm 32 33 extern "C" void LLVMInitializeLanaiTarget() { 34 // Register the target. 35 RegisterTargetMachine<LanaiTargetMachine> registered_target(TheLanaiTarget); 36 } 37 38 static std::string computeDataLayout() { 39 // Data layout (keep in sync with clang/lib/Basic/Targets.cpp) 40 return "E" // Big endian 41 "-m:e" // ELF name manging 42 "-p:32:32" // 32-bit pointers, 32 bit aligned 43 "-i64:64" // 64 bit integers, 64 bit aligned 44 "-a:0:32" // 32 bit alignment of objects of aggregate type 45 "-n32" // 32 bit native integer width 46 "-S64"; // 64 bit natural stack alignment 47 } 48 49 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { 50 if (!RM.hasValue()) 51 return Reloc::PIC_; 52 return *RM; 53 } 54 55 LanaiTargetMachine::LanaiTargetMachine(const Target &T, const Triple &TT, 56 StringRef Cpu, StringRef FeatureString, 57 const TargetOptions &Options, 58 Optional<Reloc::Model> RM, 59 CodeModel::Model CodeModel, 60 CodeGenOpt::Level OptLevel) 61 : LLVMTargetMachine(T, computeDataLayout(), TT, Cpu, FeatureString, Options, 62 getEffectiveRelocModel(RM), CodeModel, OptLevel), 63 Subtarget(TT, Cpu, FeatureString, *this, Options, CodeModel, OptLevel), 64 TLOF(new LanaiTargetObjectFile()) { 65 initAsmInfo(); 66 } 67 68 TargetIRAnalysis LanaiTargetMachine::getTargetIRAnalysis() { 69 return TargetIRAnalysis([this](const Function &F) { 70 return TargetTransformInfo(LanaiTTIImpl(this, F)); 71 }); 72 } 73 74 namespace { 75 // Lanai Code Generator Pass Configuration Options. 76 class LanaiPassConfig : public TargetPassConfig { 77 public: 78 LanaiPassConfig(LanaiTargetMachine *TM, PassManagerBase *PassManager) 79 : TargetPassConfig(TM, *PassManager) {} 80 81 LanaiTargetMachine &getLanaiTargetMachine() const { 82 return getTM<LanaiTargetMachine>(); 83 } 84 85 bool addInstSelector() override; 86 void addPreSched2() override; 87 void addPreEmitPass() override; 88 }; 89 } // namespace 90 91 TargetPassConfig * 92 LanaiTargetMachine::createPassConfig(PassManagerBase &PassManager) { 93 return new LanaiPassConfig(this, &PassManager); 94 } 95 96 // Install an instruction selector pass. 97 bool LanaiPassConfig::addInstSelector() { 98 addPass(createLanaiISelDag(getLanaiTargetMachine())); 99 return false; 100 } 101 102 // Implemented by targets that want to run passes immediately before 103 // machine code is emitted. 104 void LanaiPassConfig::addPreEmitPass() { 105 addPass(createLanaiDelaySlotFillerPass(getLanaiTargetMachine())); 106 } 107 108 // Run passes after prolog-epilog insertion and before the second instruction 109 // scheduling pass. 110 void LanaiPassConfig::addPreSched2() { 111 addPass(createLanaiMemAluCombinerPass()); 112 } 113