1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/IR/Module.h"
21 #include "llvm/PassManager.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
25 #include "llvm/Transforms/Scalar.h"
26 
27 using namespace llvm;
28 
29 static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
30       cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
31 
32 static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
33       cl::Hidden, cl::ZeroOrMore, cl::init(false),
34       cl::desc("Disable Hexagon MI Scheduling"));
35 
36 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
37       cl::Hidden, cl::ZeroOrMore, cl::init(false),
38       cl::desc("Disable Hexagon CFG Optimization"));
39 
40 
41 /// HexagonTargetMachineModule - Note that this is used on hosts that
42 /// cannot link in a library unless there are references into the
43 /// library.  In particular, it seems that it is not possible to get
44 /// things to work on Win32 without this.  Though it is unused, do not
45 /// remove it.
46 extern "C" int HexagonTargetMachineModule;
47 int HexagonTargetMachineModule = 0;
48 
49 extern "C" void LLVMInitializeHexagonTarget() {
50   // Register the target.
51   RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
52 }
53 
54 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
55   return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
56 }
57 
58 static MachineSchedRegistry
59 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
60                     createVLIWMachineSched);
61 
62 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
63 ///
64 
65 /// Hexagon_TODO: Do I need an aggregate alignment?
66 ///
67 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
68                                            StringRef CPU, StringRef FS,
69                                            const TargetOptions &Options,
70                                            Reloc::Model RM, CodeModel::Model CM,
71                                            CodeGenOpt::Level OL)
72     : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
73       TLOF(make_unique<HexagonTargetObjectFile>()),
74       Subtarget(TT, CPU, FS, *this) {
75     initAsmInfo();
76 }
77 
78 HexagonTargetMachine::~HexagonTargetMachine() {}
79 
80 namespace {
81 /// Hexagon Code Generator Pass Configuration Options.
82 class HexagonPassConfig : public TargetPassConfig {
83 public:
84   HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
85     : TargetPassConfig(TM, PM) {
86     // FIXME: Rather than calling enablePass(&MachineSchedulerID) below, define
87     // HexagonSubtarget::enableMachineScheduler() { return true; }.
88     // That will bypass the SelectionDAG VLIW scheduler, which is probably just
89     // hurting compile time and will be removed eventually anyway.
90     if (DisableHexagonMISched)
91       disablePass(&MachineSchedulerID);
92     else
93       enablePass(&MachineSchedulerID);
94   }
95 
96   HexagonTargetMachine &getHexagonTargetMachine() const {
97     return getTM<HexagonTargetMachine>();
98   }
99 
100   ScheduleDAGInstrs *
101   createMachineScheduler(MachineSchedContext *C) const override {
102     return createVLIWMachineSched(C);
103   }
104 
105   bool addInstSelector() override;
106   void addPreRegAlloc() override;
107   void addPostRegAlloc() override;
108   void addPreSched2() override;
109   void addPreEmitPass() override;
110 };
111 } // namespace
112 
113 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
114   return new HexagonPassConfig(this, PM);
115 }
116 
117 bool HexagonPassConfig::addInstSelector() {
118   HexagonTargetMachine &TM = getHexagonTargetMachine();
119   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
120 
121   if (!NoOpt)
122     addPass(createHexagonRemoveExtendArgs(TM));
123 
124   addPass(createHexagonISelDag(TM, getOptLevel()));
125 
126   if (!NoOpt) {
127     addPass(createHexagonPeephole());
128     printAndVerify("After hexagon peephole pass");
129   }
130 
131   return false;
132 }
133 
134 void HexagonPassConfig::addPreRegAlloc() {
135   if (getOptLevel() != CodeGenOpt::None)
136     if (!DisableHardwareLoops)
137       addPass(createHexagonHardwareLoops(), false);
138 }
139 
140 void HexagonPassConfig::addPostRegAlloc() {
141   const HexagonTargetMachine &TM = getHexagonTargetMachine();
142   if (getOptLevel() != CodeGenOpt::None)
143     if (!DisableHexagonCFGOpt)
144       addPass(createHexagonCFGOptimizer(TM), false);
145 }
146 
147 void HexagonPassConfig::addPreSched2() {
148   const HexagonTargetMachine &TM = getHexagonTargetMachine();
149 
150   addPass(createHexagonCopyToCombine(), false);
151   if (getOptLevel() != CodeGenOpt::None)
152     addPass(&IfConverterID, false);
153   addPass(createHexagonSplitConst32AndConst64(TM));
154 }
155 
156 void HexagonPassConfig::addPreEmitPass() {
157   const HexagonTargetMachine &TM = getHexagonTargetMachine();
158   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
159 
160   if (!NoOpt)
161     addPass(createHexagonNewValueJump(), false);
162 
163   // Expand Spill code for predicate registers.
164   addPass(createHexagonExpandPredSpillCode(TM), false);
165 
166   // Split up TFRcondsets into conditional transfers.
167   addPass(createHexagonSplitTFRCondSets(TM), false);
168 
169   // Create Packets.
170   if (!NoOpt) {
171     if (!DisableHardwareLoops)
172       addPass(createHexagonFixupHwLoops(), false);
173     addPass(createHexagonPacketizer(), false);
174   }
175 }
176