1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Implements the info about Hexagon target spec. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "HexagonTargetMachine.h" 15 #include "Hexagon.h" 16 #include "HexagonISelLowering.h" 17 #include "HexagonMachineScheduler.h" 18 #include "llvm/CodeGen/Passes.h" 19 #include "llvm/IR/Module.h" 20 #include "llvm/PassManager.h" 21 #include "llvm/Support/CommandLine.h" 22 #include "llvm/Support/TargetRegistry.h" 23 #include "llvm/Transforms/IPO/PassManagerBuilder.h" 24 #include "llvm/Transforms/Scalar.h" 25 26 using namespace llvm; 27 28 static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops", 29 cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target")); 30 31 static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched", 32 cl::Hidden, cl::ZeroOrMore, cl::init(false), 33 cl::desc("Disable Hexagon MI Scheduling")); 34 35 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt", 36 cl::Hidden, cl::ZeroOrMore, cl::init(false), 37 cl::desc("Disable Hexagon CFG Optimization")); 38 39 40 /// HexagonTargetMachineModule - Note that this is used on hosts that 41 /// cannot link in a library unless there are references into the 42 /// library. In particular, it seems that it is not possible to get 43 /// things to work on Win32 without this. Though it is unused, do not 44 /// remove it. 45 extern "C" int HexagonTargetMachineModule; 46 int HexagonTargetMachineModule = 0; 47 48 extern "C" void LLVMInitializeHexagonTarget() { 49 // Register the target. 50 RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget); 51 } 52 53 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) { 54 return new VLIWMachineScheduler(C, new ConvergingVLIWScheduler()); 55 } 56 57 static MachineSchedRegistry 58 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", 59 createVLIWMachineSched); 60 61 /// HexagonTargetMachine ctor - Create an ILP32 architecture model. 62 /// 63 64 /// Hexagon_TODO: Do I need an aggregate alignment? 65 /// 66 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT, 67 StringRef CPU, StringRef FS, 68 const TargetOptions &Options, 69 Reloc::Model RM, 70 CodeModel::Model CM, 71 CodeGenOpt::Level OL) 72 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 73 DL("e-p:32:32:32-" 74 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-" 75 "f64:64:64-f32:32:32-a0:0-n32") , 76 Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this), 77 TSInfo(*this), 78 FrameLowering(Subtarget), 79 InstrItins(&Subtarget.getInstrItineraryData()) { 80 setMCUseCFI(false); 81 } 82 83 // addPassesForOptimizations - Allow the backend (target) to add Target 84 // Independent Optimization passes to the Pass Manager. 85 bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) { 86 if (getOptLevel() != CodeGenOpt::None) { 87 PM.add(createConstantPropagationPass()); 88 PM.add(createLoopSimplifyPass()); 89 PM.add(createDeadCodeEliminationPass()); 90 PM.add(createConstantPropagationPass()); 91 PM.add(createLoopUnrollPass()); 92 PM.add(createLoopStrengthReducePass()); 93 } 94 return true; 95 } 96 97 namespace { 98 /// Hexagon Code Generator Pass Configuration Options. 99 class HexagonPassConfig : public TargetPassConfig { 100 public: 101 HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM) 102 : TargetPassConfig(TM, PM) { 103 // Enable MI scheduler. 104 if (!DisableHexagonMISched) { 105 enablePass(&MachineSchedulerID); 106 MachineSchedRegistry::setDefault(createVLIWMachineSched); 107 } 108 } 109 110 HexagonTargetMachine &getHexagonTargetMachine() const { 111 return getTM<HexagonTargetMachine>(); 112 } 113 114 virtual bool addInstSelector(); 115 virtual bool addPreRegAlloc(); 116 virtual bool addPostRegAlloc(); 117 virtual bool addPreSched2(); 118 virtual bool addPreEmitPass(); 119 }; 120 } // namespace 121 122 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) { 123 return new HexagonPassConfig(this, PM); 124 } 125 126 bool HexagonPassConfig::addInstSelector() { 127 const HexagonTargetMachine &TM = getHexagonTargetMachine(); 128 bool NoOpt = (getOptLevel() == CodeGenOpt::None); 129 130 if (!NoOpt) 131 addPass(createHexagonRemoveExtendArgs(TM)); 132 133 addPass(createHexagonISelDag(TM, getOptLevel())); 134 135 if (!NoOpt) { 136 addPass(createHexagonPeephole()); 137 printAndVerify("After hexagon peephole pass"); 138 } 139 140 return false; 141 } 142 143 bool HexagonPassConfig::addPreRegAlloc() { 144 if (getOptLevel() != CodeGenOpt::None) 145 if (!DisableHardwareLoops) 146 addPass(createHexagonHardwareLoops()); 147 return false; 148 } 149 150 bool HexagonPassConfig::addPostRegAlloc() { 151 const HexagonTargetMachine &TM = getHexagonTargetMachine(); 152 if (getOptLevel() != CodeGenOpt::None) 153 if (!DisableHexagonCFGOpt) 154 addPass(createHexagonCFGOptimizer(TM)); 155 return false; 156 } 157 158 bool HexagonPassConfig::addPreSched2() { 159 if (getOptLevel() != CodeGenOpt::None) 160 addPass(&IfConverterID); 161 return false; 162 } 163 164 bool HexagonPassConfig::addPreEmitPass() { 165 const HexagonTargetMachine &TM = getHexagonTargetMachine(); 166 bool NoOpt = (getOptLevel() == CodeGenOpt::None); 167 168 if (!NoOpt) 169 addPass(createHexagonNewValueJump()); 170 171 // Expand Spill code for predicate registers. 172 addPass(createHexagonExpandPredSpillCode(TM)); 173 174 // Split up TFRcondsets into conditional transfers. 175 addPass(createHexagonSplitTFRCondSets(TM)); 176 177 // Create Packets. 178 if (!NoOpt) { 179 if (!DisableHardwareLoops) 180 addPass(createHexagonFixupHwLoops()); 181 addPass(createHexagonPacketizer()); 182 } 183 184 return false; 185 } 186