1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
22 #include "llvm/IR/LegacyPassManager.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
27 #include "llvm/Transforms/Scalar.h"
28 
29 using namespace llvm;
30 
31 static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
32   cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
33 
34 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
35   cl::init(true), cl::desc("Enable RDF-based optimizations"));
36 
37 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
38   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
39 
40 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
41   cl::Hidden, cl::ZeroOrMore, cl::init(false),
42   cl::desc("Disable Hexagon Addressing Mode Optimization"));
43 
44 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
45   cl::Hidden, cl::ZeroOrMore, cl::init(false),
46   cl::desc("Disable Hexagon CFG Optimization"));
47 
48 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
49   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
50 
51 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
52   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
53 
54 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
55   cl::init(true), cl::Hidden, cl::ZeroOrMore,
56   cl::desc("Early expansion of MUX"));
57 
58 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
59   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
60 
61 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
62   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
63 
64 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
65   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
66 
67 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
68   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
69 
70 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
71   cl::desc("Enable converting conditional transfers into MUX instructions"));
72 
73 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
74   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
75   "predicate instructions"));
76 
77 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
78   cl::init(false), cl::Hidden, cl::ZeroOrMore,
79   cl::desc("Enable loop data prefetch on Hexagon"));
80 
81 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
82   cl::desc("Disable splitting double registers"));
83 
84 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
85   cl::Hidden, cl::desc("Bit simplification"));
86 
87 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
88   cl::Hidden, cl::desc("Loop rescheduling"));
89 
90 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
91   cl::Hidden, cl::desc("Disable backend optimizations"));
92 
93 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
94   cl::Hidden, cl::ZeroOrMore, cl::init(false),
95   cl::desc("Enable Hexagon Vector print instr pass"));
96 
97 static cl::opt<bool> EnableTrapUnreachable("hexagon-trap-unreachable",
98   cl::Hidden, cl::ZeroOrMore, cl::init(false),
99   cl::desc("Enable generating trap for unreachable"));
100 
101 /// HexagonTargetMachineModule - Note that this is used on hosts that
102 /// cannot link in a library unless there are references into the
103 /// library.  In particular, it seems that it is not possible to get
104 /// things to work on Win32 without this.  Though it is unused, do not
105 /// remove it.
106 extern "C" int HexagonTargetMachineModule;
107 int HexagonTargetMachineModule = 0;
108 
109 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
110   ScheduleDAGMILive *DAG =
111     new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
112   DAG->addMutation(make_unique<HexagonSubtarget::UsrOverflowMutation>());
113   DAG->addMutation(make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
114   DAG->addMutation(make_unique<HexagonSubtarget::CallMutation>());
115   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
116   return DAG;
117 }
118 
119 static MachineSchedRegistry
120 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
121                     createVLIWMachineSched);
122 
123 namespace llvm {
124   extern char &HexagonExpandCondsetsID;
125   void initializeHexagonConstExtendersPass(PassRegistry&);
126   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
127   void initializeHexagonExpandCondsetsPass(PassRegistry&);
128   void initializeHexagonGenMuxPass(PassRegistry&);
129   void initializeHexagonHardwareLoopsPass(PassRegistry&);
130   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
131   void initializeHexagonVectorLoopCarriedReusePass(PassRegistry&);
132   void initializeHexagonNewValueJumpPass(PassRegistry&);
133   void initializeHexagonOptAddrModePass(PassRegistry&);
134   void initializeHexagonPacketizerPass(PassRegistry&);
135   void initializeHexagonRDFOptPass(PassRegistry&);
136   Pass *createHexagonLoopIdiomPass();
137   Pass *createHexagonVectorLoopCarriedReusePass();
138 
139   FunctionPass *createHexagonBitSimplify();
140   FunctionPass *createHexagonBranchRelaxation();
141   FunctionPass *createHexagonCallFrameInformation();
142   FunctionPass *createHexagonCFGOptimizer();
143   FunctionPass *createHexagonCommonGEP();
144   FunctionPass *createHexagonConstExtenders();
145   FunctionPass *createHexagonConstPropagationPass();
146   FunctionPass *createHexagonCopyToCombine();
147   FunctionPass *createHexagonEarlyIfConversion();
148   FunctionPass *createHexagonFixupHwLoops();
149   FunctionPass *createHexagonGatherPacketize();
150   FunctionPass *createHexagonGenExtract();
151   FunctionPass *createHexagonGenInsert();
152   FunctionPass *createHexagonGenMux();
153   FunctionPass *createHexagonGenPredicate();
154   FunctionPass *createHexagonHardwareLoops();
155   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
156                                      CodeGenOpt::Level OptLevel);
157   FunctionPass *createHexagonLoopRescheduling();
158   FunctionPass *createHexagonNewValueJump();
159   FunctionPass *createHexagonOptimizeSZextends();
160   FunctionPass *createHexagonOptAddrMode();
161   FunctionPass *createHexagonPacketizer();
162   FunctionPass *createHexagonPeephole();
163   FunctionPass *createHexagonRDFOpt();
164   FunctionPass *createHexagonSplitConst32AndConst64();
165   FunctionPass *createHexagonSplitDoubleRegs();
166   FunctionPass *createHexagonStoreWidening();
167   FunctionPass *createHexagonVectorPrint();
168 } // end namespace llvm;
169 
170 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
171   if (!RM.hasValue())
172     return Reloc::Static;
173   return *RM;
174 }
175 
176 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
177   if (CM)
178     return *CM;
179   return CodeModel::Small;
180 }
181 
182 extern "C" void LLVMInitializeHexagonTarget() {
183   // Register the target.
184   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
185 
186   PassRegistry &PR = *PassRegistry::getPassRegistry();
187   initializeHexagonConstExtendersPass(PR);
188   initializeHexagonEarlyIfConversionPass(PR);
189   initializeHexagonGenMuxPass(PR);
190   initializeHexagonHardwareLoopsPass(PR);
191   initializeHexagonLoopIdiomRecognizePass(PR);
192   initializeHexagonVectorLoopCarriedReusePass(PR);
193   initializeHexagonNewValueJumpPass(PR);
194   initializeHexagonOptAddrModePass(PR);
195   initializeHexagonPacketizerPass(PR);
196   initializeHexagonRDFOptPass(PR);
197 }
198 
199 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
200                                            StringRef CPU, StringRef FS,
201                                            const TargetOptions &Options,
202                                            Optional<Reloc::Model> RM,
203                                            Optional<CodeModel::Model> CM,
204                                            CodeGenOpt::Level OL, bool JIT)
205     // Specify the vector alignment explicitly. For v512x1, the calculated
206     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
207     // the required minimum of 64 bytes.
208     : LLVMTargetMachine(
209           T,
210           "e-m:e-p:32:32:32-a:0-n16:32-"
211           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
212           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
213           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
214           getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL)),
215       TLOF(make_unique<HexagonTargetObjectFile>()) {
216   if (EnableTrapUnreachable)
217     this->Options.TrapUnreachable = true;
218   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
219   initAsmInfo();
220 }
221 
222 const HexagonSubtarget *
223 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
224   AttributeList FnAttrs = F.getAttributes();
225   Attribute CPUAttr =
226       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
227   Attribute FSAttr =
228       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
229 
230   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
231                         ? CPUAttr.getValueAsString().str()
232                         : TargetCPU;
233   std::string FS = !FSAttr.hasAttribute(Attribute::None)
234                        ? FSAttr.getValueAsString().str()
235                        : TargetFS;
236 
237   auto &I = SubtargetMap[CPU + FS];
238   if (!I) {
239     // This needs to be done before we create a new subtarget since any
240     // creation will depend on the TM and the code generation flags on the
241     // function that reside in TargetOptions.
242     resetTargetOptions(F);
243     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
244   }
245   return I.get();
246 }
247 
248 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
249   PMB.addExtension(
250     PassManagerBuilder::EP_LateLoopOptimizations,
251     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
252       PM.add(createHexagonLoopIdiomPass());
253     });
254   PMB.addExtension(
255     PassManagerBuilder::EP_LoopOptimizerEnd,
256     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
257       PM.add(createHexagonVectorLoopCarriedReusePass());
258     });
259 }
260 
261 TargetTransformInfo
262 HexagonTargetMachine::getTargetTransformInfo(const Function &F) {
263   return TargetTransformInfo(HexagonTTIImpl(this, F));
264 }
265 
266 
267 HexagonTargetMachine::~HexagonTargetMachine() {}
268 
269 namespace {
270 /// Hexagon Code Generator Pass Configuration Options.
271 class HexagonPassConfig : public TargetPassConfig {
272 public:
273   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
274     : TargetPassConfig(TM, PM) {}
275 
276   HexagonTargetMachine &getHexagonTargetMachine() const {
277     return getTM<HexagonTargetMachine>();
278   }
279 
280   ScheduleDAGInstrs *
281   createMachineScheduler(MachineSchedContext *C) const override {
282     return createVLIWMachineSched(C);
283   }
284 
285   void addIRPasses() override;
286   bool addInstSelector() override;
287   void addPreRegAlloc() override;
288   void addPostRegAlloc() override;
289   void addPreSched2() override;
290   void addPreEmitPass() override;
291 };
292 } // namespace
293 
294 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
295   return new HexagonPassConfig(*this, PM);
296 }
297 
298 void HexagonPassConfig::addIRPasses() {
299   TargetPassConfig::addIRPasses();
300   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
301 
302   addPass(createAtomicExpandPass());
303   if (!NoOpt) {
304     if (EnableLoopPrefetch)
305       addPass(createLoopDataPrefetchPass());
306     if (EnableCommGEP)
307       addPass(createHexagonCommonGEP());
308     // Replace certain combinations of shifts and ands with extracts.
309     if (EnableGenExtract)
310       addPass(createHexagonGenExtract());
311   }
312 }
313 
314 bool HexagonPassConfig::addInstSelector() {
315   HexagonTargetMachine &TM = getHexagonTargetMachine();
316   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
317 
318   if (!NoOpt)
319     addPass(createHexagonOptimizeSZextends());
320 
321   addPass(createHexagonISelDag(TM, getOptLevel()));
322 
323   if (!NoOpt) {
324     // Create logical operations on predicate registers.
325     if (EnableGenPred)
326       addPass(createHexagonGenPredicate());
327     // Rotate loops to expose bit-simplification opportunities.
328     if (EnableLoopResched)
329       addPass(createHexagonLoopRescheduling());
330     // Split double registers.
331     if (!DisableHSDR)
332       addPass(createHexagonSplitDoubleRegs());
333     // Bit simplification.
334     if (EnableBitSimplify)
335       addPass(createHexagonBitSimplify());
336     addPass(createHexagonPeephole());
337     // Constant propagation.
338     if (!DisableHCP) {
339       addPass(createHexagonConstPropagationPass());
340       addPass(&UnreachableMachineBlockElimID);
341     }
342     if (EnableGenInsert)
343       addPass(createHexagonGenInsert());
344     if (EnableEarlyIf)
345       addPass(createHexagonEarlyIfConversion());
346   }
347 
348   return false;
349 }
350 
351 void HexagonPassConfig::addPreRegAlloc() {
352   if (getOptLevel() != CodeGenOpt::None) {
353     if (EnableCExtOpt)
354       addPass(createHexagonConstExtenders());
355     if (EnableExpandCondsets)
356       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
357     if (!DisableStoreWidening)
358       addPass(createHexagonStoreWidening());
359     if (!DisableHardwareLoops)
360       addPass(createHexagonHardwareLoops());
361   }
362   if (TM->getOptLevel() >= CodeGenOpt::Default)
363     addPass(&MachinePipelinerID);
364 }
365 
366 void HexagonPassConfig::addPostRegAlloc() {
367   if (getOptLevel() != CodeGenOpt::None) {
368     if (EnableRDFOpt)
369       addPass(createHexagonRDFOpt());
370     if (!DisableHexagonCFGOpt)
371       addPass(createHexagonCFGOptimizer());
372     if (!DisableAModeOpt)
373       addPass(createHexagonOptAddrMode());
374   }
375 }
376 
377 void HexagonPassConfig::addPreSched2() {
378   addPass(createHexagonCopyToCombine());
379   if (getOptLevel() != CodeGenOpt::None)
380     addPass(&IfConverterID);
381   addPass(createHexagonSplitConst32AndConst64());
382 }
383 
384 void HexagonPassConfig::addPreEmitPass() {
385   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
386 
387   if (!NoOpt)
388     addPass(createHexagonNewValueJump());
389 
390   addPass(createHexagonBranchRelaxation());
391 
392   // Create Packets.
393   if (!NoOpt) {
394     if (!DisableHardwareLoops)
395       addPass(createHexagonFixupHwLoops());
396     // Generate MUX from pairs of conditional transfers.
397     if (EnableGenMux)
398       addPass(createHexagonGenMux());
399   }
400 
401   // Create packets for 2 instructions that consitute a gather instruction.
402   // Do this regardless of the opt level.
403   addPass(createHexagonGatherPacketize(), false);
404 
405   if (!NoOpt)
406     addPass(createHexagonPacketizer(), false);
407 
408   if (EnableVectorPrint)
409     addPass(createHexagonVectorPrint(), false);
410 
411   // Add CFI instructions if necessary.
412   addPass(createHexagonCallFrameInformation(), false);
413 }
414