1 //===- HexagonSubtarget.cpp - Hexagon Subtarget Information ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the Hexagon specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Hexagon.h"
15 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "MCTargetDesc/HexagonMCTargetDesc.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/MachineOperand.h"
25 #include "llvm/CodeGen/ScheduleDAG.h"
26 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include <algorithm>
30 #include <cassert>
31 #include <map>
32 
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "hexagon-subtarget"
36 
37 #define GET_SUBTARGETINFO_CTOR
38 #define GET_SUBTARGETINFO_TARGET_DESC
39 #include "HexagonGenSubtargetInfo.inc"
40 
41 static cl::opt<bool> EnableMemOps("enable-hexagon-memops",
42   cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(true),
43   cl::desc("Generate V4 MEMOP in code generation for Hexagon target"));
44 
45 static cl::opt<bool> DisableMemOps("disable-hexagon-memops",
46   cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(false),
47   cl::desc("Do not generate V4 MEMOP in code generation for Hexagon target"));
48 
49 static cl::opt<bool> EnableIEEERndNear("enable-hexagon-ieee-rnd-near",
50   cl::Hidden, cl::ZeroOrMore, cl::init(false),
51   cl::desc("Generate non-chopped conversion from fp to int."));
52 
53 static cl::opt<bool> EnableBSBSched("enable-bsb-sched",
54   cl::Hidden, cl::ZeroOrMore, cl::init(true));
55 
56 static cl::opt<bool> EnableHexagonHVXDouble("enable-hexagon-hvx-double",
57   cl::Hidden, cl::ZeroOrMore, cl::init(false),
58   cl::desc("Enable Hexagon Double Vector eXtensions"));
59 
60 static cl::opt<bool> EnableHexagonHVX("enable-hexagon-hvx",
61   cl::Hidden, cl::ZeroOrMore, cl::init(false),
62   cl::desc("Enable Hexagon Vector eXtensions"));
63 
64 static cl::opt<bool> EnableTCLatencySched("enable-tc-latency-sched",
65   cl::Hidden, cl::ZeroOrMore, cl::init(false));
66 
67 static cl::opt<bool> EnableDotCurSched("enable-cur-sched",
68   cl::Hidden, cl::ZeroOrMore, cl::init(true),
69   cl::desc("Enable the scheduler to generate .cur"));
70 
71 static cl::opt<bool> EnableVecFrwdSched("enable-evec-frwd-sched",
72   cl::Hidden, cl::ZeroOrMore, cl::init(true));
73 
74 static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
75   cl::Hidden, cl::ZeroOrMore, cl::init(false),
76   cl::desc("Disable Hexagon MI Scheduling"));
77 
78 static cl::opt<bool> EnableSubregLiveness("hexagon-subreg-liveness",
79   cl::Hidden, cl::ZeroOrMore, cl::init(true),
80   cl::desc("Enable subregister liveness tracking for Hexagon"));
81 
82 static cl::opt<bool> OverrideLongCalls("hexagon-long-calls",
83   cl::Hidden, cl::ZeroOrMore, cl::init(false),
84   cl::desc("If present, forces/disables the use of long calls"));
85 
86 static cl::opt<bool> EnablePredicatedCalls("hexagon-pred-calls",
87   cl::Hidden, cl::ZeroOrMore, cl::init(false),
88   cl::desc("Consider calls to be predicable"));
89 
90 void HexagonSubtarget::initializeEnvironment() {
91   UseMemOps = false;
92   ModeIEEERndNear = false;
93   UseBSBScheduling = false;
94 }
95 
96 HexagonSubtarget &
97 HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
98   CPUString = Hexagon_MC::selectHexagonCPU(getTargetTriple(), CPU);
99 
100   static std::map<StringRef, HexagonArchEnum> CpuTable {
101     { "hexagonv4", V4 },
102     { "hexagonv5", V5 },
103     { "hexagonv55", V55 },
104     { "hexagonv60", V60 },
105     { "hexagonv62", V62 },
106   };
107 
108   auto foundIt = CpuTable.find(CPUString);
109   if (foundIt != CpuTable.end())
110     HexagonArchVersion = foundIt->second;
111   else
112     llvm_unreachable("Unrecognized Hexagon processor version");
113 
114   UseHVXOps = false;
115   UseHVXDblOps = false;
116   UseLongCalls = false;
117   ParseSubtargetFeatures(CPUString, FS);
118 
119   if (EnableHexagonHVX.getPosition())
120     UseHVXOps = EnableHexagonHVX;
121   if (EnableHexagonHVXDouble.getPosition())
122     UseHVXDblOps = EnableHexagonHVXDouble;
123   if (OverrideLongCalls.getPosition())
124     UseLongCalls = OverrideLongCalls;
125 
126   return *this;
127 }
128 
129 HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
130                                    StringRef FS, const TargetMachine &TM)
131     : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU),
132       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this) {
133   initializeEnvironment();
134 
135   // Initialize scheduling itinerary for the specified CPU.
136   InstrItins = getInstrItineraryForCPU(CPUString);
137 
138   // UseMemOps on by default unless disabled explicitly
139   if (DisableMemOps)
140     UseMemOps = false;
141   else if (EnableMemOps)
142     UseMemOps = true;
143   else
144     UseMemOps = false;
145 
146   if (EnableIEEERndNear)
147     ModeIEEERndNear = true;
148   else
149     ModeIEEERndNear = false;
150 
151   UseBSBScheduling = hasV60TOps() && EnableBSBSched;
152 }
153 
154 /// \brief Perform target specific adjustments to the latency of a schedule
155 /// dependency.
156 void HexagonSubtarget::adjustSchedDependency(SUnit *Src, SUnit *Dst,
157                                              SDep &Dep) const {
158   MachineInstr *SrcInst = Src->getInstr();
159   MachineInstr *DstInst = Dst->getInstr();
160   if (!Src->isInstr() || !Dst->isInstr())
161     return;
162 
163   const HexagonInstrInfo *QII = getInstrInfo();
164 
165   // Instructions with .new operands have zero latency.
166   SmallSet<SUnit *, 4> ExclSrc;
167   SmallSet<SUnit *, 4> ExclDst;
168   if (QII->canExecuteInBundle(*SrcInst, *DstInst) &&
169       isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) {
170     Dep.setLatency(0);
171     return;
172   }
173 
174   if (!hasV60TOps())
175     return;
176 
177   // If it's a REG_SEQUENCE, use its destination instruction to determine
178   // the correct latency.
179   if (DstInst->isRegSequence() && Dst->NumSuccs == 1) {
180     unsigned RSeqReg = DstInst->getOperand(0).getReg();
181     MachineInstr *RSeqDst = Dst->Succs[0].getSUnit()->getInstr();
182     unsigned UseIdx = -1;
183     for (unsigned OpNum = 0; OpNum < RSeqDst->getNumOperands(); OpNum++) {
184       const MachineOperand &MO = RSeqDst->getOperand(OpNum);
185       if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == RSeqReg) {
186         UseIdx = OpNum;
187         break;
188       }
189     }
190     unsigned RSeqLatency = (InstrInfo.getOperandLatency(&InstrItins, *SrcInst,
191                                                         0, *RSeqDst, UseIdx));
192     Dep.setLatency(RSeqLatency);
193   }
194 
195   // Try to schedule uses near definitions to generate .cur.
196   ExclSrc.clear();
197   ExclDst.clear();
198   if (EnableDotCurSched && QII->isToBeScheduledASAP(*SrcInst, *DstInst) &&
199       isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) {
200     Dep.setLatency(0);
201     return;
202   }
203 
204   updateLatency(*SrcInst, *DstInst, Dep);
205 }
206 
207 void HexagonSubtarget::HexagonDAGMutation::apply(ScheduleDAGInstrs *DAG) {
208   for (auto &SU : DAG->SUnits) {
209     if (!SU.isInstr())
210       continue;
211     SmallVector<SDep, 4> Erase;
212     for (auto &D : SU.Preds)
213       if (D.getKind() == SDep::Output && D.getReg() == Hexagon::USR_OVF)
214         Erase.push_back(D);
215     for (auto &E : Erase)
216       SU.removePred(E);
217   }
218 
219   for (auto &SU : DAG->SUnits) {
220     // Update the latency of chain edges between v60 vector load or store
221     // instructions to be 1. These instruction cannot be scheduled in the
222     // same packet.
223     MachineInstr &MI1 = *SU.getInstr();
224     auto *QII = static_cast<const HexagonInstrInfo*>(DAG->TII);
225     bool IsStoreMI1 = MI1.mayStore();
226     bool IsLoadMI1 = MI1.mayLoad();
227     if (!QII->isHVXVec(MI1) || !(IsStoreMI1 || IsLoadMI1))
228       continue;
229     for (auto &SI : SU.Succs) {
230       if (SI.getKind() != SDep::Order || SI.getLatency() != 0)
231         continue;
232       MachineInstr &MI2 = *SI.getSUnit()->getInstr();
233       if (!QII->isHVXVec(MI2))
234         continue;
235       if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) {
236         SI.setLatency(1);
237         SU.setHeightDirty();
238         // Change the dependence in the opposite direction too.
239         for (auto &PI : SI.getSUnit()->Preds) {
240           if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order)
241             continue;
242           PI.setLatency(1);
243           SI.getSUnit()->setDepthDirty();
244         }
245       }
246     }
247   }
248 }
249 
250 void HexagonSubtarget::getPostRAMutations(
251     std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
252   Mutations.push_back(
253       llvm::make_unique<HexagonSubtarget::HexagonDAGMutation>());
254 }
255 
256 void HexagonSubtarget::getSMSMutations(
257     std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
258   Mutations.push_back(
259       llvm::make_unique<HexagonSubtarget::HexagonDAGMutation>());
260 }
261 
262 // Pin the vtable to this file.
263 void HexagonSubtarget::anchor() {}
264 
265 bool HexagonSubtarget::enableMachineScheduler() const {
266   if (DisableHexagonMISched.getNumOccurrences())
267     return !DisableHexagonMISched;
268   return true;
269 }
270 
271 bool HexagonSubtarget::usePredicatedCalls() const {
272   return EnablePredicatedCalls;
273 }
274 
275 void HexagonSubtarget::updateLatency(MachineInstr &SrcInst,
276       MachineInstr &DstInst, SDep &Dep) const {
277   if (Dep.isArtificial()) {
278     Dep.setLatency(1);
279     return;
280   }
281 
282   if (!hasV60TOps())
283     return;
284 
285   auto &QII = static_cast<const HexagonInstrInfo&>(*getInstrInfo());
286 
287   // BSB scheduling.
288   if (QII.isHVXVec(SrcInst) || useBSBScheduling())
289     Dep.setLatency((Dep.getLatency() + 1) >> 1);
290 }
291 
292 void HexagonSubtarget::restoreLatency(SUnit *Src, SUnit *Dst) const {
293   MachineInstr *SrcI = Src->getInstr();
294   for (auto &I : Src->Succs) {
295     if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
296       continue;
297     unsigned DepR = I.getReg();
298     int DefIdx = -1;
299     for (unsigned OpNum = 0; OpNum < SrcI->getNumOperands(); OpNum++) {
300       const MachineOperand &MO = SrcI->getOperand(OpNum);
301       if (MO.isReg() && MO.isDef() && MO.getReg() == DepR)
302         DefIdx = OpNum;
303     }
304     assert(DefIdx >= 0 && "Def Reg not found in Src MI");
305     MachineInstr *DstI = Dst->getInstr();
306     for (unsigned OpNum = 0; OpNum < DstI->getNumOperands(); OpNum++) {
307       const MachineOperand &MO = DstI->getOperand(OpNum);
308       if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) {
309         int Latency = (InstrInfo.getOperandLatency(&InstrItins, *SrcI,
310                                                    DefIdx, *DstI, OpNum));
311 
312         // For some instructions (ex: COPY), we might end up with < 0 latency
313         // as they don't have any Itinerary class associated with them.
314         if (Latency <= 0)
315           Latency = 1;
316 
317         I.setLatency(Latency);
318         updateLatency(*SrcI, *DstI, I);
319       }
320     }
321 
322     // Update the latency of opposite edge too.
323     for (auto &J : Dst->Preds) {
324       if (J.getSUnit() != Src)
325         continue;
326       J.setLatency(I.getLatency());
327     }
328   }
329 }
330 
331 /// Change the latency between the two SUnits.
332 void HexagonSubtarget::changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat)
333       const {
334   for (auto &I : Src->Succs) {
335     if (I.getSUnit() != Dst)
336       continue;
337     SDep T = I;
338     I.setLatency(Lat);
339 
340     // Update the latency of opposite edge too.
341     T.setSUnit(Src);
342     auto F = std::find(Dst->Preds.begin(), Dst->Preds.end(), T);
343     assert(F != Dst->Preds.end());
344     F->setLatency(I.getLatency());
345   }
346 }
347 
348 /// If the SUnit has a zero latency edge, return the other SUnit.
349 static SUnit *getZeroLatency(SUnit *N, SmallVector<SDep, 4> &Deps) {
350   for (auto &I : Deps)
351     if (I.isAssignedRegDep() && I.getLatency() == 0 &&
352         !I.getSUnit()->getInstr()->isPseudo())
353       return I.getSUnit();
354   return nullptr;
355 }
356 
357 // Return true if these are the best two instructions to schedule
358 // together with a zero latency. Only one dependence should have a zero
359 // latency. If there are multiple choices, choose the best, and change
360 // the others, if needed.
361 bool HexagonSubtarget::isBestZeroLatency(SUnit *Src, SUnit *Dst,
362       const HexagonInstrInfo *TII, SmallSet<SUnit*, 4> &ExclSrc,
363       SmallSet<SUnit*, 4> &ExclDst) const {
364   MachineInstr &SrcInst = *Src->getInstr();
365   MachineInstr &DstInst = *Dst->getInstr();
366 
367   // Ignore Boundary SU nodes as these have null instructions.
368   if (Dst->isBoundaryNode())
369     return false;
370 
371   if (SrcInst.isPHI() || DstInst.isPHI())
372     return false;
373 
374   if (!TII->isToBeScheduledASAP(SrcInst, DstInst) &&
375       !TII->canExecuteInBundle(SrcInst, DstInst))
376     return false;
377 
378   // The architecture doesn't allow three dependent instructions in the same
379   // packet. So, if the destination has a zero latency successor, then it's
380   // not a candidate for a zero latency predecessor.
381   if (getZeroLatency(Dst, Dst->Succs) != nullptr)
382     return false;
383 
384   // Check if the Dst instruction is the best candidate first.
385   SUnit *Best = nullptr;
386   SUnit *DstBest = nullptr;
387   SUnit *SrcBest = getZeroLatency(Dst, Dst->Preds);
388   if (SrcBest == nullptr || Src->NodeNum >= SrcBest->NodeNum) {
389     // Check that Src doesn't have a better candidate.
390     DstBest = getZeroLatency(Src, Src->Succs);
391     if (DstBest == nullptr || Dst->NodeNum <= DstBest->NodeNum)
392       Best = Dst;
393   }
394   if (Best != Dst)
395     return false;
396 
397   // The caller frequently adds the same dependence twice. If so, then
398   // return true for this case too.
399   if ((Src == SrcBest && Dst == DstBest ) ||
400       (SrcBest == nullptr && Dst == DstBest) ||
401       (Src == SrcBest && Dst == nullptr))
402     return true;
403 
404   // Reassign the latency for the previous bests, which requires setting
405   // the dependence edge in both directions.
406   if (SrcBest != nullptr) {
407     if (!hasV60TOps())
408       changeLatency(SrcBest, Dst, 1);
409     else
410       restoreLatency(SrcBest, Dst);
411   }
412   if (DstBest != nullptr) {
413     if (!hasV60TOps())
414       changeLatency(Src, DstBest, 1);
415     else
416       restoreLatency(Src, DstBest);
417   }
418 
419   // Attempt to find another opprotunity for zero latency in a different
420   // dependence.
421   if (SrcBest && DstBest)
422     // If there is an edge from SrcBest to DstBst, then try to change that
423     // to 0 now.
424     changeLatency(SrcBest, DstBest, 0);
425   else if (DstBest) {
426     // Check if the previous best destination instruction has a new zero
427     // latency dependence opportunity.
428     ExclSrc.insert(Src);
429     for (auto &I : DstBest->Preds)
430       if (ExclSrc.count(I.getSUnit()) == 0 &&
431           isBestZeroLatency(I.getSUnit(), DstBest, TII, ExclSrc, ExclDst))
432         changeLatency(I.getSUnit(), DstBest, 0);
433   } else if (SrcBest) {
434     // Check if previous best source instruction has a new zero latency
435     // dependence opportunity.
436     ExclDst.insert(Dst);
437     for (auto &I : SrcBest->Succs)
438       if (ExclDst.count(I.getSUnit()) == 0 &&
439           isBestZeroLatency(SrcBest, I.getSUnit(), TII, ExclSrc, ExclDst))
440         changeLatency(SrcBest, I.getSUnit(), 0);
441   }
442 
443   return true;
444 }
445 
446 unsigned HexagonSubtarget::getL1CacheLineSize() const {
447   return 32;
448 }
449 
450 unsigned HexagonSubtarget::getL1PrefetchDistance() const {
451   return 32;
452 }
453 
454 bool HexagonSubtarget::enableSubRegLiveness() const {
455   return EnableSubregLiveness;
456 }
457