1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class prints an ARM MCInst to a .s file.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMInstPrinter.h"
15 #include "Utils/ARMBaseInfo.h"
16 #include "MCTargetDesc/ARMAddressingModes.h"
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/SubtargetFeature.h"
25 #include "llvm/Support/Casting.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include <algorithm>
30 #include <cassert>
31 #include <cstdint>
32 
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "asm-printer"
36 
37 #define PRINT_ALIAS_INSTR
38 #include "ARMGenAsmWriter.inc"
39 
40 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
41 ///
42 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
43 static unsigned translateShiftImm(unsigned imm) {
44   // lsr #32 and asr #32 exist, but should be encoded as a 0.
45   assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
46 
47   if (imm == 0)
48     return 32;
49   return imm;
50 }
51 
52 /// Prints the shift value with an immediate value.
53 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
54                              unsigned ShImm, bool UseMarkup) {
55   if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
56     return;
57   O << ", ";
58 
59   assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
60   O << getShiftOpcStr(ShOpc);
61 
62   if (ShOpc != ARM_AM::rrx) {
63     O << " ";
64     if (UseMarkup)
65       O << "<imm:";
66     O << "#" << translateShiftImm(ShImm);
67     if (UseMarkup)
68       O << ">";
69   }
70 }
71 
72 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
73                                const MCRegisterInfo &MRI)
74     : MCInstPrinter(MAI, MII, MRI) {}
75 
76 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
77   OS << markup("<reg:") << getRegisterName(RegNo) << markup(">");
78 }
79 
80 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
81                                StringRef Annot, const MCSubtargetInfo &STI) {
82   unsigned Opcode = MI->getOpcode();
83 
84   switch (Opcode) {
85   // Check for MOVs and print canonical forms, instead.
86   case ARM::MOVsr: {
87     // FIXME: Thumb variants?
88     const MCOperand &Dst = MI->getOperand(0);
89     const MCOperand &MO1 = MI->getOperand(1);
90     const MCOperand &MO2 = MI->getOperand(2);
91     const MCOperand &MO3 = MI->getOperand(3);
92 
93     O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
94     printSBitModifierOperand(MI, 6, STI, O);
95     printPredicateOperand(MI, 4, STI, O);
96 
97     O << '\t';
98     printRegName(O, Dst.getReg());
99     O << ", ";
100     printRegName(O, MO1.getReg());
101 
102     O << ", ";
103     printRegName(O, MO2.getReg());
104     assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
105     printAnnotation(O, Annot);
106     return;
107   }
108 
109   case ARM::MOVsi: {
110     // FIXME: Thumb variants?
111     const MCOperand &Dst = MI->getOperand(0);
112     const MCOperand &MO1 = MI->getOperand(1);
113     const MCOperand &MO2 = MI->getOperand(2);
114 
115     O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
116     printSBitModifierOperand(MI, 5, STI, O);
117     printPredicateOperand(MI, 3, STI, O);
118 
119     O << '\t';
120     printRegName(O, Dst.getReg());
121     O << ", ";
122     printRegName(O, MO1.getReg());
123 
124     if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
125       printAnnotation(O, Annot);
126       return;
127     }
128 
129     O << ", " << markup("<imm:") << "#"
130       << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">");
131     printAnnotation(O, Annot);
132     return;
133   }
134 
135   // A8.6.123 PUSH
136   case ARM::STMDB_UPD:
137   case ARM::t2STMDB_UPD:
138     if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
139       // Should only print PUSH if there are at least two registers in the list.
140       O << '\t' << "push";
141       printPredicateOperand(MI, 2, STI, O);
142       if (Opcode == ARM::t2STMDB_UPD)
143         O << ".w";
144       O << '\t';
145       printRegisterList(MI, 4, STI, O);
146       printAnnotation(O, Annot);
147       return;
148     } else
149       break;
150 
151   case ARM::STR_PRE_IMM:
152     if (MI->getOperand(2).getReg() == ARM::SP &&
153         MI->getOperand(3).getImm() == -4) {
154       O << '\t' << "push";
155       printPredicateOperand(MI, 4, STI, O);
156       O << "\t{";
157       printRegName(O, MI->getOperand(1).getReg());
158       O << "}";
159       printAnnotation(O, Annot);
160       return;
161     } else
162       break;
163 
164   // A8.6.122 POP
165   case ARM::LDMIA_UPD:
166   case ARM::t2LDMIA_UPD:
167     if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
168       // Should only print POP if there are at least two registers in the list.
169       O << '\t' << "pop";
170       printPredicateOperand(MI, 2, STI, O);
171       if (Opcode == ARM::t2LDMIA_UPD)
172         O << ".w";
173       O << '\t';
174       printRegisterList(MI, 4, STI, O);
175       printAnnotation(O, Annot);
176       return;
177     } else
178       break;
179 
180   case ARM::LDR_POST_IMM:
181     if (MI->getOperand(2).getReg() == ARM::SP &&
182         MI->getOperand(4).getImm() == 4) {
183       O << '\t' << "pop";
184       printPredicateOperand(MI, 5, STI, O);
185       O << "\t{";
186       printRegName(O, MI->getOperand(0).getReg());
187       O << "}";
188       printAnnotation(O, Annot);
189       return;
190     } else
191       break;
192 
193   // A8.6.355 VPUSH
194   case ARM::VSTMSDB_UPD:
195   case ARM::VSTMDDB_UPD:
196     if (MI->getOperand(0).getReg() == ARM::SP) {
197       O << '\t' << "vpush";
198       printPredicateOperand(MI, 2, STI, O);
199       O << '\t';
200       printRegisterList(MI, 4, STI, O);
201       printAnnotation(O, Annot);
202       return;
203     } else
204       break;
205 
206   // A8.6.354 VPOP
207   case ARM::VLDMSIA_UPD:
208   case ARM::VLDMDIA_UPD:
209     if (MI->getOperand(0).getReg() == ARM::SP) {
210       O << '\t' << "vpop";
211       printPredicateOperand(MI, 2, STI, O);
212       O << '\t';
213       printRegisterList(MI, 4, STI, O);
214       printAnnotation(O, Annot);
215       return;
216     } else
217       break;
218 
219   case ARM::tLDMIA: {
220     bool Writeback = true;
221     unsigned BaseReg = MI->getOperand(0).getReg();
222     for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
223       if (MI->getOperand(i).getReg() == BaseReg)
224         Writeback = false;
225     }
226 
227     O << "\tldm";
228 
229     printPredicateOperand(MI, 1, STI, O);
230     O << '\t';
231     printRegName(O, BaseReg);
232     if (Writeback)
233       O << "!";
234     O << ", ";
235     printRegisterList(MI, 3, STI, O);
236     printAnnotation(O, Annot);
237     return;
238   }
239 
240   // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
241   // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
242   // a single GPRPair reg operand is used in the .td file to replace the two
243   // GPRs. However, when decoding them, the two GRPs cannot be automatically
244   // expressed as a GPRPair, so we have to manually merge them.
245   // FIXME: We would really like to be able to tablegen'erate this.
246   case ARM::LDREXD:
247   case ARM::STREXD:
248   case ARM::LDAEXD:
249   case ARM::STLEXD: {
250     const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID);
251     bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
252     unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
253     if (MRC.contains(Reg)) {
254       MCInst NewMI;
255       MCOperand NewReg;
256       NewMI.setOpcode(Opcode);
257 
258       if (isStore)
259         NewMI.addOperand(MI->getOperand(0));
260       NewReg = MCOperand::createReg(MRI.getMatchingSuperReg(
261           Reg, ARM::gsub_0, &MRI.getRegClass(ARM::GPRPairRegClassID)));
262       NewMI.addOperand(NewReg);
263 
264       // Copy the rest operands into NewMI.
265       for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
266         NewMI.addOperand(MI->getOperand(i));
267       printInstruction(&NewMI, STI, O);
268       return;
269     }
270     break;
271   }
272   case ARM::TSB:
273   case ARM::t2TSB:
274     O << "\ttsb\tcsync";
275     return;
276   }
277 
278   if (!printAliasInstr(MI, STI, O))
279     printInstruction(MI, STI, O);
280 
281   printAnnotation(O, Annot);
282 }
283 
284 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
285                                   const MCSubtargetInfo &STI, raw_ostream &O) {
286   const MCOperand &Op = MI->getOperand(OpNo);
287   if (Op.isReg()) {
288     unsigned Reg = Op.getReg();
289     printRegName(O, Reg);
290   } else if (Op.isImm()) {
291     O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">");
292   } else {
293     assert(Op.isExpr() && "unknown operand kind in printOperand");
294     const MCExpr *Expr = Op.getExpr();
295     switch (Expr->getKind()) {
296     case MCExpr::Binary:
297       O << '#';
298       Expr->print(O, &MAI);
299       break;
300     case MCExpr::Constant: {
301       // If a symbolic branch target was added as a constant expression then
302       // print that address in hex. And only print 32 unsigned bits for the
303       // address.
304       const MCConstantExpr *Constant = cast<MCConstantExpr>(Expr);
305       int64_t TargetAddress;
306       if (!Constant->evaluateAsAbsolute(TargetAddress)) {
307         O << '#';
308         Expr->print(O, &MAI);
309       } else {
310         O << "0x";
311         O.write_hex(static_cast<uint32_t>(TargetAddress));
312       }
313       break;
314     }
315     default:
316       // FIXME: Should we always treat this as if it is a constant literal and
317       // prefix it with '#'?
318       Expr->print(O, &MAI);
319       break;
320     }
321   }
322 }
323 
324 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
325                                                const MCSubtargetInfo &STI,
326                                                raw_ostream &O) {
327   const MCOperand &MO1 = MI->getOperand(OpNum);
328   if (MO1.isExpr()) {
329     MO1.getExpr()->print(O, &MAI);
330     return;
331   }
332 
333   O << markup("<mem:") << "[pc, ";
334 
335   int32_t OffImm = (int32_t)MO1.getImm();
336   bool isSub = OffImm < 0;
337 
338   // Special value for #-0. All others are normal.
339   if (OffImm == INT32_MIN)
340     OffImm = 0;
341   if (isSub) {
342     O << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
343   } else {
344     O << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
345   }
346   O << "]" << markup(">");
347 }
348 
349 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
350 // "Addressing Mode 1 - Data-processing operands" forms.  This includes:
351 //    REG 0   0           - e.g. R5
352 //    REG REG 0,SH_OPC    - e.g. R5, ROR R3
353 //    REG 0   IMM,SH_OPC  - e.g. R5, LSL #3
354 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
355                                           const MCSubtargetInfo &STI,
356                                           raw_ostream &O) {
357   const MCOperand &MO1 = MI->getOperand(OpNum);
358   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
359   const MCOperand &MO3 = MI->getOperand(OpNum + 2);
360 
361   printRegName(O, MO1.getReg());
362 
363   // Print the shift opc.
364   ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
365   O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
366   if (ShOpc == ARM_AM::rrx)
367     return;
368 
369   O << ' ';
370   printRegName(O, MO2.getReg());
371   assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
372 }
373 
374 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
375                                           const MCSubtargetInfo &STI,
376                                           raw_ostream &O) {
377   const MCOperand &MO1 = MI->getOperand(OpNum);
378   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
379 
380   printRegName(O, MO1.getReg());
381 
382   // Print the shift opc.
383   printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
384                    ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
385 }
386 
387 //===--------------------------------------------------------------------===//
388 // Addressing Mode #2
389 //===--------------------------------------------------------------------===//
390 
391 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
392                                                 const MCSubtargetInfo &STI,
393                                                 raw_ostream &O) {
394   const MCOperand &MO1 = MI->getOperand(Op);
395   const MCOperand &MO2 = MI->getOperand(Op + 1);
396   const MCOperand &MO3 = MI->getOperand(Op + 2);
397 
398   O << markup("<mem:") << "[";
399   printRegName(O, MO1.getReg());
400 
401   if (!MO2.getReg()) {
402     if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
403       O << ", " << markup("<imm:") << "#"
404         << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
405         << ARM_AM::getAM2Offset(MO3.getImm()) << markup(">");
406     }
407     O << "]" << markup(">");
408     return;
409   }
410 
411   O << ", ";
412   O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
413   printRegName(O, MO2.getReg());
414 
415   printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
416                    ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup);
417   O << "]" << markup(">");
418 }
419 
420 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
421                                       const MCSubtargetInfo &STI,
422                                       raw_ostream &O) {
423   const MCOperand &MO1 = MI->getOperand(Op);
424   const MCOperand &MO2 = MI->getOperand(Op + 1);
425   O << markup("<mem:") << "[";
426   printRegName(O, MO1.getReg());
427   O << ", ";
428   printRegName(O, MO2.getReg());
429   O << "]" << markup(">");
430 }
431 
432 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
433                                       const MCSubtargetInfo &STI,
434                                       raw_ostream &O) {
435   const MCOperand &MO1 = MI->getOperand(Op);
436   const MCOperand &MO2 = MI->getOperand(Op + 1);
437   O << markup("<mem:") << "[";
438   printRegName(O, MO1.getReg());
439   O << ", ";
440   printRegName(O, MO2.getReg());
441   O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">");
442 }
443 
444 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
445                                            const MCSubtargetInfo &STI,
446                                            raw_ostream &O) {
447   const MCOperand &MO1 = MI->getOperand(Op);
448 
449   if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
450     printOperand(MI, Op, STI, O);
451     return;
452   }
453 
454 #ifndef NDEBUG
455   const MCOperand &MO3 = MI->getOperand(Op + 2);
456   unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
457   assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op");
458 #endif
459 
460   printAM2PreOrOffsetIndexOp(MI, Op, STI, O);
461 }
462 
463 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
464                                                  unsigned OpNum,
465                                                  const MCSubtargetInfo &STI,
466                                                  raw_ostream &O) {
467   const MCOperand &MO1 = MI->getOperand(OpNum);
468   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
469 
470   if (!MO1.getReg()) {
471     unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
472     O << markup("<imm:") << '#'
473       << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) << ImmOffs
474       << markup(">");
475     return;
476   }
477 
478   O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()));
479   printRegName(O, MO1.getReg());
480 
481   printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
482                    ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup);
483 }
484 
485 //===--------------------------------------------------------------------===//
486 // Addressing Mode #3
487 //===--------------------------------------------------------------------===//
488 
489 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
490                                                 raw_ostream &O,
491                                                 bool AlwaysPrintImm0) {
492   const MCOperand &MO1 = MI->getOperand(Op);
493   const MCOperand &MO2 = MI->getOperand(Op + 1);
494   const MCOperand &MO3 = MI->getOperand(Op + 2);
495 
496   O << markup("<mem:") << '[';
497   printRegName(O, MO1.getReg());
498 
499   if (MO2.getReg()) {
500     O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
501     printRegName(O, MO2.getReg());
502     O << ']' << markup(">");
503     return;
504   }
505 
506   // If the op is sub we have to print the immediate even if it is 0
507   unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
508   ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
509 
510   if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) {
511     O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(op) << ImmOffs
512       << markup(">");
513   }
514   O << ']' << markup(">");
515 }
516 
517 template <bool AlwaysPrintImm0>
518 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
519                                            const MCSubtargetInfo &STI,
520                                            raw_ostream &O) {
521   const MCOperand &MO1 = MI->getOperand(Op);
522   if (!MO1.isReg()) { //  For label symbolic references.
523     printOperand(MI, Op, STI, O);
524     return;
525   }
526 
527   assert(ARM_AM::getAM3IdxMode(MI->getOperand(Op + 2).getImm()) !=
528              ARMII::IndexModePost &&
529          "unexpected idxmode");
530   printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
531 }
532 
533 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
534                                                  unsigned OpNum,
535                                                  const MCSubtargetInfo &STI,
536                                                  raw_ostream &O) {
537   const MCOperand &MO1 = MI->getOperand(OpNum);
538   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
539 
540   if (MO1.getReg()) {
541     O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()));
542     printRegName(O, MO1.getReg());
543     return;
544   }
545 
546   unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
547   O << markup("<imm:") << '#'
548     << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
549     << markup(">");
550 }
551 
552 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum,
553                                              const MCSubtargetInfo &STI,
554                                              raw_ostream &O) {
555   const MCOperand &MO = MI->getOperand(OpNum);
556   unsigned Imm = MO.getImm();
557   O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
558     << markup(">");
559 }
560 
561 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
562                                             const MCSubtargetInfo &STI,
563                                             raw_ostream &O) {
564   const MCOperand &MO1 = MI->getOperand(OpNum);
565   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
566 
567   O << (MO2.getImm() ? "" : "-");
568   printRegName(O, MO1.getReg());
569 }
570 
571 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum,
572                                                const MCSubtargetInfo &STI,
573                                                raw_ostream &O) {
574   const MCOperand &MO = MI->getOperand(OpNum);
575   unsigned Imm = MO.getImm();
576   O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
577     << markup(">");
578 }
579 
580 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
581                                            const MCSubtargetInfo &STI,
582                                            raw_ostream &O) {
583   ARM_AM::AMSubMode Mode =
584       ARM_AM::getAM4SubMode(MI->getOperand(OpNum).getImm());
585   O << ARM_AM::getAMSubModeStr(Mode);
586 }
587 
588 template <bool AlwaysPrintImm0>
589 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
590                                            const MCSubtargetInfo &STI,
591                                            raw_ostream &O) {
592   const MCOperand &MO1 = MI->getOperand(OpNum);
593   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
594 
595   if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
596     printOperand(MI, OpNum, STI, O);
597     return;
598   }
599 
600   O << markup("<mem:") << "[";
601   printRegName(O, MO1.getReg());
602 
603   unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
604   ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm());
605   if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
606     O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(Op)
607       << ImmOffs * 4 << markup(">");
608   }
609   O << "]" << markup(">");
610 }
611 
612 template <bool AlwaysPrintImm0>
613 void ARMInstPrinter::printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum,
614                                                const MCSubtargetInfo &STI,
615                                                raw_ostream &O) {
616   const MCOperand &MO1 = MI->getOperand(OpNum);
617   const MCOperand &MO2 = MI->getOperand(OpNum+1);
618 
619   if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
620     printOperand(MI, OpNum, STI, O);
621     return;
622   }
623 
624   O << markup("<mem:") << "[";
625   printRegName(O, MO1.getReg());
626 
627   unsigned ImmOffs = ARM_AM::getAM5FP16Offset(MO2.getImm());
628   unsigned Op = ARM_AM::getAM5FP16Op(MO2.getImm());
629   if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
630     O << ", "
631       << markup("<imm:")
632       << "#"
633       << ARM_AM::getAddrOpcStr(ARM_AM::getAM5FP16Op(MO2.getImm()))
634       << ImmOffs * 2
635       << markup(">");
636   }
637   O << "]" << markup(">");
638 }
639 
640 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
641                                            const MCSubtargetInfo &STI,
642                                            raw_ostream &O) {
643   const MCOperand &MO1 = MI->getOperand(OpNum);
644   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
645 
646   O << markup("<mem:") << "[";
647   printRegName(O, MO1.getReg());
648   if (MO2.getImm()) {
649     O << ":" << (MO2.getImm() << 3);
650   }
651   O << "]" << markup(">");
652 }
653 
654 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
655                                            const MCSubtargetInfo &STI,
656                                            raw_ostream &O) {
657   const MCOperand &MO1 = MI->getOperand(OpNum);
658   O << markup("<mem:") << "[";
659   printRegName(O, MO1.getReg());
660   O << "]" << markup(">");
661 }
662 
663 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
664                                                  unsigned OpNum,
665                                                  const MCSubtargetInfo &STI,
666                                                  raw_ostream &O) {
667   const MCOperand &MO = MI->getOperand(OpNum);
668   if (MO.getReg() == 0)
669     O << "!";
670   else {
671     O << ", ";
672     printRegName(O, MO.getReg());
673   }
674 }
675 
676 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
677                                                     unsigned OpNum,
678                                                     const MCSubtargetInfo &STI,
679                                                     raw_ostream &O) {
680   const MCOperand &MO = MI->getOperand(OpNum);
681   uint32_t v = ~MO.getImm();
682   int32_t lsb = countTrailingZeros(v);
683   int32_t width = (32 - countLeadingZeros(v)) - lsb;
684   assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
685   O << markup("<imm:") << '#' << lsb << markup(">") << ", " << markup("<imm:")
686     << '#' << width << markup(">");
687 }
688 
689 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
690                                      const MCSubtargetInfo &STI,
691                                      raw_ostream &O) {
692   unsigned val = MI->getOperand(OpNum).getImm();
693   O << ARM_MB::MemBOptToString(val, STI.getFeatureBits()[ARM::HasV8Ops]);
694 }
695 
696 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
697                                           const MCSubtargetInfo &STI,
698                                           raw_ostream &O) {
699   unsigned val = MI->getOperand(OpNum).getImm();
700   O << ARM_ISB::InstSyncBOptToString(val);
701 }
702 
703 void ARMInstPrinter::printTraceSyncBOption(const MCInst *MI, unsigned OpNum,
704                                           const MCSubtargetInfo &STI,
705                                           raw_ostream &O) {
706   unsigned val = MI->getOperand(OpNum).getImm();
707   O << ARM_TSB::TraceSyncBOptToString(val);
708 }
709 
710 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
711                                           const MCSubtargetInfo &STI,
712                                           raw_ostream &O) {
713   unsigned ShiftOp = MI->getOperand(OpNum).getImm();
714   bool isASR = (ShiftOp & (1 << 5)) != 0;
715   unsigned Amt = ShiftOp & 0x1f;
716   if (isASR) {
717     O << ", asr " << markup("<imm:") << "#" << (Amt == 0 ? 32 : Amt)
718       << markup(">");
719   } else if (Amt) {
720     O << ", lsl " << markup("<imm:") << "#" << Amt << markup(">");
721   }
722 }
723 
724 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
725                                          const MCSubtargetInfo &STI,
726                                          raw_ostream &O) {
727   unsigned Imm = MI->getOperand(OpNum).getImm();
728   if (Imm == 0)
729     return;
730   assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
731   O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">");
732 }
733 
734 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
735                                          const MCSubtargetInfo &STI,
736                                          raw_ostream &O) {
737   unsigned Imm = MI->getOperand(OpNum).getImm();
738   // A shift amount of 32 is encoded as 0.
739   if (Imm == 0)
740     Imm = 32;
741   assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
742   O << ", asr " << markup("<imm:") << "#" << Imm << markup(">");
743 }
744 
745 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
746                                        const MCSubtargetInfo &STI,
747                                        raw_ostream &O) {
748   assert(std::is_sorted(MI->begin() + OpNum, MI->end(),
749                         [&](const MCOperand &LHS, const MCOperand &RHS) {
750                           return MRI.getEncodingValue(LHS.getReg()) <
751                                  MRI.getEncodingValue(RHS.getReg());
752                         }));
753 
754   O << "{";
755   for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
756     if (i != OpNum)
757       O << ", ";
758     printRegName(O, MI->getOperand(i).getReg());
759   }
760   O << "}";
761 }
762 
763 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
764                                          const MCSubtargetInfo &STI,
765                                          raw_ostream &O) {
766   unsigned Reg = MI->getOperand(OpNum).getReg();
767   printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
768   O << ", ";
769   printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
770 }
771 
772 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
773                                         const MCSubtargetInfo &STI,
774                                         raw_ostream &O) {
775   const MCOperand &Op = MI->getOperand(OpNum);
776   if (Op.getImm())
777     O << "be";
778   else
779     O << "le";
780 }
781 
782 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
783                                   const MCSubtargetInfo &STI, raw_ostream &O) {
784   const MCOperand &Op = MI->getOperand(OpNum);
785   O << ARM_PROC::IModToString(Op.getImm());
786 }
787 
788 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
789                                    const MCSubtargetInfo &STI, raw_ostream &O) {
790   const MCOperand &Op = MI->getOperand(OpNum);
791   unsigned IFlags = Op.getImm();
792   for (int i = 2; i >= 0; --i)
793     if (IFlags & (1 << i))
794       O << ARM_PROC::IFlagsToString(1 << i);
795 
796   if (IFlags == 0)
797     O << "none";
798 }
799 
800 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
801                                          const MCSubtargetInfo &STI,
802                                          raw_ostream &O) {
803   const MCOperand &Op = MI->getOperand(OpNum);
804   const FeatureBitset &FeatureBits = STI.getFeatureBits();
805   if (FeatureBits[ARM::FeatureMClass]) {
806 
807     unsigned SYSm = Op.getImm() & 0xFFF; // 12-bit SYSm
808     unsigned Opcode = MI->getOpcode();
809 
810     // For writes, handle extended mask bits if the DSP extension is present.
811     if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) {
812       auto TheReg =ARMSysReg::lookupMClassSysRegBy12bitSYSmValue(SYSm);
813       if (TheReg && TheReg->isInRequiredFeatures({ARM::FeatureDSP})) {
814           O << TheReg->Name;
815           return;
816       }
817     }
818 
819     // Handle the basic 8-bit mask.
820     SYSm &= 0xff;
821     if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
822       // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
823       // alias for MSR APSR_nzcvq.
824       auto TheReg = ARMSysReg::lookupMClassSysRegAPSRNonDeprecated(SYSm);
825       if (TheReg) {
826           O << TheReg->Name;
827           return;
828       }
829     }
830 
831     auto TheReg = ARMSysReg::lookupMClassSysRegBy8bitSYSmValue(SYSm);
832     if (TheReg) {
833       O << TheReg->Name;
834       return;
835     }
836 
837     O << SYSm;
838 
839     return;
840   }
841 
842   // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
843   // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
844   unsigned SpecRegRBit = Op.getImm() >> 4;
845   unsigned Mask = Op.getImm() & 0xf;
846 
847   if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
848     O << "APSR_";
849     switch (Mask) {
850     default:
851       llvm_unreachable("Unexpected mask value!");
852     case 4:
853       O << "g";
854       return;
855     case 8:
856       O << "nzcvq";
857       return;
858     case 12:
859       O << "nzcvqg";
860       return;
861     }
862   }
863 
864   if (SpecRegRBit)
865     O << "SPSR";
866   else
867     O << "CPSR";
868 
869   if (Mask) {
870     O << '_';
871     if (Mask & 8)
872       O << 'f';
873     if (Mask & 4)
874       O << 's';
875     if (Mask & 2)
876       O << 'x';
877     if (Mask & 1)
878       O << 'c';
879   }
880 }
881 
882 void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum,
883                                            const MCSubtargetInfo &STI,
884                                            raw_ostream &O) {
885   uint32_t Banked = MI->getOperand(OpNum).getImm();
886   auto TheReg = ARMBankedReg::lookupBankedRegByEncoding(Banked);
887   assert(TheReg && "invalid banked register operand");
888   std::string Name = TheReg->Name;
889 
890   uint32_t isSPSR = (Banked & 0x20) >> 5;
891   if (isSPSR)
892     Name.replace(0, 4, "SPSR"); // convert 'spsr_' to 'SPSR_'
893   O << Name;
894 }
895 
896 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
897                                            const MCSubtargetInfo &STI,
898                                            raw_ostream &O) {
899   ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
900   // Handle the undefined 15 CC value here for printing so we don't abort().
901   if ((unsigned)CC == 15)
902     O << "<und>";
903   else if (CC != ARMCC::AL)
904     O << ARMCondCodeToString(CC);
905 }
906 
907 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
908                                                     unsigned OpNum,
909                                                     const MCSubtargetInfo &STI,
910                                                     raw_ostream &O) {
911   ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
912   O << ARMCondCodeToString(CC);
913 }
914 
915 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
916                                               const MCSubtargetInfo &STI,
917                                               raw_ostream &O) {
918   if (MI->getOperand(OpNum).getReg()) {
919     assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
920            "Expect ARM CPSR register!");
921     O << 's';
922   }
923 }
924 
925 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
926                                           const MCSubtargetInfo &STI,
927                                           raw_ostream &O) {
928   O << MI->getOperand(OpNum).getImm();
929 }
930 
931 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
932                                      const MCSubtargetInfo &STI,
933                                      raw_ostream &O) {
934   O << "p" << MI->getOperand(OpNum).getImm();
935 }
936 
937 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
938                                      const MCSubtargetInfo &STI,
939                                      raw_ostream &O) {
940   O << "c" << MI->getOperand(OpNum).getImm();
941 }
942 
943 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
944                                           const MCSubtargetInfo &STI,
945                                           raw_ostream &O) {
946   O << "{" << MI->getOperand(OpNum).getImm() << "}";
947 }
948 
949 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
950                                   const MCSubtargetInfo &STI, raw_ostream &O) {
951   llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
952 }
953 
954 template <unsigned scale>
955 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
956                                           const MCSubtargetInfo &STI,
957                                           raw_ostream &O) {
958   const MCOperand &MO = MI->getOperand(OpNum);
959 
960   if (MO.isExpr()) {
961     MO.getExpr()->print(O, &MAI);
962     return;
963   }
964 
965   int32_t OffImm = (int32_t)MO.getImm() << scale;
966 
967   O << markup("<imm:");
968   if (OffImm == INT32_MIN)
969     O << "#-0";
970   else if (OffImm < 0)
971     O << "#-" << -OffImm;
972   else
973     O << "#" << OffImm;
974   O << markup(">");
975 }
976 
977 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
978                                             const MCSubtargetInfo &STI,
979                                             raw_ostream &O) {
980   O << markup("<imm:") << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
981     << markup(">");
982 }
983 
984 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
985                                      const MCSubtargetInfo &STI,
986                                      raw_ostream &O) {
987   unsigned Imm = MI->getOperand(OpNum).getImm();
988   O << markup("<imm:") << "#" << formatImm((Imm == 0 ? 32 : Imm))
989     << markup(">");
990 }
991 
992 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
993                                       const MCSubtargetInfo &STI,
994                                       raw_ostream &O) {
995   // (3 - the number of trailing zeros) is the number of then / else.
996   unsigned Mask = MI->getOperand(OpNum).getImm();
997   unsigned Firstcond = MI->getOperand(OpNum - 1).getImm();
998   unsigned CondBit0 = Firstcond & 1;
999   unsigned NumTZ = countTrailingZeros(Mask);
1000   assert(NumTZ <= 3 && "Invalid IT mask!");
1001   for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
1002     bool T = ((Mask >> Pos) & 1) == CondBit0;
1003     if (T)
1004       O << 't';
1005     else
1006       O << 'e';
1007   }
1008 }
1009 
1010 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
1011                                                  const MCSubtargetInfo &STI,
1012                                                  raw_ostream &O) {
1013   const MCOperand &MO1 = MI->getOperand(Op);
1014   const MCOperand &MO2 = MI->getOperand(Op + 1);
1015 
1016   if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1017     printOperand(MI, Op, STI, O);
1018     return;
1019   }
1020 
1021   O << markup("<mem:") << "[";
1022   printRegName(O, MO1.getReg());
1023   if (unsigned RegNum = MO2.getReg()) {
1024     O << ", ";
1025     printRegName(O, RegNum);
1026   }
1027   O << "]" << markup(">");
1028 }
1029 
1030 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
1031                                                     unsigned Op,
1032                                                     const MCSubtargetInfo &STI,
1033                                                     raw_ostream &O,
1034                                                     unsigned Scale) {
1035   const MCOperand &MO1 = MI->getOperand(Op);
1036   const MCOperand &MO2 = MI->getOperand(Op + 1);
1037 
1038   if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1039     printOperand(MI, Op, STI, O);
1040     return;
1041   }
1042 
1043   O << markup("<mem:") << "[";
1044   printRegName(O, MO1.getReg());
1045   if (unsigned ImmOffs = MO2.getImm()) {
1046     O << ", " << markup("<imm:") << "#" << formatImm(ImmOffs * Scale)
1047       << markup(">");
1048   }
1049   O << "]" << markup(">");
1050 }
1051 
1052 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
1053                                                      unsigned Op,
1054                                                      const MCSubtargetInfo &STI,
1055                                                      raw_ostream &O) {
1056   printThumbAddrModeImm5SOperand(MI, Op, STI, O, 1);
1057 }
1058 
1059 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
1060                                                      unsigned Op,
1061                                                      const MCSubtargetInfo &STI,
1062                                                      raw_ostream &O) {
1063   printThumbAddrModeImm5SOperand(MI, Op, STI, O, 2);
1064 }
1065 
1066 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
1067                                                      unsigned Op,
1068                                                      const MCSubtargetInfo &STI,
1069                                                      raw_ostream &O) {
1070   printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1071 }
1072 
1073 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
1074                                                  const MCSubtargetInfo &STI,
1075                                                  raw_ostream &O) {
1076   printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1077 }
1078 
1079 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1080 // register with shift forms.
1081 // REG 0   0           - e.g. R5
1082 // REG IMM, SH_OPC     - e.g. R5, LSL #3
1083 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1084                                       const MCSubtargetInfo &STI,
1085                                       raw_ostream &O) {
1086   const MCOperand &MO1 = MI->getOperand(OpNum);
1087   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1088 
1089   unsigned Reg = MO1.getReg();
1090   printRegName(O, Reg);
1091 
1092   // Print the shift opc.
1093   assert(MO2.isImm() && "Not a valid t2_so_reg value!");
1094   printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
1095                    ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
1096 }
1097 
1098 template <bool AlwaysPrintImm0>
1099 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
1100                                                const MCSubtargetInfo &STI,
1101                                                raw_ostream &O) {
1102   const MCOperand &MO1 = MI->getOperand(OpNum);
1103   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1104 
1105   if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1106     printOperand(MI, OpNum, STI, O);
1107     return;
1108   }
1109 
1110   O << markup("<mem:") << "[";
1111   printRegName(O, MO1.getReg());
1112 
1113   int32_t OffImm = (int32_t)MO2.getImm();
1114   bool isSub = OffImm < 0;
1115   // Special value for #-0. All others are normal.
1116   if (OffImm == INT32_MIN)
1117     OffImm = 0;
1118   if (isSub) {
1119     O << ", " << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
1120   } else if (AlwaysPrintImm0 || OffImm > 0) {
1121     O << ", " << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
1122   }
1123   O << "]" << markup(">");
1124 }
1125 
1126 template <bool AlwaysPrintImm0>
1127 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
1128                                                 unsigned OpNum,
1129                                                 const MCSubtargetInfo &STI,
1130                                                 raw_ostream &O) {
1131   const MCOperand &MO1 = MI->getOperand(OpNum);
1132   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1133 
1134   O << markup("<mem:") << "[";
1135   printRegName(O, MO1.getReg());
1136 
1137   int32_t OffImm = (int32_t)MO2.getImm();
1138   bool isSub = OffImm < 0;
1139   // Don't print +0.
1140   if (OffImm == INT32_MIN)
1141     OffImm = 0;
1142   if (isSub) {
1143     O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1144   } else if (AlwaysPrintImm0 || OffImm > 0) {
1145     O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1146   }
1147   O << "]" << markup(">");
1148 }
1149 
1150 template <bool AlwaysPrintImm0>
1151 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
1152                                                   unsigned OpNum,
1153                                                   const MCSubtargetInfo &STI,
1154                                                   raw_ostream &O) {
1155   const MCOperand &MO1 = MI->getOperand(OpNum);
1156   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1157 
1158   if (!MO1.isReg()) { //  For label symbolic references.
1159     printOperand(MI, OpNum, STI, O);
1160     return;
1161   }
1162 
1163   O << markup("<mem:") << "[";
1164   printRegName(O, MO1.getReg());
1165 
1166   int32_t OffImm = (int32_t)MO2.getImm();
1167   bool isSub = OffImm < 0;
1168 
1169   assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1170 
1171   // Don't print +0.
1172   if (OffImm == INT32_MIN)
1173     OffImm = 0;
1174   if (isSub) {
1175     O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1176   } else if (AlwaysPrintImm0 || OffImm > 0) {
1177     O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1178   }
1179   O << "]" << markup(">");
1180 }
1181 
1182 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(
1183     const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1184     raw_ostream &O) {
1185   const MCOperand &MO1 = MI->getOperand(OpNum);
1186   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1187 
1188   O << markup("<mem:") << "[";
1189   printRegName(O, MO1.getReg());
1190   if (MO2.getImm()) {
1191     O << ", " << markup("<imm:") << "#" << formatImm(MO2.getImm() * 4)
1192       << markup(">");
1193   }
1194   O << "]" << markup(">");
1195 }
1196 
1197 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(
1198     const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1199     raw_ostream &O) {
1200   const MCOperand &MO1 = MI->getOperand(OpNum);
1201   int32_t OffImm = (int32_t)MO1.getImm();
1202   O << ", " << markup("<imm:");
1203   if (OffImm == INT32_MIN)
1204     O << "#-0";
1205   else if (OffImm < 0)
1206     O << "#-" << -OffImm;
1207   else
1208     O << "#" << OffImm;
1209   O << markup(">");
1210 }
1211 
1212 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(
1213     const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1214     raw_ostream &O) {
1215   const MCOperand &MO1 = MI->getOperand(OpNum);
1216   int32_t OffImm = (int32_t)MO1.getImm();
1217 
1218   assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1219 
1220   O << ", " << markup("<imm:");
1221   if (OffImm == INT32_MIN)
1222     O << "#-0";
1223   else if (OffImm < 0)
1224     O << "#-" << -OffImm;
1225   else
1226     O << "#" << OffImm;
1227   O << markup(">");
1228 }
1229 
1230 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1231                                                  unsigned OpNum,
1232                                                  const MCSubtargetInfo &STI,
1233                                                  raw_ostream &O) {
1234   const MCOperand &MO1 = MI->getOperand(OpNum);
1235   const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1236   const MCOperand &MO3 = MI->getOperand(OpNum + 2);
1237 
1238   O << markup("<mem:") << "[";
1239   printRegName(O, MO1.getReg());
1240 
1241   assert(MO2.getReg() && "Invalid so_reg load / store address!");
1242   O << ", ";
1243   printRegName(O, MO2.getReg());
1244 
1245   unsigned ShAmt = MO3.getImm();
1246   if (ShAmt) {
1247     assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1248     O << ", lsl " << markup("<imm:") << "#" << ShAmt << markup(">");
1249   }
1250   O << "]" << markup(">");
1251 }
1252 
1253 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1254                                        const MCSubtargetInfo &STI,
1255                                        raw_ostream &O) {
1256   const MCOperand &MO = MI->getOperand(OpNum);
1257   O << markup("<imm:") << '#' << ARM_AM::getFPImmFloat(MO.getImm())
1258     << markup(">");
1259 }
1260 
1261 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
1262                                             const MCSubtargetInfo &STI,
1263                                             raw_ostream &O) {
1264   unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1265   unsigned EltBits;
1266   uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1267   O << markup("<imm:") << "#0x";
1268   O.write_hex(Val);
1269   O << markup(">");
1270 }
1271 
1272 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1273                                             const MCSubtargetInfo &STI,
1274                                             raw_ostream &O) {
1275   unsigned Imm = MI->getOperand(OpNum).getImm();
1276   O << markup("<imm:") << "#" << formatImm(Imm + 1) << markup(">");
1277 }
1278 
1279 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1280                                         const MCSubtargetInfo &STI,
1281                                         raw_ostream &O) {
1282   unsigned Imm = MI->getOperand(OpNum).getImm();
1283   if (Imm == 0)
1284     return;
1285   assert(Imm <= 3 && "illegal ror immediate!");
1286   O << ", ror " << markup("<imm:") << "#" << 8 * Imm << markup(">");
1287 }
1288 
1289 void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
1290                                         const MCSubtargetInfo &STI,
1291                                         raw_ostream &O) {
1292   MCOperand Op = MI->getOperand(OpNum);
1293 
1294   // Support for fixups (MCFixup)
1295   if (Op.isExpr())
1296     return printOperand(MI, OpNum, STI, O);
1297 
1298   unsigned Bits = Op.getImm() & 0xFF;
1299   unsigned Rot = (Op.getImm() & 0xF00) >> 7;
1300 
1301   bool PrintUnsigned = false;
1302   switch (MI->getOpcode()) {
1303   case ARM::MOVi:
1304     // Movs to PC should be treated unsigned
1305     PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1306     break;
1307   case ARM::MSRi:
1308     // Movs to special registers should be treated unsigned
1309     PrintUnsigned = true;
1310     break;
1311   }
1312 
1313   int32_t Rotated = ARM_AM::rotr32(Bits, Rot);
1314   if (ARM_AM::getSOImmVal(Rotated) == Op.getImm()) {
1315     // #rot has the least possible value
1316     O << "#" << markup("<imm:");
1317     if (PrintUnsigned)
1318       O << static_cast<uint32_t>(Rotated);
1319     else
1320       O << Rotated;
1321     O << markup(">");
1322     return;
1323   }
1324 
1325   // Explicit #bits, #rot implied
1326   O << "#" << markup("<imm:") << Bits << markup(">") << ", #" << markup("<imm:")
1327     << Rot << markup(">");
1328 }
1329 
1330 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1331                                   const MCSubtargetInfo &STI, raw_ostream &O) {
1332   O << markup("<imm:") << "#" << 16 - MI->getOperand(OpNum).getImm()
1333     << markup(">");
1334 }
1335 
1336 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1337                                   const MCSubtargetInfo &STI, raw_ostream &O) {
1338   O << markup("<imm:") << "#" << 32 - MI->getOperand(OpNum).getImm()
1339     << markup(">");
1340 }
1341 
1342 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1343                                       const MCSubtargetInfo &STI,
1344                                       raw_ostream &O) {
1345   O << "[" << MI->getOperand(OpNum).getImm() << "]";
1346 }
1347 
1348 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1349                                         const MCSubtargetInfo &STI,
1350                                         raw_ostream &O) {
1351   O << "{";
1352   printRegName(O, MI->getOperand(OpNum).getReg());
1353   O << "}";
1354 }
1355 
1356 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1357                                         const MCSubtargetInfo &STI,
1358                                         raw_ostream &O) {
1359   unsigned Reg = MI->getOperand(OpNum).getReg();
1360   unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1361   unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1362   O << "{";
1363   printRegName(O, Reg0);
1364   O << ", ";
1365   printRegName(O, Reg1);
1366   O << "}";
1367 }
1368 
1369 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
1370                                               const MCSubtargetInfo &STI,
1371                                               raw_ostream &O) {
1372   unsigned Reg = MI->getOperand(OpNum).getReg();
1373   unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1374   unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1375   O << "{";
1376   printRegName(O, Reg0);
1377   O << ", ";
1378   printRegName(O, Reg1);
1379   O << "}";
1380 }
1381 
1382 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1383                                           const MCSubtargetInfo &STI,
1384                                           raw_ostream &O) {
1385   // Normally, it's not safe to use register enum values directly with
1386   // addition to get the next register, but for VFP registers, the
1387   // sort order is guaranteed because they're all of the form D<n>.
1388   O << "{";
1389   printRegName(O, MI->getOperand(OpNum).getReg());
1390   O << ", ";
1391   printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1392   O << ", ";
1393   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1394   O << "}";
1395 }
1396 
1397 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1398                                          const MCSubtargetInfo &STI,
1399                                          raw_ostream &O) {
1400   // Normally, it's not safe to use register enum values directly with
1401   // addition to get the next register, but for VFP registers, the
1402   // sort order is guaranteed because they're all of the form D<n>.
1403   O << "{";
1404   printRegName(O, MI->getOperand(OpNum).getReg());
1405   O << ", ";
1406   printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1407   O << ", ";
1408   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1409   O << ", ";
1410   printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1411   O << "}";
1412 }
1413 
1414 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1415                                                 unsigned OpNum,
1416                                                 const MCSubtargetInfo &STI,
1417                                                 raw_ostream &O) {
1418   O << "{";
1419   printRegName(O, MI->getOperand(OpNum).getReg());
1420   O << "[]}";
1421 }
1422 
1423 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1424                                                 unsigned OpNum,
1425                                                 const MCSubtargetInfo &STI,
1426                                                 raw_ostream &O) {
1427   unsigned Reg = MI->getOperand(OpNum).getReg();
1428   unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1429   unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1430   O << "{";
1431   printRegName(O, Reg0);
1432   O << "[], ";
1433   printRegName(O, Reg1);
1434   O << "[]}";
1435 }
1436 
1437 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1438                                                   unsigned OpNum,
1439                                                   const MCSubtargetInfo &STI,
1440                                                   raw_ostream &O) {
1441   // Normally, it's not safe to use register enum values directly with
1442   // addition to get the next register, but for VFP registers, the
1443   // sort order is guaranteed because they're all of the form D<n>.
1444   O << "{";
1445   printRegName(O, MI->getOperand(OpNum).getReg());
1446   O << "[], ";
1447   printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1448   O << "[], ";
1449   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1450   O << "[]}";
1451 }
1452 
1453 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1454                                                  unsigned OpNum,
1455                                                  const MCSubtargetInfo &STI,
1456                                                  raw_ostream &O) {
1457   // Normally, it's not safe to use register enum values directly with
1458   // addition to get the next register, but for VFP registers, the
1459   // sort order is guaranteed because they're all of the form D<n>.
1460   O << "{";
1461   printRegName(O, MI->getOperand(OpNum).getReg());
1462   O << "[], ";
1463   printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1464   O << "[], ";
1465   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1466   O << "[], ";
1467   printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1468   O << "[]}";
1469 }
1470 
1471 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(
1472     const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1473     raw_ostream &O) {
1474   unsigned Reg = MI->getOperand(OpNum).getReg();
1475   unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1476   unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1477   O << "{";
1478   printRegName(O, Reg0);
1479   O << "[], ";
1480   printRegName(O, Reg1);
1481   O << "[]}";
1482 }
1483 
1484 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(
1485     const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1486     raw_ostream &O) {
1487   // Normally, it's not safe to use register enum values directly with
1488   // addition to get the next register, but for VFP registers, the
1489   // sort order is guaranteed because they're all of the form D<n>.
1490   O << "{";
1491   printRegName(O, MI->getOperand(OpNum).getReg());
1492   O << "[], ";
1493   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1494   O << "[], ";
1495   printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1496   O << "[]}";
1497 }
1498 
1499 void ARMInstPrinter::printVectorListFourSpacedAllLanes(
1500     const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1501     raw_ostream &O) {
1502   // Normally, it's not safe to use register enum values directly with
1503   // addition to get the next register, but for VFP registers, the
1504   // sort order is guaranteed because they're all of the form D<n>.
1505   O << "{";
1506   printRegName(O, MI->getOperand(OpNum).getReg());
1507   O << "[], ";
1508   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1509   O << "[], ";
1510   printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1511   O << "[], ";
1512   printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1513   O << "[]}";
1514 }
1515 
1516 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1517                                                 unsigned OpNum,
1518                                                 const MCSubtargetInfo &STI,
1519                                                 raw_ostream &O) {
1520   // Normally, it's not safe to use register enum values directly with
1521   // addition to get the next register, but for VFP registers, the
1522   // sort order is guaranteed because they're all of the form D<n>.
1523   O << "{";
1524   printRegName(O, MI->getOperand(OpNum).getReg());
1525   O << ", ";
1526   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1527   O << ", ";
1528   printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1529   O << "}";
1530 }
1531 
1532 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
1533                                                const MCSubtargetInfo &STI,
1534                                                raw_ostream &O) {
1535   // Normally, it's not safe to use register enum values directly with
1536   // addition to get the next register, but for VFP registers, the
1537   // sort order is guaranteed because they're all of the form D<n>.
1538   O << "{";
1539   printRegName(O, MI->getOperand(OpNum).getReg());
1540   O << ", ";
1541   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1542   O << ", ";
1543   printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1544   O << ", ";
1545   printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1546   O << "}";
1547 }
1548 
1549 template<int64_t Angle, int64_t Remainder>
1550 void ARMInstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo,
1551                                             const MCSubtargetInfo &STI,
1552                                             raw_ostream &O) {
1553   unsigned Val = MI->getOperand(OpNo).getImm();
1554   O << "#" << (Val * Angle) + Remainder;
1555 }
1556 
1557