1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class prints an ARM MCInst to a .s file.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMInstPrinter.h"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/raw_ostream.h"
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "asm-printer"
26 
27 #include "ARMGenAsmWriter.inc"
28 
29 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
30 ///
31 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
32 static unsigned translateShiftImm(unsigned imm) {
33   // lsr #32 and asr #32 exist, but should be encoded as a 0.
34   assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
35 
36   if (imm == 0)
37     return 32;
38   return imm;
39 }
40 
41 /// Prints the shift value with an immediate value.
42 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
43                           unsigned ShImm, bool UseMarkup) {
44   if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
45     return;
46   O << ", ";
47 
48   assert (!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
49   O << getShiftOpcStr(ShOpc);
50 
51   if (ShOpc != ARM_AM::rrx) {
52     O << " ";
53     if (UseMarkup)
54       O << "<imm:";
55     O << "#" << translateShiftImm(ShImm);
56     if (UseMarkup)
57       O << ">";
58   }
59 }
60 
61 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
62                                const MCInstrInfo &MII,
63                                const MCRegisterInfo &MRI,
64                                const MCSubtargetInfo &STI) :
65   MCInstPrinter(MAI, MII, MRI) {
66   // Initialize the set of available features.
67   setAvailableFeatures(STI.getFeatureBits());
68 }
69 
70 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
71   OS << markup("<reg:")
72      << getRegisterName(RegNo)
73      << markup(">");
74 }
75 
76 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
77                                StringRef Annot) {
78   unsigned Opcode = MI->getOpcode();
79 
80   switch(Opcode) {
81 
82   // Check for HINT instructions w/ canonical names.
83   case ARM::HINT:
84   case ARM::tHINT:
85   case ARM::t2HINT:
86     switch (MI->getOperand(0).getImm()) {
87     case 0: O << "\tnop"; break;
88     case 1: O << "\tyield"; break;
89     case 2: O << "\twfe"; break;
90     case 3: O << "\twfi"; break;
91     case 4: O << "\tsev"; break;
92     case 5:
93       if ((getAvailableFeatures() & ARM::HasV8Ops)) {
94         O << "\tsevl";
95         break;
96       } // Fallthrough for non-v8
97     default:
98       // Anything else should just print normally.
99       printInstruction(MI, O);
100       printAnnotation(O, Annot);
101       return;
102     }
103     printPredicateOperand(MI, 1, O);
104     if (Opcode == ARM::t2HINT)
105       O << ".w";
106     printAnnotation(O, Annot);
107     return;
108 
109   // Check for MOVs and print canonical forms, instead.
110   case ARM::MOVsr: {
111     // FIXME: Thumb variants?
112     const MCOperand &Dst = MI->getOperand(0);
113     const MCOperand &MO1 = MI->getOperand(1);
114     const MCOperand &MO2 = MI->getOperand(2);
115     const MCOperand &MO3 = MI->getOperand(3);
116 
117     O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
118     printSBitModifierOperand(MI, 6, O);
119     printPredicateOperand(MI, 4, O);
120 
121     O << '\t';
122     printRegName(O, Dst.getReg());
123     O << ", ";
124     printRegName(O, MO1.getReg());
125 
126     O << ", ";
127     printRegName(O, MO2.getReg());
128     assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
129     printAnnotation(O, Annot);
130     return;
131   }
132 
133   case ARM::MOVsi: {
134     // FIXME: Thumb variants?
135     const MCOperand &Dst = MI->getOperand(0);
136     const MCOperand &MO1 = MI->getOperand(1);
137     const MCOperand &MO2 = MI->getOperand(2);
138 
139     O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
140     printSBitModifierOperand(MI, 5, O);
141     printPredicateOperand(MI, 3, O);
142 
143     O << '\t';
144     printRegName(O, Dst.getReg());
145     O << ", ";
146     printRegName(O, MO1.getReg());
147 
148     if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
149       printAnnotation(O, Annot);
150       return;
151     }
152 
153     O << ", "
154       << markup("<imm:")
155       << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()))
156       << markup(">");
157     printAnnotation(O, Annot);
158     return;
159   }
160 
161   // A8.6.123 PUSH
162   case ARM::STMDB_UPD:
163   case ARM::t2STMDB_UPD:
164     if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
165       // Should only print PUSH if there are at least two registers in the list.
166       O << '\t' << "push";
167       printPredicateOperand(MI, 2, O);
168       if (Opcode == ARM::t2STMDB_UPD)
169         O << ".w";
170       O << '\t';
171       printRegisterList(MI, 4, O);
172       printAnnotation(O, Annot);
173       return;
174     } else
175       break;
176 
177   case ARM::STR_PRE_IMM:
178     if (MI->getOperand(2).getReg() == ARM::SP &&
179         MI->getOperand(3).getImm() == -4) {
180       O << '\t' << "push";
181       printPredicateOperand(MI, 4, O);
182       O << "\t{";
183       printRegName(O, MI->getOperand(1).getReg());
184       O << "}";
185       printAnnotation(O, Annot);
186       return;
187     } else
188       break;
189 
190   // A8.6.122 POP
191   case ARM::LDMIA_UPD:
192   case ARM::t2LDMIA_UPD:
193     if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
194       // Should only print POP if there are at least two registers in the list.
195       O << '\t' << "pop";
196       printPredicateOperand(MI, 2, O);
197       if (Opcode == ARM::t2LDMIA_UPD)
198         O << ".w";
199       O << '\t';
200       printRegisterList(MI, 4, O);
201       printAnnotation(O, Annot);
202       return;
203     } else
204       break;
205 
206   case ARM::LDR_POST_IMM:
207     if (MI->getOperand(2).getReg() == ARM::SP &&
208         MI->getOperand(4).getImm() == 4) {
209       O << '\t' << "pop";
210       printPredicateOperand(MI, 5, O);
211       O << "\t{";
212       printRegName(O, MI->getOperand(0).getReg());
213       O << "}";
214       printAnnotation(O, Annot);
215       return;
216     } else
217       break;
218 
219   // A8.6.355 VPUSH
220   case ARM::VSTMSDB_UPD:
221   case ARM::VSTMDDB_UPD:
222     if (MI->getOperand(0).getReg() == ARM::SP) {
223       O << '\t' << "vpush";
224       printPredicateOperand(MI, 2, O);
225       O << '\t';
226       printRegisterList(MI, 4, O);
227       printAnnotation(O, Annot);
228       return;
229     } else
230       break;
231 
232   // A8.6.354 VPOP
233   case ARM::VLDMSIA_UPD:
234   case ARM::VLDMDIA_UPD:
235     if (MI->getOperand(0).getReg() == ARM::SP) {
236       O << '\t' << "vpop";
237       printPredicateOperand(MI, 2, O);
238       O << '\t';
239       printRegisterList(MI, 4, O);
240       printAnnotation(O, Annot);
241       return;
242     } else
243       break;
244 
245   case ARM::tLDMIA: {
246     bool Writeback = true;
247     unsigned BaseReg = MI->getOperand(0).getReg();
248     for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
249       if (MI->getOperand(i).getReg() == BaseReg)
250         Writeback = false;
251     }
252 
253     O << "\tldm";
254 
255     printPredicateOperand(MI, 1, O);
256     O << '\t';
257     printRegName(O, BaseReg);
258     if (Writeback) O << "!";
259     O << ", ";
260     printRegisterList(MI, 3, O);
261     printAnnotation(O, Annot);
262     return;
263   }
264 
265   // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
266   // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
267   // a single GPRPair reg operand is used in the .td file to replace the two
268   // GPRs. However, when decoding them, the two GRPs cannot be automatically
269   // expressed as a GPRPair, so we have to manually merge them.
270   // FIXME: We would really like to be able to tablegen'erate this.
271   case ARM::LDREXD: case ARM::STREXD:
272   case ARM::LDAEXD: case ARM::STLEXD: {
273     const MCRegisterClass& MRC = MRI.getRegClass(ARM::GPRRegClassID);
274     bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
275     unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
276     if (MRC.contains(Reg)) {
277       MCInst NewMI;
278       MCOperand NewReg;
279       NewMI.setOpcode(Opcode);
280 
281       if (isStore)
282         NewMI.addOperand(MI->getOperand(0));
283       NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
284         &MRI.getRegClass(ARM::GPRPairRegClassID)));
285       NewMI.addOperand(NewReg);
286 
287       // Copy the rest operands into NewMI.
288       for(unsigned i= isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
289         NewMI.addOperand(MI->getOperand(i));
290       printInstruction(&NewMI, O);
291       return;
292     }
293     break;
294   }
295     // B9.3.3 ERET (Thumb)
296     // For a target that has Virtualization Extensions, ERET is the preferred
297     // disassembly of SUBS PC, LR, #0
298   case ARM::t2SUBS_PC_LR: {
299     if (MI->getNumOperands() == 3 &&
300         MI->getOperand(0).isImm() &&
301         MI->getOperand(0).getImm() == 0 &&
302         (getAvailableFeatures() & ARM::FeatureVirtualization)) {
303       O << "\teret";
304       printPredicateOperand(MI, 1, O);
305       printAnnotation(O, Annot);
306       return;
307     }
308     break;
309   }
310   }
311 
312   printInstruction(MI, O);
313   printAnnotation(O, Annot);
314 }
315 
316 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
317                                   raw_ostream &O) {
318   const MCOperand &Op = MI->getOperand(OpNo);
319   if (Op.isReg()) {
320     unsigned Reg = Op.getReg();
321     printRegName(O, Reg);
322   } else if (Op.isImm()) {
323     O << markup("<imm:")
324       << '#' << formatImm(Op.getImm())
325       << markup(">");
326   } else {
327     assert(Op.isExpr() && "unknown operand kind in printOperand");
328     const MCExpr *Expr = Op.getExpr();
329     switch (Expr->getKind()) {
330     case MCExpr::Binary:
331       O << '#' << *Expr;
332       break;
333     case MCExpr::Constant: {
334       // If a symbolic branch target was added as a constant expression then
335       // print that address in hex. And only print 32 unsigned bits for the
336       // address.
337       const MCConstantExpr *Constant = cast<MCConstantExpr>(Expr);
338       int64_t TargetAddress;
339       if (!Constant->EvaluateAsAbsolute(TargetAddress)) {
340         O << '#' << *Expr;
341       } else {
342         O << "0x";
343         O.write_hex(static_cast<uint32_t>(TargetAddress));
344       }
345       break;
346     }
347     default:
348       // FIXME: Should we always treat this as if it is a constant literal and
349       // prefix it with '#'?
350       O << *Expr;
351       break;
352     }
353   }
354 }
355 
356 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
357                                                raw_ostream &O) {
358   const MCOperand &MO1 = MI->getOperand(OpNum);
359   if (MO1.isExpr()) {
360     O << *MO1.getExpr();
361     return;
362   }
363 
364   O << markup("<mem:") << "[pc, ";
365 
366   int32_t OffImm = (int32_t)MO1.getImm();
367   bool isSub = OffImm < 0;
368 
369   // Special value for #-0. All others are normal.
370   if (OffImm == INT32_MIN)
371     OffImm = 0;
372   if (isSub) {
373     O << markup("<imm:")
374       << "#-" << formatImm(-OffImm)
375       << markup(">");
376   } else {
377     O << markup("<imm:")
378       << "#" << formatImm(OffImm)
379       << markup(">");
380   }
381   O << "]" << markup(">");
382 }
383 
384 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
385 // "Addressing Mode 1 - Data-processing operands" forms.  This includes:
386 //    REG 0   0           - e.g. R5
387 //    REG REG 0,SH_OPC    - e.g. R5, ROR R3
388 //    REG 0   IMM,SH_OPC  - e.g. R5, LSL #3
389 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
390                                        raw_ostream &O) {
391   const MCOperand &MO1 = MI->getOperand(OpNum);
392   const MCOperand &MO2 = MI->getOperand(OpNum+1);
393   const MCOperand &MO3 = MI->getOperand(OpNum+2);
394 
395   printRegName(O, MO1.getReg());
396 
397   // Print the shift opc.
398   ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
399   O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
400   if (ShOpc == ARM_AM::rrx)
401     return;
402 
403   O << ' ';
404   printRegName(O, MO2.getReg());
405   assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
406 }
407 
408 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
409                                        raw_ostream &O) {
410   const MCOperand &MO1 = MI->getOperand(OpNum);
411   const MCOperand &MO2 = MI->getOperand(OpNum+1);
412 
413   printRegName(O, MO1.getReg());
414 
415   // Print the shift opc.
416   printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
417                    ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
418 }
419 
420 
421 //===--------------------------------------------------------------------===//
422 // Addressing Mode #2
423 //===--------------------------------------------------------------------===//
424 
425 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
426                                                 raw_ostream &O) {
427   const MCOperand &MO1 = MI->getOperand(Op);
428   const MCOperand &MO2 = MI->getOperand(Op+1);
429   const MCOperand &MO3 = MI->getOperand(Op+2);
430 
431   O << markup("<mem:") << "[";
432   printRegName(O, MO1.getReg());
433 
434   if (!MO2.getReg()) {
435     if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
436       O << ", "
437         << markup("<imm:")
438         << "#"
439         << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
440         << ARM_AM::getAM2Offset(MO3.getImm())
441         << markup(">");
442     }
443     O << "]" << markup(">");
444     return;
445   }
446 
447   O << ", ";
448   O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
449   printRegName(O, MO2.getReg());
450 
451   printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
452                    ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup);
453   O << "]" << markup(">");
454 }
455 
456 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
457                                            raw_ostream &O) {
458   const MCOperand &MO1 = MI->getOperand(Op);
459   const MCOperand &MO2 = MI->getOperand(Op+1);
460   O << markup("<mem:") << "[";
461   printRegName(O, MO1.getReg());
462   O << ", ";
463   printRegName(O, MO2.getReg());
464   O << "]" << markup(">");
465 }
466 
467 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
468                                            raw_ostream &O) {
469   const MCOperand &MO1 = MI->getOperand(Op);
470   const MCOperand &MO2 = MI->getOperand(Op+1);
471   O << markup("<mem:") << "[";
472   printRegName(O, MO1.getReg());
473   O << ", ";
474   printRegName(O, MO2.getReg());
475   O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">");
476 }
477 
478 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
479                                            raw_ostream &O) {
480   const MCOperand &MO1 = MI->getOperand(Op);
481 
482   if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
483     printOperand(MI, Op, O);
484     return;
485   }
486 
487 #ifndef NDEBUG
488   const MCOperand &MO3 = MI->getOperand(Op+2);
489   unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
490   assert(IdxMode != ARMII::IndexModePost &&
491          "Should be pre or offset index op");
492 #endif
493 
494   printAM2PreOrOffsetIndexOp(MI, Op, O);
495 }
496 
497 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
498                                                  unsigned OpNum,
499                                                  raw_ostream &O) {
500   const MCOperand &MO1 = MI->getOperand(OpNum);
501   const MCOperand &MO2 = MI->getOperand(OpNum+1);
502 
503   if (!MO1.getReg()) {
504     unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
505     O << markup("<imm:")
506       << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
507       << ImmOffs
508       << markup(">");
509     return;
510   }
511 
512   O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()));
513   printRegName(O, MO1.getReg());
514 
515   printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
516                    ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup);
517 }
518 
519 //===--------------------------------------------------------------------===//
520 // Addressing Mode #3
521 //===--------------------------------------------------------------------===//
522 
523 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
524                                                 raw_ostream &O,
525                                                 bool AlwaysPrintImm0) {
526   const MCOperand &MO1 = MI->getOperand(Op);
527   const MCOperand &MO2 = MI->getOperand(Op+1);
528   const MCOperand &MO3 = MI->getOperand(Op+2);
529 
530   O << markup("<mem:") << '[';
531   printRegName(O, MO1.getReg());
532 
533   if (MO2.getReg()) {
534     O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
535     printRegName(O, MO2.getReg());
536     O << ']' << markup(">");
537     return;
538   }
539 
540   //If the op is sub we have to print the immediate even if it is 0
541   unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
542   ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
543 
544   if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) {
545     O << ", "
546       << markup("<imm:")
547       << "#"
548       << ARM_AM::getAddrOpcStr(op)
549       << ImmOffs
550       << markup(">");
551   }
552   O << ']' << markup(">");
553 }
554 
555 template <bool AlwaysPrintImm0>
556 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
557                                            raw_ostream &O) {
558   const MCOperand &MO1 = MI->getOperand(Op);
559   if (!MO1.isReg()) {   //  For label symbolic references.
560     printOperand(MI, Op, O);
561     return;
562   }
563 
564   assert(ARM_AM::getAM3IdxMode(MI->getOperand(Op + 2).getImm()) !=
565              ARMII::IndexModePost &&
566          "unexpected idxmode");
567   printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
568 }
569 
570 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
571                                                  unsigned OpNum,
572                                                  raw_ostream &O) {
573   const MCOperand &MO1 = MI->getOperand(OpNum);
574   const MCOperand &MO2 = MI->getOperand(OpNum+1);
575 
576   if (MO1.getReg()) {
577     O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()));
578     printRegName(O, MO1.getReg());
579     return;
580   }
581 
582   unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
583   O << markup("<imm:")
584     << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
585     << markup(">");
586 }
587 
588 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
589                                              unsigned OpNum,
590                                              raw_ostream &O) {
591   const MCOperand &MO = MI->getOperand(OpNum);
592   unsigned Imm = MO.getImm();
593   O << markup("<imm:")
594     << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
595     << markup(">");
596 }
597 
598 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
599                                             raw_ostream &O) {
600   const MCOperand &MO1 = MI->getOperand(OpNum);
601   const MCOperand &MO2 = MI->getOperand(OpNum+1);
602 
603   O << (MO2.getImm() ? "" : "-");
604   printRegName(O, MO1.getReg());
605 }
606 
607 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
608                                              unsigned OpNum,
609                                              raw_ostream &O) {
610   const MCOperand &MO = MI->getOperand(OpNum);
611   unsigned Imm = MO.getImm();
612   O << markup("<imm:")
613     << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
614     << markup(">");
615 }
616 
617 
618 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
619                                            raw_ostream &O) {
620   ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
621                                                  .getImm());
622   O << ARM_AM::getAMSubModeStr(Mode);
623 }
624 
625 template <bool AlwaysPrintImm0>
626 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
627                                            raw_ostream &O) {
628   const MCOperand &MO1 = MI->getOperand(OpNum);
629   const MCOperand &MO2 = MI->getOperand(OpNum+1);
630 
631   if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
632     printOperand(MI, OpNum, O);
633     return;
634   }
635 
636   O << markup("<mem:") << "[";
637   printRegName(O, MO1.getReg());
638 
639   unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
640   unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
641   if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
642     O << ", "
643       << markup("<imm:")
644       << "#"
645       << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
646       << ImmOffs * 4
647       << markup(">");
648   }
649   O << "]" << markup(">");
650 }
651 
652 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
653                                            raw_ostream &O) {
654   const MCOperand &MO1 = MI->getOperand(OpNum);
655   const MCOperand &MO2 = MI->getOperand(OpNum+1);
656 
657   O << markup("<mem:") << "[";
658   printRegName(O, MO1.getReg());
659   if (MO2.getImm()) {
660     O << ":" << (MO2.getImm() << 3);
661   }
662   O << "]" << markup(">");
663 }
664 
665 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
666                                            raw_ostream &O) {
667   const MCOperand &MO1 = MI->getOperand(OpNum);
668   O << markup("<mem:") << "[";
669   printRegName(O, MO1.getReg());
670   O << "]" << markup(">");
671 }
672 
673 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
674                                                  unsigned OpNum,
675                                                  raw_ostream &O) {
676   const MCOperand &MO = MI->getOperand(OpNum);
677   if (MO.getReg() == 0)
678     O << "!";
679   else {
680     O << ", ";
681     printRegName(O, MO.getReg());
682   }
683 }
684 
685 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
686                                                     unsigned OpNum,
687                                                     raw_ostream &O) {
688   const MCOperand &MO = MI->getOperand(OpNum);
689   uint32_t v = ~MO.getImm();
690   int32_t lsb = countTrailingZeros(v);
691   int32_t width = (32 - countLeadingZeros (v)) - lsb;
692   assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
693   O << markup("<imm:") << '#' << lsb << markup(">")
694     << ", "
695     << markup("<imm:") << '#' << width << markup(">");
696 }
697 
698 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
699                                      raw_ostream &O) {
700   unsigned val = MI->getOperand(OpNum).getImm();
701   O << ARM_MB::MemBOptToString(val, (getAvailableFeatures() & ARM::HasV8Ops));
702 }
703 
704 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
705                                           raw_ostream &O) {
706   unsigned val = MI->getOperand(OpNum).getImm();
707   O << ARM_ISB::InstSyncBOptToString(val);
708 }
709 
710 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
711                                           raw_ostream &O) {
712   unsigned ShiftOp = MI->getOperand(OpNum).getImm();
713   bool isASR = (ShiftOp & (1 << 5)) != 0;
714   unsigned Amt = ShiftOp & 0x1f;
715   if (isASR) {
716     O << ", asr "
717       << markup("<imm:")
718       << "#" << (Amt == 0 ? 32 : Amt)
719       << markup(">");
720   }
721   else if (Amt) {
722     O << ", lsl "
723       << markup("<imm:")
724       << "#" << Amt
725       << markup(">");
726   }
727 }
728 
729 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
730                                          raw_ostream &O) {
731   unsigned Imm = MI->getOperand(OpNum).getImm();
732   if (Imm == 0)
733     return;
734   assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
735   O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">");
736 }
737 
738 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
739                                          raw_ostream &O) {
740   unsigned Imm = MI->getOperand(OpNum).getImm();
741   // A shift amount of 32 is encoded as 0.
742   if (Imm == 0)
743     Imm = 32;
744   assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
745   O << ", asr " << markup("<imm:") << "#" << Imm << markup(">");
746 }
747 
748 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
749                                        raw_ostream &O) {
750   O << "{";
751   for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
752     if (i != OpNum) O << ", ";
753     printRegName(O, MI->getOperand(i).getReg());
754   }
755   O << "}";
756 }
757 
758 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
759                                          raw_ostream &O) {
760   unsigned Reg = MI->getOperand(OpNum).getReg();
761   printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
762   O << ", ";
763   printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
764 }
765 
766 
767 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
768                                         raw_ostream &O) {
769   const MCOperand &Op = MI->getOperand(OpNum);
770   if (Op.getImm())
771     O << "be";
772   else
773     O << "le";
774 }
775 
776 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
777                                   raw_ostream &O) {
778   const MCOperand &Op = MI->getOperand(OpNum);
779   O << ARM_PROC::IModToString(Op.getImm());
780 }
781 
782 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
783                                    raw_ostream &O) {
784   const MCOperand &Op = MI->getOperand(OpNum);
785   unsigned IFlags = Op.getImm();
786   for (int i=2; i >= 0; --i)
787     if (IFlags & (1 << i))
788       O << ARM_PROC::IFlagsToString(1 << i);
789 
790   if (IFlags == 0)
791     O << "none";
792 }
793 
794 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
795                                          raw_ostream &O) {
796   const MCOperand &Op = MI->getOperand(OpNum);
797   unsigned SpecRegRBit = Op.getImm() >> 4;
798   unsigned Mask = Op.getImm() & 0xf;
799   uint64_t FeatureBits = getAvailableFeatures();
800 
801   if (FeatureBits & ARM::FeatureMClass) {
802     unsigned SYSm = Op.getImm();
803     unsigned Opcode = MI->getOpcode();
804 
805     // For writes, handle extended mask bits if the DSP extension is present.
806     if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::FeatureDSPThumb2)) {
807       switch (SYSm) {
808       case 0x400: O << "apsr_g"; return;
809       case 0xc00: O << "apsr_nzcvqg"; return;
810       case 0x401: O << "iapsr_g"; return;
811       case 0xc01: O << "iapsr_nzcvqg"; return;
812       case 0x402: O << "eapsr_g"; return;
813       case 0xc02: O << "eapsr_nzcvqg"; return;
814       case 0x403: O << "xpsr_g"; return;
815       case 0xc03: O << "xpsr_nzcvqg"; return;
816       }
817     }
818 
819     // Handle the basic 8-bit mask.
820     SYSm &= 0xff;
821 
822     if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::HasV7Ops)) {
823       // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
824       // alias for MSR APSR_nzcvq.
825       switch (SYSm) {
826       case 0: O << "apsr_nzcvq"; return;
827       case 1: O << "iapsr_nzcvq"; return;
828       case 2: O << "eapsr_nzcvq"; return;
829       case 3: O << "xpsr_nzcvq"; return;
830       }
831     }
832 
833     switch (SYSm) {
834     default: llvm_unreachable("Unexpected mask value!");
835     case  0: O << "apsr"; return;
836     case  1: O << "iapsr"; return;
837     case  2: O << "eapsr"; return;
838     case  3: O << "xpsr"; return;
839     case  5: O << "ipsr"; return;
840     case  6: O << "epsr"; return;
841     case  7: O << "iepsr"; return;
842     case  8: O << "msp"; return;
843     case  9: O << "psp"; return;
844     case 16: O << "primask"; return;
845     case 17: O << "basepri"; return;
846     case 18: O << "basepri_max"; return;
847     case 19: O << "faultmask"; return;
848     case 20: O << "control"; return;
849     }
850   }
851 
852   // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
853   // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
854   if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
855     O << "APSR_";
856     switch (Mask) {
857     default: llvm_unreachable("Unexpected mask value!");
858     case 4:  O << "g"; return;
859     case 8:  O << "nzcvq"; return;
860     case 12: O << "nzcvqg"; return;
861     }
862   }
863 
864   if (SpecRegRBit)
865     O << "SPSR";
866   else
867     O << "CPSR";
868 
869   if (Mask) {
870     O << '_';
871     if (Mask & 8) O << 'f';
872     if (Mask & 4) O << 's';
873     if (Mask & 2) O << 'x';
874     if (Mask & 1) O << 'c';
875   }
876 }
877 
878 void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum,
879                                            raw_ostream &O) {
880   uint32_t Banked = MI->getOperand(OpNum).getImm();
881   uint32_t R = (Banked & 0x20) >> 5;
882   uint32_t SysM = Banked & 0x1f;
883 
884   // Nothing much we can do about this, the encodings are specified in B9.2.3 of
885   // the ARM ARM v7C, and are all over the shop.
886   if (R) {
887     O << "SPSR_";
888 
889     switch(SysM) {
890     case 0x0e: O << "fiq"; return;
891     case 0x10: O << "irq"; return;
892     case 0x12: O << "svc"; return;
893     case 0x14: O << "abt"; return;
894     case 0x16: O << "und"; return;
895     case 0x1c: O << "mon"; return;
896     case 0x1e: O << "hyp"; return;
897     default: llvm_unreachable("Invalid banked SPSR register");
898     }
899   }
900 
901   assert(!R && "should have dealt with SPSR regs");
902   const char *RegNames[] = {
903     "r8_usr", "r9_usr", "r10_usr", "r11_usr", "r12_usr", "sp_usr", "lr_usr", "",
904     "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq", "lr_fiq", "",
905     "lr_irq", "sp_irq", "lr_svc",  "sp_svc",  "lr_abt",  "sp_abt", "lr_und", "sp_und",
906     "",       "",       "",        "",        "lr_mon",  "sp_mon", "elr_hyp", "sp_hyp"
907   };
908   const char *Name = RegNames[SysM];
909   assert(Name[0] && "invalid banked register operand");
910 
911   O << Name;
912 }
913 
914 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
915                                            raw_ostream &O) {
916   ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
917   // Handle the undefined 15 CC value here for printing so we don't abort().
918   if ((unsigned)CC == 15)
919     O << "<und>";
920   else if (CC != ARMCC::AL)
921     O << ARMCondCodeToString(CC);
922 }
923 
924 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
925                                                     unsigned OpNum,
926                                                     raw_ostream &O) {
927   ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
928   O << ARMCondCodeToString(CC);
929 }
930 
931 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
932                                               raw_ostream &O) {
933   if (MI->getOperand(OpNum).getReg()) {
934     assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
935            "Expect ARM CPSR register!");
936     O << 's';
937   }
938 }
939 
940 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
941                                           raw_ostream &O) {
942   O << MI->getOperand(OpNum).getImm();
943 }
944 
945 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
946                                      raw_ostream &O) {
947   O << "p" << MI->getOperand(OpNum).getImm();
948 }
949 
950 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
951                                      raw_ostream &O) {
952   O << "c" << MI->getOperand(OpNum).getImm();
953 }
954 
955 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
956                                           raw_ostream &O) {
957   O << "{" << MI->getOperand(OpNum).getImm() << "}";
958 }
959 
960 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
961                                   raw_ostream &O) {
962   llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
963 }
964 
965 template<unsigned scale>
966 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
967                                   raw_ostream &O) {
968   const MCOperand &MO = MI->getOperand(OpNum);
969 
970   if (MO.isExpr()) {
971     O << *MO.getExpr();
972     return;
973   }
974 
975   int32_t OffImm = (int32_t)MO.getImm() << scale;
976 
977   O << markup("<imm:");
978   if (OffImm == INT32_MIN)
979     O << "#-0";
980   else if (OffImm < 0)
981     O << "#-" << -OffImm;
982   else
983     O << "#" << OffImm;
984   O << markup(">");
985 }
986 
987 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
988                                             raw_ostream &O) {
989   O << markup("<imm:")
990     << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
991     << markup(">");
992 }
993 
994 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
995                                      raw_ostream &O) {
996   unsigned Imm = MI->getOperand(OpNum).getImm();
997   O << markup("<imm:")
998     << "#" << formatImm((Imm == 0 ? 32 : Imm))
999     << markup(">");
1000 }
1001 
1002 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
1003                                       raw_ostream &O) {
1004   // (3 - the number of trailing zeros) is the number of then / else.
1005   unsigned Mask = MI->getOperand(OpNum).getImm();
1006   unsigned Firstcond = MI->getOperand(OpNum-1).getImm();
1007   unsigned CondBit0 = Firstcond & 1;
1008   unsigned NumTZ = countTrailingZeros(Mask);
1009   assert(NumTZ <= 3 && "Invalid IT mask!");
1010   for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
1011     bool T = ((Mask >> Pos) & 1) == CondBit0;
1012     if (T)
1013       O << 't';
1014     else
1015       O << 'e';
1016   }
1017 }
1018 
1019 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
1020                                                  raw_ostream &O) {
1021   const MCOperand &MO1 = MI->getOperand(Op);
1022   const MCOperand &MO2 = MI->getOperand(Op + 1);
1023 
1024   if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
1025     printOperand(MI, Op, O);
1026     return;
1027   }
1028 
1029   O << markup("<mem:") << "[";
1030   printRegName(O, MO1.getReg());
1031   if (unsigned RegNum = MO2.getReg()) {
1032     O << ", ";
1033     printRegName(O, RegNum);
1034   }
1035   O << "]" << markup(">");
1036 }
1037 
1038 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
1039                                                     unsigned Op,
1040                                                     raw_ostream &O,
1041                                                     unsigned Scale) {
1042   const MCOperand &MO1 = MI->getOperand(Op);
1043   const MCOperand &MO2 = MI->getOperand(Op + 1);
1044 
1045   if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
1046     printOperand(MI, Op, O);
1047     return;
1048   }
1049 
1050   O << markup("<mem:") << "[";
1051   printRegName(O, MO1.getReg());
1052   if (unsigned ImmOffs = MO2.getImm()) {
1053     O << ", "
1054       << markup("<imm:")
1055       << "#" << formatImm(ImmOffs * Scale)
1056       << markup(">");
1057   }
1058   O << "]" << markup(">");
1059 }
1060 
1061 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
1062                                                      unsigned Op,
1063                                                      raw_ostream &O) {
1064   printThumbAddrModeImm5SOperand(MI, Op, O, 1);
1065 }
1066 
1067 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
1068                                                      unsigned Op,
1069                                                      raw_ostream &O) {
1070   printThumbAddrModeImm5SOperand(MI, Op, O, 2);
1071 }
1072 
1073 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
1074                                                      unsigned Op,
1075                                                      raw_ostream &O) {
1076   printThumbAddrModeImm5SOperand(MI, Op, O, 4);
1077 }
1078 
1079 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
1080                                                  raw_ostream &O) {
1081   printThumbAddrModeImm5SOperand(MI, Op, O, 4);
1082 }
1083 
1084 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1085 // register with shift forms.
1086 // REG 0   0           - e.g. R5
1087 // REG IMM, SH_OPC     - e.g. R5, LSL #3
1088 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1089                                       raw_ostream &O) {
1090   const MCOperand &MO1 = MI->getOperand(OpNum);
1091   const MCOperand &MO2 = MI->getOperand(OpNum+1);
1092 
1093   unsigned Reg = MO1.getReg();
1094   printRegName(O, Reg);
1095 
1096   // Print the shift opc.
1097   assert(MO2.isImm() && "Not a valid t2_so_reg value!");
1098   printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
1099                    ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
1100 }
1101 
1102 template <bool AlwaysPrintImm0>
1103 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
1104                                                raw_ostream &O) {
1105   const MCOperand &MO1 = MI->getOperand(OpNum);
1106   const MCOperand &MO2 = MI->getOperand(OpNum+1);
1107 
1108   if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
1109     printOperand(MI, OpNum, O);
1110     return;
1111   }
1112 
1113   O << markup("<mem:") << "[";
1114   printRegName(O, MO1.getReg());
1115 
1116   int32_t OffImm = (int32_t)MO2.getImm();
1117   bool isSub = OffImm < 0;
1118   // Special value for #-0. All others are normal.
1119   if (OffImm == INT32_MIN)
1120     OffImm = 0;
1121   if (isSub) {
1122     O << ", "
1123       << markup("<imm:")
1124       << "#-" << formatImm(-OffImm)
1125       << markup(">");
1126   }
1127   else if (AlwaysPrintImm0 || OffImm > 0) {
1128     O << ", "
1129       << markup("<imm:")
1130       << "#" << formatImm(OffImm)
1131       << markup(">");
1132   }
1133   O << "]" << markup(">");
1134 }
1135 
1136 template<bool AlwaysPrintImm0>
1137 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
1138                                                 unsigned OpNum,
1139                                                 raw_ostream &O) {
1140   const MCOperand &MO1 = MI->getOperand(OpNum);
1141   const MCOperand &MO2 = MI->getOperand(OpNum+1);
1142 
1143   O << markup("<mem:") << "[";
1144   printRegName(O, MO1.getReg());
1145 
1146   int32_t OffImm = (int32_t)MO2.getImm();
1147   bool isSub = OffImm < 0;
1148   // Don't print +0.
1149   if (OffImm == INT32_MIN)
1150     OffImm = 0;
1151   if (isSub) {
1152     O << ", "
1153       << markup("<imm:")
1154       << "#-" << -OffImm
1155       << markup(">");
1156   } else if (AlwaysPrintImm0 || OffImm > 0) {
1157     O << ", "
1158       << markup("<imm:")
1159       << "#" << OffImm
1160       << markup(">");
1161   }
1162   O << "]" << markup(">");
1163 }
1164 
1165 template<bool AlwaysPrintImm0>
1166 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
1167                                                   unsigned OpNum,
1168                                                   raw_ostream &O) {
1169   const MCOperand &MO1 = MI->getOperand(OpNum);
1170   const MCOperand &MO2 = MI->getOperand(OpNum+1);
1171 
1172   if (!MO1.isReg()) {   //  For label symbolic references.
1173     printOperand(MI, OpNum, O);
1174     return;
1175   }
1176 
1177   O << markup("<mem:") << "[";
1178   printRegName(O, MO1.getReg());
1179 
1180   int32_t OffImm = (int32_t)MO2.getImm();
1181   bool isSub = OffImm < 0;
1182 
1183   assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1184 
1185   // Don't print +0.
1186   if (OffImm == INT32_MIN)
1187     OffImm = 0;
1188   if (isSub) {
1189     O << ", "
1190       << markup("<imm:")
1191       << "#-" << -OffImm
1192       << markup(">");
1193   } else if (AlwaysPrintImm0 || OffImm > 0) {
1194     O << ", "
1195       << markup("<imm:")
1196       << "#" << OffImm
1197       << markup(">");
1198   }
1199   O << "]" << markup(">");
1200 }
1201 
1202 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
1203                                                        unsigned OpNum,
1204                                                        raw_ostream &O) {
1205   const MCOperand &MO1 = MI->getOperand(OpNum);
1206   const MCOperand &MO2 = MI->getOperand(OpNum+1);
1207 
1208   O << markup("<mem:") << "[";
1209   printRegName(O, MO1.getReg());
1210   if (MO2.getImm()) {
1211     O << ", "
1212       << markup("<imm:")
1213       << "#" << formatImm(MO2.getImm() * 4)
1214       << markup(">");
1215   }
1216   O << "]" << markup(">");
1217 }
1218 
1219 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
1220                                                       unsigned OpNum,
1221                                                       raw_ostream &O) {
1222   const MCOperand &MO1 = MI->getOperand(OpNum);
1223   int32_t OffImm = (int32_t)MO1.getImm();
1224   O << ", " << markup("<imm:");
1225   if (OffImm == INT32_MIN)
1226     O << "#-0";
1227   else if (OffImm < 0)
1228     O << "#-" << -OffImm;
1229   else
1230     O << "#" << OffImm;
1231   O << markup(">");
1232 }
1233 
1234 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
1235                                                         unsigned OpNum,
1236                                                         raw_ostream &O) {
1237   const MCOperand &MO1 = MI->getOperand(OpNum);
1238   int32_t OffImm = (int32_t)MO1.getImm();
1239 
1240   assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1241 
1242   O << ", " << markup("<imm:");
1243   if (OffImm == INT32_MIN)
1244     O << "#-0";
1245   else if (OffImm < 0)
1246     O << "#-" << -OffImm;
1247   else
1248     O << "#" << OffImm;
1249   O << markup(">");
1250 }
1251 
1252 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1253                                                  unsigned OpNum,
1254                                                  raw_ostream &O) {
1255   const MCOperand &MO1 = MI->getOperand(OpNum);
1256   const MCOperand &MO2 = MI->getOperand(OpNum+1);
1257   const MCOperand &MO3 = MI->getOperand(OpNum+2);
1258 
1259   O << markup("<mem:") << "[";
1260   printRegName(O, MO1.getReg());
1261 
1262   assert(MO2.getReg() && "Invalid so_reg load / store address!");
1263   O << ", ";
1264   printRegName(O, MO2.getReg());
1265 
1266   unsigned ShAmt = MO3.getImm();
1267   if (ShAmt) {
1268     assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1269     O << ", lsl "
1270       << markup("<imm:")
1271       << "#" << ShAmt
1272       << markup(">");
1273   }
1274   O << "]" << markup(">");
1275 }
1276 
1277 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1278                                        raw_ostream &O) {
1279   const MCOperand &MO = MI->getOperand(OpNum);
1280   O << markup("<imm:")
1281     << '#' << ARM_AM::getFPImmFloat(MO.getImm())
1282     << markup(">");
1283 }
1284 
1285 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
1286                                             raw_ostream &O) {
1287   unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1288   unsigned EltBits;
1289   uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1290   O << markup("<imm:")
1291     << "#0x";
1292   O.write_hex(Val);
1293   O << markup(">");
1294 }
1295 
1296 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1297                                             raw_ostream &O) {
1298   unsigned Imm = MI->getOperand(OpNum).getImm();
1299   O << markup("<imm:")
1300     << "#" << formatImm(Imm + 1)
1301     << markup(">");
1302 }
1303 
1304 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1305                                         raw_ostream &O) {
1306   unsigned Imm = MI->getOperand(OpNum).getImm();
1307   if (Imm == 0)
1308     return;
1309   O << ", ror "
1310     << markup("<imm:")
1311     << "#";
1312   switch (Imm) {
1313   default: assert (0 && "illegal ror immediate!");
1314   case 1: O << "8"; break;
1315   case 2: O << "16"; break;
1316   case 3: O << "24"; break;
1317   }
1318   O << markup(">");
1319 }
1320 
1321 void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
1322                                         raw_ostream &O) {
1323   MCOperand Op = MI->getOperand(OpNum);
1324 
1325   // Support for fixups (MCFixup)
1326   if (Op.isExpr())
1327     return printOperand(MI, OpNum, O);
1328 
1329   unsigned Bits = Op.getImm() & 0xFF;
1330   unsigned Rot = (Op.getImm() & 0xF00) >> 7;
1331 
1332   bool  PrintUnsigned = false;
1333   switch (MI->getOpcode()){
1334   case ARM::MOVi:
1335     // Movs to PC should be treated unsigned
1336     PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1337     break;
1338   case ARM::MSRi:
1339     // Movs to special registers should be treated unsigned
1340     PrintUnsigned = true;
1341     break;
1342   }
1343 
1344   int32_t Rotated = ARM_AM::rotr32(Bits, Rot);
1345   if (ARM_AM::getSOImmVal(Rotated) == Op.getImm()) {
1346     // #rot has the least possible value
1347     O << "#" << markup("<imm:");
1348     if (PrintUnsigned)
1349       O << static_cast<uint32_t>(Rotated);
1350     else
1351       O << Rotated;
1352     O << markup(">");
1353     return;
1354   }
1355 
1356   // Explicit #bits, #rot implied
1357   O << "#"
1358     << markup("<imm:")
1359     << Bits
1360     << markup(">")
1361     << ", #"
1362     << markup("<imm:")
1363     << Rot
1364     << markup(">");
1365 }
1366 
1367 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1368                                   raw_ostream &O) {
1369   O << markup("<imm:")
1370     << "#" << 16 - MI->getOperand(OpNum).getImm()
1371     << markup(">");
1372 }
1373 
1374 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1375                                   raw_ostream &O) {
1376   O << markup("<imm:")
1377     << "#" << 32 - MI->getOperand(OpNum).getImm()
1378     << markup(">");
1379 }
1380 
1381 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1382                                       raw_ostream &O) {
1383   O << "[" << MI->getOperand(OpNum).getImm() << "]";
1384 }
1385 
1386 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1387                                         raw_ostream &O) {
1388   O << "{";
1389   printRegName(O, MI->getOperand(OpNum).getReg());
1390   O << "}";
1391 }
1392 
1393 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1394                                           raw_ostream &O) {
1395   unsigned Reg = MI->getOperand(OpNum).getReg();
1396   unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1397   unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1398   O << "{";
1399   printRegName(O, Reg0);
1400   O << ", ";
1401   printRegName(O, Reg1);
1402   O << "}";
1403 }
1404 
1405 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI,
1406                                               unsigned OpNum,
1407                                               raw_ostream &O) {
1408   unsigned Reg = MI->getOperand(OpNum).getReg();
1409   unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1410   unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1411   O << "{";
1412   printRegName(O, Reg0);
1413   O << ", ";
1414   printRegName(O, Reg1);
1415   O << "}";
1416 }
1417 
1418 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1419                                           raw_ostream &O) {
1420   // Normally, it's not safe to use register enum values directly with
1421   // addition to get the next register, but for VFP registers, the
1422   // sort order is guaranteed because they're all of the form D<n>.
1423   O << "{";
1424   printRegName(O, MI->getOperand(OpNum).getReg());
1425   O << ", ";
1426   printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1427   O << ", ";
1428   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1429   O << "}";
1430 }
1431 
1432 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1433                                          raw_ostream &O) {
1434   // Normally, it's not safe to use register enum values directly with
1435   // addition to get the next register, but for VFP registers, the
1436   // sort order is guaranteed because they're all of the form D<n>.
1437   O << "{";
1438   printRegName(O, MI->getOperand(OpNum).getReg());
1439   O << ", ";
1440   printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1441   O << ", ";
1442   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1443   O << ", ";
1444   printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1445   O << "}";
1446 }
1447 
1448 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1449                                                 unsigned OpNum,
1450                                                 raw_ostream &O) {
1451   O << "{";
1452   printRegName(O, MI->getOperand(OpNum).getReg());
1453   O << "[]}";
1454 }
1455 
1456 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1457                                                 unsigned OpNum,
1458                                                 raw_ostream &O) {
1459   unsigned Reg = MI->getOperand(OpNum).getReg();
1460   unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1461   unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1462   O << "{";
1463   printRegName(O, Reg0);
1464   O << "[], ";
1465   printRegName(O, Reg1);
1466   O << "[]}";
1467 }
1468 
1469 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1470                                                   unsigned OpNum,
1471                                                   raw_ostream &O) {
1472   // Normally, it's not safe to use register enum values directly with
1473   // addition to get the next register, but for VFP registers, the
1474   // sort order is guaranteed because they're all of the form D<n>.
1475   O << "{";
1476   printRegName(O, MI->getOperand(OpNum).getReg());
1477   O << "[], ";
1478   printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1479   O << "[], ";
1480   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1481   O << "[]}";
1482 }
1483 
1484 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1485                                                   unsigned OpNum,
1486                                                   raw_ostream &O) {
1487   // Normally, it's not safe to use register enum values directly with
1488   // addition to get the next register, but for VFP registers, the
1489   // sort order is guaranteed because they're all of the form D<n>.
1490   O << "{";
1491   printRegName(O, MI->getOperand(OpNum).getReg());
1492   O << "[], ";
1493   printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1494   O << "[], ";
1495   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1496   O << "[], ";
1497   printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1498   O << "[]}";
1499 }
1500 
1501 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
1502                                                       unsigned OpNum,
1503                                                       raw_ostream &O) {
1504   unsigned Reg = MI->getOperand(OpNum).getReg();
1505   unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1506   unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1507   O << "{";
1508   printRegName(O, Reg0);
1509   O << "[], ";
1510   printRegName(O, Reg1);
1511   O << "[]}";
1512 }
1513 
1514 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
1515                                                         unsigned OpNum,
1516                                                         raw_ostream &O) {
1517   // Normally, it's not safe to use register enum values directly with
1518   // addition to get the next register, but for VFP registers, the
1519   // sort order is guaranteed because they're all of the form D<n>.
1520   O << "{";
1521   printRegName(O, MI->getOperand(OpNum).getReg());
1522   O  << "[], ";
1523   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1524   O << "[], ";
1525   printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1526   O << "[]}";
1527 }
1528 
1529 void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI,
1530                                                        unsigned OpNum,
1531                                                        raw_ostream &O) {
1532   // Normally, it's not safe to use register enum values directly with
1533   // addition to get the next register, but for VFP registers, the
1534   // sort order is guaranteed because they're all of the form D<n>.
1535   O << "{";
1536   printRegName(O, MI->getOperand(OpNum).getReg());
1537   O << "[], ";
1538   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1539   O << "[], ";
1540   printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1541   O << "[], ";
1542   printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1543   O << "[]}";
1544 }
1545 
1546 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1547                                                 unsigned OpNum,
1548                                                 raw_ostream &O) {
1549   // Normally, it's not safe to use register enum values directly with
1550   // addition to get the next register, but for VFP registers, the
1551   // sort order is guaranteed because they're all of the form D<n>.
1552   O << "{";
1553   printRegName(O, MI->getOperand(OpNum).getReg());
1554   O << ", ";
1555   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1556   O << ", ";
1557   printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1558   O << "}";
1559 }
1560 
1561 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI,
1562                                                 unsigned OpNum,
1563                                                 raw_ostream &O) {
1564   // Normally, it's not safe to use register enum values directly with
1565   // addition to get the next register, but for VFP registers, the
1566   // sort order is guaranteed because they're all of the form D<n>.
1567   O << "{";
1568   printRegName(O, MI->getOperand(OpNum).getReg());
1569   O << ", ";
1570   printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1571   O << ", ";
1572   printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1573   O << ", ";
1574   printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1575   O << "}";
1576 }
1577