1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "ARMFeatures.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "MCTargetDesc/ARMBaseInfo.h" 13 #include "MCTargetDesc/ARMMCExpr.h" 14 #include "llvm/ADT/STLExtras.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringExtras.h" 17 #include "llvm/ADT/StringSwitch.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/ADT/Twine.h" 20 #include "llvm/MC/MCAsmInfo.h" 21 #include "llvm/MC/MCAssembler.h" 22 #include "llvm/MC/MCContext.h" 23 #include "llvm/MC/MCDisassembler.h" 24 #include "llvm/MC/MCELFStreamer.h" 25 #include "llvm/MC/MCExpr.h" 26 #include "llvm/MC/MCInst.h" 27 #include "llvm/MC/MCInstrDesc.h" 28 #include "llvm/MC/MCInstrInfo.h" 29 #include "llvm/MC/MCObjectFileInfo.h" 30 #include "llvm/MC/MCParser/MCAsmLexer.h" 31 #include "llvm/MC/MCParser/MCAsmParser.h" 32 #include "llvm/MC/MCParser/MCAsmParserUtils.h" 33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 34 #include "llvm/MC/MCRegisterInfo.h" 35 #include "llvm/MC/MCSection.h" 36 #include "llvm/MC/MCStreamer.h" 37 #include "llvm/MC/MCSubtargetInfo.h" 38 #include "llvm/MC/MCSymbol.h" 39 #include "llvm/MC/MCTargetAsmParser.h" 40 #include "llvm/Support/ARMBuildAttributes.h" 41 #include "llvm/Support/ARMEHABI.h" 42 #include "llvm/Support/TargetParser.h" 43 #include "llvm/Support/COFF.h" 44 #include "llvm/Support/Debug.h" 45 #include "llvm/Support/ELF.h" 46 #include "llvm/Support/MathExtras.h" 47 #include "llvm/Support/SourceMgr.h" 48 #include "llvm/Support/TargetRegistry.h" 49 #include "llvm/Support/raw_ostream.h" 50 51 using namespace llvm; 52 53 namespace { 54 55 class ARMOperand; 56 57 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; 58 59 class UnwindContext { 60 MCAsmParser &Parser; 61 62 typedef SmallVector<SMLoc, 4> Locs; 63 64 Locs FnStartLocs; 65 Locs CantUnwindLocs; 66 Locs PersonalityLocs; 67 Locs PersonalityIndexLocs; 68 Locs HandlerDataLocs; 69 int FPReg; 70 71 public: 72 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} 73 74 bool hasFnStart() const { return !FnStartLocs.empty(); } 75 bool cantUnwind() const { return !CantUnwindLocs.empty(); } 76 bool hasHandlerData() const { return !HandlerDataLocs.empty(); } 77 bool hasPersonality() const { 78 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty()); 79 } 80 81 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); } 82 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); } 83 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); } 84 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); } 85 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); } 86 87 void saveFPReg(int Reg) { FPReg = Reg; } 88 int getFPReg() const { return FPReg; } 89 90 void emitFnStartLocNotes() const { 91 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end(); 92 FI != FE; ++FI) 93 Parser.Note(*FI, ".fnstart was specified here"); 94 } 95 void emitCantUnwindLocNotes() const { 96 for (Locs::const_iterator UI = CantUnwindLocs.begin(), 97 UE = CantUnwindLocs.end(); UI != UE; ++UI) 98 Parser.Note(*UI, ".cantunwind was specified here"); 99 } 100 void emitHandlerDataLocNotes() const { 101 for (Locs::const_iterator HI = HandlerDataLocs.begin(), 102 HE = HandlerDataLocs.end(); HI != HE; ++HI) 103 Parser.Note(*HI, ".handlerdata was specified here"); 104 } 105 void emitPersonalityLocNotes() const { 106 for (Locs::const_iterator PI = PersonalityLocs.begin(), 107 PE = PersonalityLocs.end(), 108 PII = PersonalityIndexLocs.begin(), 109 PIE = PersonalityIndexLocs.end(); 110 PI != PE || PII != PIE;) { 111 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer())) 112 Parser.Note(*PI++, ".personality was specified here"); 113 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer())) 114 Parser.Note(*PII++, ".personalityindex was specified here"); 115 else 116 llvm_unreachable(".personality and .personalityindex cannot be " 117 "at the same location"); 118 } 119 } 120 121 void reset() { 122 FnStartLocs = Locs(); 123 CantUnwindLocs = Locs(); 124 PersonalityLocs = Locs(); 125 HandlerDataLocs = Locs(); 126 PersonalityIndexLocs = Locs(); 127 FPReg = ARM::SP; 128 } 129 }; 130 131 class ARMAsmParser : public MCTargetAsmParser { 132 MCSubtargetInfo &STI; 133 const MCInstrInfo &MII; 134 const MCRegisterInfo *MRI; 135 UnwindContext UC; 136 137 ARMTargetStreamer &getTargetStreamer() { 138 assert(getParser().getStreamer().getTargetStreamer() && 139 "do not have a target streamer"); 140 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); 141 return static_cast<ARMTargetStreamer &>(TS); 142 } 143 144 // Map of register aliases registers via the .req directive. 145 StringMap<unsigned> RegisterReqs; 146 147 bool NextSymbolIsThumb; 148 149 struct { 150 ARMCC::CondCodes Cond; // Condition for IT block. 151 unsigned Mask:4; // Condition mask for instructions. 152 // Starting at first 1 (from lsb). 153 // '1' condition as indicated in IT. 154 // '0' inverse of condition (else). 155 // Count of instructions in IT block is 156 // 4 - trailingzeroes(mask) 157 158 bool FirstCond; // Explicit flag for when we're parsing the 159 // First instruction in the IT block. It's 160 // implied in the mask, so needs special 161 // handling. 162 163 unsigned CurPosition; // Current position in parsing of IT 164 // block. In range [0,3]. Initialized 165 // according to count of instructions in block. 166 // ~0U if no active IT block. 167 } ITState; 168 bool inITBlock() { return ITState.CurPosition != ~0U; } 169 bool lastInITBlock() { 170 return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask); 171 } 172 void forwardITPosition() { 173 if (!inITBlock()) return; 174 // Move to the next instruction in the IT block, if there is one. If not, 175 // mark the block as done. 176 unsigned TZ = countTrailingZeros(ITState.Mask); 177 if (++ITState.CurPosition == 5 - TZ) 178 ITState.CurPosition = ~0U; // Done with the IT block after this. 179 } 180 181 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) { 182 return getParser().Note(L, Msg, Ranges); 183 } 184 bool Warning(SMLoc L, const Twine &Msg, 185 ArrayRef<SMRange> Ranges = None) { 186 return getParser().Warning(L, Msg, Ranges); 187 } 188 bool Error(SMLoc L, const Twine &Msg, 189 ArrayRef<SMRange> Ranges = None) { 190 return getParser().Error(L, Msg, Ranges); 191 } 192 193 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands, 194 unsigned ListNo, bool IsARPop = false); 195 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands, 196 unsigned ListNo); 197 198 int tryParseRegister(); 199 bool tryParseRegisterWithWriteBack(OperandVector &); 200 int tryParseShiftRegister(OperandVector &); 201 bool parseRegisterList(OperandVector &); 202 bool parseMemory(OperandVector &); 203 bool parseOperand(OperandVector &, StringRef Mnemonic); 204 bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 205 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 206 unsigned &ShiftAmount); 207 bool parseLiteralValues(unsigned Size, SMLoc L); 208 bool parseDirectiveThumb(SMLoc L); 209 bool parseDirectiveARM(SMLoc L); 210 bool parseDirectiveThumbFunc(SMLoc L); 211 bool parseDirectiveCode(SMLoc L); 212 bool parseDirectiveSyntax(SMLoc L); 213 bool parseDirectiveReq(StringRef Name, SMLoc L); 214 bool parseDirectiveUnreq(SMLoc L); 215 bool parseDirectiveArch(SMLoc L); 216 bool parseDirectiveEabiAttr(SMLoc L); 217 bool parseDirectiveCPU(SMLoc L); 218 bool parseDirectiveFPU(SMLoc L); 219 bool parseDirectiveFnStart(SMLoc L); 220 bool parseDirectiveFnEnd(SMLoc L); 221 bool parseDirectiveCantUnwind(SMLoc L); 222 bool parseDirectivePersonality(SMLoc L); 223 bool parseDirectiveHandlerData(SMLoc L); 224 bool parseDirectiveSetFP(SMLoc L); 225 bool parseDirectivePad(SMLoc L); 226 bool parseDirectiveRegSave(SMLoc L, bool IsVector); 227 bool parseDirectiveInst(SMLoc L, char Suffix = '\0'); 228 bool parseDirectiveLtorg(SMLoc L); 229 bool parseDirectiveEven(SMLoc L); 230 bool parseDirectivePersonalityIndex(SMLoc L); 231 bool parseDirectiveUnwindRaw(SMLoc L); 232 bool parseDirectiveTLSDescSeq(SMLoc L); 233 bool parseDirectiveMovSP(SMLoc L); 234 bool parseDirectiveObjectArch(SMLoc L); 235 bool parseDirectiveArchExtension(SMLoc L); 236 bool parseDirectiveAlign(SMLoc L); 237 bool parseDirectiveThumbSet(SMLoc L); 238 239 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 240 bool &CarrySetting, unsigned &ProcessorIMod, 241 StringRef &ITMask); 242 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst, 243 bool &CanAcceptCarrySet, 244 bool &CanAcceptPredicationCode); 245 246 void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting, 247 OperandVector &Operands); 248 bool isThumb() const { 249 // FIXME: Can tablegen auto-generate this? 250 return STI.getFeatureBits()[ARM::ModeThumb]; 251 } 252 bool isThumbOne() const { 253 return isThumb() && !STI.getFeatureBits()[ARM::FeatureThumb2]; 254 } 255 bool isThumbTwo() const { 256 return isThumb() && STI.getFeatureBits()[ARM::FeatureThumb2]; 257 } 258 bool hasThumb() const { 259 return STI.getFeatureBits()[ARM::HasV4TOps]; 260 } 261 bool hasV6Ops() const { 262 return STI.getFeatureBits()[ARM::HasV6Ops]; 263 } 264 bool hasV6MOps() const { 265 return STI.getFeatureBits()[ARM::HasV6MOps]; 266 } 267 bool hasV7Ops() const { 268 return STI.getFeatureBits()[ARM::HasV7Ops]; 269 } 270 bool hasV8Ops() const { 271 return STI.getFeatureBits()[ARM::HasV8Ops]; 272 } 273 bool hasARM() const { 274 return !STI.getFeatureBits()[ARM::FeatureNoARM]; 275 } 276 bool hasThumb2DSP() const { 277 return STI.getFeatureBits()[ARM::FeatureDSPThumb2]; 278 } 279 bool hasD16() const { 280 return STI.getFeatureBits()[ARM::FeatureD16]; 281 } 282 bool hasV8_1aOps() const { 283 return STI.getFeatureBits()[ARM::HasV8_1aOps]; 284 } 285 286 void SwitchMode() { 287 uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 288 setAvailableFeatures(FB); 289 } 290 bool isMClass() const { 291 return STI.getFeatureBits()[ARM::FeatureMClass]; 292 } 293 294 /// @name Auto-generated Match Functions 295 /// { 296 297 #define GET_ASSEMBLER_HEADER 298 #include "ARMGenAsmMatcher.inc" 299 300 /// } 301 302 OperandMatchResultTy parseITCondCode(OperandVector &); 303 OperandMatchResultTy parseCoprocNumOperand(OperandVector &); 304 OperandMatchResultTy parseCoprocRegOperand(OperandVector &); 305 OperandMatchResultTy parseCoprocOptionOperand(OperandVector &); 306 OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &); 307 OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &); 308 OperandMatchResultTy parseProcIFlagsOperand(OperandVector &); 309 OperandMatchResultTy parseMSRMaskOperand(OperandVector &); 310 OperandMatchResultTy parseBankedRegOperand(OperandVector &); 311 OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low, 312 int High); 313 OperandMatchResultTy parsePKHLSLImm(OperandVector &O) { 314 return parsePKHImm(O, "lsl", 0, 31); 315 } 316 OperandMatchResultTy parsePKHASRImm(OperandVector &O) { 317 return parsePKHImm(O, "asr", 1, 32); 318 } 319 OperandMatchResultTy parseSetEndImm(OperandVector &); 320 OperandMatchResultTy parseShifterImm(OperandVector &); 321 OperandMatchResultTy parseRotImm(OperandVector &); 322 OperandMatchResultTy parseModImm(OperandVector &); 323 OperandMatchResultTy parseBitfield(OperandVector &); 324 OperandMatchResultTy parsePostIdxReg(OperandVector &); 325 OperandMatchResultTy parseAM3Offset(OperandVector &); 326 OperandMatchResultTy parseFPImm(OperandVector &); 327 OperandMatchResultTy parseVectorList(OperandVector &); 328 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, 329 SMLoc &EndLoc); 330 331 // Asm Match Converter Methods 332 void cvtThumbMultiply(MCInst &Inst, const OperandVector &); 333 void cvtThumbBranches(MCInst &Inst, const OperandVector &); 334 335 bool validateInstruction(MCInst &Inst, const OperandVector &Ops); 336 bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out); 337 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands); 338 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands); 339 340 public: 341 enum ARMMatchResultTy { 342 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 343 Match_RequiresNotITBlock, 344 Match_RequiresV6, 345 Match_RequiresThumb2, 346 #define GET_OPERAND_DIAGNOSTIC_TYPES 347 #include "ARMGenAsmMatcher.inc" 348 349 }; 350 351 ARMAsmParser(MCSubtargetInfo &STI, MCAsmParser &Parser, 352 const MCInstrInfo &MII, const MCTargetOptions &Options) 353 : STI(STI), MII(MII), UC(Parser) { 354 MCAsmParserExtension::Initialize(Parser); 355 356 // Cache the MCRegisterInfo. 357 MRI = getContext().getRegisterInfo(); 358 359 // Initialize the set of available features. 360 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 361 362 // Not in an ITBlock to start with. 363 ITState.CurPosition = ~0U; 364 365 NextSymbolIsThumb = false; 366 } 367 368 // Implementation of the MCTargetAsmParser interface: 369 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 370 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 371 SMLoc NameLoc, OperandVector &Operands) override; 372 bool ParseDirective(AsmToken DirectiveID) override; 373 374 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, 375 unsigned Kind) override; 376 unsigned checkTargetMatchPredicate(MCInst &Inst) override; 377 378 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 379 OperandVector &Operands, MCStreamer &Out, 380 uint64_t &ErrorInfo, 381 bool MatchingInlineAsm) override; 382 void onLabelParsed(MCSymbol *Symbol) override; 383 }; 384 } // end anonymous namespace 385 386 namespace { 387 388 /// ARMOperand - Instances of this class represent a parsed ARM machine 389 /// operand. 390 class ARMOperand : public MCParsedAsmOperand { 391 enum KindTy { 392 k_CondCode, 393 k_CCOut, 394 k_ITCondMask, 395 k_CoprocNum, 396 k_CoprocReg, 397 k_CoprocOption, 398 k_Immediate, 399 k_MemBarrierOpt, 400 k_InstSyncBarrierOpt, 401 k_Memory, 402 k_PostIndexRegister, 403 k_MSRMask, 404 k_BankedReg, 405 k_ProcIFlags, 406 k_VectorIndex, 407 k_Register, 408 k_RegisterList, 409 k_DPRRegisterList, 410 k_SPRRegisterList, 411 k_VectorList, 412 k_VectorListAllLanes, 413 k_VectorListIndexed, 414 k_ShiftedRegister, 415 k_ShiftedImmediate, 416 k_ShifterImmediate, 417 k_RotateImmediate, 418 k_ModifiedImmediate, 419 k_BitfieldDescriptor, 420 k_Token 421 } Kind; 422 423 SMLoc StartLoc, EndLoc, AlignmentLoc; 424 SmallVector<unsigned, 8> Registers; 425 426 struct CCOp { 427 ARMCC::CondCodes Val; 428 }; 429 430 struct CopOp { 431 unsigned Val; 432 }; 433 434 struct CoprocOptionOp { 435 unsigned Val; 436 }; 437 438 struct ITMaskOp { 439 unsigned Mask:4; 440 }; 441 442 struct MBOptOp { 443 ARM_MB::MemBOpt Val; 444 }; 445 446 struct ISBOptOp { 447 ARM_ISB::InstSyncBOpt Val; 448 }; 449 450 struct IFlagsOp { 451 ARM_PROC::IFlags Val; 452 }; 453 454 struct MMaskOp { 455 unsigned Val; 456 }; 457 458 struct BankedRegOp { 459 unsigned Val; 460 }; 461 462 struct TokOp { 463 const char *Data; 464 unsigned Length; 465 }; 466 467 struct RegOp { 468 unsigned RegNum; 469 }; 470 471 // A vector register list is a sequential list of 1 to 4 registers. 472 struct VectorListOp { 473 unsigned RegNum; 474 unsigned Count; 475 unsigned LaneIndex; 476 bool isDoubleSpaced; 477 }; 478 479 struct VectorIndexOp { 480 unsigned Val; 481 }; 482 483 struct ImmOp { 484 const MCExpr *Val; 485 }; 486 487 /// Combined record for all forms of ARM address expressions. 488 struct MemoryOp { 489 unsigned BaseRegNum; 490 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 491 // was specified. 492 const MCConstantExpr *OffsetImm; // Offset immediate value 493 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 494 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 495 unsigned ShiftImm; // shift for OffsetReg. 496 unsigned Alignment; // 0 = no alignment specified 497 // n = alignment in bytes (2, 4, 8, 16, or 32) 498 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 499 }; 500 501 struct PostIdxRegOp { 502 unsigned RegNum; 503 bool isAdd; 504 ARM_AM::ShiftOpc ShiftTy; 505 unsigned ShiftImm; 506 }; 507 508 struct ShifterImmOp { 509 bool isASR; 510 unsigned Imm; 511 }; 512 513 struct RegShiftedRegOp { 514 ARM_AM::ShiftOpc ShiftTy; 515 unsigned SrcReg; 516 unsigned ShiftReg; 517 unsigned ShiftImm; 518 }; 519 520 struct RegShiftedImmOp { 521 ARM_AM::ShiftOpc ShiftTy; 522 unsigned SrcReg; 523 unsigned ShiftImm; 524 }; 525 526 struct RotImmOp { 527 unsigned Imm; 528 }; 529 530 struct ModImmOp { 531 unsigned Bits; 532 unsigned Rot; 533 }; 534 535 struct BitfieldOp { 536 unsigned LSB; 537 unsigned Width; 538 }; 539 540 union { 541 struct CCOp CC; 542 struct CopOp Cop; 543 struct CoprocOptionOp CoprocOption; 544 struct MBOptOp MBOpt; 545 struct ISBOptOp ISBOpt; 546 struct ITMaskOp ITMask; 547 struct IFlagsOp IFlags; 548 struct MMaskOp MMask; 549 struct BankedRegOp BankedReg; 550 struct TokOp Tok; 551 struct RegOp Reg; 552 struct VectorListOp VectorList; 553 struct VectorIndexOp VectorIndex; 554 struct ImmOp Imm; 555 struct MemoryOp Memory; 556 struct PostIdxRegOp PostIdxReg; 557 struct ShifterImmOp ShifterImm; 558 struct RegShiftedRegOp RegShiftedReg; 559 struct RegShiftedImmOp RegShiftedImm; 560 struct RotImmOp RotImm; 561 struct ModImmOp ModImm; 562 struct BitfieldOp Bitfield; 563 }; 564 565 public: 566 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 567 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 568 Kind = o.Kind; 569 StartLoc = o.StartLoc; 570 EndLoc = o.EndLoc; 571 switch (Kind) { 572 case k_CondCode: 573 CC = o.CC; 574 break; 575 case k_ITCondMask: 576 ITMask = o.ITMask; 577 break; 578 case k_Token: 579 Tok = o.Tok; 580 break; 581 case k_CCOut: 582 case k_Register: 583 Reg = o.Reg; 584 break; 585 case k_RegisterList: 586 case k_DPRRegisterList: 587 case k_SPRRegisterList: 588 Registers = o.Registers; 589 break; 590 case k_VectorList: 591 case k_VectorListAllLanes: 592 case k_VectorListIndexed: 593 VectorList = o.VectorList; 594 break; 595 case k_CoprocNum: 596 case k_CoprocReg: 597 Cop = o.Cop; 598 break; 599 case k_CoprocOption: 600 CoprocOption = o.CoprocOption; 601 break; 602 case k_Immediate: 603 Imm = o.Imm; 604 break; 605 case k_MemBarrierOpt: 606 MBOpt = o.MBOpt; 607 break; 608 case k_InstSyncBarrierOpt: 609 ISBOpt = o.ISBOpt; 610 case k_Memory: 611 Memory = o.Memory; 612 break; 613 case k_PostIndexRegister: 614 PostIdxReg = o.PostIdxReg; 615 break; 616 case k_MSRMask: 617 MMask = o.MMask; 618 break; 619 case k_BankedReg: 620 BankedReg = o.BankedReg; 621 break; 622 case k_ProcIFlags: 623 IFlags = o.IFlags; 624 break; 625 case k_ShifterImmediate: 626 ShifterImm = o.ShifterImm; 627 break; 628 case k_ShiftedRegister: 629 RegShiftedReg = o.RegShiftedReg; 630 break; 631 case k_ShiftedImmediate: 632 RegShiftedImm = o.RegShiftedImm; 633 break; 634 case k_RotateImmediate: 635 RotImm = o.RotImm; 636 break; 637 case k_ModifiedImmediate: 638 ModImm = o.ModImm; 639 break; 640 case k_BitfieldDescriptor: 641 Bitfield = o.Bitfield; 642 break; 643 case k_VectorIndex: 644 VectorIndex = o.VectorIndex; 645 break; 646 } 647 } 648 649 /// getStartLoc - Get the location of the first token of this operand. 650 SMLoc getStartLoc() const override { return StartLoc; } 651 /// getEndLoc - Get the location of the last token of this operand. 652 SMLoc getEndLoc() const override { return EndLoc; } 653 /// getLocRange - Get the range between the first and last token of this 654 /// operand. 655 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 656 657 /// getAlignmentLoc - Get the location of the Alignment token of this operand. 658 SMLoc getAlignmentLoc() const { 659 assert(Kind == k_Memory && "Invalid access!"); 660 return AlignmentLoc; 661 } 662 663 ARMCC::CondCodes getCondCode() const { 664 assert(Kind == k_CondCode && "Invalid access!"); 665 return CC.Val; 666 } 667 668 unsigned getCoproc() const { 669 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 670 return Cop.Val; 671 } 672 673 StringRef getToken() const { 674 assert(Kind == k_Token && "Invalid access!"); 675 return StringRef(Tok.Data, Tok.Length); 676 } 677 678 unsigned getReg() const override { 679 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 680 return Reg.RegNum; 681 } 682 683 const SmallVectorImpl<unsigned> &getRegList() const { 684 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || 685 Kind == k_SPRRegisterList) && "Invalid access!"); 686 return Registers; 687 } 688 689 const MCExpr *getImm() const { 690 assert(isImm() && "Invalid access!"); 691 return Imm.Val; 692 } 693 694 unsigned getVectorIndex() const { 695 assert(Kind == k_VectorIndex && "Invalid access!"); 696 return VectorIndex.Val; 697 } 698 699 ARM_MB::MemBOpt getMemBarrierOpt() const { 700 assert(Kind == k_MemBarrierOpt && "Invalid access!"); 701 return MBOpt.Val; 702 } 703 704 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const { 705 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!"); 706 return ISBOpt.Val; 707 } 708 709 ARM_PROC::IFlags getProcIFlags() const { 710 assert(Kind == k_ProcIFlags && "Invalid access!"); 711 return IFlags.Val; 712 } 713 714 unsigned getMSRMask() const { 715 assert(Kind == k_MSRMask && "Invalid access!"); 716 return MMask.Val; 717 } 718 719 unsigned getBankedReg() const { 720 assert(Kind == k_BankedReg && "Invalid access!"); 721 return BankedReg.Val; 722 } 723 724 bool isCoprocNum() const { return Kind == k_CoprocNum; } 725 bool isCoprocReg() const { return Kind == k_CoprocReg; } 726 bool isCoprocOption() const { return Kind == k_CoprocOption; } 727 bool isCondCode() const { return Kind == k_CondCode; } 728 bool isCCOut() const { return Kind == k_CCOut; } 729 bool isITMask() const { return Kind == k_ITCondMask; } 730 bool isITCondCode() const { return Kind == k_CondCode; } 731 bool isImm() const override { return Kind == k_Immediate; } 732 // checks whether this operand is an unsigned offset which fits is a field 733 // of specified width and scaled by a specific number of bits 734 template<unsigned width, unsigned scale> 735 bool isUnsignedOffset() const { 736 if (!isImm()) return false; 737 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 738 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 739 int64_t Val = CE->getValue(); 740 int64_t Align = 1LL << scale; 741 int64_t Max = Align * ((1LL << width) - 1); 742 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max); 743 } 744 return false; 745 } 746 // checks whether this operand is an signed offset which fits is a field 747 // of specified width and scaled by a specific number of bits 748 template<unsigned width, unsigned scale> 749 bool isSignedOffset() const { 750 if (!isImm()) return false; 751 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 752 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 753 int64_t Val = CE->getValue(); 754 int64_t Align = 1LL << scale; 755 int64_t Max = Align * ((1LL << (width-1)) - 1); 756 int64_t Min = -Align * (1LL << (width-1)); 757 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max); 758 } 759 return false; 760 } 761 762 // checks whether this operand is a memory operand computed as an offset 763 // applied to PC. the offset may have 8 bits of magnitude and is represented 764 // with two bits of shift. textually it may be either [pc, #imm], #imm or 765 // relocable expression... 766 bool isThumbMemPC() const { 767 int64_t Val = 0; 768 if (isImm()) { 769 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 770 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val); 771 if (!CE) return false; 772 Val = CE->getValue(); 773 } 774 else if (isMem()) { 775 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false; 776 if(Memory.BaseRegNum != ARM::PC) return false; 777 Val = Memory.OffsetImm->getValue(); 778 } 779 else return false; 780 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020); 781 } 782 bool isFPImm() const { 783 if (!isImm()) return false; 784 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 785 if (!CE) return false; 786 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 787 return Val != -1; 788 } 789 bool isFBits16() const { 790 if (!isImm()) return false; 791 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 792 if (!CE) return false; 793 int64_t Value = CE->getValue(); 794 return Value >= 0 && Value <= 16; 795 } 796 bool isFBits32() const { 797 if (!isImm()) return false; 798 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 799 if (!CE) return false; 800 int64_t Value = CE->getValue(); 801 return Value >= 1 && Value <= 32; 802 } 803 bool isImm8s4() const { 804 if (!isImm()) return false; 805 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 806 if (!CE) return false; 807 int64_t Value = CE->getValue(); 808 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 809 } 810 bool isImm0_1020s4() const { 811 if (!isImm()) return false; 812 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 813 if (!CE) return false; 814 int64_t Value = CE->getValue(); 815 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 816 } 817 bool isImm0_508s4() const { 818 if (!isImm()) return false; 819 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 820 if (!CE) return false; 821 int64_t Value = CE->getValue(); 822 return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 823 } 824 bool isImm0_508s4Neg() const { 825 if (!isImm()) return false; 826 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 827 if (!CE) return false; 828 int64_t Value = -CE->getValue(); 829 // explicitly exclude zero. we want that to use the normal 0_508 version. 830 return ((Value & 3) == 0) && Value > 0 && Value <= 508; 831 } 832 bool isImm0_239() const { 833 if (!isImm()) return false; 834 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 835 if (!CE) return false; 836 int64_t Value = CE->getValue(); 837 return Value >= 0 && Value < 240; 838 } 839 bool isImm0_255() const { 840 if (!isImm()) return false; 841 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 842 if (!CE) return false; 843 int64_t Value = CE->getValue(); 844 return Value >= 0 && Value < 256; 845 } 846 bool isImm0_4095() const { 847 if (!isImm()) return false; 848 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 849 if (!CE) return false; 850 int64_t Value = CE->getValue(); 851 return Value >= 0 && Value < 4096; 852 } 853 bool isImm0_4095Neg() const { 854 if (!isImm()) return false; 855 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 856 if (!CE) return false; 857 int64_t Value = -CE->getValue(); 858 return Value > 0 && Value < 4096; 859 } 860 bool isImm0_1() const { 861 if (!isImm()) return false; 862 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 863 if (!CE) return false; 864 int64_t Value = CE->getValue(); 865 return Value >= 0 && Value < 2; 866 } 867 bool isImm0_3() const { 868 if (!isImm()) return false; 869 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 870 if (!CE) return false; 871 int64_t Value = CE->getValue(); 872 return Value >= 0 && Value < 4; 873 } 874 bool isImm0_7() const { 875 if (!isImm()) return false; 876 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 877 if (!CE) return false; 878 int64_t Value = CE->getValue(); 879 return Value >= 0 && Value < 8; 880 } 881 bool isImm0_15() const { 882 if (!isImm()) return false; 883 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 884 if (!CE) return false; 885 int64_t Value = CE->getValue(); 886 return Value >= 0 && Value < 16; 887 } 888 bool isImm0_31() const { 889 if (!isImm()) return false; 890 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 891 if (!CE) return false; 892 int64_t Value = CE->getValue(); 893 return Value >= 0 && Value < 32; 894 } 895 bool isImm0_63() const { 896 if (!isImm()) return false; 897 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 898 if (!CE) return false; 899 int64_t Value = CE->getValue(); 900 return Value >= 0 && Value < 64; 901 } 902 bool isImm8() const { 903 if (!isImm()) return false; 904 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 905 if (!CE) return false; 906 int64_t Value = CE->getValue(); 907 return Value == 8; 908 } 909 bool isImm16() const { 910 if (!isImm()) return false; 911 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 912 if (!CE) return false; 913 int64_t Value = CE->getValue(); 914 return Value == 16; 915 } 916 bool isImm32() const { 917 if (!isImm()) return false; 918 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 919 if (!CE) return false; 920 int64_t Value = CE->getValue(); 921 return Value == 32; 922 } 923 bool isShrImm8() const { 924 if (!isImm()) return false; 925 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 926 if (!CE) return false; 927 int64_t Value = CE->getValue(); 928 return Value > 0 && Value <= 8; 929 } 930 bool isShrImm16() const { 931 if (!isImm()) return false; 932 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 933 if (!CE) return false; 934 int64_t Value = CE->getValue(); 935 return Value > 0 && Value <= 16; 936 } 937 bool isShrImm32() const { 938 if (!isImm()) return false; 939 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 940 if (!CE) return false; 941 int64_t Value = CE->getValue(); 942 return Value > 0 && Value <= 32; 943 } 944 bool isShrImm64() const { 945 if (!isImm()) return false; 946 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 947 if (!CE) return false; 948 int64_t Value = CE->getValue(); 949 return Value > 0 && Value <= 64; 950 } 951 bool isImm1_7() const { 952 if (!isImm()) return false; 953 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 954 if (!CE) return false; 955 int64_t Value = CE->getValue(); 956 return Value > 0 && Value < 8; 957 } 958 bool isImm1_15() const { 959 if (!isImm()) return false; 960 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 961 if (!CE) return false; 962 int64_t Value = CE->getValue(); 963 return Value > 0 && Value < 16; 964 } 965 bool isImm1_31() const { 966 if (!isImm()) return false; 967 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 968 if (!CE) return false; 969 int64_t Value = CE->getValue(); 970 return Value > 0 && Value < 32; 971 } 972 bool isImm1_16() const { 973 if (!isImm()) return false; 974 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 975 if (!CE) return false; 976 int64_t Value = CE->getValue(); 977 return Value > 0 && Value < 17; 978 } 979 bool isImm1_32() const { 980 if (!isImm()) return false; 981 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 982 if (!CE) return false; 983 int64_t Value = CE->getValue(); 984 return Value > 0 && Value < 33; 985 } 986 bool isImm0_32() const { 987 if (!isImm()) return false; 988 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 989 if (!CE) return false; 990 int64_t Value = CE->getValue(); 991 return Value >= 0 && Value < 33; 992 } 993 bool isImm0_65535() const { 994 if (!isImm()) return false; 995 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 996 if (!CE) return false; 997 int64_t Value = CE->getValue(); 998 return Value >= 0 && Value < 65536; 999 } 1000 bool isImm256_65535Expr() const { 1001 if (!isImm()) return false; 1002 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1003 // If it's not a constant expression, it'll generate a fixup and be 1004 // handled later. 1005 if (!CE) return true; 1006 int64_t Value = CE->getValue(); 1007 return Value >= 256 && Value < 65536; 1008 } 1009 bool isImm0_65535Expr() const { 1010 if (!isImm()) return false; 1011 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1012 // If it's not a constant expression, it'll generate a fixup and be 1013 // handled later. 1014 if (!CE) return true; 1015 int64_t Value = CE->getValue(); 1016 return Value >= 0 && Value < 65536; 1017 } 1018 bool isImm24bit() const { 1019 if (!isImm()) return false; 1020 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1021 if (!CE) return false; 1022 int64_t Value = CE->getValue(); 1023 return Value >= 0 && Value <= 0xffffff; 1024 } 1025 bool isImmThumbSR() const { 1026 if (!isImm()) return false; 1027 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1028 if (!CE) return false; 1029 int64_t Value = CE->getValue(); 1030 return Value > 0 && Value < 33; 1031 } 1032 bool isPKHLSLImm() const { 1033 if (!isImm()) return false; 1034 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1035 if (!CE) return false; 1036 int64_t Value = CE->getValue(); 1037 return Value >= 0 && Value < 32; 1038 } 1039 bool isPKHASRImm() const { 1040 if (!isImm()) return false; 1041 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1042 if (!CE) return false; 1043 int64_t Value = CE->getValue(); 1044 return Value > 0 && Value <= 32; 1045 } 1046 bool isAdrLabel() const { 1047 // If we have an immediate that's not a constant, treat it as a label 1048 // reference needing a fixup. 1049 if (isImm() && !isa<MCConstantExpr>(getImm())) 1050 return true; 1051 1052 // If it is a constant, it must fit into a modified immediate encoding. 1053 if (!isImm()) return false; 1054 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1055 if (!CE) return false; 1056 int64_t Value = CE->getValue(); 1057 return (ARM_AM::getSOImmVal(Value) != -1 || 1058 ARM_AM::getSOImmVal(-Value) != -1); 1059 } 1060 bool isT2SOImm() const { 1061 if (!isImm()) return false; 1062 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1063 if (!CE) return false; 1064 int64_t Value = CE->getValue(); 1065 return ARM_AM::getT2SOImmVal(Value) != -1; 1066 } 1067 bool isT2SOImmNot() const { 1068 if (!isImm()) return false; 1069 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1070 if (!CE) return false; 1071 int64_t Value = CE->getValue(); 1072 return ARM_AM::getT2SOImmVal(Value) == -1 && 1073 ARM_AM::getT2SOImmVal(~Value) != -1; 1074 } 1075 bool isT2SOImmNeg() const { 1076 if (!isImm()) return false; 1077 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1078 if (!CE) return false; 1079 int64_t Value = CE->getValue(); 1080 // Only use this when not representable as a plain so_imm. 1081 return ARM_AM::getT2SOImmVal(Value) == -1 && 1082 ARM_AM::getT2SOImmVal(-Value) != -1; 1083 } 1084 bool isSetEndImm() const { 1085 if (!isImm()) return false; 1086 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1087 if (!CE) return false; 1088 int64_t Value = CE->getValue(); 1089 return Value == 1 || Value == 0; 1090 } 1091 bool isReg() const override { return Kind == k_Register; } 1092 bool isRegList() const { return Kind == k_RegisterList; } 1093 bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 1094 bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 1095 bool isToken() const override { return Kind == k_Token; } 1096 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 1097 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; } 1098 bool isMem() const override { return Kind == k_Memory; } 1099 bool isShifterImm() const { return Kind == k_ShifterImmediate; } 1100 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } 1101 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } 1102 bool isRotImm() const { return Kind == k_RotateImmediate; } 1103 bool isModImm() const { return Kind == k_ModifiedImmediate; } 1104 bool isModImmNot() const { 1105 if (!isImm()) return false; 1106 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1107 if (!CE) return false; 1108 int64_t Value = CE->getValue(); 1109 return ARM_AM::getSOImmVal(~Value) != -1; 1110 } 1111 bool isModImmNeg() const { 1112 if (!isImm()) return false; 1113 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1114 if (!CE) return false; 1115 int64_t Value = CE->getValue(); 1116 return ARM_AM::getSOImmVal(Value) == -1 && 1117 ARM_AM::getSOImmVal(-Value) != -1; 1118 } 1119 bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 1120 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } 1121 bool isPostIdxReg() const { 1122 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; 1123 } 1124 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const { 1125 if (!isMem()) 1126 return false; 1127 // No offset of any kind. 1128 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && 1129 (alignOK || Memory.Alignment == Alignment); 1130 } 1131 bool isMemPCRelImm12() const { 1132 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1133 return false; 1134 // Base register must be PC. 1135 if (Memory.BaseRegNum != ARM::PC) 1136 return false; 1137 // Immediate offset in range [-4095, 4095]. 1138 if (!Memory.OffsetImm) return true; 1139 int64_t Val = Memory.OffsetImm->getValue(); 1140 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1141 } 1142 bool isAlignedMemory() const { 1143 return isMemNoOffset(true); 1144 } 1145 bool isAlignedMemoryNone() const { 1146 return isMemNoOffset(false, 0); 1147 } 1148 bool isDupAlignedMemoryNone() const { 1149 return isMemNoOffset(false, 0); 1150 } 1151 bool isAlignedMemory16() const { 1152 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2. 1153 return true; 1154 return isMemNoOffset(false, 0); 1155 } 1156 bool isDupAlignedMemory16() const { 1157 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2. 1158 return true; 1159 return isMemNoOffset(false, 0); 1160 } 1161 bool isAlignedMemory32() const { 1162 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4. 1163 return true; 1164 return isMemNoOffset(false, 0); 1165 } 1166 bool isDupAlignedMemory32() const { 1167 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4. 1168 return true; 1169 return isMemNoOffset(false, 0); 1170 } 1171 bool isAlignedMemory64() const { 1172 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1173 return true; 1174 return isMemNoOffset(false, 0); 1175 } 1176 bool isDupAlignedMemory64() const { 1177 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1178 return true; 1179 return isMemNoOffset(false, 0); 1180 } 1181 bool isAlignedMemory64or128() const { 1182 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1183 return true; 1184 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. 1185 return true; 1186 return isMemNoOffset(false, 0); 1187 } 1188 bool isDupAlignedMemory64or128() const { 1189 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1190 return true; 1191 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. 1192 return true; 1193 return isMemNoOffset(false, 0); 1194 } 1195 bool isAlignedMemory64or128or256() const { 1196 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1197 return true; 1198 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. 1199 return true; 1200 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32. 1201 return true; 1202 return isMemNoOffset(false, 0); 1203 } 1204 bool isAddrMode2() const { 1205 if (!isMem() || Memory.Alignment != 0) return false; 1206 // Check for register offset. 1207 if (Memory.OffsetRegNum) return true; 1208 // Immediate offset in range [-4095, 4095]. 1209 if (!Memory.OffsetImm) return true; 1210 int64_t Val = Memory.OffsetImm->getValue(); 1211 return Val > -4096 && Val < 4096; 1212 } 1213 bool isAM2OffsetImm() const { 1214 if (!isImm()) return false; 1215 // Immediate offset in range [-4095, 4095]. 1216 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1217 if (!CE) return false; 1218 int64_t Val = CE->getValue(); 1219 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096); 1220 } 1221 bool isAddrMode3() const { 1222 // If we have an immediate that's not a constant, treat it as a label 1223 // reference needing a fixup. If it is a constant, it's something else 1224 // and we reject it. 1225 if (isImm() && !isa<MCConstantExpr>(getImm())) 1226 return true; 1227 if (!isMem() || Memory.Alignment != 0) return false; 1228 // No shifts are legal for AM3. 1229 if (Memory.ShiftType != ARM_AM::no_shift) return false; 1230 // Check for register offset. 1231 if (Memory.OffsetRegNum) return true; 1232 // Immediate offset in range [-255, 255]. 1233 if (!Memory.OffsetImm) return true; 1234 int64_t Val = Memory.OffsetImm->getValue(); 1235 // The #-0 offset is encoded as INT32_MIN, and we have to check 1236 // for this too. 1237 return (Val > -256 && Val < 256) || Val == INT32_MIN; 1238 } 1239 bool isAM3Offset() const { 1240 if (Kind != k_Immediate && Kind != k_PostIndexRegister) 1241 return false; 1242 if (Kind == k_PostIndexRegister) 1243 return PostIdxReg.ShiftTy == ARM_AM::no_shift; 1244 // Immediate offset in range [-255, 255]. 1245 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1246 if (!CE) return false; 1247 int64_t Val = CE->getValue(); 1248 // Special case, #-0 is INT32_MIN. 1249 return (Val > -256 && Val < 256) || Val == INT32_MIN; 1250 } 1251 bool isAddrMode5() const { 1252 // If we have an immediate that's not a constant, treat it as a label 1253 // reference needing a fixup. If it is a constant, it's something else 1254 // and we reject it. 1255 if (isImm() && !isa<MCConstantExpr>(getImm())) 1256 return true; 1257 if (!isMem() || Memory.Alignment != 0) return false; 1258 // Check for register offset. 1259 if (Memory.OffsetRegNum) return false; 1260 // Immediate offset in range [-1020, 1020] and a multiple of 4. 1261 if (!Memory.OffsetImm) return true; 1262 int64_t Val = Memory.OffsetImm->getValue(); 1263 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 1264 Val == INT32_MIN; 1265 } 1266 bool isMemTBB() const { 1267 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1268 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1269 return false; 1270 return true; 1271 } 1272 bool isMemTBH() const { 1273 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1274 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 1275 Memory.Alignment != 0 ) 1276 return false; 1277 return true; 1278 } 1279 bool isMemRegOffset() const { 1280 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0) 1281 return false; 1282 return true; 1283 } 1284 bool isT2MemRegOffset() const { 1285 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1286 Memory.Alignment != 0) 1287 return false; 1288 // Only lsl #{0, 1, 2, 3} allowed. 1289 if (Memory.ShiftType == ARM_AM::no_shift) 1290 return true; 1291 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 1292 return false; 1293 return true; 1294 } 1295 bool isMemThumbRR() const { 1296 // Thumb reg+reg addressing is simple. Just two registers, a base and 1297 // an offset. No shifts, negations or any other complicating factors. 1298 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1299 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1300 return false; 1301 return isARMLowRegister(Memory.BaseRegNum) && 1302 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 1303 } 1304 bool isMemThumbRIs4() const { 1305 if (!isMem() || Memory.OffsetRegNum != 0 || 1306 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1307 return false; 1308 // Immediate offset, multiple of 4 in range [0, 124]. 1309 if (!Memory.OffsetImm) return true; 1310 int64_t Val = Memory.OffsetImm->getValue(); 1311 return Val >= 0 && Val <= 124 && (Val % 4) == 0; 1312 } 1313 bool isMemThumbRIs2() const { 1314 if (!isMem() || Memory.OffsetRegNum != 0 || 1315 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1316 return false; 1317 // Immediate offset, multiple of 4 in range [0, 62]. 1318 if (!Memory.OffsetImm) return true; 1319 int64_t Val = Memory.OffsetImm->getValue(); 1320 return Val >= 0 && Val <= 62 && (Val % 2) == 0; 1321 } 1322 bool isMemThumbRIs1() const { 1323 if (!isMem() || Memory.OffsetRegNum != 0 || 1324 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1325 return false; 1326 // Immediate offset in range [0, 31]. 1327 if (!Memory.OffsetImm) return true; 1328 int64_t Val = Memory.OffsetImm->getValue(); 1329 return Val >= 0 && Val <= 31; 1330 } 1331 bool isMemThumbSPI() const { 1332 if (!isMem() || Memory.OffsetRegNum != 0 || 1333 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 1334 return false; 1335 // Immediate offset, multiple of 4 in range [0, 1020]. 1336 if (!Memory.OffsetImm) return true; 1337 int64_t Val = Memory.OffsetImm->getValue(); 1338 return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 1339 } 1340 bool isMemImm8s4Offset() const { 1341 // If we have an immediate that's not a constant, treat it as a label 1342 // reference needing a fixup. If it is a constant, it's something else 1343 // and we reject it. 1344 if (isImm() && !isa<MCConstantExpr>(getImm())) 1345 return true; 1346 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1347 return false; 1348 // Immediate offset a multiple of 4 in range [-1020, 1020]. 1349 if (!Memory.OffsetImm) return true; 1350 int64_t Val = Memory.OffsetImm->getValue(); 1351 // Special case, #-0 is INT32_MIN. 1352 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN; 1353 } 1354 bool isMemImm0_1020s4Offset() const { 1355 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1356 return false; 1357 // Immediate offset a multiple of 4 in range [0, 1020]. 1358 if (!Memory.OffsetImm) return true; 1359 int64_t Val = Memory.OffsetImm->getValue(); 1360 return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 1361 } 1362 bool isMemImm8Offset() const { 1363 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1364 return false; 1365 // Base reg of PC isn't allowed for these encodings. 1366 if (Memory.BaseRegNum == ARM::PC) return false; 1367 // Immediate offset in range [-255, 255]. 1368 if (!Memory.OffsetImm) return true; 1369 int64_t Val = Memory.OffsetImm->getValue(); 1370 return (Val == INT32_MIN) || (Val > -256 && Val < 256); 1371 } 1372 bool isMemPosImm8Offset() const { 1373 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1374 return false; 1375 // Immediate offset in range [0, 255]. 1376 if (!Memory.OffsetImm) return true; 1377 int64_t Val = Memory.OffsetImm->getValue(); 1378 return Val >= 0 && Val < 256; 1379 } 1380 bool isMemNegImm8Offset() const { 1381 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1382 return false; 1383 // Base reg of PC isn't allowed for these encodings. 1384 if (Memory.BaseRegNum == ARM::PC) return false; 1385 // Immediate offset in range [-255, -1]. 1386 if (!Memory.OffsetImm) return false; 1387 int64_t Val = Memory.OffsetImm->getValue(); 1388 return (Val == INT32_MIN) || (Val > -256 && Val < 0); 1389 } 1390 bool isMemUImm12Offset() const { 1391 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1392 return false; 1393 // Immediate offset in range [0, 4095]. 1394 if (!Memory.OffsetImm) return true; 1395 int64_t Val = Memory.OffsetImm->getValue(); 1396 return (Val >= 0 && Val < 4096); 1397 } 1398 bool isMemImm12Offset() const { 1399 // If we have an immediate that's not a constant, treat it as a label 1400 // reference needing a fixup. If it is a constant, it's something else 1401 // and we reject it. 1402 if (isImm() && !isa<MCConstantExpr>(getImm())) 1403 return true; 1404 1405 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1406 return false; 1407 // Immediate offset in range [-4095, 4095]. 1408 if (!Memory.OffsetImm) return true; 1409 int64_t Val = Memory.OffsetImm->getValue(); 1410 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1411 } 1412 bool isPostIdxImm8() const { 1413 if (!isImm()) return false; 1414 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1415 if (!CE) return false; 1416 int64_t Val = CE->getValue(); 1417 return (Val > -256 && Val < 256) || (Val == INT32_MIN); 1418 } 1419 bool isPostIdxImm8s4() const { 1420 if (!isImm()) return false; 1421 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1422 if (!CE) return false; 1423 int64_t Val = CE->getValue(); 1424 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 1425 (Val == INT32_MIN); 1426 } 1427 1428 bool isMSRMask() const { return Kind == k_MSRMask; } 1429 bool isBankedReg() const { return Kind == k_BankedReg; } 1430 bool isProcIFlags() const { return Kind == k_ProcIFlags; } 1431 1432 // NEON operands. 1433 bool isSingleSpacedVectorList() const { 1434 return Kind == k_VectorList && !VectorList.isDoubleSpaced; 1435 } 1436 bool isDoubleSpacedVectorList() const { 1437 return Kind == k_VectorList && VectorList.isDoubleSpaced; 1438 } 1439 bool isVecListOneD() const { 1440 if (!isSingleSpacedVectorList()) return false; 1441 return VectorList.Count == 1; 1442 } 1443 1444 bool isVecListDPair() const { 1445 if (!isSingleSpacedVectorList()) return false; 1446 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1447 .contains(VectorList.RegNum)); 1448 } 1449 1450 bool isVecListThreeD() const { 1451 if (!isSingleSpacedVectorList()) return false; 1452 return VectorList.Count == 3; 1453 } 1454 1455 bool isVecListFourD() const { 1456 if (!isSingleSpacedVectorList()) return false; 1457 return VectorList.Count == 4; 1458 } 1459 1460 bool isVecListDPairSpaced() const { 1461 if (Kind != k_VectorList) return false; 1462 if (isSingleSpacedVectorList()) return false; 1463 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] 1464 .contains(VectorList.RegNum)); 1465 } 1466 1467 bool isVecListThreeQ() const { 1468 if (!isDoubleSpacedVectorList()) return false; 1469 return VectorList.Count == 3; 1470 } 1471 1472 bool isVecListFourQ() const { 1473 if (!isDoubleSpacedVectorList()) return false; 1474 return VectorList.Count == 4; 1475 } 1476 1477 bool isSingleSpacedVectorAllLanes() const { 1478 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; 1479 } 1480 bool isDoubleSpacedVectorAllLanes() const { 1481 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; 1482 } 1483 bool isVecListOneDAllLanes() const { 1484 if (!isSingleSpacedVectorAllLanes()) return false; 1485 return VectorList.Count == 1; 1486 } 1487 1488 bool isVecListDPairAllLanes() const { 1489 if (!isSingleSpacedVectorAllLanes()) return false; 1490 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1491 .contains(VectorList.RegNum)); 1492 } 1493 1494 bool isVecListDPairSpacedAllLanes() const { 1495 if (!isDoubleSpacedVectorAllLanes()) return false; 1496 return VectorList.Count == 2; 1497 } 1498 1499 bool isVecListThreeDAllLanes() const { 1500 if (!isSingleSpacedVectorAllLanes()) return false; 1501 return VectorList.Count == 3; 1502 } 1503 1504 bool isVecListThreeQAllLanes() const { 1505 if (!isDoubleSpacedVectorAllLanes()) return false; 1506 return VectorList.Count == 3; 1507 } 1508 1509 bool isVecListFourDAllLanes() const { 1510 if (!isSingleSpacedVectorAllLanes()) return false; 1511 return VectorList.Count == 4; 1512 } 1513 1514 bool isVecListFourQAllLanes() const { 1515 if (!isDoubleSpacedVectorAllLanes()) return false; 1516 return VectorList.Count == 4; 1517 } 1518 1519 bool isSingleSpacedVectorIndexed() const { 1520 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; 1521 } 1522 bool isDoubleSpacedVectorIndexed() const { 1523 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; 1524 } 1525 bool isVecListOneDByteIndexed() const { 1526 if (!isSingleSpacedVectorIndexed()) return false; 1527 return VectorList.Count == 1 && VectorList.LaneIndex <= 7; 1528 } 1529 1530 bool isVecListOneDHWordIndexed() const { 1531 if (!isSingleSpacedVectorIndexed()) return false; 1532 return VectorList.Count == 1 && VectorList.LaneIndex <= 3; 1533 } 1534 1535 bool isVecListOneDWordIndexed() const { 1536 if (!isSingleSpacedVectorIndexed()) return false; 1537 return VectorList.Count == 1 && VectorList.LaneIndex <= 1; 1538 } 1539 1540 bool isVecListTwoDByteIndexed() const { 1541 if (!isSingleSpacedVectorIndexed()) return false; 1542 return VectorList.Count == 2 && VectorList.LaneIndex <= 7; 1543 } 1544 1545 bool isVecListTwoDHWordIndexed() const { 1546 if (!isSingleSpacedVectorIndexed()) return false; 1547 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1548 } 1549 1550 bool isVecListTwoQWordIndexed() const { 1551 if (!isDoubleSpacedVectorIndexed()) return false; 1552 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1553 } 1554 1555 bool isVecListTwoQHWordIndexed() const { 1556 if (!isDoubleSpacedVectorIndexed()) return false; 1557 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1558 } 1559 1560 bool isVecListTwoDWordIndexed() const { 1561 if (!isSingleSpacedVectorIndexed()) return false; 1562 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1563 } 1564 1565 bool isVecListThreeDByteIndexed() const { 1566 if (!isSingleSpacedVectorIndexed()) return false; 1567 return VectorList.Count == 3 && VectorList.LaneIndex <= 7; 1568 } 1569 1570 bool isVecListThreeDHWordIndexed() const { 1571 if (!isSingleSpacedVectorIndexed()) return false; 1572 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1573 } 1574 1575 bool isVecListThreeQWordIndexed() const { 1576 if (!isDoubleSpacedVectorIndexed()) return false; 1577 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1578 } 1579 1580 bool isVecListThreeQHWordIndexed() const { 1581 if (!isDoubleSpacedVectorIndexed()) return false; 1582 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1583 } 1584 1585 bool isVecListThreeDWordIndexed() const { 1586 if (!isSingleSpacedVectorIndexed()) return false; 1587 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1588 } 1589 1590 bool isVecListFourDByteIndexed() const { 1591 if (!isSingleSpacedVectorIndexed()) return false; 1592 return VectorList.Count == 4 && VectorList.LaneIndex <= 7; 1593 } 1594 1595 bool isVecListFourDHWordIndexed() const { 1596 if (!isSingleSpacedVectorIndexed()) return false; 1597 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1598 } 1599 1600 bool isVecListFourQWordIndexed() const { 1601 if (!isDoubleSpacedVectorIndexed()) return false; 1602 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1603 } 1604 1605 bool isVecListFourQHWordIndexed() const { 1606 if (!isDoubleSpacedVectorIndexed()) return false; 1607 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1608 } 1609 1610 bool isVecListFourDWordIndexed() const { 1611 if (!isSingleSpacedVectorIndexed()) return false; 1612 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1613 } 1614 1615 bool isVectorIndex8() const { 1616 if (Kind != k_VectorIndex) return false; 1617 return VectorIndex.Val < 8; 1618 } 1619 bool isVectorIndex16() const { 1620 if (Kind != k_VectorIndex) return false; 1621 return VectorIndex.Val < 4; 1622 } 1623 bool isVectorIndex32() const { 1624 if (Kind != k_VectorIndex) return false; 1625 return VectorIndex.Val < 2; 1626 } 1627 1628 bool isNEONi8splat() const { 1629 if (!isImm()) return false; 1630 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1631 // Must be a constant. 1632 if (!CE) return false; 1633 int64_t Value = CE->getValue(); 1634 // i8 value splatted across 8 bytes. The immediate is just the 8 byte 1635 // value. 1636 return Value >= 0 && Value < 256; 1637 } 1638 1639 bool isNEONi16splat() const { 1640 if (isNEONByteReplicate(2)) 1641 return false; // Leave that for bytes replication and forbid by default. 1642 if (!isImm()) 1643 return false; 1644 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1645 // Must be a constant. 1646 if (!CE) return false; 1647 unsigned Value = CE->getValue(); 1648 return ARM_AM::isNEONi16splat(Value); 1649 } 1650 1651 bool isNEONi16splatNot() const { 1652 if (!isImm()) 1653 return false; 1654 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1655 // Must be a constant. 1656 if (!CE) return false; 1657 unsigned Value = CE->getValue(); 1658 return ARM_AM::isNEONi16splat(~Value & 0xffff); 1659 } 1660 1661 bool isNEONi32splat() const { 1662 if (isNEONByteReplicate(4)) 1663 return false; // Leave that for bytes replication and forbid by default. 1664 if (!isImm()) 1665 return false; 1666 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1667 // Must be a constant. 1668 if (!CE) return false; 1669 unsigned Value = CE->getValue(); 1670 return ARM_AM::isNEONi32splat(Value); 1671 } 1672 1673 bool isNEONi32splatNot() const { 1674 if (!isImm()) 1675 return false; 1676 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1677 // Must be a constant. 1678 if (!CE) return false; 1679 unsigned Value = CE->getValue(); 1680 return ARM_AM::isNEONi32splat(~Value); 1681 } 1682 1683 bool isNEONByteReplicate(unsigned NumBytes) const { 1684 if (!isImm()) 1685 return false; 1686 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1687 // Must be a constant. 1688 if (!CE) 1689 return false; 1690 int64_t Value = CE->getValue(); 1691 if (!Value) 1692 return false; // Don't bother with zero. 1693 1694 unsigned char B = Value & 0xff; 1695 for (unsigned i = 1; i < NumBytes; ++i) { 1696 Value >>= 8; 1697 if ((Value & 0xff) != B) 1698 return false; 1699 } 1700 return true; 1701 } 1702 bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); } 1703 bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); } 1704 bool isNEONi32vmov() const { 1705 if (isNEONByteReplicate(4)) 1706 return false; // Let it to be classified as byte-replicate case. 1707 if (!isImm()) 1708 return false; 1709 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1710 // Must be a constant. 1711 if (!CE) 1712 return false; 1713 int64_t Value = CE->getValue(); 1714 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1715 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1716 // FIXME: This is probably wrong and a copy and paste from previous example 1717 return (Value >= 0 && Value < 256) || 1718 (Value >= 0x0100 && Value <= 0xff00) || 1719 (Value >= 0x010000 && Value <= 0xff0000) || 1720 (Value >= 0x01000000 && Value <= 0xff000000) || 1721 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1722 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1723 } 1724 bool isNEONi32vmovNeg() const { 1725 if (!isImm()) return false; 1726 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1727 // Must be a constant. 1728 if (!CE) return false; 1729 int64_t Value = ~CE->getValue(); 1730 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1731 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1732 // FIXME: This is probably wrong and a copy and paste from previous example 1733 return (Value >= 0 && Value < 256) || 1734 (Value >= 0x0100 && Value <= 0xff00) || 1735 (Value >= 0x010000 && Value <= 0xff0000) || 1736 (Value >= 0x01000000 && Value <= 0xff000000) || 1737 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1738 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1739 } 1740 1741 bool isNEONi64splat() const { 1742 if (!isImm()) return false; 1743 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1744 // Must be a constant. 1745 if (!CE) return false; 1746 uint64_t Value = CE->getValue(); 1747 // i64 value with each byte being either 0 or 0xff. 1748 for (unsigned i = 0; i < 8; ++i) 1749 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 1750 return true; 1751 } 1752 1753 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 1754 // Add as immediates when possible. Null MCExpr = 0. 1755 if (!Expr) 1756 Inst.addOperand(MCOperand::createImm(0)); 1757 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 1758 Inst.addOperand(MCOperand::createImm(CE->getValue())); 1759 else 1760 Inst.addOperand(MCOperand::createExpr(Expr)); 1761 } 1762 1763 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 1764 assert(N == 2 && "Invalid number of operands!"); 1765 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); 1766 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 1767 Inst.addOperand(MCOperand::createReg(RegNum)); 1768 } 1769 1770 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 1771 assert(N == 1 && "Invalid number of operands!"); 1772 Inst.addOperand(MCOperand::createImm(getCoproc())); 1773 } 1774 1775 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 1776 assert(N == 1 && "Invalid number of operands!"); 1777 Inst.addOperand(MCOperand::createImm(getCoproc())); 1778 } 1779 1780 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 1781 assert(N == 1 && "Invalid number of operands!"); 1782 Inst.addOperand(MCOperand::createImm(CoprocOption.Val)); 1783 } 1784 1785 void addITMaskOperands(MCInst &Inst, unsigned N) const { 1786 assert(N == 1 && "Invalid number of operands!"); 1787 Inst.addOperand(MCOperand::createImm(ITMask.Mask)); 1788 } 1789 1790 void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 1791 assert(N == 1 && "Invalid number of operands!"); 1792 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); 1793 } 1794 1795 void addCCOutOperands(MCInst &Inst, unsigned N) const { 1796 assert(N == 1 && "Invalid number of operands!"); 1797 Inst.addOperand(MCOperand::createReg(getReg())); 1798 } 1799 1800 void addRegOperands(MCInst &Inst, unsigned N) const { 1801 assert(N == 1 && "Invalid number of operands!"); 1802 Inst.addOperand(MCOperand::createReg(getReg())); 1803 } 1804 1805 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 1806 assert(N == 3 && "Invalid number of operands!"); 1807 assert(isRegShiftedReg() && 1808 "addRegShiftedRegOperands() on non-RegShiftedReg!"); 1809 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg)); 1810 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); 1811 Inst.addOperand(MCOperand::createImm( 1812 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1813 } 1814 1815 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 1816 assert(N == 2 && "Invalid number of operands!"); 1817 assert(isRegShiftedImm() && 1818 "addRegShiftedImmOperands() on non-RegShiftedImm!"); 1819 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg)); 1820 // Shift of #32 is encoded as 0 where permitted 1821 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); 1822 Inst.addOperand(MCOperand::createImm( 1823 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); 1824 } 1825 1826 void addShifterImmOperands(MCInst &Inst, unsigned N) const { 1827 assert(N == 1 && "Invalid number of operands!"); 1828 Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) | 1829 ShifterImm.Imm)); 1830 } 1831 1832 void addRegListOperands(MCInst &Inst, unsigned N) const { 1833 assert(N == 1 && "Invalid number of operands!"); 1834 const SmallVectorImpl<unsigned> &RegList = getRegList(); 1835 for (SmallVectorImpl<unsigned>::const_iterator 1836 I = RegList.begin(), E = RegList.end(); I != E; ++I) 1837 Inst.addOperand(MCOperand::createReg(*I)); 1838 } 1839 1840 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 1841 addRegListOperands(Inst, N); 1842 } 1843 1844 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 1845 addRegListOperands(Inst, N); 1846 } 1847 1848 void addRotImmOperands(MCInst &Inst, unsigned N) const { 1849 assert(N == 1 && "Invalid number of operands!"); 1850 // Encoded as val>>3. The printer handles display as 8, 16, 24. 1851 Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3)); 1852 } 1853 1854 void addModImmOperands(MCInst &Inst, unsigned N) const { 1855 assert(N == 1 && "Invalid number of operands!"); 1856 1857 // Support for fixups (MCFixup) 1858 if (isImm()) 1859 return addImmOperands(Inst, N); 1860 1861 Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7))); 1862 } 1863 1864 void addModImmNotOperands(MCInst &Inst, unsigned N) const { 1865 assert(N == 1 && "Invalid number of operands!"); 1866 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1867 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue()); 1868 Inst.addOperand(MCOperand::createImm(Enc)); 1869 } 1870 1871 void addModImmNegOperands(MCInst &Inst, unsigned N) const { 1872 assert(N == 1 && "Invalid number of operands!"); 1873 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1874 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue()); 1875 Inst.addOperand(MCOperand::createImm(Enc)); 1876 } 1877 1878 void addBitfieldOperands(MCInst &Inst, unsigned N) const { 1879 assert(N == 1 && "Invalid number of operands!"); 1880 // Munge the lsb/width into a bitfield mask. 1881 unsigned lsb = Bitfield.LSB; 1882 unsigned width = Bitfield.Width; 1883 // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 1884 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 1885 (32 - (lsb + width))); 1886 Inst.addOperand(MCOperand::createImm(Mask)); 1887 } 1888 1889 void addImmOperands(MCInst &Inst, unsigned N) const { 1890 assert(N == 1 && "Invalid number of operands!"); 1891 addExpr(Inst, getImm()); 1892 } 1893 1894 void addFBits16Operands(MCInst &Inst, unsigned N) const { 1895 assert(N == 1 && "Invalid number of operands!"); 1896 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1897 Inst.addOperand(MCOperand::createImm(16 - CE->getValue())); 1898 } 1899 1900 void addFBits32Operands(MCInst &Inst, unsigned N) const { 1901 assert(N == 1 && "Invalid number of operands!"); 1902 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1903 Inst.addOperand(MCOperand::createImm(32 - CE->getValue())); 1904 } 1905 1906 void addFPImmOperands(MCInst &Inst, unsigned N) const { 1907 assert(N == 1 && "Invalid number of operands!"); 1908 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1909 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 1910 Inst.addOperand(MCOperand::createImm(Val)); 1911 } 1912 1913 void addImm8s4Operands(MCInst &Inst, unsigned N) const { 1914 assert(N == 1 && "Invalid number of operands!"); 1915 // FIXME: We really want to scale the value here, but the LDRD/STRD 1916 // instruction don't encode operands that way yet. 1917 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1918 Inst.addOperand(MCOperand::createImm(CE->getValue())); 1919 } 1920 1921 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 1922 assert(N == 1 && "Invalid number of operands!"); 1923 // The immediate is scaled by four in the encoding and is stored 1924 // in the MCInst as such. Lop off the low two bits here. 1925 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1926 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4)); 1927 } 1928 1929 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { 1930 assert(N == 1 && "Invalid number of operands!"); 1931 // The immediate is scaled by four in the encoding and is stored 1932 // in the MCInst as such. Lop off the low two bits here. 1933 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1934 Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4))); 1935 } 1936 1937 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 1938 assert(N == 1 && "Invalid number of operands!"); 1939 // The immediate is scaled by four in the encoding and is stored 1940 // in the MCInst as such. Lop off the low two bits here. 1941 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1942 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4)); 1943 } 1944 1945 void addImm1_16Operands(MCInst &Inst, unsigned N) const { 1946 assert(N == 1 && "Invalid number of operands!"); 1947 // The constant encodes as the immediate-1, and we store in the instruction 1948 // the bits as encoded, so subtract off one here. 1949 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1950 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1)); 1951 } 1952 1953 void addImm1_32Operands(MCInst &Inst, unsigned N) const { 1954 assert(N == 1 && "Invalid number of operands!"); 1955 // The constant encodes as the immediate-1, and we store in the instruction 1956 // the bits as encoded, so subtract off one here. 1957 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1958 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1)); 1959 } 1960 1961 void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 1962 assert(N == 1 && "Invalid number of operands!"); 1963 // The constant encodes as the immediate, except for 32, which encodes as 1964 // zero. 1965 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1966 unsigned Imm = CE->getValue(); 1967 Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm))); 1968 } 1969 1970 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1971 assert(N == 1 && "Invalid number of operands!"); 1972 // An ASR value of 32 encodes as 0, so that's how we want to add it to 1973 // the instruction as well. 1974 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1975 int Val = CE->getValue(); 1976 Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val)); 1977 } 1978 1979 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 1980 assert(N == 1 && "Invalid number of operands!"); 1981 // The operand is actually a t2_so_imm, but we have its bitwise 1982 // negation in the assembly source, so twiddle it here. 1983 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1984 Inst.addOperand(MCOperand::createImm(~CE->getValue())); 1985 } 1986 1987 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { 1988 assert(N == 1 && "Invalid number of operands!"); 1989 // The operand is actually a t2_so_imm, but we have its 1990 // negation in the assembly source, so twiddle it here. 1991 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1992 Inst.addOperand(MCOperand::createImm(-CE->getValue())); 1993 } 1994 1995 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { 1996 assert(N == 1 && "Invalid number of operands!"); 1997 // The operand is actually an imm0_4095, but we have its 1998 // negation in the assembly source, so twiddle it here. 1999 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2000 Inst.addOperand(MCOperand::createImm(-CE->getValue())); 2001 } 2002 2003 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const { 2004 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) { 2005 Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2)); 2006 return; 2007 } 2008 2009 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val); 2010 assert(SR && "Unknown value type!"); 2011 Inst.addOperand(MCOperand::createExpr(SR)); 2012 } 2013 2014 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const { 2015 assert(N == 1 && "Invalid number of operands!"); 2016 if (isImm()) { 2017 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2018 if (CE) { 2019 Inst.addOperand(MCOperand::createImm(CE->getValue())); 2020 return; 2021 } 2022 2023 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val); 2024 assert(SR && "Unknown value type!"); 2025 Inst.addOperand(MCOperand::createExpr(SR)); 2026 return; 2027 } 2028 2029 assert(isMem() && "Unknown value type!"); 2030 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!"); 2031 Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue())); 2032 } 2033 2034 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 2035 assert(N == 1 && "Invalid number of operands!"); 2036 Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt()))); 2037 } 2038 2039 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { 2040 assert(N == 1 && "Invalid number of operands!"); 2041 Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt()))); 2042 } 2043 2044 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 2045 assert(N == 1 && "Invalid number of operands!"); 2046 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2047 } 2048 2049 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { 2050 assert(N == 1 && "Invalid number of operands!"); 2051 int32_t Imm = Memory.OffsetImm->getValue(); 2052 Inst.addOperand(MCOperand::createImm(Imm)); 2053 } 2054 2055 void addAdrLabelOperands(MCInst &Inst, unsigned N) const { 2056 assert(N == 1 && "Invalid number of operands!"); 2057 assert(isImm() && "Not an immediate!"); 2058 2059 // If we have an immediate that's not a constant, treat it as a label 2060 // reference needing a fixup. 2061 if (!isa<MCConstantExpr>(getImm())) { 2062 Inst.addOperand(MCOperand::createExpr(getImm())); 2063 return; 2064 } 2065 2066 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2067 int Val = CE->getValue(); 2068 Inst.addOperand(MCOperand::createImm(Val)); 2069 } 2070 2071 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 2072 assert(N == 2 && "Invalid number of operands!"); 2073 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2074 Inst.addOperand(MCOperand::createImm(Memory.Alignment)); 2075 } 2076 2077 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const { 2078 addAlignedMemoryOperands(Inst, N); 2079 } 2080 2081 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const { 2082 addAlignedMemoryOperands(Inst, N); 2083 } 2084 2085 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const { 2086 addAlignedMemoryOperands(Inst, N); 2087 } 2088 2089 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const { 2090 addAlignedMemoryOperands(Inst, N); 2091 } 2092 2093 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const { 2094 addAlignedMemoryOperands(Inst, N); 2095 } 2096 2097 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const { 2098 addAlignedMemoryOperands(Inst, N); 2099 } 2100 2101 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const { 2102 addAlignedMemoryOperands(Inst, N); 2103 } 2104 2105 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const { 2106 addAlignedMemoryOperands(Inst, N); 2107 } 2108 2109 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const { 2110 addAlignedMemoryOperands(Inst, N); 2111 } 2112 2113 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const { 2114 addAlignedMemoryOperands(Inst, N); 2115 } 2116 2117 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const { 2118 addAlignedMemoryOperands(Inst, N); 2119 } 2120 2121 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 2122 assert(N == 3 && "Invalid number of operands!"); 2123 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2124 if (!Memory.OffsetRegNum) { 2125 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2126 // Special case for #-0 2127 if (Val == INT32_MIN) Val = 0; 2128 if (Val < 0) Val = -Val; 2129 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 2130 } else { 2131 // For register offset, we encode the shift type and negation flag 2132 // here. 2133 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 2134 Memory.ShiftImm, Memory.ShiftType); 2135 } 2136 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2137 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 2138 Inst.addOperand(MCOperand::createImm(Val)); 2139 } 2140 2141 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 2142 assert(N == 2 && "Invalid number of operands!"); 2143 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2144 assert(CE && "non-constant AM2OffsetImm operand!"); 2145 int32_t Val = CE->getValue(); 2146 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2147 // Special case for #-0 2148 if (Val == INT32_MIN) Val = 0; 2149 if (Val < 0) Val = -Val; 2150 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 2151 Inst.addOperand(MCOperand::createReg(0)); 2152 Inst.addOperand(MCOperand::createImm(Val)); 2153 } 2154 2155 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 2156 assert(N == 3 && "Invalid number of operands!"); 2157 // If we have an immediate that's not a constant, treat it as a label 2158 // reference needing a fixup. If it is a constant, it's something else 2159 // and we reject it. 2160 if (isImm()) { 2161 Inst.addOperand(MCOperand::createExpr(getImm())); 2162 Inst.addOperand(MCOperand::createReg(0)); 2163 Inst.addOperand(MCOperand::createImm(0)); 2164 return; 2165 } 2166 2167 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2168 if (!Memory.OffsetRegNum) { 2169 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2170 // Special case for #-0 2171 if (Val == INT32_MIN) Val = 0; 2172 if (Val < 0) Val = -Val; 2173 Val = ARM_AM::getAM3Opc(AddSub, Val); 2174 } else { 2175 // For register offset, we encode the shift type and negation flag 2176 // here. 2177 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 2178 } 2179 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2180 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 2181 Inst.addOperand(MCOperand::createImm(Val)); 2182 } 2183 2184 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 2185 assert(N == 2 && "Invalid number of operands!"); 2186 if (Kind == k_PostIndexRegister) { 2187 int32_t Val = 2188 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 2189 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); 2190 Inst.addOperand(MCOperand::createImm(Val)); 2191 return; 2192 } 2193 2194 // Constant offset. 2195 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 2196 int32_t Val = CE->getValue(); 2197 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2198 // Special case for #-0 2199 if (Val == INT32_MIN) Val = 0; 2200 if (Val < 0) Val = -Val; 2201 Val = ARM_AM::getAM3Opc(AddSub, Val); 2202 Inst.addOperand(MCOperand::createReg(0)); 2203 Inst.addOperand(MCOperand::createImm(Val)); 2204 } 2205 2206 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 2207 assert(N == 2 && "Invalid number of operands!"); 2208 // If we have an immediate that's not a constant, treat it as a label 2209 // reference needing a fixup. If it is a constant, it's something else 2210 // and we reject it. 2211 if (isImm()) { 2212 Inst.addOperand(MCOperand::createExpr(getImm())); 2213 Inst.addOperand(MCOperand::createImm(0)); 2214 return; 2215 } 2216 2217 // The lower two bits are always zero and as such are not encoded. 2218 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 2219 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2220 // Special case for #-0 2221 if (Val == INT32_MIN) Val = 0; 2222 if (Val < 0) Val = -Val; 2223 Val = ARM_AM::getAM5Opc(AddSub, Val); 2224 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2225 Inst.addOperand(MCOperand::createImm(Val)); 2226 } 2227 2228 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 2229 assert(N == 2 && "Invalid number of operands!"); 2230 // If we have an immediate that's not a constant, treat it as a label 2231 // reference needing a fixup. If it is a constant, it's something else 2232 // and we reject it. 2233 if (isImm()) { 2234 Inst.addOperand(MCOperand::createExpr(getImm())); 2235 Inst.addOperand(MCOperand::createImm(0)); 2236 return; 2237 } 2238 2239 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2240 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2241 Inst.addOperand(MCOperand::createImm(Val)); 2242 } 2243 2244 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 2245 assert(N == 2 && "Invalid number of operands!"); 2246 // The lower two bits are always zero and as such are not encoded. 2247 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 2248 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2249 Inst.addOperand(MCOperand::createImm(Val)); 2250 } 2251 2252 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 2253 assert(N == 2 && "Invalid number of operands!"); 2254 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2255 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2256 Inst.addOperand(MCOperand::createImm(Val)); 2257 } 2258 2259 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 2260 addMemImm8OffsetOperands(Inst, N); 2261 } 2262 2263 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 2264 addMemImm8OffsetOperands(Inst, N); 2265 } 2266 2267 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 2268 assert(N == 2 && "Invalid number of operands!"); 2269 // If this is an immediate, it's a label reference. 2270 if (isImm()) { 2271 addExpr(Inst, getImm()); 2272 Inst.addOperand(MCOperand::createImm(0)); 2273 return; 2274 } 2275 2276 // Otherwise, it's a normal memory reg+offset. 2277 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2278 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2279 Inst.addOperand(MCOperand::createImm(Val)); 2280 } 2281 2282 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 2283 assert(N == 2 && "Invalid number of operands!"); 2284 // If this is an immediate, it's a label reference. 2285 if (isImm()) { 2286 addExpr(Inst, getImm()); 2287 Inst.addOperand(MCOperand::createImm(0)); 2288 return; 2289 } 2290 2291 // Otherwise, it's a normal memory reg+offset. 2292 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2293 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2294 Inst.addOperand(MCOperand::createImm(Val)); 2295 } 2296 2297 void addMemTBBOperands(MCInst &Inst, unsigned N) const { 2298 assert(N == 2 && "Invalid number of operands!"); 2299 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2300 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 2301 } 2302 2303 void addMemTBHOperands(MCInst &Inst, unsigned N) const { 2304 assert(N == 2 && "Invalid number of operands!"); 2305 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2306 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 2307 } 2308 2309 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 2310 assert(N == 3 && "Invalid number of operands!"); 2311 unsigned Val = 2312 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 2313 Memory.ShiftImm, Memory.ShiftType); 2314 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2315 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 2316 Inst.addOperand(MCOperand::createImm(Val)); 2317 } 2318 2319 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 2320 assert(N == 3 && "Invalid number of operands!"); 2321 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2322 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 2323 Inst.addOperand(MCOperand::createImm(Memory.ShiftImm)); 2324 } 2325 2326 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 2327 assert(N == 2 && "Invalid number of operands!"); 2328 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2329 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); 2330 } 2331 2332 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 2333 assert(N == 2 && "Invalid number of operands!"); 2334 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 2335 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2336 Inst.addOperand(MCOperand::createImm(Val)); 2337 } 2338 2339 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 2340 assert(N == 2 && "Invalid number of operands!"); 2341 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 2342 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2343 Inst.addOperand(MCOperand::createImm(Val)); 2344 } 2345 2346 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 2347 assert(N == 2 && "Invalid number of operands!"); 2348 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 2349 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2350 Inst.addOperand(MCOperand::createImm(Val)); 2351 } 2352 2353 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 2354 assert(N == 2 && "Invalid number of operands!"); 2355 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 2356 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); 2357 Inst.addOperand(MCOperand::createImm(Val)); 2358 } 2359 2360 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 2361 assert(N == 1 && "Invalid number of operands!"); 2362 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2363 assert(CE && "non-constant post-idx-imm8 operand!"); 2364 int Imm = CE->getValue(); 2365 bool isAdd = Imm >= 0; 2366 if (Imm == INT32_MIN) Imm = 0; 2367 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 2368 Inst.addOperand(MCOperand::createImm(Imm)); 2369 } 2370 2371 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 2372 assert(N == 1 && "Invalid number of operands!"); 2373 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2374 assert(CE && "non-constant post-idx-imm8s4 operand!"); 2375 int Imm = CE->getValue(); 2376 bool isAdd = Imm >= 0; 2377 if (Imm == INT32_MIN) Imm = 0; 2378 // Immediate is scaled by 4. 2379 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 2380 Inst.addOperand(MCOperand::createImm(Imm)); 2381 } 2382 2383 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 2384 assert(N == 2 && "Invalid number of operands!"); 2385 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); 2386 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd)); 2387 } 2388 2389 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 2390 assert(N == 2 && "Invalid number of operands!"); 2391 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); 2392 // The sign, shift type, and shift amount are encoded in a single operand 2393 // using the AM2 encoding helpers. 2394 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 2395 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 2396 PostIdxReg.ShiftTy); 2397 Inst.addOperand(MCOperand::createImm(Imm)); 2398 } 2399 2400 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 2401 assert(N == 1 && "Invalid number of operands!"); 2402 Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask()))); 2403 } 2404 2405 void addBankedRegOperands(MCInst &Inst, unsigned N) const { 2406 assert(N == 1 && "Invalid number of operands!"); 2407 Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg()))); 2408 } 2409 2410 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 2411 assert(N == 1 && "Invalid number of operands!"); 2412 Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags()))); 2413 } 2414 2415 void addVecListOperands(MCInst &Inst, unsigned N) const { 2416 assert(N == 1 && "Invalid number of operands!"); 2417 Inst.addOperand(MCOperand::createReg(VectorList.RegNum)); 2418 } 2419 2420 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { 2421 assert(N == 2 && "Invalid number of operands!"); 2422 Inst.addOperand(MCOperand::createReg(VectorList.RegNum)); 2423 Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex)); 2424 } 2425 2426 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 2427 assert(N == 1 && "Invalid number of operands!"); 2428 Inst.addOperand(MCOperand::createImm(getVectorIndex())); 2429 } 2430 2431 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 2432 assert(N == 1 && "Invalid number of operands!"); 2433 Inst.addOperand(MCOperand::createImm(getVectorIndex())); 2434 } 2435 2436 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 2437 assert(N == 1 && "Invalid number of operands!"); 2438 Inst.addOperand(MCOperand::createImm(getVectorIndex())); 2439 } 2440 2441 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 2442 assert(N == 1 && "Invalid number of operands!"); 2443 // The immediate encodes the type of constant as well as the value. 2444 // Mask in that this is an i8 splat. 2445 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2446 Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00)); 2447 } 2448 2449 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 2450 assert(N == 1 && "Invalid number of operands!"); 2451 // The immediate encodes the type of constant as well as the value. 2452 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2453 unsigned Value = CE->getValue(); 2454 Value = ARM_AM::encodeNEONi16splat(Value); 2455 Inst.addOperand(MCOperand::createImm(Value)); 2456 } 2457 2458 void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const { 2459 assert(N == 1 && "Invalid number of operands!"); 2460 // The immediate encodes the type of constant as well as the value. 2461 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2462 unsigned Value = CE->getValue(); 2463 Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff); 2464 Inst.addOperand(MCOperand::createImm(Value)); 2465 } 2466 2467 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 2468 assert(N == 1 && "Invalid number of operands!"); 2469 // The immediate encodes the type of constant as well as the value. 2470 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2471 unsigned Value = CE->getValue(); 2472 Value = ARM_AM::encodeNEONi32splat(Value); 2473 Inst.addOperand(MCOperand::createImm(Value)); 2474 } 2475 2476 void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const { 2477 assert(N == 1 && "Invalid number of operands!"); 2478 // The immediate encodes the type of constant as well as the value. 2479 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2480 unsigned Value = CE->getValue(); 2481 Value = ARM_AM::encodeNEONi32splat(~Value); 2482 Inst.addOperand(MCOperand::createImm(Value)); 2483 } 2484 2485 void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const { 2486 assert(N == 1 && "Invalid number of operands!"); 2487 // The immediate encodes the type of constant as well as the value. 2488 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2489 unsigned Value = CE->getValue(); 2490 assert((Inst.getOpcode() == ARM::VMOVv8i8 || 2491 Inst.getOpcode() == ARM::VMOVv16i8) && 2492 "All vmvn instructions that wants to replicate non-zero byte " 2493 "always must be replaced with VMOVv8i8 or VMOVv16i8."); 2494 unsigned B = ((~Value) & 0xff); 2495 B |= 0xe00; // cmode = 0b1110 2496 Inst.addOperand(MCOperand::createImm(B)); 2497 } 2498 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 2499 assert(N == 1 && "Invalid number of operands!"); 2500 // The immediate encodes the type of constant as well as the value. 2501 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2502 unsigned Value = CE->getValue(); 2503 if (Value >= 256 && Value <= 0xffff) 2504 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2505 else if (Value > 0xffff && Value <= 0xffffff) 2506 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2507 else if (Value > 0xffffff) 2508 Value = (Value >> 24) | 0x600; 2509 Inst.addOperand(MCOperand::createImm(Value)); 2510 } 2511 2512 void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const { 2513 assert(N == 1 && "Invalid number of operands!"); 2514 // The immediate encodes the type of constant as well as the value. 2515 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2516 unsigned Value = CE->getValue(); 2517 assert((Inst.getOpcode() == ARM::VMOVv8i8 || 2518 Inst.getOpcode() == ARM::VMOVv16i8) && 2519 "All instructions that wants to replicate non-zero byte " 2520 "always must be replaced with VMOVv8i8 or VMOVv16i8."); 2521 unsigned B = Value & 0xff; 2522 B |= 0xe00; // cmode = 0b1110 2523 Inst.addOperand(MCOperand::createImm(B)); 2524 } 2525 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { 2526 assert(N == 1 && "Invalid number of operands!"); 2527 // The immediate encodes the type of constant as well as the value. 2528 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2529 unsigned Value = ~CE->getValue(); 2530 if (Value >= 256 && Value <= 0xffff) 2531 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2532 else if (Value > 0xffff && Value <= 0xffffff) 2533 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2534 else if (Value > 0xffffff) 2535 Value = (Value >> 24) | 0x600; 2536 Inst.addOperand(MCOperand::createImm(Value)); 2537 } 2538 2539 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 2540 assert(N == 1 && "Invalid number of operands!"); 2541 // The immediate encodes the type of constant as well as the value. 2542 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2543 uint64_t Value = CE->getValue(); 2544 unsigned Imm = 0; 2545 for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 2546 Imm |= (Value & 1) << i; 2547 } 2548 Inst.addOperand(MCOperand::createImm(Imm | 0x1e00)); 2549 } 2550 2551 void print(raw_ostream &OS) const override; 2552 2553 static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) { 2554 auto Op = make_unique<ARMOperand>(k_ITCondMask); 2555 Op->ITMask.Mask = Mask; 2556 Op->StartLoc = S; 2557 Op->EndLoc = S; 2558 return Op; 2559 } 2560 2561 static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC, 2562 SMLoc S) { 2563 auto Op = make_unique<ARMOperand>(k_CondCode); 2564 Op->CC.Val = CC; 2565 Op->StartLoc = S; 2566 Op->EndLoc = S; 2567 return Op; 2568 } 2569 2570 static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) { 2571 auto Op = make_unique<ARMOperand>(k_CoprocNum); 2572 Op->Cop.Val = CopVal; 2573 Op->StartLoc = S; 2574 Op->EndLoc = S; 2575 return Op; 2576 } 2577 2578 static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) { 2579 auto Op = make_unique<ARMOperand>(k_CoprocReg); 2580 Op->Cop.Val = CopVal; 2581 Op->StartLoc = S; 2582 Op->EndLoc = S; 2583 return Op; 2584 } 2585 2586 static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S, 2587 SMLoc E) { 2588 auto Op = make_unique<ARMOperand>(k_CoprocOption); 2589 Op->Cop.Val = Val; 2590 Op->StartLoc = S; 2591 Op->EndLoc = E; 2592 return Op; 2593 } 2594 2595 static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) { 2596 auto Op = make_unique<ARMOperand>(k_CCOut); 2597 Op->Reg.RegNum = RegNum; 2598 Op->StartLoc = S; 2599 Op->EndLoc = S; 2600 return Op; 2601 } 2602 2603 static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) { 2604 auto Op = make_unique<ARMOperand>(k_Token); 2605 Op->Tok.Data = Str.data(); 2606 Op->Tok.Length = Str.size(); 2607 Op->StartLoc = S; 2608 Op->EndLoc = S; 2609 return Op; 2610 } 2611 2612 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S, 2613 SMLoc E) { 2614 auto Op = make_unique<ARMOperand>(k_Register); 2615 Op->Reg.RegNum = RegNum; 2616 Op->StartLoc = S; 2617 Op->EndLoc = E; 2618 return Op; 2619 } 2620 2621 static std::unique_ptr<ARMOperand> 2622 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, 2623 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, 2624 SMLoc E) { 2625 auto Op = make_unique<ARMOperand>(k_ShiftedRegister); 2626 Op->RegShiftedReg.ShiftTy = ShTy; 2627 Op->RegShiftedReg.SrcReg = SrcReg; 2628 Op->RegShiftedReg.ShiftReg = ShiftReg; 2629 Op->RegShiftedReg.ShiftImm = ShiftImm; 2630 Op->StartLoc = S; 2631 Op->EndLoc = E; 2632 return Op; 2633 } 2634 2635 static std::unique_ptr<ARMOperand> 2636 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, 2637 unsigned ShiftImm, SMLoc S, SMLoc E) { 2638 auto Op = make_unique<ARMOperand>(k_ShiftedImmediate); 2639 Op->RegShiftedImm.ShiftTy = ShTy; 2640 Op->RegShiftedImm.SrcReg = SrcReg; 2641 Op->RegShiftedImm.ShiftImm = ShiftImm; 2642 Op->StartLoc = S; 2643 Op->EndLoc = E; 2644 return Op; 2645 } 2646 2647 static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm, 2648 SMLoc S, SMLoc E) { 2649 auto Op = make_unique<ARMOperand>(k_ShifterImmediate); 2650 Op->ShifterImm.isASR = isASR; 2651 Op->ShifterImm.Imm = Imm; 2652 Op->StartLoc = S; 2653 Op->EndLoc = E; 2654 return Op; 2655 } 2656 2657 static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S, 2658 SMLoc E) { 2659 auto Op = make_unique<ARMOperand>(k_RotateImmediate); 2660 Op->RotImm.Imm = Imm; 2661 Op->StartLoc = S; 2662 Op->EndLoc = E; 2663 return Op; 2664 } 2665 2666 static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot, 2667 SMLoc S, SMLoc E) { 2668 auto Op = make_unique<ARMOperand>(k_ModifiedImmediate); 2669 Op->ModImm.Bits = Bits; 2670 Op->ModImm.Rot = Rot; 2671 Op->StartLoc = S; 2672 Op->EndLoc = E; 2673 return Op; 2674 } 2675 2676 static std::unique_ptr<ARMOperand> 2677 CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) { 2678 auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor); 2679 Op->Bitfield.LSB = LSB; 2680 Op->Bitfield.Width = Width; 2681 Op->StartLoc = S; 2682 Op->EndLoc = E; 2683 return Op; 2684 } 2685 2686 static std::unique_ptr<ARMOperand> 2687 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs, 2688 SMLoc StartLoc, SMLoc EndLoc) { 2689 assert (Regs.size() > 0 && "RegList contains no registers?"); 2690 KindTy Kind = k_RegisterList; 2691 2692 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second)) 2693 Kind = k_DPRRegisterList; 2694 else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 2695 contains(Regs.front().second)) 2696 Kind = k_SPRRegisterList; 2697 2698 // Sort based on the register encoding values. 2699 array_pod_sort(Regs.begin(), Regs.end()); 2700 2701 auto Op = make_unique<ARMOperand>(Kind); 2702 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator 2703 I = Regs.begin(), E = Regs.end(); I != E; ++I) 2704 Op->Registers.push_back(I->second); 2705 Op->StartLoc = StartLoc; 2706 Op->EndLoc = EndLoc; 2707 return Op; 2708 } 2709 2710 static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum, 2711 unsigned Count, 2712 bool isDoubleSpaced, 2713 SMLoc S, SMLoc E) { 2714 auto Op = make_unique<ARMOperand>(k_VectorList); 2715 Op->VectorList.RegNum = RegNum; 2716 Op->VectorList.Count = Count; 2717 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2718 Op->StartLoc = S; 2719 Op->EndLoc = E; 2720 return Op; 2721 } 2722 2723 static std::unique_ptr<ARMOperand> 2724 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced, 2725 SMLoc S, SMLoc E) { 2726 auto Op = make_unique<ARMOperand>(k_VectorListAllLanes); 2727 Op->VectorList.RegNum = RegNum; 2728 Op->VectorList.Count = Count; 2729 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2730 Op->StartLoc = S; 2731 Op->EndLoc = E; 2732 return Op; 2733 } 2734 2735 static std::unique_ptr<ARMOperand> 2736 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index, 2737 bool isDoubleSpaced, SMLoc S, SMLoc E) { 2738 auto Op = make_unique<ARMOperand>(k_VectorListIndexed); 2739 Op->VectorList.RegNum = RegNum; 2740 Op->VectorList.Count = Count; 2741 Op->VectorList.LaneIndex = Index; 2742 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2743 Op->StartLoc = S; 2744 Op->EndLoc = E; 2745 return Op; 2746 } 2747 2748 static std::unique_ptr<ARMOperand> 2749 CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) { 2750 auto Op = make_unique<ARMOperand>(k_VectorIndex); 2751 Op->VectorIndex.Val = Idx; 2752 Op->StartLoc = S; 2753 Op->EndLoc = E; 2754 return Op; 2755 } 2756 2757 static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S, 2758 SMLoc E) { 2759 auto Op = make_unique<ARMOperand>(k_Immediate); 2760 Op->Imm.Val = Val; 2761 Op->StartLoc = S; 2762 Op->EndLoc = E; 2763 return Op; 2764 } 2765 2766 static std::unique_ptr<ARMOperand> 2767 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm, 2768 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, 2769 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S, 2770 SMLoc E, SMLoc AlignmentLoc = SMLoc()) { 2771 auto Op = make_unique<ARMOperand>(k_Memory); 2772 Op->Memory.BaseRegNum = BaseRegNum; 2773 Op->Memory.OffsetImm = OffsetImm; 2774 Op->Memory.OffsetRegNum = OffsetRegNum; 2775 Op->Memory.ShiftType = ShiftType; 2776 Op->Memory.ShiftImm = ShiftImm; 2777 Op->Memory.Alignment = Alignment; 2778 Op->Memory.isNegative = isNegative; 2779 Op->StartLoc = S; 2780 Op->EndLoc = E; 2781 Op->AlignmentLoc = AlignmentLoc; 2782 return Op; 2783 } 2784 2785 static std::unique_ptr<ARMOperand> 2786 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, 2787 unsigned ShiftImm, SMLoc S, SMLoc E) { 2788 auto Op = make_unique<ARMOperand>(k_PostIndexRegister); 2789 Op->PostIdxReg.RegNum = RegNum; 2790 Op->PostIdxReg.isAdd = isAdd; 2791 Op->PostIdxReg.ShiftTy = ShiftTy; 2792 Op->PostIdxReg.ShiftImm = ShiftImm; 2793 Op->StartLoc = S; 2794 Op->EndLoc = E; 2795 return Op; 2796 } 2797 2798 static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, 2799 SMLoc S) { 2800 auto Op = make_unique<ARMOperand>(k_MemBarrierOpt); 2801 Op->MBOpt.Val = Opt; 2802 Op->StartLoc = S; 2803 Op->EndLoc = S; 2804 return Op; 2805 } 2806 2807 static std::unique_ptr<ARMOperand> 2808 CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) { 2809 auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt); 2810 Op->ISBOpt.Val = Opt; 2811 Op->StartLoc = S; 2812 Op->EndLoc = S; 2813 return Op; 2814 } 2815 2816 static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags, 2817 SMLoc S) { 2818 auto Op = make_unique<ARMOperand>(k_ProcIFlags); 2819 Op->IFlags.Val = IFlags; 2820 Op->StartLoc = S; 2821 Op->EndLoc = S; 2822 return Op; 2823 } 2824 2825 static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) { 2826 auto Op = make_unique<ARMOperand>(k_MSRMask); 2827 Op->MMask.Val = MMask; 2828 Op->StartLoc = S; 2829 Op->EndLoc = S; 2830 return Op; 2831 } 2832 2833 static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) { 2834 auto Op = make_unique<ARMOperand>(k_BankedReg); 2835 Op->BankedReg.Val = Reg; 2836 Op->StartLoc = S; 2837 Op->EndLoc = S; 2838 return Op; 2839 } 2840 }; 2841 2842 } // end anonymous namespace. 2843 2844 void ARMOperand::print(raw_ostream &OS) const { 2845 switch (Kind) { 2846 case k_CondCode: 2847 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 2848 break; 2849 case k_CCOut: 2850 OS << "<ccout " << getReg() << ">"; 2851 break; 2852 case k_ITCondMask: { 2853 static const char *const MaskStr[] = { 2854 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", 2855 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" 2856 }; 2857 assert((ITMask.Mask & 0xf) == ITMask.Mask); 2858 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 2859 break; 2860 } 2861 case k_CoprocNum: 2862 OS << "<coprocessor number: " << getCoproc() << ">"; 2863 break; 2864 case k_CoprocReg: 2865 OS << "<coprocessor register: " << getCoproc() << ">"; 2866 break; 2867 case k_CoprocOption: 2868 OS << "<coprocessor option: " << CoprocOption.Val << ">"; 2869 break; 2870 case k_MSRMask: 2871 OS << "<mask: " << getMSRMask() << ">"; 2872 break; 2873 case k_BankedReg: 2874 OS << "<banked reg: " << getBankedReg() << ">"; 2875 break; 2876 case k_Immediate: 2877 OS << *getImm(); 2878 break; 2879 case k_MemBarrierOpt: 2880 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">"; 2881 break; 2882 case k_InstSyncBarrierOpt: 2883 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">"; 2884 break; 2885 case k_Memory: 2886 OS << "<memory " 2887 << " base:" << Memory.BaseRegNum; 2888 OS << ">"; 2889 break; 2890 case k_PostIndexRegister: 2891 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 2892 << PostIdxReg.RegNum; 2893 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 2894 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 2895 << PostIdxReg.ShiftImm; 2896 OS << ">"; 2897 break; 2898 case k_ProcIFlags: { 2899 OS << "<ARM_PROC::"; 2900 unsigned IFlags = getProcIFlags(); 2901 for (int i=2; i >= 0; --i) 2902 if (IFlags & (1 << i)) 2903 OS << ARM_PROC::IFlagsToString(1 << i); 2904 OS << ">"; 2905 break; 2906 } 2907 case k_Register: 2908 OS << "<register " << getReg() << ">"; 2909 break; 2910 case k_ShifterImmediate: 2911 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 2912 << " #" << ShifterImm.Imm << ">"; 2913 break; 2914 case k_ShiftedRegister: 2915 OS << "<so_reg_reg " 2916 << RegShiftedReg.SrcReg << " " 2917 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) 2918 << " " << RegShiftedReg.ShiftReg << ">"; 2919 break; 2920 case k_ShiftedImmediate: 2921 OS << "<so_reg_imm " 2922 << RegShiftedImm.SrcReg << " " 2923 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) 2924 << " #" << RegShiftedImm.ShiftImm << ">"; 2925 break; 2926 case k_RotateImmediate: 2927 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 2928 break; 2929 case k_ModifiedImmediate: 2930 OS << "<mod_imm #" << ModImm.Bits << ", #" 2931 << ModImm.Rot << ")>"; 2932 break; 2933 case k_BitfieldDescriptor: 2934 OS << "<bitfield " << "lsb: " << Bitfield.LSB 2935 << ", width: " << Bitfield.Width << ">"; 2936 break; 2937 case k_RegisterList: 2938 case k_DPRRegisterList: 2939 case k_SPRRegisterList: { 2940 OS << "<register_list "; 2941 2942 const SmallVectorImpl<unsigned> &RegList = getRegList(); 2943 for (SmallVectorImpl<unsigned>::const_iterator 2944 I = RegList.begin(), E = RegList.end(); I != E; ) { 2945 OS << *I; 2946 if (++I < E) OS << ", "; 2947 } 2948 2949 OS << ">"; 2950 break; 2951 } 2952 case k_VectorList: 2953 OS << "<vector_list " << VectorList.Count << " * " 2954 << VectorList.RegNum << ">"; 2955 break; 2956 case k_VectorListAllLanes: 2957 OS << "<vector_list(all lanes) " << VectorList.Count << " * " 2958 << VectorList.RegNum << ">"; 2959 break; 2960 case k_VectorListIndexed: 2961 OS << "<vector_list(lane " << VectorList.LaneIndex << ") " 2962 << VectorList.Count << " * " << VectorList.RegNum << ">"; 2963 break; 2964 case k_Token: 2965 OS << "'" << getToken() << "'"; 2966 break; 2967 case k_VectorIndex: 2968 OS << "<vectorindex " << getVectorIndex() << ">"; 2969 break; 2970 } 2971 } 2972 2973 /// @name Auto-generated Match Functions 2974 /// { 2975 2976 static unsigned MatchRegisterName(StringRef Name); 2977 2978 /// } 2979 2980 bool ARMAsmParser::ParseRegister(unsigned &RegNo, 2981 SMLoc &StartLoc, SMLoc &EndLoc) { 2982 const AsmToken &Tok = getParser().getTok(); 2983 StartLoc = Tok.getLoc(); 2984 EndLoc = Tok.getEndLoc(); 2985 RegNo = tryParseRegister(); 2986 2987 return (RegNo == (unsigned)-1); 2988 } 2989 2990 /// Try to parse a register name. The token must be an Identifier when called, 2991 /// and if it is a register name the token is eaten and the register number is 2992 /// returned. Otherwise return -1. 2993 /// 2994 int ARMAsmParser::tryParseRegister() { 2995 MCAsmParser &Parser = getParser(); 2996 const AsmToken &Tok = Parser.getTok(); 2997 if (Tok.isNot(AsmToken::Identifier)) return -1; 2998 2999 std::string lowerCase = Tok.getString().lower(); 3000 unsigned RegNum = MatchRegisterName(lowerCase); 3001 if (!RegNum) { 3002 RegNum = StringSwitch<unsigned>(lowerCase) 3003 .Case("r13", ARM::SP) 3004 .Case("r14", ARM::LR) 3005 .Case("r15", ARM::PC) 3006 .Case("ip", ARM::R12) 3007 // Additional register name aliases for 'gas' compatibility. 3008 .Case("a1", ARM::R0) 3009 .Case("a2", ARM::R1) 3010 .Case("a3", ARM::R2) 3011 .Case("a4", ARM::R3) 3012 .Case("v1", ARM::R4) 3013 .Case("v2", ARM::R5) 3014 .Case("v3", ARM::R6) 3015 .Case("v4", ARM::R7) 3016 .Case("v5", ARM::R8) 3017 .Case("v6", ARM::R9) 3018 .Case("v7", ARM::R10) 3019 .Case("v8", ARM::R11) 3020 .Case("sb", ARM::R9) 3021 .Case("sl", ARM::R10) 3022 .Case("fp", ARM::R11) 3023 .Default(0); 3024 } 3025 if (!RegNum) { 3026 // Check for aliases registered via .req. Canonicalize to lower case. 3027 // That's more consistent since register names are case insensitive, and 3028 // it's how the original entry was passed in from MC/MCParser/AsmParser. 3029 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); 3030 // If no match, return failure. 3031 if (Entry == RegisterReqs.end()) 3032 return -1; 3033 Parser.Lex(); // Eat identifier token. 3034 return Entry->getValue(); 3035 } 3036 3037 // Some FPUs only have 16 D registers, so D16-D31 are invalid 3038 if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31) 3039 return -1; 3040 3041 Parser.Lex(); // Eat identifier token. 3042 3043 return RegNum; 3044 } 3045 3046 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 3047 // If a recoverable error occurs, return 1. If an irrecoverable error 3048 // occurs, return -1. An irrecoverable error is one where tokens have been 3049 // consumed in the process of trying to parse the shifter (i.e., when it is 3050 // indeed a shifter operand, but malformed). 3051 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) { 3052 MCAsmParser &Parser = getParser(); 3053 SMLoc S = Parser.getTok().getLoc(); 3054 const AsmToken &Tok = Parser.getTok(); 3055 if (Tok.isNot(AsmToken::Identifier)) 3056 return -1; 3057 3058 std::string lowerCase = Tok.getString().lower(); 3059 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 3060 .Case("asl", ARM_AM::lsl) 3061 .Case("lsl", ARM_AM::lsl) 3062 .Case("lsr", ARM_AM::lsr) 3063 .Case("asr", ARM_AM::asr) 3064 .Case("ror", ARM_AM::ror) 3065 .Case("rrx", ARM_AM::rrx) 3066 .Default(ARM_AM::no_shift); 3067 3068 if (ShiftTy == ARM_AM::no_shift) 3069 return 1; 3070 3071 Parser.Lex(); // Eat the operator. 3072 3073 // The source register for the shift has already been added to the 3074 // operand list, so we need to pop it off and combine it into the shifted 3075 // register operand instead. 3076 std::unique_ptr<ARMOperand> PrevOp( 3077 (ARMOperand *)Operands.pop_back_val().release()); 3078 if (!PrevOp->isReg()) 3079 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 3080 int SrcReg = PrevOp->getReg(); 3081 3082 SMLoc EndLoc; 3083 int64_t Imm = 0; 3084 int ShiftReg = 0; 3085 if (ShiftTy == ARM_AM::rrx) { 3086 // RRX Doesn't have an explicit shift amount. The encoder expects 3087 // the shift register to be the same as the source register. Seems odd, 3088 // but OK. 3089 ShiftReg = SrcReg; 3090 } else { 3091 // Figure out if this is shifted by a constant or a register (for non-RRX). 3092 if (Parser.getTok().is(AsmToken::Hash) || 3093 Parser.getTok().is(AsmToken::Dollar)) { 3094 Parser.Lex(); // Eat hash. 3095 SMLoc ImmLoc = Parser.getTok().getLoc(); 3096 const MCExpr *ShiftExpr = nullptr; 3097 if (getParser().parseExpression(ShiftExpr, EndLoc)) { 3098 Error(ImmLoc, "invalid immediate shift value"); 3099 return -1; 3100 } 3101 // The expression must be evaluatable as an immediate. 3102 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 3103 if (!CE) { 3104 Error(ImmLoc, "invalid immediate shift value"); 3105 return -1; 3106 } 3107 // Range check the immediate. 3108 // lsl, ror: 0 <= imm <= 31 3109 // lsr, asr: 0 <= imm <= 32 3110 Imm = CE->getValue(); 3111 if (Imm < 0 || 3112 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 3113 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 3114 Error(ImmLoc, "immediate shift value out of range"); 3115 return -1; 3116 } 3117 // shift by zero is a nop. Always send it through as lsl. 3118 // ('as' compatibility) 3119 if (Imm == 0) 3120 ShiftTy = ARM_AM::lsl; 3121 } else if (Parser.getTok().is(AsmToken::Identifier)) { 3122 SMLoc L = Parser.getTok().getLoc(); 3123 EndLoc = Parser.getTok().getEndLoc(); 3124 ShiftReg = tryParseRegister(); 3125 if (ShiftReg == -1) { 3126 Error(L, "expected immediate or register in shift operand"); 3127 return -1; 3128 } 3129 } else { 3130 Error(Parser.getTok().getLoc(), 3131 "expected immediate or register in shift operand"); 3132 return -1; 3133 } 3134 } 3135 3136 if (ShiftReg && ShiftTy != ARM_AM::rrx) 3137 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 3138 ShiftReg, Imm, 3139 S, EndLoc)); 3140 else 3141 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 3142 S, EndLoc)); 3143 3144 return 0; 3145 } 3146 3147 3148 /// Try to parse a register name. The token must be an Identifier when called. 3149 /// If it's a register, an AsmOperand is created. Another AsmOperand is created 3150 /// if there is a "writeback". 'true' if it's not a register. 3151 /// 3152 /// TODO this is likely to change to allow different register types and or to 3153 /// parse for a specific register type. 3154 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) { 3155 MCAsmParser &Parser = getParser(); 3156 const AsmToken &RegTok = Parser.getTok(); 3157 int RegNo = tryParseRegister(); 3158 if (RegNo == -1) 3159 return true; 3160 3161 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(), 3162 RegTok.getEndLoc())); 3163 3164 const AsmToken &ExclaimTok = Parser.getTok(); 3165 if (ExclaimTok.is(AsmToken::Exclaim)) { 3166 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 3167 ExclaimTok.getLoc())); 3168 Parser.Lex(); // Eat exclaim token 3169 return false; 3170 } 3171 3172 // Also check for an index operand. This is only legal for vector registers, 3173 // but that'll get caught OK in operand matching, so we don't need to 3174 // explicitly filter everything else out here. 3175 if (Parser.getTok().is(AsmToken::LBrac)) { 3176 SMLoc SIdx = Parser.getTok().getLoc(); 3177 Parser.Lex(); // Eat left bracket token. 3178 3179 const MCExpr *ImmVal; 3180 if (getParser().parseExpression(ImmVal)) 3181 return true; 3182 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 3183 if (!MCE) 3184 return TokError("immediate value expected for vector index"); 3185 3186 if (Parser.getTok().isNot(AsmToken::RBrac)) 3187 return Error(Parser.getTok().getLoc(), "']' expected"); 3188 3189 SMLoc E = Parser.getTok().getEndLoc(); 3190 Parser.Lex(); // Eat right bracket token. 3191 3192 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 3193 SIdx, E, 3194 getContext())); 3195 } 3196 3197 return false; 3198 } 3199 3200 /// MatchCoprocessorOperandName - Try to parse an coprocessor related 3201 /// instruction with a symbolic operand name. 3202 /// We accept "crN" syntax for GAS compatibility. 3203 /// <operand-name> ::= <prefix><number> 3204 /// If CoprocOp is 'c', then: 3205 /// <prefix> ::= c | cr 3206 /// If CoprocOp is 'p', then : 3207 /// <prefix> ::= p 3208 /// <number> ::= integer in range [0, 15] 3209 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 3210 // Use the same layout as the tablegen'erated register name matcher. Ugly, 3211 // but efficient. 3212 if (Name.size() < 2 || Name[0] != CoprocOp) 3213 return -1; 3214 Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front(); 3215 3216 switch (Name.size()) { 3217 default: return -1; 3218 case 1: 3219 switch (Name[0]) { 3220 default: return -1; 3221 case '0': return 0; 3222 case '1': return 1; 3223 case '2': return 2; 3224 case '3': return 3; 3225 case '4': return 4; 3226 case '5': return 5; 3227 case '6': return 6; 3228 case '7': return 7; 3229 case '8': return 8; 3230 case '9': return 9; 3231 } 3232 case 2: 3233 if (Name[0] != '1') 3234 return -1; 3235 switch (Name[1]) { 3236 default: return -1; 3237 // CP10 and CP11 are VFP/NEON and so vector instructions should be used. 3238 // However, old cores (v5/v6) did use them in that way. 3239 case '0': return 10; 3240 case '1': return 11; 3241 case '2': return 12; 3242 case '3': return 13; 3243 case '4': return 14; 3244 case '5': return 15; 3245 } 3246 } 3247 } 3248 3249 /// parseITCondCode - Try to parse a condition code for an IT instruction. 3250 ARMAsmParser::OperandMatchResultTy 3251 ARMAsmParser::parseITCondCode(OperandVector &Operands) { 3252 MCAsmParser &Parser = getParser(); 3253 SMLoc S = Parser.getTok().getLoc(); 3254 const AsmToken &Tok = Parser.getTok(); 3255 if (!Tok.is(AsmToken::Identifier)) 3256 return MatchOperand_NoMatch; 3257 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower()) 3258 .Case("eq", ARMCC::EQ) 3259 .Case("ne", ARMCC::NE) 3260 .Case("hs", ARMCC::HS) 3261 .Case("cs", ARMCC::HS) 3262 .Case("lo", ARMCC::LO) 3263 .Case("cc", ARMCC::LO) 3264 .Case("mi", ARMCC::MI) 3265 .Case("pl", ARMCC::PL) 3266 .Case("vs", ARMCC::VS) 3267 .Case("vc", ARMCC::VC) 3268 .Case("hi", ARMCC::HI) 3269 .Case("ls", ARMCC::LS) 3270 .Case("ge", ARMCC::GE) 3271 .Case("lt", ARMCC::LT) 3272 .Case("gt", ARMCC::GT) 3273 .Case("le", ARMCC::LE) 3274 .Case("al", ARMCC::AL) 3275 .Default(~0U); 3276 if (CC == ~0U) 3277 return MatchOperand_NoMatch; 3278 Parser.Lex(); // Eat the token. 3279 3280 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 3281 3282 return MatchOperand_Success; 3283 } 3284 3285 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 3286 /// token must be an Identifier when called, and if it is a coprocessor 3287 /// number, the token is eaten and the operand is added to the operand list. 3288 ARMAsmParser::OperandMatchResultTy 3289 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) { 3290 MCAsmParser &Parser = getParser(); 3291 SMLoc S = Parser.getTok().getLoc(); 3292 const AsmToken &Tok = Parser.getTok(); 3293 if (Tok.isNot(AsmToken::Identifier)) 3294 return MatchOperand_NoMatch; 3295 3296 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 3297 if (Num == -1) 3298 return MatchOperand_NoMatch; 3299 // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions 3300 if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11)) 3301 return MatchOperand_NoMatch; 3302 3303 Parser.Lex(); // Eat identifier token. 3304 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 3305 return MatchOperand_Success; 3306 } 3307 3308 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 3309 /// token must be an Identifier when called, and if it is a coprocessor 3310 /// number, the token is eaten and the operand is added to the operand list. 3311 ARMAsmParser::OperandMatchResultTy 3312 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) { 3313 MCAsmParser &Parser = getParser(); 3314 SMLoc S = Parser.getTok().getLoc(); 3315 const AsmToken &Tok = Parser.getTok(); 3316 if (Tok.isNot(AsmToken::Identifier)) 3317 return MatchOperand_NoMatch; 3318 3319 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 3320 if (Reg == -1) 3321 return MatchOperand_NoMatch; 3322 3323 Parser.Lex(); // Eat identifier token. 3324 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 3325 return MatchOperand_Success; 3326 } 3327 3328 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 3329 /// coproc_option : '{' imm0_255 '}' 3330 ARMAsmParser::OperandMatchResultTy 3331 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) { 3332 MCAsmParser &Parser = getParser(); 3333 SMLoc S = Parser.getTok().getLoc(); 3334 3335 // If this isn't a '{', this isn't a coprocessor immediate operand. 3336 if (Parser.getTok().isNot(AsmToken::LCurly)) 3337 return MatchOperand_NoMatch; 3338 Parser.Lex(); // Eat the '{' 3339 3340 const MCExpr *Expr; 3341 SMLoc Loc = Parser.getTok().getLoc(); 3342 if (getParser().parseExpression(Expr)) { 3343 Error(Loc, "illegal expression"); 3344 return MatchOperand_ParseFail; 3345 } 3346 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 3347 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 3348 Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 3349 return MatchOperand_ParseFail; 3350 } 3351 int Val = CE->getValue(); 3352 3353 // Check for and consume the closing '}' 3354 if (Parser.getTok().isNot(AsmToken::RCurly)) 3355 return MatchOperand_ParseFail; 3356 SMLoc E = Parser.getTok().getEndLoc(); 3357 Parser.Lex(); // Eat the '}' 3358 3359 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 3360 return MatchOperand_Success; 3361 } 3362 3363 // For register list parsing, we need to map from raw GPR register numbering 3364 // to the enumeration values. The enumeration values aren't sorted by 3365 // register number due to our using "sp", "lr" and "pc" as canonical names. 3366 static unsigned getNextRegister(unsigned Reg) { 3367 // If this is a GPR, we need to do it manually, otherwise we can rely 3368 // on the sort ordering of the enumeration since the other reg-classes 3369 // are sane. 3370 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3371 return Reg + 1; 3372 switch(Reg) { 3373 default: llvm_unreachable("Invalid GPR number!"); 3374 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 3375 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 3376 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 3377 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 3378 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 3379 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 3380 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 3381 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 3382 } 3383 } 3384 3385 // Return the low-subreg of a given Q register. 3386 static unsigned getDRegFromQReg(unsigned QReg) { 3387 switch (QReg) { 3388 default: llvm_unreachable("expected a Q register!"); 3389 case ARM::Q0: return ARM::D0; 3390 case ARM::Q1: return ARM::D2; 3391 case ARM::Q2: return ARM::D4; 3392 case ARM::Q3: return ARM::D6; 3393 case ARM::Q4: return ARM::D8; 3394 case ARM::Q5: return ARM::D10; 3395 case ARM::Q6: return ARM::D12; 3396 case ARM::Q7: return ARM::D14; 3397 case ARM::Q8: return ARM::D16; 3398 case ARM::Q9: return ARM::D18; 3399 case ARM::Q10: return ARM::D20; 3400 case ARM::Q11: return ARM::D22; 3401 case ARM::Q12: return ARM::D24; 3402 case ARM::Q13: return ARM::D26; 3403 case ARM::Q14: return ARM::D28; 3404 case ARM::Q15: return ARM::D30; 3405 } 3406 } 3407 3408 /// Parse a register list. 3409 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) { 3410 MCAsmParser &Parser = getParser(); 3411 assert(Parser.getTok().is(AsmToken::LCurly) && 3412 "Token is not a Left Curly Brace"); 3413 SMLoc S = Parser.getTok().getLoc(); 3414 Parser.Lex(); // Eat '{' token. 3415 SMLoc RegLoc = Parser.getTok().getLoc(); 3416 3417 // Check the first register in the list to see what register class 3418 // this is a list of. 3419 int Reg = tryParseRegister(); 3420 if (Reg == -1) 3421 return Error(RegLoc, "register expected"); 3422 3423 // The reglist instructions have at most 16 registers, so reserve 3424 // space for that many. 3425 int EReg = 0; 3426 SmallVector<std::pair<unsigned, unsigned>, 16> Registers; 3427 3428 // Allow Q regs and just interpret them as the two D sub-registers. 3429 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3430 Reg = getDRegFromQReg(Reg); 3431 EReg = MRI->getEncodingValue(Reg); 3432 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3433 ++Reg; 3434 } 3435 const MCRegisterClass *RC; 3436 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3437 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 3438 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 3439 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 3440 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 3441 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 3442 else 3443 return Error(RegLoc, "invalid register in register list"); 3444 3445 // Store the register. 3446 EReg = MRI->getEncodingValue(Reg); 3447 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3448 3449 // This starts immediately after the first register token in the list, 3450 // so we can see either a comma or a minus (range separator) as a legal 3451 // next token. 3452 while (Parser.getTok().is(AsmToken::Comma) || 3453 Parser.getTok().is(AsmToken::Minus)) { 3454 if (Parser.getTok().is(AsmToken::Minus)) { 3455 Parser.Lex(); // Eat the minus. 3456 SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3457 int EndReg = tryParseRegister(); 3458 if (EndReg == -1) 3459 return Error(AfterMinusLoc, "register expected"); 3460 // Allow Q regs and just interpret them as the two D sub-registers. 3461 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3462 EndReg = getDRegFromQReg(EndReg) + 1; 3463 // If the register is the same as the start reg, there's nothing 3464 // more to do. 3465 if (Reg == EndReg) 3466 continue; 3467 // The register must be in the same register class as the first. 3468 if (!RC->contains(EndReg)) 3469 return Error(AfterMinusLoc, "invalid register in register list"); 3470 // Ranges must go from low to high. 3471 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) 3472 return Error(AfterMinusLoc, "bad range in register list"); 3473 3474 // Add all the registers in the range to the register list. 3475 while (Reg != EndReg) { 3476 Reg = getNextRegister(Reg); 3477 EReg = MRI->getEncodingValue(Reg); 3478 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3479 } 3480 continue; 3481 } 3482 Parser.Lex(); // Eat the comma. 3483 RegLoc = Parser.getTok().getLoc(); 3484 int OldReg = Reg; 3485 const AsmToken RegTok = Parser.getTok(); 3486 Reg = tryParseRegister(); 3487 if (Reg == -1) 3488 return Error(RegLoc, "register expected"); 3489 // Allow Q regs and just interpret them as the two D sub-registers. 3490 bool isQReg = false; 3491 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3492 Reg = getDRegFromQReg(Reg); 3493 isQReg = true; 3494 } 3495 // The register must be in the same register class as the first. 3496 if (!RC->contains(Reg)) 3497 return Error(RegLoc, "invalid register in register list"); 3498 // List must be monotonically increasing. 3499 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { 3500 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3501 Warning(RegLoc, "register list not in ascending order"); 3502 else 3503 return Error(RegLoc, "register list not in ascending order"); 3504 } 3505 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) { 3506 Warning(RegLoc, "duplicated register (" + RegTok.getString() + 3507 ") in register list"); 3508 continue; 3509 } 3510 // VFP register lists must also be contiguous. 3511 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 3512 Reg != OldReg + 1) 3513 return Error(RegLoc, "non-contiguous register range"); 3514 EReg = MRI->getEncodingValue(Reg); 3515 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3516 if (isQReg) { 3517 EReg = MRI->getEncodingValue(++Reg); 3518 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3519 } 3520 } 3521 3522 if (Parser.getTok().isNot(AsmToken::RCurly)) 3523 return Error(Parser.getTok().getLoc(), "'}' expected"); 3524 SMLoc E = Parser.getTok().getEndLoc(); 3525 Parser.Lex(); // Eat '}' token. 3526 3527 // Push the register list operand. 3528 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 3529 3530 // The ARM system instruction variants for LDM/STM have a '^' token here. 3531 if (Parser.getTok().is(AsmToken::Caret)) { 3532 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); 3533 Parser.Lex(); // Eat '^' token. 3534 } 3535 3536 return false; 3537 } 3538 3539 // Helper function to parse the lane index for vector lists. 3540 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3541 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) { 3542 MCAsmParser &Parser = getParser(); 3543 Index = 0; // Always return a defined index value. 3544 if (Parser.getTok().is(AsmToken::LBrac)) { 3545 Parser.Lex(); // Eat the '['. 3546 if (Parser.getTok().is(AsmToken::RBrac)) { 3547 // "Dn[]" is the 'all lanes' syntax. 3548 LaneKind = AllLanes; 3549 EndLoc = Parser.getTok().getEndLoc(); 3550 Parser.Lex(); // Eat the ']'. 3551 return MatchOperand_Success; 3552 } 3553 3554 // There's an optional '#' token here. Normally there wouldn't be, but 3555 // inline assemble puts one in, and it's friendly to accept that. 3556 if (Parser.getTok().is(AsmToken::Hash)) 3557 Parser.Lex(); // Eat '#' or '$'. 3558 3559 const MCExpr *LaneIndex; 3560 SMLoc Loc = Parser.getTok().getLoc(); 3561 if (getParser().parseExpression(LaneIndex)) { 3562 Error(Loc, "illegal expression"); 3563 return MatchOperand_ParseFail; 3564 } 3565 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); 3566 if (!CE) { 3567 Error(Loc, "lane index must be empty or an integer"); 3568 return MatchOperand_ParseFail; 3569 } 3570 if (Parser.getTok().isNot(AsmToken::RBrac)) { 3571 Error(Parser.getTok().getLoc(), "']' expected"); 3572 return MatchOperand_ParseFail; 3573 } 3574 EndLoc = Parser.getTok().getEndLoc(); 3575 Parser.Lex(); // Eat the ']'. 3576 int64_t Val = CE->getValue(); 3577 3578 // FIXME: Make this range check context sensitive for .8, .16, .32. 3579 if (Val < 0 || Val > 7) { 3580 Error(Parser.getTok().getLoc(), "lane index out of range"); 3581 return MatchOperand_ParseFail; 3582 } 3583 Index = Val; 3584 LaneKind = IndexedLane; 3585 return MatchOperand_Success; 3586 } 3587 LaneKind = NoLanes; 3588 return MatchOperand_Success; 3589 } 3590 3591 // parse a vector register list 3592 ARMAsmParser::OperandMatchResultTy 3593 ARMAsmParser::parseVectorList(OperandVector &Operands) { 3594 MCAsmParser &Parser = getParser(); 3595 VectorLaneTy LaneKind; 3596 unsigned LaneIndex; 3597 SMLoc S = Parser.getTok().getLoc(); 3598 // As an extension (to match gas), support a plain D register or Q register 3599 // (without encosing curly braces) as a single or double entry list, 3600 // respectively. 3601 if (Parser.getTok().is(AsmToken::Identifier)) { 3602 SMLoc E = Parser.getTok().getEndLoc(); 3603 int Reg = tryParseRegister(); 3604 if (Reg == -1) 3605 return MatchOperand_NoMatch; 3606 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 3607 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 3608 if (Res != MatchOperand_Success) 3609 return Res; 3610 switch (LaneKind) { 3611 case NoLanes: 3612 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); 3613 break; 3614 case AllLanes: 3615 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, 3616 S, E)); 3617 break; 3618 case IndexedLane: 3619 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 3620 LaneIndex, 3621 false, S, E)); 3622 break; 3623 } 3624 return MatchOperand_Success; 3625 } 3626 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3627 Reg = getDRegFromQReg(Reg); 3628 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 3629 if (Res != MatchOperand_Success) 3630 return Res; 3631 switch (LaneKind) { 3632 case NoLanes: 3633 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3634 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3635 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); 3636 break; 3637 case AllLanes: 3638 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3639 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3640 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, 3641 S, E)); 3642 break; 3643 case IndexedLane: 3644 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 3645 LaneIndex, 3646 false, S, E)); 3647 break; 3648 } 3649 return MatchOperand_Success; 3650 } 3651 Error(S, "vector register expected"); 3652 return MatchOperand_ParseFail; 3653 } 3654 3655 if (Parser.getTok().isNot(AsmToken::LCurly)) 3656 return MatchOperand_NoMatch; 3657 3658 Parser.Lex(); // Eat '{' token. 3659 SMLoc RegLoc = Parser.getTok().getLoc(); 3660 3661 int Reg = tryParseRegister(); 3662 if (Reg == -1) { 3663 Error(RegLoc, "register expected"); 3664 return MatchOperand_ParseFail; 3665 } 3666 unsigned Count = 1; 3667 int Spacing = 0; 3668 unsigned FirstReg = Reg; 3669 // The list is of D registers, but we also allow Q regs and just interpret 3670 // them as the two D sub-registers. 3671 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3672 FirstReg = Reg = getDRegFromQReg(Reg); 3673 Spacing = 1; // double-spacing requires explicit D registers, otherwise 3674 // it's ambiguous with four-register single spaced. 3675 ++Reg; 3676 ++Count; 3677 } 3678 3679 SMLoc E; 3680 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success) 3681 return MatchOperand_ParseFail; 3682 3683 while (Parser.getTok().is(AsmToken::Comma) || 3684 Parser.getTok().is(AsmToken::Minus)) { 3685 if (Parser.getTok().is(AsmToken::Minus)) { 3686 if (!Spacing) 3687 Spacing = 1; // Register range implies a single spaced list. 3688 else if (Spacing == 2) { 3689 Error(Parser.getTok().getLoc(), 3690 "sequential registers in double spaced list"); 3691 return MatchOperand_ParseFail; 3692 } 3693 Parser.Lex(); // Eat the minus. 3694 SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3695 int EndReg = tryParseRegister(); 3696 if (EndReg == -1) { 3697 Error(AfterMinusLoc, "register expected"); 3698 return MatchOperand_ParseFail; 3699 } 3700 // Allow Q regs and just interpret them as the two D sub-registers. 3701 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3702 EndReg = getDRegFromQReg(EndReg) + 1; 3703 // If the register is the same as the start reg, there's nothing 3704 // more to do. 3705 if (Reg == EndReg) 3706 continue; 3707 // The register must be in the same register class as the first. 3708 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { 3709 Error(AfterMinusLoc, "invalid register in register list"); 3710 return MatchOperand_ParseFail; 3711 } 3712 // Ranges must go from low to high. 3713 if (Reg > EndReg) { 3714 Error(AfterMinusLoc, "bad range in register list"); 3715 return MatchOperand_ParseFail; 3716 } 3717 // Parse the lane specifier if present. 3718 VectorLaneTy NextLaneKind; 3719 unsigned NextLaneIndex; 3720 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 3721 MatchOperand_Success) 3722 return MatchOperand_ParseFail; 3723 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3724 Error(AfterMinusLoc, "mismatched lane index in register list"); 3725 return MatchOperand_ParseFail; 3726 } 3727 3728 // Add all the registers in the range to the register list. 3729 Count += EndReg - Reg; 3730 Reg = EndReg; 3731 continue; 3732 } 3733 Parser.Lex(); // Eat the comma. 3734 RegLoc = Parser.getTok().getLoc(); 3735 int OldReg = Reg; 3736 Reg = tryParseRegister(); 3737 if (Reg == -1) { 3738 Error(RegLoc, "register expected"); 3739 return MatchOperand_ParseFail; 3740 } 3741 // vector register lists must be contiguous. 3742 // It's OK to use the enumeration values directly here rather, as the 3743 // VFP register classes have the enum sorted properly. 3744 // 3745 // The list is of D registers, but we also allow Q regs and just interpret 3746 // them as the two D sub-registers. 3747 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3748 if (!Spacing) 3749 Spacing = 1; // Register range implies a single spaced list. 3750 else if (Spacing == 2) { 3751 Error(RegLoc, 3752 "invalid register in double-spaced list (must be 'D' register')"); 3753 return MatchOperand_ParseFail; 3754 } 3755 Reg = getDRegFromQReg(Reg); 3756 if (Reg != OldReg + 1) { 3757 Error(RegLoc, "non-contiguous register range"); 3758 return MatchOperand_ParseFail; 3759 } 3760 ++Reg; 3761 Count += 2; 3762 // Parse the lane specifier if present. 3763 VectorLaneTy NextLaneKind; 3764 unsigned NextLaneIndex; 3765 SMLoc LaneLoc = Parser.getTok().getLoc(); 3766 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 3767 MatchOperand_Success) 3768 return MatchOperand_ParseFail; 3769 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3770 Error(LaneLoc, "mismatched lane index in register list"); 3771 return MatchOperand_ParseFail; 3772 } 3773 continue; 3774 } 3775 // Normal D register. 3776 // Figure out the register spacing (single or double) of the list if 3777 // we don't know it already. 3778 if (!Spacing) 3779 Spacing = 1 + (Reg == OldReg + 2); 3780 3781 // Just check that it's contiguous and keep going. 3782 if (Reg != OldReg + Spacing) { 3783 Error(RegLoc, "non-contiguous register range"); 3784 return MatchOperand_ParseFail; 3785 } 3786 ++Count; 3787 // Parse the lane specifier if present. 3788 VectorLaneTy NextLaneKind; 3789 unsigned NextLaneIndex; 3790 SMLoc EndLoc = Parser.getTok().getLoc(); 3791 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success) 3792 return MatchOperand_ParseFail; 3793 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3794 Error(EndLoc, "mismatched lane index in register list"); 3795 return MatchOperand_ParseFail; 3796 } 3797 } 3798 3799 if (Parser.getTok().isNot(AsmToken::RCurly)) { 3800 Error(Parser.getTok().getLoc(), "'}' expected"); 3801 return MatchOperand_ParseFail; 3802 } 3803 E = Parser.getTok().getEndLoc(); 3804 Parser.Lex(); // Eat '}' token. 3805 3806 switch (LaneKind) { 3807 case NoLanes: 3808 // Two-register operands have been converted to the 3809 // composite register classes. 3810 if (Count == 2) { 3811 const MCRegisterClass *RC = (Spacing == 1) ? 3812 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3813 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3814 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3815 } 3816 3817 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, 3818 (Spacing == 2), S, E)); 3819 break; 3820 case AllLanes: 3821 // Two-register operands have been converted to the 3822 // composite register classes. 3823 if (Count == 2) { 3824 const MCRegisterClass *RC = (Spacing == 1) ? 3825 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3826 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3827 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3828 } 3829 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 3830 (Spacing == 2), 3831 S, E)); 3832 break; 3833 case IndexedLane: 3834 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 3835 LaneIndex, 3836 (Spacing == 2), 3837 S, E)); 3838 break; 3839 } 3840 return MatchOperand_Success; 3841 } 3842 3843 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 3844 ARMAsmParser::OperandMatchResultTy 3845 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) { 3846 MCAsmParser &Parser = getParser(); 3847 SMLoc S = Parser.getTok().getLoc(); 3848 const AsmToken &Tok = Parser.getTok(); 3849 unsigned Opt; 3850 3851 if (Tok.is(AsmToken::Identifier)) { 3852 StringRef OptStr = Tok.getString(); 3853 3854 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower()) 3855 .Case("sy", ARM_MB::SY) 3856 .Case("st", ARM_MB::ST) 3857 .Case("ld", ARM_MB::LD) 3858 .Case("sh", ARM_MB::ISH) 3859 .Case("ish", ARM_MB::ISH) 3860 .Case("shst", ARM_MB::ISHST) 3861 .Case("ishst", ARM_MB::ISHST) 3862 .Case("ishld", ARM_MB::ISHLD) 3863 .Case("nsh", ARM_MB::NSH) 3864 .Case("un", ARM_MB::NSH) 3865 .Case("nshst", ARM_MB::NSHST) 3866 .Case("nshld", ARM_MB::NSHLD) 3867 .Case("unst", ARM_MB::NSHST) 3868 .Case("osh", ARM_MB::OSH) 3869 .Case("oshst", ARM_MB::OSHST) 3870 .Case("oshld", ARM_MB::OSHLD) 3871 .Default(~0U); 3872 3873 // ishld, oshld, nshld and ld are only available from ARMv8. 3874 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD || 3875 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD)) 3876 Opt = ~0U; 3877 3878 if (Opt == ~0U) 3879 return MatchOperand_NoMatch; 3880 3881 Parser.Lex(); // Eat identifier token. 3882 } else if (Tok.is(AsmToken::Hash) || 3883 Tok.is(AsmToken::Dollar) || 3884 Tok.is(AsmToken::Integer)) { 3885 if (Parser.getTok().isNot(AsmToken::Integer)) 3886 Parser.Lex(); // Eat '#' or '$'. 3887 SMLoc Loc = Parser.getTok().getLoc(); 3888 3889 const MCExpr *MemBarrierID; 3890 if (getParser().parseExpression(MemBarrierID)) { 3891 Error(Loc, "illegal expression"); 3892 return MatchOperand_ParseFail; 3893 } 3894 3895 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID); 3896 if (!CE) { 3897 Error(Loc, "constant expression expected"); 3898 return MatchOperand_ParseFail; 3899 } 3900 3901 int Val = CE->getValue(); 3902 if (Val & ~0xf) { 3903 Error(Loc, "immediate value out of range"); 3904 return MatchOperand_ParseFail; 3905 } 3906 3907 Opt = ARM_MB::RESERVED_0 + Val; 3908 } else 3909 return MatchOperand_ParseFail; 3910 3911 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 3912 return MatchOperand_Success; 3913 } 3914 3915 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options. 3916 ARMAsmParser::OperandMatchResultTy 3917 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) { 3918 MCAsmParser &Parser = getParser(); 3919 SMLoc S = Parser.getTok().getLoc(); 3920 const AsmToken &Tok = Parser.getTok(); 3921 unsigned Opt; 3922 3923 if (Tok.is(AsmToken::Identifier)) { 3924 StringRef OptStr = Tok.getString(); 3925 3926 if (OptStr.equals_lower("sy")) 3927 Opt = ARM_ISB::SY; 3928 else 3929 return MatchOperand_NoMatch; 3930 3931 Parser.Lex(); // Eat identifier token. 3932 } else if (Tok.is(AsmToken::Hash) || 3933 Tok.is(AsmToken::Dollar) || 3934 Tok.is(AsmToken::Integer)) { 3935 if (Parser.getTok().isNot(AsmToken::Integer)) 3936 Parser.Lex(); // Eat '#' or '$'. 3937 SMLoc Loc = Parser.getTok().getLoc(); 3938 3939 const MCExpr *ISBarrierID; 3940 if (getParser().parseExpression(ISBarrierID)) { 3941 Error(Loc, "illegal expression"); 3942 return MatchOperand_ParseFail; 3943 } 3944 3945 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID); 3946 if (!CE) { 3947 Error(Loc, "constant expression expected"); 3948 return MatchOperand_ParseFail; 3949 } 3950 3951 int Val = CE->getValue(); 3952 if (Val & ~0xf) { 3953 Error(Loc, "immediate value out of range"); 3954 return MatchOperand_ParseFail; 3955 } 3956 3957 Opt = ARM_ISB::RESERVED_0 + Val; 3958 } else 3959 return MatchOperand_ParseFail; 3960 3961 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt( 3962 (ARM_ISB::InstSyncBOpt)Opt, S)); 3963 return MatchOperand_Success; 3964 } 3965 3966 3967 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 3968 ARMAsmParser::OperandMatchResultTy 3969 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) { 3970 MCAsmParser &Parser = getParser(); 3971 SMLoc S = Parser.getTok().getLoc(); 3972 const AsmToken &Tok = Parser.getTok(); 3973 if (!Tok.is(AsmToken::Identifier)) 3974 return MatchOperand_NoMatch; 3975 StringRef IFlagsStr = Tok.getString(); 3976 3977 // An iflags string of "none" is interpreted to mean that none of the AIF 3978 // bits are set. Not a terribly useful instruction, but a valid encoding. 3979 unsigned IFlags = 0; 3980 if (IFlagsStr != "none") { 3981 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 3982 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 3983 .Case("a", ARM_PROC::A) 3984 .Case("i", ARM_PROC::I) 3985 .Case("f", ARM_PROC::F) 3986 .Default(~0U); 3987 3988 // If some specific iflag is already set, it means that some letter is 3989 // present more than once, this is not acceptable. 3990 if (Flag == ~0U || (IFlags & Flag)) 3991 return MatchOperand_NoMatch; 3992 3993 IFlags |= Flag; 3994 } 3995 } 3996 3997 Parser.Lex(); // Eat identifier token. 3998 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 3999 return MatchOperand_Success; 4000 } 4001 4002 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 4003 ARMAsmParser::OperandMatchResultTy 4004 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) { 4005 MCAsmParser &Parser = getParser(); 4006 SMLoc S = Parser.getTok().getLoc(); 4007 const AsmToken &Tok = Parser.getTok(); 4008 if (!Tok.is(AsmToken::Identifier)) 4009 return MatchOperand_NoMatch; 4010 StringRef Mask = Tok.getString(); 4011 4012 if (isMClass()) { 4013 // See ARMv6-M 10.1.1 4014 std::string Name = Mask.lower(); 4015 unsigned FlagsVal = StringSwitch<unsigned>(Name) 4016 // Note: in the documentation: 4017 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias 4018 // for MSR APSR_nzcvq. 4019 // but we do make it an alias here. This is so to get the "mask encoding" 4020 // bits correct on MSR APSR writes. 4021 // 4022 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers 4023 // should really only be allowed when writing a special register. Note 4024 // they get dropped in the MRS instruction reading a special register as 4025 // the SYSm field is only 8 bits. 4026 .Case("apsr", 0x800) 4027 .Case("apsr_nzcvq", 0x800) 4028 .Case("apsr_g", 0x400) 4029 .Case("apsr_nzcvqg", 0xc00) 4030 .Case("iapsr", 0x801) 4031 .Case("iapsr_nzcvq", 0x801) 4032 .Case("iapsr_g", 0x401) 4033 .Case("iapsr_nzcvqg", 0xc01) 4034 .Case("eapsr", 0x802) 4035 .Case("eapsr_nzcvq", 0x802) 4036 .Case("eapsr_g", 0x402) 4037 .Case("eapsr_nzcvqg", 0xc02) 4038 .Case("xpsr", 0x803) 4039 .Case("xpsr_nzcvq", 0x803) 4040 .Case("xpsr_g", 0x403) 4041 .Case("xpsr_nzcvqg", 0xc03) 4042 .Case("ipsr", 0x805) 4043 .Case("epsr", 0x806) 4044 .Case("iepsr", 0x807) 4045 .Case("msp", 0x808) 4046 .Case("psp", 0x809) 4047 .Case("primask", 0x810) 4048 .Case("basepri", 0x811) 4049 .Case("basepri_max", 0x812) 4050 .Case("faultmask", 0x813) 4051 .Case("control", 0x814) 4052 .Default(~0U); 4053 4054 if (FlagsVal == ~0U) 4055 return MatchOperand_NoMatch; 4056 4057 if (!hasThumb2DSP() && (FlagsVal & 0x400)) 4058 // The _g and _nzcvqg versions are only valid if the DSP extension is 4059 // available. 4060 return MatchOperand_NoMatch; 4061 4062 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813) 4063 // basepri, basepri_max and faultmask only valid for V7m. 4064 return MatchOperand_NoMatch; 4065 4066 Parser.Lex(); // Eat identifier token. 4067 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 4068 return MatchOperand_Success; 4069 } 4070 4071 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 4072 size_t Start = 0, Next = Mask.find('_'); 4073 StringRef Flags = ""; 4074 std::string SpecReg = Mask.slice(Start, Next).lower(); 4075 if (Next != StringRef::npos) 4076 Flags = Mask.slice(Next+1, Mask.size()); 4077 4078 // FlagsVal contains the complete mask: 4079 // 3-0: Mask 4080 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 4081 unsigned FlagsVal = 0; 4082 4083 if (SpecReg == "apsr") { 4084 FlagsVal = StringSwitch<unsigned>(Flags) 4085 .Case("nzcvq", 0x8) // same as CPSR_f 4086 .Case("g", 0x4) // same as CPSR_s 4087 .Case("nzcvqg", 0xc) // same as CPSR_fs 4088 .Default(~0U); 4089 4090 if (FlagsVal == ~0U) { 4091 if (!Flags.empty()) 4092 return MatchOperand_NoMatch; 4093 else 4094 FlagsVal = 8; // No flag 4095 } 4096 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 4097 // cpsr_all is an alias for cpsr_fc, as is plain cpsr. 4098 if (Flags == "all" || Flags == "") 4099 Flags = "fc"; 4100 for (int i = 0, e = Flags.size(); i != e; ++i) { 4101 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 4102 .Case("c", 1) 4103 .Case("x", 2) 4104 .Case("s", 4) 4105 .Case("f", 8) 4106 .Default(~0U); 4107 4108 // If some specific flag is already set, it means that some letter is 4109 // present more than once, this is not acceptable. 4110 if (FlagsVal == ~0U || (FlagsVal & Flag)) 4111 return MatchOperand_NoMatch; 4112 FlagsVal |= Flag; 4113 } 4114 } else // No match for special register. 4115 return MatchOperand_NoMatch; 4116 4117 // Special register without flags is NOT equivalent to "fc" flags. 4118 // NOTE: This is a divergence from gas' behavior. Uncommenting the following 4119 // two lines would enable gas compatibility at the expense of breaking 4120 // round-tripping. 4121 // 4122 // if (!FlagsVal) 4123 // FlagsVal = 0x9; 4124 4125 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 4126 if (SpecReg == "spsr") 4127 FlagsVal |= 16; 4128 4129 Parser.Lex(); // Eat identifier token. 4130 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 4131 return MatchOperand_Success; 4132 } 4133 4134 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for 4135 /// use in the MRS/MSR instructions added to support virtualization. 4136 ARMAsmParser::OperandMatchResultTy 4137 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) { 4138 MCAsmParser &Parser = getParser(); 4139 SMLoc S = Parser.getTok().getLoc(); 4140 const AsmToken &Tok = Parser.getTok(); 4141 if (!Tok.is(AsmToken::Identifier)) 4142 return MatchOperand_NoMatch; 4143 StringRef RegName = Tok.getString(); 4144 4145 // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM 4146 // and bit 5 is R. 4147 unsigned Encoding = StringSwitch<unsigned>(RegName.lower()) 4148 .Case("r8_usr", 0x00) 4149 .Case("r9_usr", 0x01) 4150 .Case("r10_usr", 0x02) 4151 .Case("r11_usr", 0x03) 4152 .Case("r12_usr", 0x04) 4153 .Case("sp_usr", 0x05) 4154 .Case("lr_usr", 0x06) 4155 .Case("r8_fiq", 0x08) 4156 .Case("r9_fiq", 0x09) 4157 .Case("r10_fiq", 0x0a) 4158 .Case("r11_fiq", 0x0b) 4159 .Case("r12_fiq", 0x0c) 4160 .Case("sp_fiq", 0x0d) 4161 .Case("lr_fiq", 0x0e) 4162 .Case("lr_irq", 0x10) 4163 .Case("sp_irq", 0x11) 4164 .Case("lr_svc", 0x12) 4165 .Case("sp_svc", 0x13) 4166 .Case("lr_abt", 0x14) 4167 .Case("sp_abt", 0x15) 4168 .Case("lr_und", 0x16) 4169 .Case("sp_und", 0x17) 4170 .Case("lr_mon", 0x1c) 4171 .Case("sp_mon", 0x1d) 4172 .Case("elr_hyp", 0x1e) 4173 .Case("sp_hyp", 0x1f) 4174 .Case("spsr_fiq", 0x2e) 4175 .Case("spsr_irq", 0x30) 4176 .Case("spsr_svc", 0x32) 4177 .Case("spsr_abt", 0x34) 4178 .Case("spsr_und", 0x36) 4179 .Case("spsr_mon", 0x3c) 4180 .Case("spsr_hyp", 0x3e) 4181 .Default(~0U); 4182 4183 if (Encoding == ~0U) 4184 return MatchOperand_NoMatch; 4185 4186 Parser.Lex(); // Eat identifier token. 4187 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S)); 4188 return MatchOperand_Success; 4189 } 4190 4191 ARMAsmParser::OperandMatchResultTy 4192 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low, 4193 int High) { 4194 MCAsmParser &Parser = getParser(); 4195 const AsmToken &Tok = Parser.getTok(); 4196 if (Tok.isNot(AsmToken::Identifier)) { 4197 Error(Parser.getTok().getLoc(), Op + " operand expected."); 4198 return MatchOperand_ParseFail; 4199 } 4200 StringRef ShiftName = Tok.getString(); 4201 std::string LowerOp = Op.lower(); 4202 std::string UpperOp = Op.upper(); 4203 if (ShiftName != LowerOp && ShiftName != UpperOp) { 4204 Error(Parser.getTok().getLoc(), Op + " operand expected."); 4205 return MatchOperand_ParseFail; 4206 } 4207 Parser.Lex(); // Eat shift type token. 4208 4209 // There must be a '#' and a shift amount. 4210 if (Parser.getTok().isNot(AsmToken::Hash) && 4211 Parser.getTok().isNot(AsmToken::Dollar)) { 4212 Error(Parser.getTok().getLoc(), "'#' expected"); 4213 return MatchOperand_ParseFail; 4214 } 4215 Parser.Lex(); // Eat hash token. 4216 4217 const MCExpr *ShiftAmount; 4218 SMLoc Loc = Parser.getTok().getLoc(); 4219 SMLoc EndLoc; 4220 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 4221 Error(Loc, "illegal expression"); 4222 return MatchOperand_ParseFail; 4223 } 4224 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 4225 if (!CE) { 4226 Error(Loc, "constant expression expected"); 4227 return MatchOperand_ParseFail; 4228 } 4229 int Val = CE->getValue(); 4230 if (Val < Low || Val > High) { 4231 Error(Loc, "immediate value out of range"); 4232 return MatchOperand_ParseFail; 4233 } 4234 4235 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc)); 4236 4237 return MatchOperand_Success; 4238 } 4239 4240 ARMAsmParser::OperandMatchResultTy 4241 ARMAsmParser::parseSetEndImm(OperandVector &Operands) { 4242 MCAsmParser &Parser = getParser(); 4243 const AsmToken &Tok = Parser.getTok(); 4244 SMLoc S = Tok.getLoc(); 4245 if (Tok.isNot(AsmToken::Identifier)) { 4246 Error(S, "'be' or 'le' operand expected"); 4247 return MatchOperand_ParseFail; 4248 } 4249 int Val = StringSwitch<int>(Tok.getString().lower()) 4250 .Case("be", 1) 4251 .Case("le", 0) 4252 .Default(-1); 4253 Parser.Lex(); // Eat the token. 4254 4255 if (Val == -1) { 4256 Error(S, "'be' or 'le' operand expected"); 4257 return MatchOperand_ParseFail; 4258 } 4259 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val, 4260 getContext()), 4261 S, Tok.getEndLoc())); 4262 return MatchOperand_Success; 4263 } 4264 4265 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 4266 /// instructions. Legal values are: 4267 /// lsl #n 'n' in [0,31] 4268 /// asr #n 'n' in [1,32] 4269 /// n == 32 encoded as n == 0. 4270 ARMAsmParser::OperandMatchResultTy 4271 ARMAsmParser::parseShifterImm(OperandVector &Operands) { 4272 MCAsmParser &Parser = getParser(); 4273 const AsmToken &Tok = Parser.getTok(); 4274 SMLoc S = Tok.getLoc(); 4275 if (Tok.isNot(AsmToken::Identifier)) { 4276 Error(S, "shift operator 'asr' or 'lsl' expected"); 4277 return MatchOperand_ParseFail; 4278 } 4279 StringRef ShiftName = Tok.getString(); 4280 bool isASR; 4281 if (ShiftName == "lsl" || ShiftName == "LSL") 4282 isASR = false; 4283 else if (ShiftName == "asr" || ShiftName == "ASR") 4284 isASR = true; 4285 else { 4286 Error(S, "shift operator 'asr' or 'lsl' expected"); 4287 return MatchOperand_ParseFail; 4288 } 4289 Parser.Lex(); // Eat the operator. 4290 4291 // A '#' and a shift amount. 4292 if (Parser.getTok().isNot(AsmToken::Hash) && 4293 Parser.getTok().isNot(AsmToken::Dollar)) { 4294 Error(Parser.getTok().getLoc(), "'#' expected"); 4295 return MatchOperand_ParseFail; 4296 } 4297 Parser.Lex(); // Eat hash token. 4298 SMLoc ExLoc = Parser.getTok().getLoc(); 4299 4300 const MCExpr *ShiftAmount; 4301 SMLoc EndLoc; 4302 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 4303 Error(ExLoc, "malformed shift expression"); 4304 return MatchOperand_ParseFail; 4305 } 4306 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 4307 if (!CE) { 4308 Error(ExLoc, "shift amount must be an immediate"); 4309 return MatchOperand_ParseFail; 4310 } 4311 4312 int64_t Val = CE->getValue(); 4313 if (isASR) { 4314 // Shift amount must be in [1,32] 4315 if (Val < 1 || Val > 32) { 4316 Error(ExLoc, "'asr' shift amount must be in range [1,32]"); 4317 return MatchOperand_ParseFail; 4318 } 4319 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 4320 if (isThumb() && Val == 32) { 4321 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode"); 4322 return MatchOperand_ParseFail; 4323 } 4324 if (Val == 32) Val = 0; 4325 } else { 4326 // Shift amount must be in [1,32] 4327 if (Val < 0 || Val > 31) { 4328 Error(ExLoc, "'lsr' shift amount must be in range [0,31]"); 4329 return MatchOperand_ParseFail; 4330 } 4331 } 4332 4333 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc)); 4334 4335 return MatchOperand_Success; 4336 } 4337 4338 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 4339 /// of instructions. Legal values are: 4340 /// ror #n 'n' in {0, 8, 16, 24} 4341 ARMAsmParser::OperandMatchResultTy 4342 ARMAsmParser::parseRotImm(OperandVector &Operands) { 4343 MCAsmParser &Parser = getParser(); 4344 const AsmToken &Tok = Parser.getTok(); 4345 SMLoc S = Tok.getLoc(); 4346 if (Tok.isNot(AsmToken::Identifier)) 4347 return MatchOperand_NoMatch; 4348 StringRef ShiftName = Tok.getString(); 4349 if (ShiftName != "ror" && ShiftName != "ROR") 4350 return MatchOperand_NoMatch; 4351 Parser.Lex(); // Eat the operator. 4352 4353 // A '#' and a rotate amount. 4354 if (Parser.getTok().isNot(AsmToken::Hash) && 4355 Parser.getTok().isNot(AsmToken::Dollar)) { 4356 Error(Parser.getTok().getLoc(), "'#' expected"); 4357 return MatchOperand_ParseFail; 4358 } 4359 Parser.Lex(); // Eat hash token. 4360 SMLoc ExLoc = Parser.getTok().getLoc(); 4361 4362 const MCExpr *ShiftAmount; 4363 SMLoc EndLoc; 4364 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 4365 Error(ExLoc, "malformed rotate expression"); 4366 return MatchOperand_ParseFail; 4367 } 4368 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 4369 if (!CE) { 4370 Error(ExLoc, "rotate amount must be an immediate"); 4371 return MatchOperand_ParseFail; 4372 } 4373 4374 int64_t Val = CE->getValue(); 4375 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 4376 // normally, zero is represented in asm by omitting the rotate operand 4377 // entirely. 4378 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 4379 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24"); 4380 return MatchOperand_ParseFail; 4381 } 4382 4383 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); 4384 4385 return MatchOperand_Success; 4386 } 4387 4388 ARMAsmParser::OperandMatchResultTy 4389 ARMAsmParser::parseModImm(OperandVector &Operands) { 4390 MCAsmParser &Parser = getParser(); 4391 MCAsmLexer &Lexer = getLexer(); 4392 int64_t Imm1, Imm2; 4393 4394 SMLoc S = Parser.getTok().getLoc(); 4395 4396 // 1) A mod_imm operand can appear in the place of a register name: 4397 // add r0, #mod_imm 4398 // add r0, r0, #mod_imm 4399 // to correctly handle the latter, we bail out as soon as we see an 4400 // identifier. 4401 // 4402 // 2) Similarly, we do not want to parse into complex operands: 4403 // mov r0, #mod_imm 4404 // mov r0, :lower16:(_foo) 4405 if (Parser.getTok().is(AsmToken::Identifier) || 4406 Parser.getTok().is(AsmToken::Colon)) 4407 return MatchOperand_NoMatch; 4408 4409 // Hash (dollar) is optional as per the ARMARM 4410 if (Parser.getTok().is(AsmToken::Hash) || 4411 Parser.getTok().is(AsmToken::Dollar)) { 4412 // Avoid parsing into complex operands (#:) 4413 if (Lexer.peekTok().is(AsmToken::Colon)) 4414 return MatchOperand_NoMatch; 4415 4416 // Eat the hash (dollar) 4417 Parser.Lex(); 4418 } 4419 4420 SMLoc Sx1, Ex1; 4421 Sx1 = Parser.getTok().getLoc(); 4422 const MCExpr *Imm1Exp; 4423 if (getParser().parseExpression(Imm1Exp, Ex1)) { 4424 Error(Sx1, "malformed expression"); 4425 return MatchOperand_ParseFail; 4426 } 4427 4428 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp); 4429 4430 if (CE) { 4431 // Immediate must fit within 32-bits 4432 Imm1 = CE->getValue(); 4433 int Enc = ARM_AM::getSOImmVal(Imm1); 4434 if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) { 4435 // We have a match! 4436 Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF), 4437 (Enc & 0xF00) >> 7, 4438 Sx1, Ex1)); 4439 return MatchOperand_Success; 4440 } 4441 4442 // We have parsed an immediate which is not for us, fallback to a plain 4443 // immediate. This can happen for instruction aliases. For an example, 4444 // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform 4445 // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite 4446 // instruction with a mod_imm operand. The alias is defined such that the 4447 // parser method is shared, that's why we have to do this here. 4448 if (Parser.getTok().is(AsmToken::EndOfStatement)) { 4449 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); 4450 return MatchOperand_Success; 4451 } 4452 } else { 4453 // Operands like #(l1 - l2) can only be evaluated at a later stage (via an 4454 // MCFixup). Fallback to a plain immediate. 4455 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); 4456 return MatchOperand_Success; 4457 } 4458 4459 // From this point onward, we expect the input to be a (#bits, #rot) pair 4460 if (Parser.getTok().isNot(AsmToken::Comma)) { 4461 Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]"); 4462 return MatchOperand_ParseFail; 4463 } 4464 4465 if (Imm1 & ~0xFF) { 4466 Error(Sx1, "immediate operand must a number in the range [0, 255]"); 4467 return MatchOperand_ParseFail; 4468 } 4469 4470 // Eat the comma 4471 Parser.Lex(); 4472 4473 // Repeat for #rot 4474 SMLoc Sx2, Ex2; 4475 Sx2 = Parser.getTok().getLoc(); 4476 4477 // Eat the optional hash (dollar) 4478 if (Parser.getTok().is(AsmToken::Hash) || 4479 Parser.getTok().is(AsmToken::Dollar)) 4480 Parser.Lex(); 4481 4482 const MCExpr *Imm2Exp; 4483 if (getParser().parseExpression(Imm2Exp, Ex2)) { 4484 Error(Sx2, "malformed expression"); 4485 return MatchOperand_ParseFail; 4486 } 4487 4488 CE = dyn_cast<MCConstantExpr>(Imm2Exp); 4489 4490 if (CE) { 4491 Imm2 = CE->getValue(); 4492 if (!(Imm2 & ~0x1E)) { 4493 // We have a match! 4494 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2)); 4495 return MatchOperand_Success; 4496 } 4497 Error(Sx2, "immediate operand must an even number in the range [0, 30]"); 4498 return MatchOperand_ParseFail; 4499 } else { 4500 Error(Sx2, "constant expression expected"); 4501 return MatchOperand_ParseFail; 4502 } 4503 } 4504 4505 ARMAsmParser::OperandMatchResultTy 4506 ARMAsmParser::parseBitfield(OperandVector &Operands) { 4507 MCAsmParser &Parser = getParser(); 4508 SMLoc S = Parser.getTok().getLoc(); 4509 // The bitfield descriptor is really two operands, the LSB and the width. 4510 if (Parser.getTok().isNot(AsmToken::Hash) && 4511 Parser.getTok().isNot(AsmToken::Dollar)) { 4512 Error(Parser.getTok().getLoc(), "'#' expected"); 4513 return MatchOperand_ParseFail; 4514 } 4515 Parser.Lex(); // Eat hash token. 4516 4517 const MCExpr *LSBExpr; 4518 SMLoc E = Parser.getTok().getLoc(); 4519 if (getParser().parseExpression(LSBExpr)) { 4520 Error(E, "malformed immediate expression"); 4521 return MatchOperand_ParseFail; 4522 } 4523 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 4524 if (!CE) { 4525 Error(E, "'lsb' operand must be an immediate"); 4526 return MatchOperand_ParseFail; 4527 } 4528 4529 int64_t LSB = CE->getValue(); 4530 // The LSB must be in the range [0,31] 4531 if (LSB < 0 || LSB > 31) { 4532 Error(E, "'lsb' operand must be in the range [0,31]"); 4533 return MatchOperand_ParseFail; 4534 } 4535 E = Parser.getTok().getLoc(); 4536 4537 // Expect another immediate operand. 4538 if (Parser.getTok().isNot(AsmToken::Comma)) { 4539 Error(Parser.getTok().getLoc(), "too few operands"); 4540 return MatchOperand_ParseFail; 4541 } 4542 Parser.Lex(); // Eat hash token. 4543 if (Parser.getTok().isNot(AsmToken::Hash) && 4544 Parser.getTok().isNot(AsmToken::Dollar)) { 4545 Error(Parser.getTok().getLoc(), "'#' expected"); 4546 return MatchOperand_ParseFail; 4547 } 4548 Parser.Lex(); // Eat hash token. 4549 4550 const MCExpr *WidthExpr; 4551 SMLoc EndLoc; 4552 if (getParser().parseExpression(WidthExpr, EndLoc)) { 4553 Error(E, "malformed immediate expression"); 4554 return MatchOperand_ParseFail; 4555 } 4556 CE = dyn_cast<MCConstantExpr>(WidthExpr); 4557 if (!CE) { 4558 Error(E, "'width' operand must be an immediate"); 4559 return MatchOperand_ParseFail; 4560 } 4561 4562 int64_t Width = CE->getValue(); 4563 // The LSB must be in the range [1,32-lsb] 4564 if (Width < 1 || Width > 32 - LSB) { 4565 Error(E, "'width' operand must be in the range [1,32-lsb]"); 4566 return MatchOperand_ParseFail; 4567 } 4568 4569 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc)); 4570 4571 return MatchOperand_Success; 4572 } 4573 4574 ARMAsmParser::OperandMatchResultTy 4575 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) { 4576 // Check for a post-index addressing register operand. Specifically: 4577 // postidx_reg := '+' register {, shift} 4578 // | '-' register {, shift} 4579 // | register {, shift} 4580 4581 // This method must return MatchOperand_NoMatch without consuming any tokens 4582 // in the case where there is no match, as other alternatives take other 4583 // parse methods. 4584 MCAsmParser &Parser = getParser(); 4585 AsmToken Tok = Parser.getTok(); 4586 SMLoc S = Tok.getLoc(); 4587 bool haveEaten = false; 4588 bool isAdd = true; 4589 if (Tok.is(AsmToken::Plus)) { 4590 Parser.Lex(); // Eat the '+' token. 4591 haveEaten = true; 4592 } else if (Tok.is(AsmToken::Minus)) { 4593 Parser.Lex(); // Eat the '-' token. 4594 isAdd = false; 4595 haveEaten = true; 4596 } 4597 4598 SMLoc E = Parser.getTok().getEndLoc(); 4599 int Reg = tryParseRegister(); 4600 if (Reg == -1) { 4601 if (!haveEaten) 4602 return MatchOperand_NoMatch; 4603 Error(Parser.getTok().getLoc(), "register expected"); 4604 return MatchOperand_ParseFail; 4605 } 4606 4607 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 4608 unsigned ShiftImm = 0; 4609 if (Parser.getTok().is(AsmToken::Comma)) { 4610 Parser.Lex(); // Eat the ','. 4611 if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 4612 return MatchOperand_ParseFail; 4613 4614 // FIXME: Only approximates end...may include intervening whitespace. 4615 E = Parser.getTok().getLoc(); 4616 } 4617 4618 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 4619 ShiftImm, S, E)); 4620 4621 return MatchOperand_Success; 4622 } 4623 4624 ARMAsmParser::OperandMatchResultTy 4625 ARMAsmParser::parseAM3Offset(OperandVector &Operands) { 4626 // Check for a post-index addressing register operand. Specifically: 4627 // am3offset := '+' register 4628 // | '-' register 4629 // | register 4630 // | # imm 4631 // | # + imm 4632 // | # - imm 4633 4634 // This method must return MatchOperand_NoMatch without consuming any tokens 4635 // in the case where there is no match, as other alternatives take other 4636 // parse methods. 4637 MCAsmParser &Parser = getParser(); 4638 AsmToken Tok = Parser.getTok(); 4639 SMLoc S = Tok.getLoc(); 4640 4641 // Do immediates first, as we always parse those if we have a '#'. 4642 if (Parser.getTok().is(AsmToken::Hash) || 4643 Parser.getTok().is(AsmToken::Dollar)) { 4644 Parser.Lex(); // Eat '#' or '$'. 4645 // Explicitly look for a '-', as we need to encode negative zero 4646 // differently. 4647 bool isNegative = Parser.getTok().is(AsmToken::Minus); 4648 const MCExpr *Offset; 4649 SMLoc E; 4650 if (getParser().parseExpression(Offset, E)) 4651 return MatchOperand_ParseFail; 4652 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4653 if (!CE) { 4654 Error(S, "constant expression expected"); 4655 return MatchOperand_ParseFail; 4656 } 4657 // Negative zero is encoded as the flag value INT32_MIN. 4658 int32_t Val = CE->getValue(); 4659 if (isNegative && Val == 0) 4660 Val = INT32_MIN; 4661 4662 Operands.push_back( 4663 ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E)); 4664 4665 return MatchOperand_Success; 4666 } 4667 4668 4669 bool haveEaten = false; 4670 bool isAdd = true; 4671 if (Tok.is(AsmToken::Plus)) { 4672 Parser.Lex(); // Eat the '+' token. 4673 haveEaten = true; 4674 } else if (Tok.is(AsmToken::Minus)) { 4675 Parser.Lex(); // Eat the '-' token. 4676 isAdd = false; 4677 haveEaten = true; 4678 } 4679 4680 Tok = Parser.getTok(); 4681 int Reg = tryParseRegister(); 4682 if (Reg == -1) { 4683 if (!haveEaten) 4684 return MatchOperand_NoMatch; 4685 Error(Tok.getLoc(), "register expected"); 4686 return MatchOperand_ParseFail; 4687 } 4688 4689 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 4690 0, S, Tok.getEndLoc())); 4691 4692 return MatchOperand_Success; 4693 } 4694 4695 /// Convert parsed operands to MCInst. Needed here because this instruction 4696 /// only has two register operands, but multiplication is commutative so 4697 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN". 4698 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst, 4699 const OperandVector &Operands) { 4700 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); 4701 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1); 4702 // If we have a three-operand form, make sure to set Rn to be the operand 4703 // that isn't the same as Rd. 4704 unsigned RegOp = 4; 4705 if (Operands.size() == 6 && 4706 ((ARMOperand &)*Operands[4]).getReg() == 4707 ((ARMOperand &)*Operands[3]).getReg()) 4708 RegOp = 5; 4709 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1); 4710 Inst.addOperand(Inst.getOperand(0)); 4711 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2); 4712 } 4713 4714 void ARMAsmParser::cvtThumbBranches(MCInst &Inst, 4715 const OperandVector &Operands) { 4716 int CondOp = -1, ImmOp = -1; 4717 switch(Inst.getOpcode()) { 4718 case ARM::tB: 4719 case ARM::tBcc: CondOp = 1; ImmOp = 2; break; 4720 4721 case ARM::t2B: 4722 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break; 4723 4724 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches"); 4725 } 4726 // first decide whether or not the branch should be conditional 4727 // by looking at it's location relative to an IT block 4728 if(inITBlock()) { 4729 // inside an IT block we cannot have any conditional branches. any 4730 // such instructions needs to be converted to unconditional form 4731 switch(Inst.getOpcode()) { 4732 case ARM::tBcc: Inst.setOpcode(ARM::tB); break; 4733 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break; 4734 } 4735 } else { 4736 // outside IT blocks we can only have unconditional branches with AL 4737 // condition code or conditional branches with non-AL condition code 4738 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode(); 4739 switch(Inst.getOpcode()) { 4740 case ARM::tB: 4741 case ARM::tBcc: 4742 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); 4743 break; 4744 case ARM::t2B: 4745 case ARM::t2Bcc: 4746 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc); 4747 break; 4748 } 4749 } 4750 4751 // now decide on encoding size based on branch target range 4752 switch(Inst.getOpcode()) { 4753 // classify tB as either t2B or t1B based on range of immediate operand 4754 case ARM::tB: { 4755 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); 4756 if (!op.isSignedOffset<11, 1>() && isThumbTwo()) 4757 Inst.setOpcode(ARM::t2B); 4758 break; 4759 } 4760 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand 4761 case ARM::tBcc: { 4762 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); 4763 if (!op.isSignedOffset<8, 1>() && isThumbTwo()) 4764 Inst.setOpcode(ARM::t2Bcc); 4765 break; 4766 } 4767 } 4768 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1); 4769 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2); 4770 } 4771 4772 /// Parse an ARM memory expression, return false if successful else return true 4773 /// or an error. The first token must be a '[' when called. 4774 bool ARMAsmParser::parseMemory(OperandVector &Operands) { 4775 MCAsmParser &Parser = getParser(); 4776 SMLoc S, E; 4777 assert(Parser.getTok().is(AsmToken::LBrac) && 4778 "Token is not a Left Bracket"); 4779 S = Parser.getTok().getLoc(); 4780 Parser.Lex(); // Eat left bracket token. 4781 4782 const AsmToken &BaseRegTok = Parser.getTok(); 4783 int BaseRegNum = tryParseRegister(); 4784 if (BaseRegNum == -1) 4785 return Error(BaseRegTok.getLoc(), "register expected"); 4786 4787 // The next token must either be a comma, a colon or a closing bracket. 4788 const AsmToken &Tok = Parser.getTok(); 4789 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) && 4790 !Tok.is(AsmToken::RBrac)) 4791 return Error(Tok.getLoc(), "malformed memory operand"); 4792 4793 if (Tok.is(AsmToken::RBrac)) { 4794 E = Tok.getEndLoc(); 4795 Parser.Lex(); // Eat right bracket token. 4796 4797 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, 4798 ARM_AM::no_shift, 0, 0, false, 4799 S, E)); 4800 4801 // If there's a pre-indexing writeback marker, '!', just add it as a token 4802 // operand. It's rather odd, but syntactically valid. 4803 if (Parser.getTok().is(AsmToken::Exclaim)) { 4804 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4805 Parser.Lex(); // Eat the '!'. 4806 } 4807 4808 return false; 4809 } 4810 4811 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) && 4812 "Lost colon or comma in memory operand?!"); 4813 if (Tok.is(AsmToken::Comma)) { 4814 Parser.Lex(); // Eat the comma. 4815 } 4816 4817 // If we have a ':', it's an alignment specifier. 4818 if (Parser.getTok().is(AsmToken::Colon)) { 4819 Parser.Lex(); // Eat the ':'. 4820 E = Parser.getTok().getLoc(); 4821 SMLoc AlignmentLoc = Tok.getLoc(); 4822 4823 const MCExpr *Expr; 4824 if (getParser().parseExpression(Expr)) 4825 return true; 4826 4827 // The expression has to be a constant. Memory references with relocations 4828 // don't come through here, as they use the <label> forms of the relevant 4829 // instructions. 4830 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4831 if (!CE) 4832 return Error (E, "constant expression expected"); 4833 4834 unsigned Align = 0; 4835 switch (CE->getValue()) { 4836 default: 4837 return Error(E, 4838 "alignment specifier must be 16, 32, 64, 128, or 256 bits"); 4839 case 16: Align = 2; break; 4840 case 32: Align = 4; break; 4841 case 64: Align = 8; break; 4842 case 128: Align = 16; break; 4843 case 256: Align = 32; break; 4844 } 4845 4846 // Now we should have the closing ']' 4847 if (Parser.getTok().isNot(AsmToken::RBrac)) 4848 return Error(Parser.getTok().getLoc(), "']' expected"); 4849 E = Parser.getTok().getEndLoc(); 4850 Parser.Lex(); // Eat right bracket token. 4851 4852 // Don't worry about range checking the value here. That's handled by 4853 // the is*() predicates. 4854 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, 4855 ARM_AM::no_shift, 0, Align, 4856 false, S, E, AlignmentLoc)); 4857 4858 // If there's a pre-indexing writeback marker, '!', just add it as a token 4859 // operand. 4860 if (Parser.getTok().is(AsmToken::Exclaim)) { 4861 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4862 Parser.Lex(); // Eat the '!'. 4863 } 4864 4865 return false; 4866 } 4867 4868 // If we have a '#', it's an immediate offset, else assume it's a register 4869 // offset. Be friendly and also accept a plain integer (without a leading 4870 // hash) for gas compatibility. 4871 if (Parser.getTok().is(AsmToken::Hash) || 4872 Parser.getTok().is(AsmToken::Dollar) || 4873 Parser.getTok().is(AsmToken::Integer)) { 4874 if (Parser.getTok().isNot(AsmToken::Integer)) 4875 Parser.Lex(); // Eat '#' or '$'. 4876 E = Parser.getTok().getLoc(); 4877 4878 bool isNegative = getParser().getTok().is(AsmToken::Minus); 4879 const MCExpr *Offset; 4880 if (getParser().parseExpression(Offset)) 4881 return true; 4882 4883 // The expression has to be a constant. Memory references with relocations 4884 // don't come through here, as they use the <label> forms of the relevant 4885 // instructions. 4886 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4887 if (!CE) 4888 return Error (E, "constant expression expected"); 4889 4890 // If the constant was #-0, represent it as INT32_MIN. 4891 int32_t Val = CE->getValue(); 4892 if (isNegative && Val == 0) 4893 CE = MCConstantExpr::create(INT32_MIN, getContext()); 4894 4895 // Now we should have the closing ']' 4896 if (Parser.getTok().isNot(AsmToken::RBrac)) 4897 return Error(Parser.getTok().getLoc(), "']' expected"); 4898 E = Parser.getTok().getEndLoc(); 4899 Parser.Lex(); // Eat right bracket token. 4900 4901 // Don't worry about range checking the value here. That's handled by 4902 // the is*() predicates. 4903 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 4904 ARM_AM::no_shift, 0, 0, 4905 false, S, E)); 4906 4907 // If there's a pre-indexing writeback marker, '!', just add it as a token 4908 // operand. 4909 if (Parser.getTok().is(AsmToken::Exclaim)) { 4910 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4911 Parser.Lex(); // Eat the '!'. 4912 } 4913 4914 return false; 4915 } 4916 4917 // The register offset is optionally preceded by a '+' or '-' 4918 bool isNegative = false; 4919 if (Parser.getTok().is(AsmToken::Minus)) { 4920 isNegative = true; 4921 Parser.Lex(); // Eat the '-'. 4922 } else if (Parser.getTok().is(AsmToken::Plus)) { 4923 // Nothing to do. 4924 Parser.Lex(); // Eat the '+'. 4925 } 4926 4927 E = Parser.getTok().getLoc(); 4928 int OffsetRegNum = tryParseRegister(); 4929 if (OffsetRegNum == -1) 4930 return Error(E, "register expected"); 4931 4932 // If there's a shift operator, handle it. 4933 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 4934 unsigned ShiftImm = 0; 4935 if (Parser.getTok().is(AsmToken::Comma)) { 4936 Parser.Lex(); // Eat the ','. 4937 if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 4938 return true; 4939 } 4940 4941 // Now we should have the closing ']' 4942 if (Parser.getTok().isNot(AsmToken::RBrac)) 4943 return Error(Parser.getTok().getLoc(), "']' expected"); 4944 E = Parser.getTok().getEndLoc(); 4945 Parser.Lex(); // Eat right bracket token. 4946 4947 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum, 4948 ShiftType, ShiftImm, 0, isNegative, 4949 S, E)); 4950 4951 // If there's a pre-indexing writeback marker, '!', just add it as a token 4952 // operand. 4953 if (Parser.getTok().is(AsmToken::Exclaim)) { 4954 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4955 Parser.Lex(); // Eat the '!'. 4956 } 4957 4958 return false; 4959 } 4960 4961 /// parseMemRegOffsetShift - one of these two: 4962 /// ( lsl | lsr | asr | ror ) , # shift_amount 4963 /// rrx 4964 /// return true if it parses a shift otherwise it returns false. 4965 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 4966 unsigned &Amount) { 4967 MCAsmParser &Parser = getParser(); 4968 SMLoc Loc = Parser.getTok().getLoc(); 4969 const AsmToken &Tok = Parser.getTok(); 4970 if (Tok.isNot(AsmToken::Identifier)) 4971 return true; 4972 StringRef ShiftName = Tok.getString(); 4973 if (ShiftName == "lsl" || ShiftName == "LSL" || 4974 ShiftName == "asl" || ShiftName == "ASL") 4975 St = ARM_AM::lsl; 4976 else if (ShiftName == "lsr" || ShiftName == "LSR") 4977 St = ARM_AM::lsr; 4978 else if (ShiftName == "asr" || ShiftName == "ASR") 4979 St = ARM_AM::asr; 4980 else if (ShiftName == "ror" || ShiftName == "ROR") 4981 St = ARM_AM::ror; 4982 else if (ShiftName == "rrx" || ShiftName == "RRX") 4983 St = ARM_AM::rrx; 4984 else 4985 return Error(Loc, "illegal shift operator"); 4986 Parser.Lex(); // Eat shift type token. 4987 4988 // rrx stands alone. 4989 Amount = 0; 4990 if (St != ARM_AM::rrx) { 4991 Loc = Parser.getTok().getLoc(); 4992 // A '#' and a shift amount. 4993 const AsmToken &HashTok = Parser.getTok(); 4994 if (HashTok.isNot(AsmToken::Hash) && 4995 HashTok.isNot(AsmToken::Dollar)) 4996 return Error(HashTok.getLoc(), "'#' expected"); 4997 Parser.Lex(); // Eat hash token. 4998 4999 const MCExpr *Expr; 5000 if (getParser().parseExpression(Expr)) 5001 return true; 5002 // Range check the immediate. 5003 // lsl, ror: 0 <= imm <= 31 5004 // lsr, asr: 0 <= imm <= 32 5005 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 5006 if (!CE) 5007 return Error(Loc, "shift amount must be an immediate"); 5008 int64_t Imm = CE->getValue(); 5009 if (Imm < 0 || 5010 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 5011 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 5012 return Error(Loc, "immediate shift value out of range"); 5013 // If <ShiftTy> #0, turn it into a no_shift. 5014 if (Imm == 0) 5015 St = ARM_AM::lsl; 5016 // For consistency, treat lsr #32 and asr #32 as having immediate value 0. 5017 if (Imm == 32) 5018 Imm = 0; 5019 Amount = Imm; 5020 } 5021 5022 return false; 5023 } 5024 5025 /// parseFPImm - A floating point immediate expression operand. 5026 ARMAsmParser::OperandMatchResultTy 5027 ARMAsmParser::parseFPImm(OperandVector &Operands) { 5028 MCAsmParser &Parser = getParser(); 5029 // Anything that can accept a floating point constant as an operand 5030 // needs to go through here, as the regular parseExpression is 5031 // integer only. 5032 // 5033 // This routine still creates a generic Immediate operand, containing 5034 // a bitcast of the 64-bit floating point value. The various operands 5035 // that accept floats can check whether the value is valid for them 5036 // via the standard is*() predicates. 5037 5038 SMLoc S = Parser.getTok().getLoc(); 5039 5040 if (Parser.getTok().isNot(AsmToken::Hash) && 5041 Parser.getTok().isNot(AsmToken::Dollar)) 5042 return MatchOperand_NoMatch; 5043 5044 // Disambiguate the VMOV forms that can accept an FP immediate. 5045 // vmov.f32 <sreg>, #imm 5046 // vmov.f64 <dreg>, #imm 5047 // vmov.f32 <dreg>, #imm @ vector f32x2 5048 // vmov.f32 <qreg>, #imm @ vector f32x4 5049 // 5050 // There are also the NEON VMOV instructions which expect an 5051 // integer constant. Make sure we don't try to parse an FPImm 5052 // for these: 5053 // vmov.i{8|16|32|64} <dreg|qreg>, #imm 5054 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]); 5055 bool isVmovf = TyOp.isToken() && 5056 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64"); 5057 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]); 5058 bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" || 5059 Mnemonic.getToken() == "fconsts"); 5060 if (!(isVmovf || isFconst)) 5061 return MatchOperand_NoMatch; 5062 5063 Parser.Lex(); // Eat '#' or '$'. 5064 5065 // Handle negation, as that still comes through as a separate token. 5066 bool isNegative = false; 5067 if (Parser.getTok().is(AsmToken::Minus)) { 5068 isNegative = true; 5069 Parser.Lex(); 5070 } 5071 const AsmToken &Tok = Parser.getTok(); 5072 SMLoc Loc = Tok.getLoc(); 5073 if (Tok.is(AsmToken::Real) && isVmovf) { 5074 APFloat RealVal(APFloat::IEEEsingle, Tok.getString()); 5075 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 5076 // If we had a '-' in front, toggle the sign bit. 5077 IntVal ^= (uint64_t)isNegative << 31; 5078 Parser.Lex(); // Eat the token. 5079 Operands.push_back(ARMOperand::CreateImm( 5080 MCConstantExpr::create(IntVal, getContext()), 5081 S, Parser.getTok().getLoc())); 5082 return MatchOperand_Success; 5083 } 5084 // Also handle plain integers. Instructions which allow floating point 5085 // immediates also allow a raw encoded 8-bit value. 5086 if (Tok.is(AsmToken::Integer) && isFconst) { 5087 int64_t Val = Tok.getIntVal(); 5088 Parser.Lex(); // Eat the token. 5089 if (Val > 255 || Val < 0) { 5090 Error(Loc, "encoded floating point value out of range"); 5091 return MatchOperand_ParseFail; 5092 } 5093 float RealVal = ARM_AM::getFPImmFloat(Val); 5094 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue(); 5095 5096 Operands.push_back(ARMOperand::CreateImm( 5097 MCConstantExpr::create(Val, getContext()), S, 5098 Parser.getTok().getLoc())); 5099 return MatchOperand_Success; 5100 } 5101 5102 Error(Loc, "invalid floating point immediate"); 5103 return MatchOperand_ParseFail; 5104 } 5105 5106 /// Parse a arm instruction operand. For now this parses the operand regardless 5107 /// of the mnemonic. 5108 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { 5109 MCAsmParser &Parser = getParser(); 5110 SMLoc S, E; 5111 5112 // Check if the current operand has a custom associated parser, if so, try to 5113 // custom parse the operand, or fallback to the general approach. 5114 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 5115 if (ResTy == MatchOperand_Success) 5116 return false; 5117 // If there wasn't a custom match, try the generic matcher below. Otherwise, 5118 // there was a match, but an error occurred, in which case, just return that 5119 // the operand parsing failed. 5120 if (ResTy == MatchOperand_ParseFail) 5121 return true; 5122 5123 switch (getLexer().getKind()) { 5124 default: 5125 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 5126 return true; 5127 case AsmToken::Identifier: { 5128 // If we've seen a branch mnemonic, the next operand must be a label. This 5129 // is true even if the label is a register name. So "br r1" means branch to 5130 // label "r1". 5131 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl"; 5132 if (!ExpectLabel) { 5133 if (!tryParseRegisterWithWriteBack(Operands)) 5134 return false; 5135 int Res = tryParseShiftRegister(Operands); 5136 if (Res == 0) // success 5137 return false; 5138 else if (Res == -1) // irrecoverable error 5139 return true; 5140 // If this is VMRS, check for the apsr_nzcv operand. 5141 if (Mnemonic == "vmrs" && 5142 Parser.getTok().getString().equals_lower("apsr_nzcv")) { 5143 S = Parser.getTok().getLoc(); 5144 Parser.Lex(); 5145 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); 5146 return false; 5147 } 5148 } 5149 5150 // Fall though for the Identifier case that is not a register or a 5151 // special name. 5152 } 5153 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) 5154 case AsmToken::Integer: // things like 1f and 2b as a branch targets 5155 case AsmToken::String: // quoted label names. 5156 case AsmToken::Dot: { // . as a branch target 5157 // This was not a register so parse other operands that start with an 5158 // identifier (like labels) as expressions and create them as immediates. 5159 const MCExpr *IdVal; 5160 S = Parser.getTok().getLoc(); 5161 if (getParser().parseExpression(IdVal)) 5162 return true; 5163 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 5164 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 5165 return false; 5166 } 5167 case AsmToken::LBrac: 5168 return parseMemory(Operands); 5169 case AsmToken::LCurly: 5170 return parseRegisterList(Operands); 5171 case AsmToken::Dollar: 5172 case AsmToken::Hash: { 5173 // #42 -> immediate. 5174 S = Parser.getTok().getLoc(); 5175 Parser.Lex(); 5176 5177 if (Parser.getTok().isNot(AsmToken::Colon)) { 5178 bool isNegative = Parser.getTok().is(AsmToken::Minus); 5179 const MCExpr *ImmVal; 5180 if (getParser().parseExpression(ImmVal)) 5181 return true; 5182 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 5183 if (CE) { 5184 int32_t Val = CE->getValue(); 5185 if (isNegative && Val == 0) 5186 ImmVal = MCConstantExpr::create(INT32_MIN, getContext()); 5187 } 5188 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 5189 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 5190 5191 // There can be a trailing '!' on operands that we want as a separate 5192 // '!' Token operand. Handle that here. For example, the compatibility 5193 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'. 5194 if (Parser.getTok().is(AsmToken::Exclaim)) { 5195 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(), 5196 Parser.getTok().getLoc())); 5197 Parser.Lex(); // Eat exclaim token 5198 } 5199 return false; 5200 } 5201 // w/ a ':' after the '#', it's just like a plain ':'. 5202 // FALLTHROUGH 5203 } 5204 case AsmToken::Colon: { 5205 // ":lower16:" and ":upper16:" expression prefixes 5206 // FIXME: Check it's an expression prefix, 5207 // e.g. (FOO - :lower16:BAR) isn't legal. 5208 ARMMCExpr::VariantKind RefKind; 5209 if (parsePrefix(RefKind)) 5210 return true; 5211 5212 const MCExpr *SubExprVal; 5213 if (getParser().parseExpression(SubExprVal)) 5214 return true; 5215 5216 const MCExpr *ExprVal = ARMMCExpr::create(RefKind, SubExprVal, 5217 getContext()); 5218 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 5219 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 5220 return false; 5221 } 5222 case AsmToken::Equal: { 5223 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val) 5224 return Error(Parser.getTok().getLoc(), "unexpected token in operand"); 5225 5226 Parser.Lex(); // Eat '=' 5227 const MCExpr *SubExprVal; 5228 if (getParser().parseExpression(SubExprVal)) 5229 return true; 5230 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 5231 5232 const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal); 5233 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E)); 5234 return false; 5235 } 5236 } 5237 } 5238 5239 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 5240 // :lower16: and :upper16:. 5241 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 5242 MCAsmParser &Parser = getParser(); 5243 RefKind = ARMMCExpr::VK_ARM_None; 5244 5245 // consume an optional '#' (GNU compatibility) 5246 if (getLexer().is(AsmToken::Hash)) 5247 Parser.Lex(); 5248 5249 // :lower16: and :upper16: modifiers 5250 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 5251 Parser.Lex(); // Eat ':' 5252 5253 if (getLexer().isNot(AsmToken::Identifier)) { 5254 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 5255 return true; 5256 } 5257 5258 enum { 5259 COFF = (1 << MCObjectFileInfo::IsCOFF), 5260 ELF = (1 << MCObjectFileInfo::IsELF), 5261 MACHO = (1 << MCObjectFileInfo::IsMachO) 5262 }; 5263 static const struct PrefixEntry { 5264 const char *Spelling; 5265 ARMMCExpr::VariantKind VariantKind; 5266 uint8_t SupportedFormats; 5267 } PrefixEntries[] = { 5268 { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO }, 5269 { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO }, 5270 }; 5271 5272 StringRef IDVal = Parser.getTok().getIdentifier(); 5273 5274 const auto &Prefix = 5275 std::find_if(std::begin(PrefixEntries), std::end(PrefixEntries), 5276 [&IDVal](const PrefixEntry &PE) { 5277 return PE.Spelling == IDVal; 5278 }); 5279 if (Prefix == std::end(PrefixEntries)) { 5280 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 5281 return true; 5282 } 5283 5284 uint8_t CurrentFormat; 5285 switch (getContext().getObjectFileInfo()->getObjectFileType()) { 5286 case MCObjectFileInfo::IsMachO: 5287 CurrentFormat = MACHO; 5288 break; 5289 case MCObjectFileInfo::IsELF: 5290 CurrentFormat = ELF; 5291 break; 5292 case MCObjectFileInfo::IsCOFF: 5293 CurrentFormat = COFF; 5294 break; 5295 } 5296 5297 if (~Prefix->SupportedFormats & CurrentFormat) { 5298 Error(Parser.getTok().getLoc(), 5299 "cannot represent relocation in the current file format"); 5300 return true; 5301 } 5302 5303 RefKind = Prefix->VariantKind; 5304 Parser.Lex(); 5305 5306 if (getLexer().isNot(AsmToken::Colon)) { 5307 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 5308 return true; 5309 } 5310 Parser.Lex(); // Eat the last ':' 5311 5312 return false; 5313 } 5314 5315 /// \brief Given a mnemonic, split out possible predication code and carry 5316 /// setting letters to form a canonical mnemonic and flags. 5317 // 5318 // FIXME: Would be nice to autogen this. 5319 // FIXME: This is a bit of a maze of special cases. 5320 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 5321 unsigned &PredicationCode, 5322 bool &CarrySetting, 5323 unsigned &ProcessorIMod, 5324 StringRef &ITMask) { 5325 PredicationCode = ARMCC::AL; 5326 CarrySetting = false; 5327 ProcessorIMod = 0; 5328 5329 // Ignore some mnemonics we know aren't predicated forms. 5330 // 5331 // FIXME: Would be nice to autogen this. 5332 if ((Mnemonic == "movs" && isThumb()) || 5333 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 5334 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 5335 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 5336 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 5337 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" || 5338 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 5339 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 5340 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || 5341 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || 5342 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || 5343 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" || 5344 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" || 5345 Mnemonic.startswith("vsel")) 5346 return Mnemonic; 5347 5348 // First, split out any predication code. Ignore mnemonics we know aren't 5349 // predicated but do have a carry-set and so weren't caught above. 5350 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 5351 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 5352 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 5353 Mnemonic != "sbcs" && Mnemonic != "rscs") { 5354 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 5355 .Case("eq", ARMCC::EQ) 5356 .Case("ne", ARMCC::NE) 5357 .Case("hs", ARMCC::HS) 5358 .Case("cs", ARMCC::HS) 5359 .Case("lo", ARMCC::LO) 5360 .Case("cc", ARMCC::LO) 5361 .Case("mi", ARMCC::MI) 5362 .Case("pl", ARMCC::PL) 5363 .Case("vs", ARMCC::VS) 5364 .Case("vc", ARMCC::VC) 5365 .Case("hi", ARMCC::HI) 5366 .Case("ls", ARMCC::LS) 5367 .Case("ge", ARMCC::GE) 5368 .Case("lt", ARMCC::LT) 5369 .Case("gt", ARMCC::GT) 5370 .Case("le", ARMCC::LE) 5371 .Case("al", ARMCC::AL) 5372 .Default(~0U); 5373 if (CC != ~0U) { 5374 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 5375 PredicationCode = CC; 5376 } 5377 } 5378 5379 // Next, determine if we have a carry setting bit. We explicitly ignore all 5380 // the instructions we know end in 's'. 5381 if (Mnemonic.endswith("s") && 5382 !(Mnemonic == "cps" || Mnemonic == "mls" || 5383 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 5384 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 5385 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 5386 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || 5387 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || 5388 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || 5389 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" || 5390 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" || 5391 (Mnemonic == "movs" && isThumb()))) { 5392 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 5393 CarrySetting = true; 5394 } 5395 5396 // The "cps" instruction can have a interrupt mode operand which is glued into 5397 // the mnemonic. Check if this is the case, split it and parse the imod op 5398 if (Mnemonic.startswith("cps")) { 5399 // Split out any imod code. 5400 unsigned IMod = 5401 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 5402 .Case("ie", ARM_PROC::IE) 5403 .Case("id", ARM_PROC::ID) 5404 .Default(~0U); 5405 if (IMod != ~0U) { 5406 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 5407 ProcessorIMod = IMod; 5408 } 5409 } 5410 5411 // The "it" instruction has the condition mask on the end of the mnemonic. 5412 if (Mnemonic.startswith("it")) { 5413 ITMask = Mnemonic.slice(2, Mnemonic.size()); 5414 Mnemonic = Mnemonic.slice(0, 2); 5415 } 5416 5417 return Mnemonic; 5418 } 5419 5420 /// \brief Given a canonical mnemonic, determine if the instruction ever allows 5421 /// inclusion of carry set or predication code operands. 5422 // 5423 // FIXME: It would be nice to autogen this. 5424 void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst, 5425 bool &CanAcceptCarrySet, 5426 bool &CanAcceptPredicationCode) { 5427 CanAcceptCarrySet = 5428 Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 5429 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 5430 Mnemonic == "add" || Mnemonic == "adc" || Mnemonic == "mul" || 5431 Mnemonic == "bic" || Mnemonic == "asr" || Mnemonic == "orr" || 5432 Mnemonic == "mvn" || Mnemonic == "rsb" || Mnemonic == "rsc" || 5433 Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "eor" || 5434 Mnemonic == "neg" || Mnemonic == "vfm" || Mnemonic == "vfnm" || 5435 (!isThumb() && 5436 (Mnemonic == "smull" || Mnemonic == "mov" || Mnemonic == "mla" || 5437 Mnemonic == "smlal" || Mnemonic == "umlal" || Mnemonic == "umull")); 5438 5439 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" || 5440 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" || 5441 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" || 5442 Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") || 5443 Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" || 5444 Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" || 5445 Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" || 5446 Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" || 5447 Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" || 5448 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") || 5449 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) { 5450 // These mnemonics are never predicable 5451 CanAcceptPredicationCode = false; 5452 } else if (!isThumb()) { 5453 // Some instructions are only predicable in Thumb mode 5454 CanAcceptPredicationCode = 5455 Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" && 5456 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" && 5457 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" && 5458 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" && 5459 Mnemonic != "ldc2" && Mnemonic != "ldc2l" && Mnemonic != "stc2" && 5460 Mnemonic != "stc2l" && !Mnemonic.startswith("rfe") && 5461 !Mnemonic.startswith("srs"); 5462 } else if (isThumbOne()) { 5463 if (hasV6MOps()) 5464 CanAcceptPredicationCode = Mnemonic != "movs"; 5465 else 5466 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs"; 5467 } else 5468 CanAcceptPredicationCode = true; 5469 } 5470 5471 // \brief Some Thumb instructions have two operand forms that are not 5472 // available as three operand, convert to two operand form if possible. 5473 // 5474 // FIXME: We would really like to be able to tablegen'erate this. 5475 void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic, 5476 bool CarrySetting, 5477 OperandVector &Operands) { 5478 if (Operands.size() != 6) 5479 return; 5480 5481 const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]); 5482 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]); 5483 if (!Op3.isReg() || !Op4.isReg()) 5484 return; 5485 5486 auto Op3Reg = Op3.getReg(); 5487 auto Op4Reg = Op4.getReg(); 5488 5489 // For most Thumb2 cases we just generate the 3 operand form and reduce 5490 // it in processInstruction(), but the 3 operand form of ADD (t2ADDrr) 5491 // won't accept SP or PC so we do the transformation here taking care 5492 // with immediate range in the 'add sp, sp #imm' case. 5493 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]); 5494 if (isThumbTwo()) { 5495 if (Mnemonic != "add") 5496 return; 5497 bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC || 5498 (Op5.isReg() && Op5.getReg() == ARM::PC); 5499 if (!TryTransform) { 5500 TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP || 5501 (Op5.isReg() && Op5.getReg() == ARM::SP)) && 5502 !(Op3Reg == ARM::SP && Op4Reg == ARM::SP && 5503 Op5.isImm() && !Op5.isImm0_508s4()); 5504 } 5505 if (!TryTransform) 5506 return; 5507 } else if (!isThumbOne()) 5508 return; 5509 5510 if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" || 5511 Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" || 5512 Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" || 5513 Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic")) 5514 return; 5515 5516 // If first 2 operands of a 3 operand instruction are the same 5517 // then transform to 2 operand version of the same instruction 5518 // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1' 5519 bool Transform = Op3Reg == Op4Reg; 5520 5521 // For communtative operations, we might be able to transform if we swap 5522 // Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially 5523 // as tADDrsp. 5524 const ARMOperand *LastOp = &Op5; 5525 bool Swap = false; 5526 if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() && 5527 ((Mnemonic == "add" && Op4Reg != ARM::SP) || 5528 Mnemonic == "and" || Mnemonic == "eor" || 5529 Mnemonic == "adc" || Mnemonic == "orr")) { 5530 Swap = true; 5531 LastOp = &Op4; 5532 Transform = true; 5533 } 5534 5535 // If both registers are the same then remove one of them from 5536 // the operand list, with certain exceptions. 5537 if (Transform) { 5538 // Don't transform 'adds Rd, Rd, Rm' or 'sub{s} Rd, Rd, Rm' because the 5539 // 2 operand forms don't exist. 5540 if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") && 5541 LastOp->isReg()) 5542 Transform = false; 5543 5544 // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into 5545 // 3-bits because the ARMARM says not to. 5546 if ((Mnemonic == "add" || Mnemonic == "sub") && LastOp->isImm0_7()) 5547 Transform = false; 5548 } 5549 5550 if (Transform) { 5551 if (Swap) 5552 std::swap(Op4, Op5); 5553 Operands.erase(Operands.begin() + 3); 5554 } 5555 } 5556 5557 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 5558 OperandVector &Operands) { 5559 // FIXME: This is all horribly hacky. We really need a better way to deal 5560 // with optional operands like this in the matcher table. 5561 5562 // The 'mov' mnemonic is special. One variant has a cc_out operand, while 5563 // another does not. Specifically, the MOVW instruction does not. So we 5564 // special case it here and remove the defaulted (non-setting) cc_out 5565 // operand if that's the instruction we're trying to match. 5566 // 5567 // We do this as post-processing of the explicit operands rather than just 5568 // conditionally adding the cc_out in the first place because we need 5569 // to check the type of the parsed immediate operand. 5570 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 5571 !static_cast<ARMOperand &>(*Operands[4]).isModImm() && 5572 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() && 5573 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) 5574 return true; 5575 5576 // Register-register 'add' for thumb does not have a cc_out operand 5577 // when there are only two register operands. 5578 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 5579 static_cast<ARMOperand &>(*Operands[3]).isReg() && 5580 static_cast<ARMOperand &>(*Operands[4]).isReg() && 5581 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) 5582 return true; 5583 // Register-register 'add' for thumb does not have a cc_out operand 5584 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 5585 // have to check the immediate range here since Thumb2 has a variant 5586 // that can handle a different range and has a cc_out operand. 5587 if (((isThumb() && Mnemonic == "add") || 5588 (isThumbTwo() && Mnemonic == "sub")) && 5589 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && 5590 static_cast<ARMOperand &>(*Operands[4]).isReg() && 5591 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP && 5592 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 5593 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) || 5594 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4())) 5595 return true; 5596 // For Thumb2, add/sub immediate does not have a cc_out operand for the 5597 // imm0_4095 variant. That's the least-preferred variant when 5598 // selecting via the generic "add" mnemonic, so to know that we 5599 // should remove the cc_out operand, we have to explicitly check that 5600 // it's not one of the other variants. Ugh. 5601 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 5602 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && 5603 static_cast<ARMOperand &>(*Operands[4]).isReg() && 5604 static_cast<ARMOperand &>(*Operands[5]).isImm()) { 5605 // Nest conditions rather than one big 'if' statement for readability. 5606 // 5607 // If both registers are low, we're in an IT block, and the immediate is 5608 // in range, we should use encoding T1 instead, which has a cc_out. 5609 if (inITBlock() && 5610 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) && 5611 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) && 5612 static_cast<ARMOperand &>(*Operands[5]).isImm0_7()) 5613 return false; 5614 // Check against T3. If the second register is the PC, this is an 5615 // alternate form of ADR, which uses encoding T4, so check for that too. 5616 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC && 5617 static_cast<ARMOperand &>(*Operands[5]).isT2SOImm()) 5618 return false; 5619 5620 // Otherwise, we use encoding T4, which does not have a cc_out 5621 // operand. 5622 return true; 5623 } 5624 5625 // The thumb2 multiply instruction doesn't have a CCOut register, so 5626 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 5627 // use the 16-bit encoding or not. 5628 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 5629 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 5630 static_cast<ARMOperand &>(*Operands[3]).isReg() && 5631 static_cast<ARMOperand &>(*Operands[4]).isReg() && 5632 static_cast<ARMOperand &>(*Operands[5]).isReg() && 5633 // If the registers aren't low regs, the destination reg isn't the 5634 // same as one of the source regs, or the cc_out operand is zero 5635 // outside of an IT block, we have to use the 32-bit encoding, so 5636 // remove the cc_out operand. 5637 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || 5638 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || 5639 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) || 5640 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() != 5641 static_cast<ARMOperand &>(*Operands[5]).getReg() && 5642 static_cast<ARMOperand &>(*Operands[3]).getReg() != 5643 static_cast<ARMOperand &>(*Operands[4]).getReg()))) 5644 return true; 5645 5646 // Also check the 'mul' syntax variant that doesn't specify an explicit 5647 // destination register. 5648 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && 5649 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 5650 static_cast<ARMOperand &>(*Operands[3]).isReg() && 5651 static_cast<ARMOperand &>(*Operands[4]).isReg() && 5652 // If the registers aren't low regs or the cc_out operand is zero 5653 // outside of an IT block, we have to use the 32-bit encoding, so 5654 // remove the cc_out operand. 5655 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || 5656 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || 5657 !inITBlock())) 5658 return true; 5659 5660 5661 5662 // Register-register 'add/sub' for thumb does not have a cc_out operand 5663 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 5664 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 5665 // right, this will result in better diagnostics (which operand is off) 5666 // anyway. 5667 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 5668 (Operands.size() == 5 || Operands.size() == 6) && 5669 static_cast<ARMOperand &>(*Operands[3]).isReg() && 5670 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP && 5671 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 5672 (static_cast<ARMOperand &>(*Operands[4]).isImm() || 5673 (Operands.size() == 6 && 5674 static_cast<ARMOperand &>(*Operands[5]).isImm()))) 5675 return true; 5676 5677 return false; 5678 } 5679 5680 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic, 5681 OperandVector &Operands) { 5682 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON 5683 unsigned RegIdx = 3; 5684 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") && 5685 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32") { 5686 if (static_cast<ARMOperand &>(*Operands[3]).isToken() && 5687 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32") 5688 RegIdx = 4; 5689 5690 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() && 5691 (ARMMCRegisterClasses[ARM::DPRRegClassID].contains( 5692 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) || 5693 ARMMCRegisterClasses[ARM::QPRRegClassID].contains( 5694 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()))) 5695 return true; 5696 } 5697 return false; 5698 } 5699 5700 static bool isDataTypeToken(StringRef Tok) { 5701 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || 5702 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || 5703 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || 5704 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || 5705 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || 5706 Tok == ".f" || Tok == ".d"; 5707 } 5708 5709 // FIXME: This bit should probably be handled via an explicit match class 5710 // in the .td files that matches the suffix instead of having it be 5711 // a literal string token the way it is now. 5712 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { 5713 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); 5714 } 5715 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features, 5716 unsigned VariantID); 5717 5718 static bool RequiresVFPRegListValidation(StringRef Inst, 5719 bool &AcceptSinglePrecisionOnly, 5720 bool &AcceptDoublePrecisionOnly) { 5721 if (Inst.size() < 7) 5722 return false; 5723 5724 if (Inst.startswith("fldm") || Inst.startswith("fstm")) { 5725 StringRef AddressingMode = Inst.substr(4, 2); 5726 if (AddressingMode == "ia" || AddressingMode == "db" || 5727 AddressingMode == "ea" || AddressingMode == "fd") { 5728 AcceptSinglePrecisionOnly = Inst[6] == 's'; 5729 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x'; 5730 return true; 5731 } 5732 } 5733 5734 return false; 5735 } 5736 5737 /// Parse an arm instruction mnemonic followed by its operands. 5738 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 5739 SMLoc NameLoc, OperandVector &Operands) { 5740 MCAsmParser &Parser = getParser(); 5741 // FIXME: Can this be done via tablegen in some fashion? 5742 bool RequireVFPRegisterListCheck; 5743 bool AcceptSinglePrecisionOnly; 5744 bool AcceptDoublePrecisionOnly; 5745 RequireVFPRegisterListCheck = 5746 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly, 5747 AcceptDoublePrecisionOnly); 5748 5749 // Apply mnemonic aliases before doing anything else, as the destination 5750 // mnemonic may include suffices and we want to handle them normally. 5751 // The generic tblgen'erated code does this later, at the start of 5752 // MatchInstructionImpl(), but that's too late for aliases that include 5753 // any sort of suffix. 5754 uint64_t AvailableFeatures = getAvailableFeatures(); 5755 unsigned AssemblerDialect = getParser().getAssemblerDialect(); 5756 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect); 5757 5758 // First check for the ARM-specific .req directive. 5759 if (Parser.getTok().is(AsmToken::Identifier) && 5760 Parser.getTok().getIdentifier() == ".req") { 5761 parseDirectiveReq(Name, NameLoc); 5762 // We always return 'error' for this, as we're done with this 5763 // statement and don't need to match the 'instruction." 5764 return true; 5765 } 5766 5767 // Create the leading tokens for the mnemonic, split by '.' characters. 5768 size_t Start = 0, Next = Name.find('.'); 5769 StringRef Mnemonic = Name.slice(Start, Next); 5770 5771 // Split out the predication code and carry setting flag from the mnemonic. 5772 unsigned PredicationCode; 5773 unsigned ProcessorIMod; 5774 bool CarrySetting; 5775 StringRef ITMask; 5776 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 5777 ProcessorIMod, ITMask); 5778 5779 // In Thumb1, only the branch (B) instruction can be predicated. 5780 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 5781 Parser.eatToEndOfStatement(); 5782 return Error(NameLoc, "conditional execution not supported in Thumb1"); 5783 } 5784 5785 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 5786 5787 // Handle the IT instruction ITMask. Convert it to a bitmask. This 5788 // is the mask as it will be for the IT encoding if the conditional 5789 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 5790 // where the conditional bit0 is zero, the instruction post-processing 5791 // will adjust the mask accordingly. 5792 if (Mnemonic == "it") { 5793 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 5794 if (ITMask.size() > 3) { 5795 Parser.eatToEndOfStatement(); 5796 return Error(Loc, "too many conditions on IT instruction"); 5797 } 5798 unsigned Mask = 8; 5799 for (unsigned i = ITMask.size(); i != 0; --i) { 5800 char pos = ITMask[i - 1]; 5801 if (pos != 't' && pos != 'e') { 5802 Parser.eatToEndOfStatement(); 5803 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 5804 } 5805 Mask >>= 1; 5806 if (ITMask[i - 1] == 't') 5807 Mask |= 8; 5808 } 5809 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 5810 } 5811 5812 // FIXME: This is all a pretty gross hack. We should automatically handle 5813 // optional operands like this via tblgen. 5814 5815 // Next, add the CCOut and ConditionCode operands, if needed. 5816 // 5817 // For mnemonics which can ever incorporate a carry setting bit or predication 5818 // code, our matching model involves us always generating CCOut and 5819 // ConditionCode operands to match the mnemonic "as written" and then we let 5820 // the matcher deal with finding the right instruction or generating an 5821 // appropriate error. 5822 bool CanAcceptCarrySet, CanAcceptPredicationCode; 5823 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode); 5824 5825 // If we had a carry-set on an instruction that can't do that, issue an 5826 // error. 5827 if (!CanAcceptCarrySet && CarrySetting) { 5828 Parser.eatToEndOfStatement(); 5829 return Error(NameLoc, "instruction '" + Mnemonic + 5830 "' can not set flags, but 's' suffix specified"); 5831 } 5832 // If we had a predication code on an instruction that can't do that, issue an 5833 // error. 5834 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 5835 Parser.eatToEndOfStatement(); 5836 return Error(NameLoc, "instruction '" + Mnemonic + 5837 "' is not predicable, but condition code specified"); 5838 } 5839 5840 // Add the carry setting operand, if necessary. 5841 if (CanAcceptCarrySet) { 5842 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 5843 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 5844 Loc)); 5845 } 5846 5847 // Add the predication code operand, if necessary. 5848 if (CanAcceptPredicationCode) { 5849 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 5850 CarrySetting); 5851 Operands.push_back(ARMOperand::CreateCondCode( 5852 ARMCC::CondCodes(PredicationCode), Loc)); 5853 } 5854 5855 // Add the processor imod operand, if necessary. 5856 if (ProcessorIMod) { 5857 Operands.push_back(ARMOperand::CreateImm( 5858 MCConstantExpr::create(ProcessorIMod, getContext()), 5859 NameLoc, NameLoc)); 5860 } else if (Mnemonic == "cps" && isMClass()) { 5861 return Error(NameLoc, "instruction 'cps' requires effect for M-class"); 5862 } 5863 5864 // Add the remaining tokens in the mnemonic. 5865 while (Next != StringRef::npos) { 5866 Start = Next; 5867 Next = Name.find('.', Start + 1); 5868 StringRef ExtraToken = Name.slice(Start, Next); 5869 5870 // Some NEON instructions have an optional datatype suffix that is 5871 // completely ignored. Check for that. 5872 if (isDataTypeToken(ExtraToken) && 5873 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) 5874 continue; 5875 5876 // For for ARM mode generate an error if the .n qualifier is used. 5877 if (ExtraToken == ".n" && !isThumb()) { 5878 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5879 Parser.eatToEndOfStatement(); 5880 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in " 5881 "arm mode"); 5882 } 5883 5884 // The .n qualifier is always discarded as that is what the tables 5885 // and matcher expect. In ARM mode the .w qualifier has no effect, 5886 // so discard it to avoid errors that can be caused by the matcher. 5887 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) { 5888 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5889 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 5890 } 5891 } 5892 5893 // Read the remaining operands. 5894 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5895 // Read the first operand. 5896 if (parseOperand(Operands, Mnemonic)) { 5897 Parser.eatToEndOfStatement(); 5898 return true; 5899 } 5900 5901 while (getLexer().is(AsmToken::Comma)) { 5902 Parser.Lex(); // Eat the comma. 5903 5904 // Parse and remember the operand. 5905 if (parseOperand(Operands, Mnemonic)) { 5906 Parser.eatToEndOfStatement(); 5907 return true; 5908 } 5909 } 5910 } 5911 5912 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5913 SMLoc Loc = getLexer().getLoc(); 5914 Parser.eatToEndOfStatement(); 5915 return Error(Loc, "unexpected token in argument list"); 5916 } 5917 5918 Parser.Lex(); // Consume the EndOfStatement 5919 5920 if (RequireVFPRegisterListCheck) { 5921 ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back()); 5922 if (AcceptSinglePrecisionOnly && !Op.isSPRRegList()) 5923 return Error(Op.getStartLoc(), 5924 "VFP/Neon single precision register expected"); 5925 if (AcceptDoublePrecisionOnly && !Op.isDPRRegList()) 5926 return Error(Op.getStartLoc(), 5927 "VFP/Neon double precision register expected"); 5928 } 5929 5930 tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands); 5931 5932 // Some instructions, mostly Thumb, have forms for the same mnemonic that 5933 // do and don't have a cc_out optional-def operand. With some spot-checks 5934 // of the operand list, we can figure out which variant we're trying to 5935 // parse and adjust accordingly before actually matching. We shouldn't ever 5936 // try to remove a cc_out operand that was explicitly set on the 5937 // mnemonic, of course (CarrySetting == true). Reason number #317 the 5938 // table driven matcher doesn't fit well with the ARM instruction set. 5939 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) 5940 Operands.erase(Operands.begin() + 1); 5941 5942 // Some instructions have the same mnemonic, but don't always 5943 // have a predicate. Distinguish them here and delete the 5944 // predicate if needed. 5945 if (shouldOmitPredicateOperand(Mnemonic, Operands)) 5946 Operands.erase(Operands.begin() + 1); 5947 5948 // ARM mode 'blx' need special handling, as the register operand version 5949 // is predicable, but the label operand version is not. So, we can't rely 5950 // on the Mnemonic based checking to correctly figure out when to put 5951 // a k_CondCode operand in the list. If we're trying to match the label 5952 // version, remove the k_CondCode operand here. 5953 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 5954 static_cast<ARMOperand &>(*Operands[2]).isImm()) 5955 Operands.erase(Operands.begin() + 1); 5956 5957 // Adjust operands of ldrexd/strexd to MCK_GPRPair. 5958 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, 5959 // a single GPRPair reg operand is used in the .td file to replace the two 5960 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically 5961 // expressed as a GPRPair, so we have to manually merge them. 5962 // FIXME: We would really like to be able to tablegen'erate this. 5963 if (!isThumb() && Operands.size() > 4 && 5964 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" || 5965 Mnemonic == "stlexd")) { 5966 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd"); 5967 unsigned Idx = isLoad ? 2 : 3; 5968 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]); 5969 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]); 5970 5971 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID); 5972 // Adjust only if Op1 and Op2 are GPRs. 5973 if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) && 5974 MRC.contains(Op2.getReg())) { 5975 unsigned Reg1 = Op1.getReg(); 5976 unsigned Reg2 = Op2.getReg(); 5977 unsigned Rt = MRI->getEncodingValue(Reg1); 5978 unsigned Rt2 = MRI->getEncodingValue(Reg2); 5979 5980 // Rt2 must be Rt + 1 and Rt must be even. 5981 if (Rt + 1 != Rt2 || (Rt & 1)) { 5982 Error(Op2.getStartLoc(), isLoad 5983 ? "destination operands must be sequential" 5984 : "source operands must be sequential"); 5985 return true; 5986 } 5987 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0, 5988 &(MRI->getRegClass(ARM::GPRPairRegClassID))); 5989 Operands[Idx] = 5990 ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc()); 5991 Operands.erase(Operands.begin() + Idx + 1); 5992 } 5993 } 5994 5995 // GNU Assembler extension (compatibility) 5996 if ((Mnemonic == "ldrd" || Mnemonic == "strd")) { 5997 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]); 5998 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); 5999 if (Op3.isMem()) { 6000 assert(Op2.isReg() && "expected register argument"); 6001 6002 unsigned SuperReg = MRI->getMatchingSuperReg( 6003 Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID)); 6004 6005 assert(SuperReg && "expected register pair"); 6006 6007 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1); 6008 6009 Operands.insert( 6010 Operands.begin() + 3, 6011 ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc())); 6012 } 6013 } 6014 6015 // FIXME: As said above, this is all a pretty gross hack. This instruction 6016 // does not fit with other "subs" and tblgen. 6017 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction 6018 // so the Mnemonic is the original name "subs" and delete the predicate 6019 // operand so it will match the table entry. 6020 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 && 6021 static_cast<ARMOperand &>(*Operands[3]).isReg() && 6022 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC && 6023 static_cast<ARMOperand &>(*Operands[4]).isReg() && 6024 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR && 6025 static_cast<ARMOperand &>(*Operands[5]).isImm()) { 6026 Operands.front() = ARMOperand::CreateToken(Name, NameLoc); 6027 Operands.erase(Operands.begin() + 1); 6028 } 6029 return false; 6030 } 6031 6032 // Validate context-sensitive operand constraints. 6033 6034 // return 'true' if register list contains non-low GPR registers, 6035 // 'false' otherwise. If Reg is in the register list or is HiReg, set 6036 // 'containsReg' to true. 6037 static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo, 6038 unsigned Reg, unsigned HiReg, 6039 bool &containsReg) { 6040 containsReg = false; 6041 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 6042 unsigned OpReg = Inst.getOperand(i).getReg(); 6043 if (OpReg == Reg) 6044 containsReg = true; 6045 // Anything other than a low register isn't legal here. 6046 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 6047 return true; 6048 } 6049 return false; 6050 } 6051 6052 // Check if the specified regisgter is in the register list of the inst, 6053 // starting at the indicated operand number. 6054 static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) { 6055 for (unsigned i = OpNo, e = Inst.getNumOperands(); i < e; ++i) { 6056 unsigned OpReg = Inst.getOperand(i).getReg(); 6057 if (OpReg == Reg) 6058 return true; 6059 } 6060 return false; 6061 } 6062 6063 // Return true if instruction has the interesting property of being 6064 // allowed in IT blocks, but not being predicable. 6065 static bool instIsBreakpoint(const MCInst &Inst) { 6066 return Inst.getOpcode() == ARM::tBKPT || 6067 Inst.getOpcode() == ARM::BKPT || 6068 Inst.getOpcode() == ARM::tHLT || 6069 Inst.getOpcode() == ARM::HLT; 6070 6071 } 6072 6073 bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst, 6074 const OperandVector &Operands, 6075 unsigned ListNo, bool IsARPop) { 6076 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); 6077 bool HasWritebackToken = Op.isToken() && Op.getToken() == "!"; 6078 6079 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP); 6080 bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR); 6081 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC); 6082 6083 if (!IsARPop && ListContainsSP) 6084 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), 6085 "SP may not be in the register list"); 6086 else if (ListContainsPC && ListContainsLR) 6087 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), 6088 "PC and LR may not be in the register list simultaneously"); 6089 else if (inITBlock() && !lastInITBlock() && ListContainsPC) 6090 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), 6091 "instruction must be outside of IT block or the last " 6092 "instruction in an IT block"); 6093 return false; 6094 } 6095 6096 bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst, 6097 const OperandVector &Operands, 6098 unsigned ListNo) { 6099 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); 6100 bool HasWritebackToken = Op.isToken() && Op.getToken() == "!"; 6101 6102 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP); 6103 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC); 6104 6105 if (ListContainsSP && ListContainsPC) 6106 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), 6107 "SP and PC may not be in the register list"); 6108 else if (ListContainsSP) 6109 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), 6110 "SP may not be in the register list"); 6111 else if (ListContainsPC) 6112 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), 6113 "PC may not be in the register list"); 6114 return false; 6115 } 6116 6117 // FIXME: We would really like to be able to tablegen'erate this. 6118 bool ARMAsmParser::validateInstruction(MCInst &Inst, 6119 const OperandVector &Operands) { 6120 const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); 6121 SMLoc Loc = Operands[0]->getStartLoc(); 6122 6123 // Check the IT block state first. 6124 // NOTE: BKPT and HLT instructions have the interesting property of being 6125 // allowed in IT blocks, but not being predicable. They just always execute. 6126 if (inITBlock() && !instIsBreakpoint(Inst)) { 6127 unsigned Bit = 1; 6128 if (ITState.FirstCond) 6129 ITState.FirstCond = false; 6130 else 6131 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 6132 // The instruction must be predicable. 6133 if (!MCID.isPredicable()) 6134 return Error(Loc, "instructions in IT block must be predicable"); 6135 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 6136 unsigned ITCond = Bit ? ITState.Cond : 6137 ARMCC::getOppositeCondition(ITState.Cond); 6138 if (Cond != ITCond) { 6139 // Find the condition code Operand to get its SMLoc information. 6140 SMLoc CondLoc; 6141 for (unsigned I = 1; I < Operands.size(); ++I) 6142 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode()) 6143 CondLoc = Operands[I]->getStartLoc(); 6144 return Error(CondLoc, "incorrect condition in IT block; got '" + 6145 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 6146 "', but expected '" + 6147 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 6148 } 6149 // Check for non-'al' condition codes outside of the IT block. 6150 } else if (isThumbTwo() && MCID.isPredicable() && 6151 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 6152 ARMCC::AL && Inst.getOpcode() != ARM::tBcc && 6153 Inst.getOpcode() != ARM::t2Bcc) 6154 return Error(Loc, "predicated instructions must be in IT block"); 6155 6156 const unsigned Opcode = Inst.getOpcode(); 6157 switch (Opcode) { 6158 case ARM::LDRD: 6159 case ARM::LDRD_PRE: 6160 case ARM::LDRD_POST: { 6161 const unsigned RtReg = Inst.getOperand(0).getReg(); 6162 6163 // Rt can't be R14. 6164 if (RtReg == ARM::LR) 6165 return Error(Operands[3]->getStartLoc(), 6166 "Rt can't be R14"); 6167 6168 const unsigned Rt = MRI->getEncodingValue(RtReg); 6169 // Rt must be even-numbered. 6170 if ((Rt & 1) == 1) 6171 return Error(Operands[3]->getStartLoc(), 6172 "Rt must be even-numbered"); 6173 6174 // Rt2 must be Rt + 1. 6175 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 6176 if (Rt2 != Rt + 1) 6177 return Error(Operands[3]->getStartLoc(), 6178 "destination operands must be sequential"); 6179 6180 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) { 6181 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); 6182 // For addressing modes with writeback, the base register needs to be 6183 // different from the destination registers. 6184 if (Rn == Rt || Rn == Rt2) 6185 return Error(Operands[3]->getStartLoc(), 6186 "base register needs to be different from destination " 6187 "registers"); 6188 } 6189 6190 return false; 6191 } 6192 case ARM::t2LDRDi8: 6193 case ARM::t2LDRD_PRE: 6194 case ARM::t2LDRD_POST: { 6195 // Rt2 must be different from Rt. 6196 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 6197 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 6198 if (Rt2 == Rt) 6199 return Error(Operands[3]->getStartLoc(), 6200 "destination operands can't be identical"); 6201 return false; 6202 } 6203 case ARM::t2BXJ: { 6204 const unsigned RmReg = Inst.getOperand(0).getReg(); 6205 // Rm = SP is no longer unpredictable in v8-A 6206 if (RmReg == ARM::SP && !hasV8Ops()) 6207 return Error(Operands[2]->getStartLoc(), 6208 "r13 (SP) is an unpredictable operand to BXJ"); 6209 return false; 6210 } 6211 case ARM::STRD: { 6212 // Rt2 must be Rt + 1. 6213 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 6214 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 6215 if (Rt2 != Rt + 1) 6216 return Error(Operands[3]->getStartLoc(), 6217 "source operands must be sequential"); 6218 return false; 6219 } 6220 case ARM::STRD_PRE: 6221 case ARM::STRD_POST: { 6222 // Rt2 must be Rt + 1. 6223 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 6224 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 6225 if (Rt2 != Rt + 1) 6226 return Error(Operands[3]->getStartLoc(), 6227 "source operands must be sequential"); 6228 return false; 6229 } 6230 case ARM::STR_PRE_IMM: 6231 case ARM::STR_PRE_REG: 6232 case ARM::STR_POST_IMM: 6233 case ARM::STR_POST_REG: 6234 case ARM::STRH_PRE: 6235 case ARM::STRH_POST: 6236 case ARM::STRB_PRE_IMM: 6237 case ARM::STRB_PRE_REG: 6238 case ARM::STRB_POST_IMM: 6239 case ARM::STRB_POST_REG: { 6240 // Rt must be different from Rn. 6241 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 6242 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 6243 6244 if (Rt == Rn) 6245 return Error(Operands[3]->getStartLoc(), 6246 "source register and base register can't be identical"); 6247 return false; 6248 } 6249 case ARM::LDR_PRE_IMM: 6250 case ARM::LDR_PRE_REG: 6251 case ARM::LDR_POST_IMM: 6252 case ARM::LDR_POST_REG: 6253 case ARM::LDRH_PRE: 6254 case ARM::LDRH_POST: 6255 case ARM::LDRSH_PRE: 6256 case ARM::LDRSH_POST: 6257 case ARM::LDRB_PRE_IMM: 6258 case ARM::LDRB_PRE_REG: 6259 case ARM::LDRB_POST_IMM: 6260 case ARM::LDRB_POST_REG: 6261 case ARM::LDRSB_PRE: 6262 case ARM::LDRSB_POST: { 6263 // Rt must be different from Rn. 6264 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 6265 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 6266 6267 if (Rt == Rn) 6268 return Error(Operands[3]->getStartLoc(), 6269 "destination register and base register can't be identical"); 6270 return false; 6271 } 6272 case ARM::SBFX: 6273 case ARM::UBFX: { 6274 // Width must be in range [1, 32-lsb]. 6275 unsigned LSB = Inst.getOperand(2).getImm(); 6276 unsigned Widthm1 = Inst.getOperand(3).getImm(); 6277 if (Widthm1 >= 32 - LSB) 6278 return Error(Operands[5]->getStartLoc(), 6279 "bitfield width must be in range [1,32-lsb]"); 6280 return false; 6281 } 6282 // Notionally handles ARM::tLDMIA_UPD too. 6283 case ARM::tLDMIA: { 6284 // If we're parsing Thumb2, the .w variant is available and handles 6285 // most cases that are normally illegal for a Thumb1 LDM instruction. 6286 // We'll make the transformation in processInstruction() if necessary. 6287 // 6288 // Thumb LDM instructions are writeback iff the base register is not 6289 // in the register list. 6290 unsigned Rn = Inst.getOperand(0).getReg(); 6291 bool HasWritebackToken = 6292 (static_cast<ARMOperand &>(*Operands[3]).isToken() && 6293 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); 6294 bool ListContainsBase; 6295 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo()) 6296 return Error(Operands[3 + HasWritebackToken]->getStartLoc(), 6297 "registers must be in range r0-r7"); 6298 // If we should have writeback, then there should be a '!' token. 6299 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo()) 6300 return Error(Operands[2]->getStartLoc(), 6301 "writeback operator '!' expected"); 6302 // If we should not have writeback, there must not be a '!'. This is 6303 // true even for the 32-bit wide encodings. 6304 if (ListContainsBase && HasWritebackToken) 6305 return Error(Operands[3]->getStartLoc(), 6306 "writeback operator '!' not allowed when base register " 6307 "in register list"); 6308 6309 if (validatetLDMRegList(Inst, Operands, 3)) 6310 return true; 6311 break; 6312 } 6313 case ARM::LDMIA_UPD: 6314 case ARM::LDMDB_UPD: 6315 case ARM::LDMIB_UPD: 6316 case ARM::LDMDA_UPD: 6317 // ARM variants loading and updating the same register are only officially 6318 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before. 6319 if (!hasV7Ops()) 6320 break; 6321 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 6322 return Error(Operands.back()->getStartLoc(), 6323 "writeback register not allowed in register list"); 6324 break; 6325 case ARM::t2LDMIA: 6326 case ARM::t2LDMDB: 6327 if (validatetLDMRegList(Inst, Operands, 3)) 6328 return true; 6329 break; 6330 case ARM::t2STMIA: 6331 case ARM::t2STMDB: 6332 if (validatetSTMRegList(Inst, Operands, 3)) 6333 return true; 6334 break; 6335 case ARM::t2LDMIA_UPD: 6336 case ARM::t2LDMDB_UPD: 6337 case ARM::t2STMIA_UPD: 6338 case ARM::t2STMDB_UPD: { 6339 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 6340 return Error(Operands.back()->getStartLoc(), 6341 "writeback register not allowed in register list"); 6342 6343 if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) { 6344 if (validatetLDMRegList(Inst, Operands, 3)) 6345 return true; 6346 } else { 6347 if (validatetSTMRegList(Inst, Operands, 3)) 6348 return true; 6349 } 6350 break; 6351 } 6352 case ARM::sysLDMIA_UPD: 6353 case ARM::sysLDMDA_UPD: 6354 case ARM::sysLDMDB_UPD: 6355 case ARM::sysLDMIB_UPD: 6356 if (!listContainsReg(Inst, 3, ARM::PC)) 6357 return Error(Operands[4]->getStartLoc(), 6358 "writeback register only allowed on system LDM " 6359 "if PC in register-list"); 6360 break; 6361 case ARM::sysSTMIA_UPD: 6362 case ARM::sysSTMDA_UPD: 6363 case ARM::sysSTMDB_UPD: 6364 case ARM::sysSTMIB_UPD: 6365 return Error(Operands[2]->getStartLoc(), 6366 "system STM cannot have writeback register"); 6367 case ARM::tMUL: { 6368 // The second source operand must be the same register as the destination 6369 // operand. 6370 // 6371 // In this case, we must directly check the parsed operands because the 6372 // cvtThumbMultiply() function is written in such a way that it guarantees 6373 // this first statement is always true for the new Inst. Essentially, the 6374 // destination is unconditionally copied into the second source operand 6375 // without checking to see if it matches what we actually parsed. 6376 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() != 6377 ((ARMOperand &)*Operands[5]).getReg()) && 6378 (((ARMOperand &)*Operands[3]).getReg() != 6379 ((ARMOperand &)*Operands[4]).getReg())) { 6380 return Error(Operands[3]->getStartLoc(), 6381 "destination register must match source register"); 6382 } 6383 break; 6384 } 6385 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2, 6386 // so only issue a diagnostic for thumb1. The instructions will be 6387 // switched to the t2 encodings in processInstruction() if necessary. 6388 case ARM::tPOP: { 6389 bool ListContainsBase; 6390 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) && 6391 !isThumbTwo()) 6392 return Error(Operands[2]->getStartLoc(), 6393 "registers must be in range r0-r7 or pc"); 6394 if (validatetLDMRegList(Inst, Operands, 2, !isMClass())) 6395 return true; 6396 break; 6397 } 6398 case ARM::tPUSH: { 6399 bool ListContainsBase; 6400 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) && 6401 !isThumbTwo()) 6402 return Error(Operands[2]->getStartLoc(), 6403 "registers must be in range r0-r7 or lr"); 6404 if (validatetSTMRegList(Inst, Operands, 2)) 6405 return true; 6406 break; 6407 } 6408 case ARM::tSTMIA_UPD: { 6409 bool ListContainsBase, InvalidLowList; 6410 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(), 6411 0, ListContainsBase); 6412 if (InvalidLowList && !isThumbTwo()) 6413 return Error(Operands[4]->getStartLoc(), 6414 "registers must be in range r0-r7"); 6415 6416 // This would be converted to a 32-bit stm, but that's not valid if the 6417 // writeback register is in the list. 6418 if (InvalidLowList && ListContainsBase) 6419 return Error(Operands[4]->getStartLoc(), 6420 "writeback operator '!' not allowed when base register " 6421 "in register list"); 6422 6423 if (validatetSTMRegList(Inst, Operands, 4)) 6424 return true; 6425 break; 6426 } 6427 case ARM::tADDrSP: { 6428 // If the non-SP source operand and the destination operand are not the 6429 // same, we need thumb2 (for the wide encoding), or we have an error. 6430 if (!isThumbTwo() && 6431 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 6432 return Error(Operands[4]->getStartLoc(), 6433 "source register must be the same as destination"); 6434 } 6435 break; 6436 } 6437 // Final range checking for Thumb unconditional branch instructions. 6438 case ARM::tB: 6439 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>()) 6440 return Error(Operands[2]->getStartLoc(), "branch target out of range"); 6441 break; 6442 case ARM::t2B: { 6443 int op = (Operands[2]->isImm()) ? 2 : 3; 6444 if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>()) 6445 return Error(Operands[op]->getStartLoc(), "branch target out of range"); 6446 break; 6447 } 6448 // Final range checking for Thumb conditional branch instructions. 6449 case ARM::tBcc: 6450 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>()) 6451 return Error(Operands[2]->getStartLoc(), "branch target out of range"); 6452 break; 6453 case ARM::t2Bcc: { 6454 int Op = (Operands[2]->isImm()) ? 2 : 3; 6455 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>()) 6456 return Error(Operands[Op]->getStartLoc(), "branch target out of range"); 6457 break; 6458 } 6459 case ARM::MOVi16: 6460 case ARM::t2MOVi16: 6461 case ARM::t2MOVTi16: 6462 { 6463 // We want to avoid misleadingly allowing something like "mov r0, <symbol>" 6464 // especially when we turn it into a movw and the expression <symbol> does 6465 // not have a :lower16: or :upper16 as part of the expression. We don't 6466 // want the behavior of silently truncating, which can be unexpected and 6467 // lead to bugs that are difficult to find since this is an easy mistake 6468 // to make. 6469 int i = (Operands[3]->isImm()) ? 3 : 4; 6470 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]); 6471 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()); 6472 if (CE) break; 6473 const MCExpr *E = dyn_cast<MCExpr>(Op.getImm()); 6474 if (!E) break; 6475 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E); 6476 if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 && 6477 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16)) 6478 return Error( 6479 Op.getStartLoc(), 6480 "immediate expression for mov requires :lower16: or :upper16"); 6481 break; 6482 } 6483 } 6484 6485 return false; 6486 } 6487 6488 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) { 6489 switch(Opc) { 6490 default: llvm_unreachable("unexpected opcode!"); 6491 // VST1LN 6492 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 6493 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 6494 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 6495 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 6496 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 6497 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 6498 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; 6499 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; 6500 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; 6501 6502 // VST2LN 6503 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 6504 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 6505 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 6506 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 6507 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 6508 6509 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 6510 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 6511 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 6512 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 6513 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 6514 6515 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; 6516 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; 6517 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; 6518 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; 6519 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; 6520 6521 // VST3LN 6522 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 6523 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 6524 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 6525 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; 6526 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 6527 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 6528 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 6529 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 6530 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; 6531 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 6532 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; 6533 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; 6534 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; 6535 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; 6536 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; 6537 6538 // VST3 6539 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 6540 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 6541 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 6542 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 6543 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 6544 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 6545 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 6546 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 6547 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 6548 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 6549 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 6550 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 6551 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; 6552 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; 6553 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; 6554 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; 6555 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; 6556 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; 6557 6558 // VST4LN 6559 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 6560 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 6561 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 6562 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; 6563 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 6564 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 6565 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 6566 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 6567 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; 6568 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 6569 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; 6570 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; 6571 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; 6572 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; 6573 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; 6574 6575 // VST4 6576 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 6577 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 6578 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 6579 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 6580 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 6581 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 6582 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 6583 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 6584 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 6585 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 6586 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 6587 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 6588 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; 6589 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; 6590 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; 6591 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; 6592 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; 6593 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; 6594 } 6595 } 6596 6597 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) { 6598 switch(Opc) { 6599 default: llvm_unreachable("unexpected opcode!"); 6600 // VLD1LN 6601 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 6602 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 6603 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 6604 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 6605 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 6606 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 6607 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; 6608 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; 6609 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; 6610 6611 // VLD2LN 6612 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 6613 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 6614 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 6615 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; 6616 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 6617 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 6618 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 6619 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 6620 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; 6621 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 6622 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; 6623 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; 6624 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; 6625 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; 6626 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; 6627 6628 // VLD3DUP 6629 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 6630 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 6631 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 6632 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; 6633 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; 6634 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 6635 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 6636 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 6637 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 6638 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; 6639 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; 6640 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 6641 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; 6642 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; 6643 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; 6644 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; 6645 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; 6646 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; 6647 6648 // VLD3LN 6649 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 6650 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 6651 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 6652 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; 6653 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 6654 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 6655 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 6656 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 6657 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; 6658 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 6659 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; 6660 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; 6661 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; 6662 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; 6663 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; 6664 6665 // VLD3 6666 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 6667 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 6668 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 6669 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 6670 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 6671 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 6672 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 6673 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 6674 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 6675 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 6676 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 6677 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 6678 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; 6679 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; 6680 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; 6681 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; 6682 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; 6683 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; 6684 6685 // VLD4LN 6686 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 6687 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 6688 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 6689 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; 6690 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 6691 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 6692 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 6693 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 6694 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; 6695 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 6696 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; 6697 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; 6698 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; 6699 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; 6700 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; 6701 6702 // VLD4DUP 6703 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 6704 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 6705 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 6706 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; 6707 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; 6708 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 6709 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 6710 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 6711 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 6712 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; 6713 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; 6714 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 6715 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; 6716 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; 6717 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; 6718 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; 6719 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; 6720 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; 6721 6722 // VLD4 6723 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 6724 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 6725 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 6726 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 6727 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 6728 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 6729 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 6730 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 6731 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 6732 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 6733 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 6734 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 6735 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; 6736 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; 6737 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; 6738 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; 6739 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; 6740 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; 6741 } 6742 } 6743 6744 bool ARMAsmParser::processInstruction(MCInst &Inst, 6745 const OperandVector &Operands, 6746 MCStreamer &Out) { 6747 switch (Inst.getOpcode()) { 6748 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction. 6749 case ARM::LDRT_POST: 6750 case ARM::LDRBT_POST: { 6751 const unsigned Opcode = 6752 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM 6753 : ARM::LDRBT_POST_IMM; 6754 MCInst TmpInst; 6755 TmpInst.setOpcode(Opcode); 6756 TmpInst.addOperand(Inst.getOperand(0)); 6757 TmpInst.addOperand(Inst.getOperand(1)); 6758 TmpInst.addOperand(Inst.getOperand(1)); 6759 TmpInst.addOperand(MCOperand::createReg(0)); 6760 TmpInst.addOperand(MCOperand::createImm(0)); 6761 TmpInst.addOperand(Inst.getOperand(2)); 6762 TmpInst.addOperand(Inst.getOperand(3)); 6763 Inst = TmpInst; 6764 return true; 6765 } 6766 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction. 6767 case ARM::STRT_POST: 6768 case ARM::STRBT_POST: { 6769 const unsigned Opcode = 6770 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM 6771 : ARM::STRBT_POST_IMM; 6772 MCInst TmpInst; 6773 TmpInst.setOpcode(Opcode); 6774 TmpInst.addOperand(Inst.getOperand(1)); 6775 TmpInst.addOperand(Inst.getOperand(0)); 6776 TmpInst.addOperand(Inst.getOperand(1)); 6777 TmpInst.addOperand(MCOperand::createReg(0)); 6778 TmpInst.addOperand(MCOperand::createImm(0)); 6779 TmpInst.addOperand(Inst.getOperand(2)); 6780 TmpInst.addOperand(Inst.getOperand(3)); 6781 Inst = TmpInst; 6782 return true; 6783 } 6784 // Alias for alternate form of 'ADR Rd, #imm' instruction. 6785 case ARM::ADDri: { 6786 if (Inst.getOperand(1).getReg() != ARM::PC || 6787 Inst.getOperand(5).getReg() != 0 || 6788 !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm())) 6789 return false; 6790 MCInst TmpInst; 6791 TmpInst.setOpcode(ARM::ADR); 6792 TmpInst.addOperand(Inst.getOperand(0)); 6793 if (Inst.getOperand(2).isImm()) { 6794 // Immediate (mod_imm) will be in its encoded form, we must unencode it 6795 // before passing it to the ADR instruction. 6796 unsigned Enc = Inst.getOperand(2).getImm(); 6797 TmpInst.addOperand(MCOperand::createImm( 6798 ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7))); 6799 } else { 6800 // Turn PC-relative expression into absolute expression. 6801 // Reading PC provides the start of the current instruction + 8 and 6802 // the transform to adr is biased by that. 6803 MCSymbol *Dot = getContext().createTempSymbol(); 6804 Out.EmitLabel(Dot); 6805 const MCExpr *OpExpr = Inst.getOperand(2).getExpr(); 6806 const MCExpr *InstPC = MCSymbolRefExpr::create(Dot, 6807 MCSymbolRefExpr::VK_None, 6808 getContext()); 6809 const MCExpr *Const8 = MCConstantExpr::create(8, getContext()); 6810 const MCExpr *ReadPC = MCBinaryExpr::createAdd(InstPC, Const8, 6811 getContext()); 6812 const MCExpr *FixupAddr = MCBinaryExpr::createAdd(ReadPC, OpExpr, 6813 getContext()); 6814 TmpInst.addOperand(MCOperand::createExpr(FixupAddr)); 6815 } 6816 TmpInst.addOperand(Inst.getOperand(3)); 6817 TmpInst.addOperand(Inst.getOperand(4)); 6818 Inst = TmpInst; 6819 return true; 6820 } 6821 // Aliases for alternate PC+imm syntax of LDR instructions. 6822 case ARM::t2LDRpcrel: 6823 // Select the narrow version if the immediate will fit. 6824 if (Inst.getOperand(1).getImm() > 0 && 6825 Inst.getOperand(1).getImm() <= 0xff && 6826 !(static_cast<ARMOperand &>(*Operands[2]).isToken() && 6827 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w")) 6828 Inst.setOpcode(ARM::tLDRpci); 6829 else 6830 Inst.setOpcode(ARM::t2LDRpci); 6831 return true; 6832 case ARM::t2LDRBpcrel: 6833 Inst.setOpcode(ARM::t2LDRBpci); 6834 return true; 6835 case ARM::t2LDRHpcrel: 6836 Inst.setOpcode(ARM::t2LDRHpci); 6837 return true; 6838 case ARM::t2LDRSBpcrel: 6839 Inst.setOpcode(ARM::t2LDRSBpci); 6840 return true; 6841 case ARM::t2LDRSHpcrel: 6842 Inst.setOpcode(ARM::t2LDRSHpci); 6843 return true; 6844 // Handle NEON VST complex aliases. 6845 case ARM::VST1LNdWB_register_Asm_8: 6846 case ARM::VST1LNdWB_register_Asm_16: 6847 case ARM::VST1LNdWB_register_Asm_32: { 6848 MCInst TmpInst; 6849 // Shuffle the operands around so the lane index operand is in the 6850 // right place. 6851 unsigned Spacing; 6852 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6853 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6854 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6855 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6856 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6857 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6858 TmpInst.addOperand(Inst.getOperand(1)); // lane 6859 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6860 TmpInst.addOperand(Inst.getOperand(6)); 6861 Inst = TmpInst; 6862 return true; 6863 } 6864 6865 case ARM::VST2LNdWB_register_Asm_8: 6866 case ARM::VST2LNdWB_register_Asm_16: 6867 case ARM::VST2LNdWB_register_Asm_32: 6868 case ARM::VST2LNqWB_register_Asm_16: 6869 case ARM::VST2LNqWB_register_Asm_32: { 6870 MCInst TmpInst; 6871 // Shuffle the operands around so the lane index operand is in the 6872 // right place. 6873 unsigned Spacing; 6874 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6875 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6876 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6877 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6878 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6879 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6880 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 6881 Spacing)); 6882 TmpInst.addOperand(Inst.getOperand(1)); // lane 6883 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6884 TmpInst.addOperand(Inst.getOperand(6)); 6885 Inst = TmpInst; 6886 return true; 6887 } 6888 6889 case ARM::VST3LNdWB_register_Asm_8: 6890 case ARM::VST3LNdWB_register_Asm_16: 6891 case ARM::VST3LNdWB_register_Asm_32: 6892 case ARM::VST3LNqWB_register_Asm_16: 6893 case ARM::VST3LNqWB_register_Asm_32: { 6894 MCInst TmpInst; 6895 // Shuffle the operands around so the lane index operand is in the 6896 // right place. 6897 unsigned Spacing; 6898 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6899 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6900 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6901 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6902 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6903 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6904 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 6905 Spacing)); 6906 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 6907 Spacing * 2)); 6908 TmpInst.addOperand(Inst.getOperand(1)); // lane 6909 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6910 TmpInst.addOperand(Inst.getOperand(6)); 6911 Inst = TmpInst; 6912 return true; 6913 } 6914 6915 case ARM::VST4LNdWB_register_Asm_8: 6916 case ARM::VST4LNdWB_register_Asm_16: 6917 case ARM::VST4LNdWB_register_Asm_32: 6918 case ARM::VST4LNqWB_register_Asm_16: 6919 case ARM::VST4LNqWB_register_Asm_32: { 6920 MCInst TmpInst; 6921 // Shuffle the operands around so the lane index operand is in the 6922 // right place. 6923 unsigned Spacing; 6924 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6925 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6926 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6927 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6928 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6929 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6930 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 6931 Spacing)); 6932 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 6933 Spacing * 2)); 6934 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 6935 Spacing * 3)); 6936 TmpInst.addOperand(Inst.getOperand(1)); // lane 6937 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6938 TmpInst.addOperand(Inst.getOperand(6)); 6939 Inst = TmpInst; 6940 return true; 6941 } 6942 6943 case ARM::VST1LNdWB_fixed_Asm_8: 6944 case ARM::VST1LNdWB_fixed_Asm_16: 6945 case ARM::VST1LNdWB_fixed_Asm_32: { 6946 MCInst TmpInst; 6947 // Shuffle the operands around so the lane index operand is in the 6948 // right place. 6949 unsigned Spacing; 6950 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6951 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6952 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6953 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6954 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 6955 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6956 TmpInst.addOperand(Inst.getOperand(1)); // lane 6957 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6958 TmpInst.addOperand(Inst.getOperand(5)); 6959 Inst = TmpInst; 6960 return true; 6961 } 6962 6963 case ARM::VST2LNdWB_fixed_Asm_8: 6964 case ARM::VST2LNdWB_fixed_Asm_16: 6965 case ARM::VST2LNdWB_fixed_Asm_32: 6966 case ARM::VST2LNqWB_fixed_Asm_16: 6967 case ARM::VST2LNqWB_fixed_Asm_32: { 6968 MCInst TmpInst; 6969 // Shuffle the operands around so the lane index operand is in the 6970 // right place. 6971 unsigned Spacing; 6972 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6973 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6974 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6975 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6976 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 6977 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6978 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 6979 Spacing)); 6980 TmpInst.addOperand(Inst.getOperand(1)); // lane 6981 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6982 TmpInst.addOperand(Inst.getOperand(5)); 6983 Inst = TmpInst; 6984 return true; 6985 } 6986 6987 case ARM::VST3LNdWB_fixed_Asm_8: 6988 case ARM::VST3LNdWB_fixed_Asm_16: 6989 case ARM::VST3LNdWB_fixed_Asm_32: 6990 case ARM::VST3LNqWB_fixed_Asm_16: 6991 case ARM::VST3LNqWB_fixed_Asm_32: { 6992 MCInst TmpInst; 6993 // Shuffle the operands around so the lane index operand is in the 6994 // right place. 6995 unsigned Spacing; 6996 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6997 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6998 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6999 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7000 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7001 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7002 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7003 Spacing)); 7004 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7005 Spacing * 2)); 7006 TmpInst.addOperand(Inst.getOperand(1)); // lane 7007 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7008 TmpInst.addOperand(Inst.getOperand(5)); 7009 Inst = TmpInst; 7010 return true; 7011 } 7012 7013 case ARM::VST4LNdWB_fixed_Asm_8: 7014 case ARM::VST4LNdWB_fixed_Asm_16: 7015 case ARM::VST4LNdWB_fixed_Asm_32: 7016 case ARM::VST4LNqWB_fixed_Asm_16: 7017 case ARM::VST4LNqWB_fixed_Asm_32: { 7018 MCInst TmpInst; 7019 // Shuffle the operands around so the lane index operand is in the 7020 // right place. 7021 unsigned Spacing; 7022 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7023 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 7024 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7025 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7026 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7027 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7028 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7029 Spacing)); 7030 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7031 Spacing * 2)); 7032 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7033 Spacing * 3)); 7034 TmpInst.addOperand(Inst.getOperand(1)); // lane 7035 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7036 TmpInst.addOperand(Inst.getOperand(5)); 7037 Inst = TmpInst; 7038 return true; 7039 } 7040 7041 case ARM::VST1LNdAsm_8: 7042 case ARM::VST1LNdAsm_16: 7043 case ARM::VST1LNdAsm_32: { 7044 MCInst TmpInst; 7045 // Shuffle the operands around so the lane index operand is in the 7046 // right place. 7047 unsigned Spacing; 7048 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7049 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7050 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7051 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7052 TmpInst.addOperand(Inst.getOperand(1)); // lane 7053 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7054 TmpInst.addOperand(Inst.getOperand(5)); 7055 Inst = TmpInst; 7056 return true; 7057 } 7058 7059 case ARM::VST2LNdAsm_8: 7060 case ARM::VST2LNdAsm_16: 7061 case ARM::VST2LNdAsm_32: 7062 case ARM::VST2LNqAsm_16: 7063 case ARM::VST2LNqAsm_32: { 7064 MCInst TmpInst; 7065 // Shuffle the operands around so the lane index operand is in the 7066 // right place. 7067 unsigned Spacing; 7068 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7069 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7070 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7071 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7072 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7073 Spacing)); 7074 TmpInst.addOperand(Inst.getOperand(1)); // lane 7075 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7076 TmpInst.addOperand(Inst.getOperand(5)); 7077 Inst = TmpInst; 7078 return true; 7079 } 7080 7081 case ARM::VST3LNdAsm_8: 7082 case ARM::VST3LNdAsm_16: 7083 case ARM::VST3LNdAsm_32: 7084 case ARM::VST3LNqAsm_16: 7085 case ARM::VST3LNqAsm_32: { 7086 MCInst TmpInst; 7087 // Shuffle the operands around so the lane index operand is in the 7088 // right place. 7089 unsigned Spacing; 7090 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7091 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7092 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7093 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7094 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7095 Spacing)); 7096 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7097 Spacing * 2)); 7098 TmpInst.addOperand(Inst.getOperand(1)); // lane 7099 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7100 TmpInst.addOperand(Inst.getOperand(5)); 7101 Inst = TmpInst; 7102 return true; 7103 } 7104 7105 case ARM::VST4LNdAsm_8: 7106 case ARM::VST4LNdAsm_16: 7107 case ARM::VST4LNdAsm_32: 7108 case ARM::VST4LNqAsm_16: 7109 case ARM::VST4LNqAsm_32: { 7110 MCInst TmpInst; 7111 // Shuffle the operands around so the lane index operand is in the 7112 // right place. 7113 unsigned Spacing; 7114 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7115 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7116 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7117 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7118 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7119 Spacing)); 7120 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7121 Spacing * 2)); 7122 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7123 Spacing * 3)); 7124 TmpInst.addOperand(Inst.getOperand(1)); // lane 7125 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7126 TmpInst.addOperand(Inst.getOperand(5)); 7127 Inst = TmpInst; 7128 return true; 7129 } 7130 7131 // Handle NEON VLD complex aliases. 7132 case ARM::VLD1LNdWB_register_Asm_8: 7133 case ARM::VLD1LNdWB_register_Asm_16: 7134 case ARM::VLD1LNdWB_register_Asm_32: { 7135 MCInst TmpInst; 7136 // Shuffle the operands around so the lane index operand is in the 7137 // right place. 7138 unsigned Spacing; 7139 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7140 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7141 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 7142 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7143 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7144 TmpInst.addOperand(Inst.getOperand(4)); // Rm 7145 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7146 TmpInst.addOperand(Inst.getOperand(1)); // lane 7147 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 7148 TmpInst.addOperand(Inst.getOperand(6)); 7149 Inst = TmpInst; 7150 return true; 7151 } 7152 7153 case ARM::VLD2LNdWB_register_Asm_8: 7154 case ARM::VLD2LNdWB_register_Asm_16: 7155 case ARM::VLD2LNdWB_register_Asm_32: 7156 case ARM::VLD2LNqWB_register_Asm_16: 7157 case ARM::VLD2LNqWB_register_Asm_32: { 7158 MCInst TmpInst; 7159 // Shuffle the operands around so the lane index operand is in the 7160 // right place. 7161 unsigned Spacing; 7162 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7163 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7164 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7165 Spacing)); 7166 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 7167 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7168 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7169 TmpInst.addOperand(Inst.getOperand(4)); // Rm 7170 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7171 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7172 Spacing)); 7173 TmpInst.addOperand(Inst.getOperand(1)); // lane 7174 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 7175 TmpInst.addOperand(Inst.getOperand(6)); 7176 Inst = TmpInst; 7177 return true; 7178 } 7179 7180 case ARM::VLD3LNdWB_register_Asm_8: 7181 case ARM::VLD3LNdWB_register_Asm_16: 7182 case ARM::VLD3LNdWB_register_Asm_32: 7183 case ARM::VLD3LNqWB_register_Asm_16: 7184 case ARM::VLD3LNqWB_register_Asm_32: { 7185 MCInst TmpInst; 7186 // Shuffle the operands around so the lane index operand is in the 7187 // right place. 7188 unsigned Spacing; 7189 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7190 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7191 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7192 Spacing)); 7193 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7194 Spacing * 2)); 7195 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 7196 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7197 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7198 TmpInst.addOperand(Inst.getOperand(4)); // Rm 7199 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7200 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7201 Spacing)); 7202 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7203 Spacing * 2)); 7204 TmpInst.addOperand(Inst.getOperand(1)); // lane 7205 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 7206 TmpInst.addOperand(Inst.getOperand(6)); 7207 Inst = TmpInst; 7208 return true; 7209 } 7210 7211 case ARM::VLD4LNdWB_register_Asm_8: 7212 case ARM::VLD4LNdWB_register_Asm_16: 7213 case ARM::VLD4LNdWB_register_Asm_32: 7214 case ARM::VLD4LNqWB_register_Asm_16: 7215 case ARM::VLD4LNqWB_register_Asm_32: { 7216 MCInst TmpInst; 7217 // Shuffle the operands around so the lane index operand is in the 7218 // right place. 7219 unsigned Spacing; 7220 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7221 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7222 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7223 Spacing)); 7224 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7225 Spacing * 2)); 7226 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7227 Spacing * 3)); 7228 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 7229 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7230 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7231 TmpInst.addOperand(Inst.getOperand(4)); // Rm 7232 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7233 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7234 Spacing)); 7235 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7236 Spacing * 2)); 7237 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7238 Spacing * 3)); 7239 TmpInst.addOperand(Inst.getOperand(1)); // lane 7240 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 7241 TmpInst.addOperand(Inst.getOperand(6)); 7242 Inst = TmpInst; 7243 return true; 7244 } 7245 7246 case ARM::VLD1LNdWB_fixed_Asm_8: 7247 case ARM::VLD1LNdWB_fixed_Asm_16: 7248 case ARM::VLD1LNdWB_fixed_Asm_32: { 7249 MCInst TmpInst; 7250 // Shuffle the operands around so the lane index operand is in the 7251 // right place. 7252 unsigned Spacing; 7253 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7254 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7255 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 7256 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7257 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7258 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7259 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7260 TmpInst.addOperand(Inst.getOperand(1)); // lane 7261 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7262 TmpInst.addOperand(Inst.getOperand(5)); 7263 Inst = TmpInst; 7264 return true; 7265 } 7266 7267 case ARM::VLD2LNdWB_fixed_Asm_8: 7268 case ARM::VLD2LNdWB_fixed_Asm_16: 7269 case ARM::VLD2LNdWB_fixed_Asm_32: 7270 case ARM::VLD2LNqWB_fixed_Asm_16: 7271 case ARM::VLD2LNqWB_fixed_Asm_32: { 7272 MCInst TmpInst; 7273 // Shuffle the operands around so the lane index operand is in the 7274 // right place. 7275 unsigned Spacing; 7276 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7277 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7278 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7279 Spacing)); 7280 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 7281 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7282 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7283 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7284 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7285 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7286 Spacing)); 7287 TmpInst.addOperand(Inst.getOperand(1)); // lane 7288 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7289 TmpInst.addOperand(Inst.getOperand(5)); 7290 Inst = TmpInst; 7291 return true; 7292 } 7293 7294 case ARM::VLD3LNdWB_fixed_Asm_8: 7295 case ARM::VLD3LNdWB_fixed_Asm_16: 7296 case ARM::VLD3LNdWB_fixed_Asm_32: 7297 case ARM::VLD3LNqWB_fixed_Asm_16: 7298 case ARM::VLD3LNqWB_fixed_Asm_32: { 7299 MCInst TmpInst; 7300 // Shuffle the operands around so the lane index operand is in the 7301 // right place. 7302 unsigned Spacing; 7303 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7304 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7305 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7306 Spacing)); 7307 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7308 Spacing * 2)); 7309 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 7310 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7311 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7312 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7313 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7314 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7315 Spacing)); 7316 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7317 Spacing * 2)); 7318 TmpInst.addOperand(Inst.getOperand(1)); // lane 7319 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7320 TmpInst.addOperand(Inst.getOperand(5)); 7321 Inst = TmpInst; 7322 return true; 7323 } 7324 7325 case ARM::VLD4LNdWB_fixed_Asm_8: 7326 case ARM::VLD4LNdWB_fixed_Asm_16: 7327 case ARM::VLD4LNdWB_fixed_Asm_32: 7328 case ARM::VLD4LNqWB_fixed_Asm_16: 7329 case ARM::VLD4LNqWB_fixed_Asm_32: { 7330 MCInst TmpInst; 7331 // Shuffle the operands around so the lane index operand is in the 7332 // right place. 7333 unsigned Spacing; 7334 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7335 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7336 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7337 Spacing)); 7338 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7339 Spacing * 2)); 7340 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7341 Spacing * 3)); 7342 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 7343 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7344 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7345 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7346 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7347 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7348 Spacing)); 7349 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7350 Spacing * 2)); 7351 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7352 Spacing * 3)); 7353 TmpInst.addOperand(Inst.getOperand(1)); // lane 7354 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7355 TmpInst.addOperand(Inst.getOperand(5)); 7356 Inst = TmpInst; 7357 return true; 7358 } 7359 7360 case ARM::VLD1LNdAsm_8: 7361 case ARM::VLD1LNdAsm_16: 7362 case ARM::VLD1LNdAsm_32: { 7363 MCInst TmpInst; 7364 // Shuffle the operands around so the lane index operand is in the 7365 // right place. 7366 unsigned Spacing; 7367 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7368 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7369 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7370 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7371 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7372 TmpInst.addOperand(Inst.getOperand(1)); // lane 7373 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7374 TmpInst.addOperand(Inst.getOperand(5)); 7375 Inst = TmpInst; 7376 return true; 7377 } 7378 7379 case ARM::VLD2LNdAsm_8: 7380 case ARM::VLD2LNdAsm_16: 7381 case ARM::VLD2LNdAsm_32: 7382 case ARM::VLD2LNqAsm_16: 7383 case ARM::VLD2LNqAsm_32: { 7384 MCInst TmpInst; 7385 // Shuffle the operands around so the lane index operand is in the 7386 // right place. 7387 unsigned Spacing; 7388 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7389 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7390 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7391 Spacing)); 7392 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7393 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7394 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7395 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7396 Spacing)); 7397 TmpInst.addOperand(Inst.getOperand(1)); // lane 7398 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7399 TmpInst.addOperand(Inst.getOperand(5)); 7400 Inst = TmpInst; 7401 return true; 7402 } 7403 7404 case ARM::VLD3LNdAsm_8: 7405 case ARM::VLD3LNdAsm_16: 7406 case ARM::VLD3LNdAsm_32: 7407 case ARM::VLD3LNqAsm_16: 7408 case ARM::VLD3LNqAsm_32: { 7409 MCInst TmpInst; 7410 // Shuffle the operands around so the lane index operand is in the 7411 // right place. 7412 unsigned Spacing; 7413 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7414 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7415 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7416 Spacing)); 7417 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7418 Spacing * 2)); 7419 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7420 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7421 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7422 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7423 Spacing)); 7424 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7425 Spacing * 2)); 7426 TmpInst.addOperand(Inst.getOperand(1)); // lane 7427 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7428 TmpInst.addOperand(Inst.getOperand(5)); 7429 Inst = TmpInst; 7430 return true; 7431 } 7432 7433 case ARM::VLD4LNdAsm_8: 7434 case ARM::VLD4LNdAsm_16: 7435 case ARM::VLD4LNdAsm_32: 7436 case ARM::VLD4LNqAsm_16: 7437 case ARM::VLD4LNqAsm_32: { 7438 MCInst TmpInst; 7439 // Shuffle the operands around so the lane index operand is in the 7440 // right place. 7441 unsigned Spacing; 7442 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7443 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7444 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7445 Spacing)); 7446 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7447 Spacing * 2)); 7448 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7449 Spacing * 3)); 7450 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7451 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7452 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7453 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7454 Spacing)); 7455 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7456 Spacing * 2)); 7457 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7458 Spacing * 3)); 7459 TmpInst.addOperand(Inst.getOperand(1)); // lane 7460 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7461 TmpInst.addOperand(Inst.getOperand(5)); 7462 Inst = TmpInst; 7463 return true; 7464 } 7465 7466 // VLD3DUP single 3-element structure to all lanes instructions. 7467 case ARM::VLD3DUPdAsm_8: 7468 case ARM::VLD3DUPdAsm_16: 7469 case ARM::VLD3DUPdAsm_32: 7470 case ARM::VLD3DUPqAsm_8: 7471 case ARM::VLD3DUPqAsm_16: 7472 case ARM::VLD3DUPqAsm_32: { 7473 MCInst TmpInst; 7474 unsigned Spacing; 7475 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7476 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7477 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7478 Spacing)); 7479 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7480 Spacing * 2)); 7481 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7482 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7483 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7484 TmpInst.addOperand(Inst.getOperand(4)); 7485 Inst = TmpInst; 7486 return true; 7487 } 7488 7489 case ARM::VLD3DUPdWB_fixed_Asm_8: 7490 case ARM::VLD3DUPdWB_fixed_Asm_16: 7491 case ARM::VLD3DUPdWB_fixed_Asm_32: 7492 case ARM::VLD3DUPqWB_fixed_Asm_8: 7493 case ARM::VLD3DUPqWB_fixed_Asm_16: 7494 case ARM::VLD3DUPqWB_fixed_Asm_32: { 7495 MCInst TmpInst; 7496 unsigned Spacing; 7497 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7498 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7499 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7500 Spacing)); 7501 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7502 Spacing * 2)); 7503 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7504 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7505 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7506 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7507 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7508 TmpInst.addOperand(Inst.getOperand(4)); 7509 Inst = TmpInst; 7510 return true; 7511 } 7512 7513 case ARM::VLD3DUPdWB_register_Asm_8: 7514 case ARM::VLD3DUPdWB_register_Asm_16: 7515 case ARM::VLD3DUPdWB_register_Asm_32: 7516 case ARM::VLD3DUPqWB_register_Asm_8: 7517 case ARM::VLD3DUPqWB_register_Asm_16: 7518 case ARM::VLD3DUPqWB_register_Asm_32: { 7519 MCInst TmpInst; 7520 unsigned Spacing; 7521 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7522 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7523 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7524 Spacing)); 7525 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7526 Spacing * 2)); 7527 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7528 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7529 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7530 TmpInst.addOperand(Inst.getOperand(3)); // Rm 7531 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7532 TmpInst.addOperand(Inst.getOperand(5)); 7533 Inst = TmpInst; 7534 return true; 7535 } 7536 7537 // VLD3 multiple 3-element structure instructions. 7538 case ARM::VLD3dAsm_8: 7539 case ARM::VLD3dAsm_16: 7540 case ARM::VLD3dAsm_32: 7541 case ARM::VLD3qAsm_8: 7542 case ARM::VLD3qAsm_16: 7543 case ARM::VLD3qAsm_32: { 7544 MCInst TmpInst; 7545 unsigned Spacing; 7546 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7547 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7548 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7549 Spacing)); 7550 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7551 Spacing * 2)); 7552 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7553 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7554 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7555 TmpInst.addOperand(Inst.getOperand(4)); 7556 Inst = TmpInst; 7557 return true; 7558 } 7559 7560 case ARM::VLD3dWB_fixed_Asm_8: 7561 case ARM::VLD3dWB_fixed_Asm_16: 7562 case ARM::VLD3dWB_fixed_Asm_32: 7563 case ARM::VLD3qWB_fixed_Asm_8: 7564 case ARM::VLD3qWB_fixed_Asm_16: 7565 case ARM::VLD3qWB_fixed_Asm_32: { 7566 MCInst TmpInst; 7567 unsigned Spacing; 7568 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7569 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7570 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7571 Spacing)); 7572 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7573 Spacing * 2)); 7574 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7575 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7576 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7577 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7578 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7579 TmpInst.addOperand(Inst.getOperand(4)); 7580 Inst = TmpInst; 7581 return true; 7582 } 7583 7584 case ARM::VLD3dWB_register_Asm_8: 7585 case ARM::VLD3dWB_register_Asm_16: 7586 case ARM::VLD3dWB_register_Asm_32: 7587 case ARM::VLD3qWB_register_Asm_8: 7588 case ARM::VLD3qWB_register_Asm_16: 7589 case ARM::VLD3qWB_register_Asm_32: { 7590 MCInst TmpInst; 7591 unsigned Spacing; 7592 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7593 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7594 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7595 Spacing)); 7596 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7597 Spacing * 2)); 7598 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7599 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7600 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7601 TmpInst.addOperand(Inst.getOperand(3)); // Rm 7602 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7603 TmpInst.addOperand(Inst.getOperand(5)); 7604 Inst = TmpInst; 7605 return true; 7606 } 7607 7608 // VLD4DUP single 3-element structure to all lanes instructions. 7609 case ARM::VLD4DUPdAsm_8: 7610 case ARM::VLD4DUPdAsm_16: 7611 case ARM::VLD4DUPdAsm_32: 7612 case ARM::VLD4DUPqAsm_8: 7613 case ARM::VLD4DUPqAsm_16: 7614 case ARM::VLD4DUPqAsm_32: { 7615 MCInst TmpInst; 7616 unsigned Spacing; 7617 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7618 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7619 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7620 Spacing)); 7621 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7622 Spacing * 2)); 7623 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7624 Spacing * 3)); 7625 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7626 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7627 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7628 TmpInst.addOperand(Inst.getOperand(4)); 7629 Inst = TmpInst; 7630 return true; 7631 } 7632 7633 case ARM::VLD4DUPdWB_fixed_Asm_8: 7634 case ARM::VLD4DUPdWB_fixed_Asm_16: 7635 case ARM::VLD4DUPdWB_fixed_Asm_32: 7636 case ARM::VLD4DUPqWB_fixed_Asm_8: 7637 case ARM::VLD4DUPqWB_fixed_Asm_16: 7638 case ARM::VLD4DUPqWB_fixed_Asm_32: { 7639 MCInst TmpInst; 7640 unsigned Spacing; 7641 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7642 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7643 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7644 Spacing)); 7645 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7646 Spacing * 2)); 7647 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7648 Spacing * 3)); 7649 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7650 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7651 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7652 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7653 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7654 TmpInst.addOperand(Inst.getOperand(4)); 7655 Inst = TmpInst; 7656 return true; 7657 } 7658 7659 case ARM::VLD4DUPdWB_register_Asm_8: 7660 case ARM::VLD4DUPdWB_register_Asm_16: 7661 case ARM::VLD4DUPdWB_register_Asm_32: 7662 case ARM::VLD4DUPqWB_register_Asm_8: 7663 case ARM::VLD4DUPqWB_register_Asm_16: 7664 case ARM::VLD4DUPqWB_register_Asm_32: { 7665 MCInst TmpInst; 7666 unsigned Spacing; 7667 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7668 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7669 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7670 Spacing)); 7671 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7672 Spacing * 2)); 7673 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7674 Spacing * 3)); 7675 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7676 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7677 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7678 TmpInst.addOperand(Inst.getOperand(3)); // Rm 7679 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7680 TmpInst.addOperand(Inst.getOperand(5)); 7681 Inst = TmpInst; 7682 return true; 7683 } 7684 7685 // VLD4 multiple 4-element structure instructions. 7686 case ARM::VLD4dAsm_8: 7687 case ARM::VLD4dAsm_16: 7688 case ARM::VLD4dAsm_32: 7689 case ARM::VLD4qAsm_8: 7690 case ARM::VLD4qAsm_16: 7691 case ARM::VLD4qAsm_32: { 7692 MCInst TmpInst; 7693 unsigned Spacing; 7694 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7695 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7696 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7697 Spacing)); 7698 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7699 Spacing * 2)); 7700 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7701 Spacing * 3)); 7702 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7703 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7704 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7705 TmpInst.addOperand(Inst.getOperand(4)); 7706 Inst = TmpInst; 7707 return true; 7708 } 7709 7710 case ARM::VLD4dWB_fixed_Asm_8: 7711 case ARM::VLD4dWB_fixed_Asm_16: 7712 case ARM::VLD4dWB_fixed_Asm_32: 7713 case ARM::VLD4qWB_fixed_Asm_8: 7714 case ARM::VLD4qWB_fixed_Asm_16: 7715 case ARM::VLD4qWB_fixed_Asm_32: { 7716 MCInst TmpInst; 7717 unsigned Spacing; 7718 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7719 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7720 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7721 Spacing)); 7722 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7723 Spacing * 2)); 7724 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7725 Spacing * 3)); 7726 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7727 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7728 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7729 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7730 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7731 TmpInst.addOperand(Inst.getOperand(4)); 7732 Inst = TmpInst; 7733 return true; 7734 } 7735 7736 case ARM::VLD4dWB_register_Asm_8: 7737 case ARM::VLD4dWB_register_Asm_16: 7738 case ARM::VLD4dWB_register_Asm_32: 7739 case ARM::VLD4qWB_register_Asm_8: 7740 case ARM::VLD4qWB_register_Asm_16: 7741 case ARM::VLD4qWB_register_Asm_32: { 7742 MCInst TmpInst; 7743 unsigned Spacing; 7744 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7745 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7746 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7747 Spacing)); 7748 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7749 Spacing * 2)); 7750 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7751 Spacing * 3)); 7752 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7753 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7754 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7755 TmpInst.addOperand(Inst.getOperand(3)); // Rm 7756 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7757 TmpInst.addOperand(Inst.getOperand(5)); 7758 Inst = TmpInst; 7759 return true; 7760 } 7761 7762 // VST3 multiple 3-element structure instructions. 7763 case ARM::VST3dAsm_8: 7764 case ARM::VST3dAsm_16: 7765 case ARM::VST3dAsm_32: 7766 case ARM::VST3qAsm_8: 7767 case ARM::VST3qAsm_16: 7768 case ARM::VST3qAsm_32: { 7769 MCInst TmpInst; 7770 unsigned Spacing; 7771 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7772 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7773 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7774 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7775 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7776 Spacing)); 7777 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7778 Spacing * 2)); 7779 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7780 TmpInst.addOperand(Inst.getOperand(4)); 7781 Inst = TmpInst; 7782 return true; 7783 } 7784 7785 case ARM::VST3dWB_fixed_Asm_8: 7786 case ARM::VST3dWB_fixed_Asm_16: 7787 case ARM::VST3dWB_fixed_Asm_32: 7788 case ARM::VST3qWB_fixed_Asm_8: 7789 case ARM::VST3qWB_fixed_Asm_16: 7790 case ARM::VST3qWB_fixed_Asm_32: { 7791 MCInst TmpInst; 7792 unsigned Spacing; 7793 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7794 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7795 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7796 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7797 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7798 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7799 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7800 Spacing)); 7801 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7802 Spacing * 2)); 7803 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7804 TmpInst.addOperand(Inst.getOperand(4)); 7805 Inst = TmpInst; 7806 return true; 7807 } 7808 7809 case ARM::VST3dWB_register_Asm_8: 7810 case ARM::VST3dWB_register_Asm_16: 7811 case ARM::VST3dWB_register_Asm_32: 7812 case ARM::VST3qWB_register_Asm_8: 7813 case ARM::VST3qWB_register_Asm_16: 7814 case ARM::VST3qWB_register_Asm_32: { 7815 MCInst TmpInst; 7816 unsigned Spacing; 7817 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7818 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7819 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7820 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7821 TmpInst.addOperand(Inst.getOperand(3)); // Rm 7822 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7823 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7824 Spacing)); 7825 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7826 Spacing * 2)); 7827 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7828 TmpInst.addOperand(Inst.getOperand(5)); 7829 Inst = TmpInst; 7830 return true; 7831 } 7832 7833 // VST4 multiple 3-element structure instructions. 7834 case ARM::VST4dAsm_8: 7835 case ARM::VST4dAsm_16: 7836 case ARM::VST4dAsm_32: 7837 case ARM::VST4qAsm_8: 7838 case ARM::VST4qAsm_16: 7839 case ARM::VST4qAsm_32: { 7840 MCInst TmpInst; 7841 unsigned Spacing; 7842 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7843 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7844 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7845 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7846 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7847 Spacing)); 7848 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7849 Spacing * 2)); 7850 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7851 Spacing * 3)); 7852 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7853 TmpInst.addOperand(Inst.getOperand(4)); 7854 Inst = TmpInst; 7855 return true; 7856 } 7857 7858 case ARM::VST4dWB_fixed_Asm_8: 7859 case ARM::VST4dWB_fixed_Asm_16: 7860 case ARM::VST4dWB_fixed_Asm_32: 7861 case ARM::VST4qWB_fixed_Asm_8: 7862 case ARM::VST4qWB_fixed_Asm_16: 7863 case ARM::VST4qWB_fixed_Asm_32: { 7864 MCInst TmpInst; 7865 unsigned Spacing; 7866 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7867 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7868 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7869 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7870 TmpInst.addOperand(MCOperand::createReg(0)); // Rm 7871 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7872 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7873 Spacing)); 7874 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7875 Spacing * 2)); 7876 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7877 Spacing * 3)); 7878 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7879 TmpInst.addOperand(Inst.getOperand(4)); 7880 Inst = TmpInst; 7881 return true; 7882 } 7883 7884 case ARM::VST4dWB_register_Asm_8: 7885 case ARM::VST4dWB_register_Asm_16: 7886 case ARM::VST4dWB_register_Asm_32: 7887 case ARM::VST4qWB_register_Asm_8: 7888 case ARM::VST4qWB_register_Asm_16: 7889 case ARM::VST4qWB_register_Asm_32: { 7890 MCInst TmpInst; 7891 unsigned Spacing; 7892 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7893 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7894 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7895 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7896 TmpInst.addOperand(Inst.getOperand(3)); // Rm 7897 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7898 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7899 Spacing)); 7900 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7901 Spacing * 2)); 7902 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() + 7903 Spacing * 3)); 7904 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7905 TmpInst.addOperand(Inst.getOperand(5)); 7906 Inst = TmpInst; 7907 return true; 7908 } 7909 7910 // Handle encoding choice for the shift-immediate instructions. 7911 case ARM::t2LSLri: 7912 case ARM::t2LSRri: 7913 case ARM::t2ASRri: { 7914 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7915 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 7916 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 7917 !(static_cast<ARMOperand &>(*Operands[3]).isToken() && 7918 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) { 7919 unsigned NewOpc; 7920 switch (Inst.getOpcode()) { 7921 default: llvm_unreachable("unexpected opcode"); 7922 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; 7923 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; 7924 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; 7925 } 7926 // The Thumb1 operands aren't in the same order. Awesome, eh? 7927 MCInst TmpInst; 7928 TmpInst.setOpcode(NewOpc); 7929 TmpInst.addOperand(Inst.getOperand(0)); 7930 TmpInst.addOperand(Inst.getOperand(5)); 7931 TmpInst.addOperand(Inst.getOperand(1)); 7932 TmpInst.addOperand(Inst.getOperand(2)); 7933 TmpInst.addOperand(Inst.getOperand(3)); 7934 TmpInst.addOperand(Inst.getOperand(4)); 7935 Inst = TmpInst; 7936 return true; 7937 } 7938 return false; 7939 } 7940 7941 // Handle the Thumb2 mode MOV complex aliases. 7942 case ARM::t2MOVsr: 7943 case ARM::t2MOVSsr: { 7944 // Which instruction to expand to depends on the CCOut operand and 7945 // whether we're in an IT block if the register operands are low 7946 // registers. 7947 bool isNarrow = false; 7948 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7949 isARMLowRegister(Inst.getOperand(1).getReg()) && 7950 isARMLowRegister(Inst.getOperand(2).getReg()) && 7951 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 7952 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) 7953 isNarrow = true; 7954 MCInst TmpInst; 7955 unsigned newOpc; 7956 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { 7957 default: llvm_unreachable("unexpected opcode!"); 7958 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; 7959 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; 7960 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; 7961 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; 7962 } 7963 TmpInst.setOpcode(newOpc); 7964 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7965 if (isNarrow) 7966 TmpInst.addOperand(MCOperand::createReg( 7967 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 7968 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7969 TmpInst.addOperand(Inst.getOperand(2)); // Rm 7970 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7971 TmpInst.addOperand(Inst.getOperand(5)); 7972 if (!isNarrow) 7973 TmpInst.addOperand(MCOperand::createReg( 7974 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 7975 Inst = TmpInst; 7976 return true; 7977 } 7978 case ARM::t2MOVsi: 7979 case ARM::t2MOVSsi: { 7980 // Which instruction to expand to depends on the CCOut operand and 7981 // whether we're in an IT block if the register operands are low 7982 // registers. 7983 bool isNarrow = false; 7984 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7985 isARMLowRegister(Inst.getOperand(1).getReg()) && 7986 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi)) 7987 isNarrow = true; 7988 MCInst TmpInst; 7989 unsigned newOpc; 7990 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) { 7991 default: llvm_unreachable("unexpected opcode!"); 7992 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; 7993 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; 7994 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; 7995 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; 7996 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; 7997 } 7998 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); 7999 if (Amount == 32) Amount = 0; 8000 TmpInst.setOpcode(newOpc); 8001 TmpInst.addOperand(Inst.getOperand(0)); // Rd 8002 if (isNarrow) 8003 TmpInst.addOperand(MCOperand::createReg( 8004 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 8005 TmpInst.addOperand(Inst.getOperand(1)); // Rn 8006 if (newOpc != ARM::t2RRX) 8007 TmpInst.addOperand(MCOperand::createImm(Amount)); 8008 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 8009 TmpInst.addOperand(Inst.getOperand(4)); 8010 if (!isNarrow) 8011 TmpInst.addOperand(MCOperand::createReg( 8012 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 8013 Inst = TmpInst; 8014 return true; 8015 } 8016 // Handle the ARM mode MOV complex aliases. 8017 case ARM::ASRr: 8018 case ARM::LSRr: 8019 case ARM::LSLr: 8020 case ARM::RORr: { 8021 ARM_AM::ShiftOpc ShiftTy; 8022 switch(Inst.getOpcode()) { 8023 default: llvm_unreachable("unexpected opcode!"); 8024 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; 8025 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; 8026 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; 8027 case ARM::RORr: ShiftTy = ARM_AM::ror; break; 8028 } 8029 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); 8030 MCInst TmpInst; 8031 TmpInst.setOpcode(ARM::MOVsr); 8032 TmpInst.addOperand(Inst.getOperand(0)); // Rd 8033 TmpInst.addOperand(Inst.getOperand(1)); // Rn 8034 TmpInst.addOperand(Inst.getOperand(2)); // Rm 8035 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty 8036 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 8037 TmpInst.addOperand(Inst.getOperand(4)); 8038 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 8039 Inst = TmpInst; 8040 return true; 8041 } 8042 case ARM::ASRi: 8043 case ARM::LSRi: 8044 case ARM::LSLi: 8045 case ARM::RORi: { 8046 ARM_AM::ShiftOpc ShiftTy; 8047 switch(Inst.getOpcode()) { 8048 default: llvm_unreachable("unexpected opcode!"); 8049 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; 8050 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; 8051 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; 8052 case ARM::RORi: ShiftTy = ARM_AM::ror; break; 8053 } 8054 // A shift by zero is a plain MOVr, not a MOVsi. 8055 unsigned Amt = Inst.getOperand(2).getImm(); 8056 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; 8057 // A shift by 32 should be encoded as 0 when permitted 8058 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr)) 8059 Amt = 0; 8060 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); 8061 MCInst TmpInst; 8062 TmpInst.setOpcode(Opc); 8063 TmpInst.addOperand(Inst.getOperand(0)); // Rd 8064 TmpInst.addOperand(Inst.getOperand(1)); // Rn 8065 if (Opc == ARM::MOVsi) 8066 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty 8067 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 8068 TmpInst.addOperand(Inst.getOperand(4)); 8069 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 8070 Inst = TmpInst; 8071 return true; 8072 } 8073 case ARM::RRXi: { 8074 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); 8075 MCInst TmpInst; 8076 TmpInst.setOpcode(ARM::MOVsi); 8077 TmpInst.addOperand(Inst.getOperand(0)); // Rd 8078 TmpInst.addOperand(Inst.getOperand(1)); // Rn 8079 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty 8080 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 8081 TmpInst.addOperand(Inst.getOperand(3)); 8082 TmpInst.addOperand(Inst.getOperand(4)); // cc_out 8083 Inst = TmpInst; 8084 return true; 8085 } 8086 case ARM::t2LDMIA_UPD: { 8087 // If this is a load of a single register, then we should use 8088 // a post-indexed LDR instruction instead, per the ARM ARM. 8089 if (Inst.getNumOperands() != 5) 8090 return false; 8091 MCInst TmpInst; 8092 TmpInst.setOpcode(ARM::t2LDR_POST); 8093 TmpInst.addOperand(Inst.getOperand(4)); // Rt 8094 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 8095 TmpInst.addOperand(Inst.getOperand(1)); // Rn 8096 TmpInst.addOperand(MCOperand::createImm(4)); 8097 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 8098 TmpInst.addOperand(Inst.getOperand(3)); 8099 Inst = TmpInst; 8100 return true; 8101 } 8102 case ARM::t2STMDB_UPD: { 8103 // If this is a store of a single register, then we should use 8104 // a pre-indexed STR instruction instead, per the ARM ARM. 8105 if (Inst.getNumOperands() != 5) 8106 return false; 8107 MCInst TmpInst; 8108 TmpInst.setOpcode(ARM::t2STR_PRE); 8109 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 8110 TmpInst.addOperand(Inst.getOperand(4)); // Rt 8111 TmpInst.addOperand(Inst.getOperand(1)); // Rn 8112 TmpInst.addOperand(MCOperand::createImm(-4)); 8113 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 8114 TmpInst.addOperand(Inst.getOperand(3)); 8115 Inst = TmpInst; 8116 return true; 8117 } 8118 case ARM::LDMIA_UPD: 8119 // If this is a load of a single register via a 'pop', then we should use 8120 // a post-indexed LDR instruction instead, per the ARM ARM. 8121 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" && 8122 Inst.getNumOperands() == 5) { 8123 MCInst TmpInst; 8124 TmpInst.setOpcode(ARM::LDR_POST_IMM); 8125 TmpInst.addOperand(Inst.getOperand(4)); // Rt 8126 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 8127 TmpInst.addOperand(Inst.getOperand(1)); // Rn 8128 TmpInst.addOperand(MCOperand::createReg(0)); // am2offset 8129 TmpInst.addOperand(MCOperand::createImm(4)); 8130 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 8131 TmpInst.addOperand(Inst.getOperand(3)); 8132 Inst = TmpInst; 8133 return true; 8134 } 8135 break; 8136 case ARM::STMDB_UPD: 8137 // If this is a store of a single register via a 'push', then we should use 8138 // a pre-indexed STR instruction instead, per the ARM ARM. 8139 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" && 8140 Inst.getNumOperands() == 5) { 8141 MCInst TmpInst; 8142 TmpInst.setOpcode(ARM::STR_PRE_IMM); 8143 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 8144 TmpInst.addOperand(Inst.getOperand(4)); // Rt 8145 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 8146 TmpInst.addOperand(MCOperand::createImm(-4)); 8147 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 8148 TmpInst.addOperand(Inst.getOperand(3)); 8149 Inst = TmpInst; 8150 } 8151 break; 8152 case ARM::t2ADDri12: 8153 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add" 8154 // mnemonic was used (not "addw"), encoding T3 is preferred. 8155 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" || 8156 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 8157 break; 8158 Inst.setOpcode(ARM::t2ADDri); 8159 Inst.addOperand(MCOperand::createReg(0)); // cc_out 8160 break; 8161 case ARM::t2SUBri12: 8162 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub" 8163 // mnemonic was used (not "subw"), encoding T3 is preferred. 8164 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" || 8165 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 8166 break; 8167 Inst.setOpcode(ARM::t2SUBri); 8168 Inst.addOperand(MCOperand::createReg(0)); // cc_out 8169 break; 8170 case ARM::tADDi8: 8171 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 8172 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 8173 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 8174 // to encoding T1 if <Rd> is omitted." 8175 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 8176 Inst.setOpcode(ARM::tADDi3); 8177 return true; 8178 } 8179 break; 8180 case ARM::tSUBi8: 8181 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 8182 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 8183 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 8184 // to encoding T1 if <Rd> is omitted." 8185 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 8186 Inst.setOpcode(ARM::tSUBi3); 8187 return true; 8188 } 8189 break; 8190 case ARM::t2ADDri: 8191 case ARM::t2SUBri: { 8192 // If the destination and first source operand are the same, and 8193 // the flags are compatible with the current IT status, use encoding T2 8194 // instead of T3. For compatibility with the system 'as'. Make sure the 8195 // wide encoding wasn't explicit. 8196 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 8197 !isARMLowRegister(Inst.getOperand(0).getReg()) || 8198 (unsigned)Inst.getOperand(2).getImm() > 255 || 8199 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) || 8200 (inITBlock() && Inst.getOperand(5).getReg() != 0)) || 8201 (static_cast<ARMOperand &>(*Operands[3]).isToken() && 8202 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) 8203 break; 8204 MCInst TmpInst; 8205 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? 8206 ARM::tADDi8 : ARM::tSUBi8); 8207 TmpInst.addOperand(Inst.getOperand(0)); 8208 TmpInst.addOperand(Inst.getOperand(5)); 8209 TmpInst.addOperand(Inst.getOperand(0)); 8210 TmpInst.addOperand(Inst.getOperand(2)); 8211 TmpInst.addOperand(Inst.getOperand(3)); 8212 TmpInst.addOperand(Inst.getOperand(4)); 8213 Inst = TmpInst; 8214 return true; 8215 } 8216 case ARM::t2ADDrr: { 8217 // If the destination and first source operand are the same, and 8218 // there's no setting of the flags, use encoding T2 instead of T3. 8219 // Note that this is only for ADD, not SUB. This mirrors the system 8220 // 'as' behaviour. Also take advantage of ADD being commutative. 8221 // Make sure the wide encoding wasn't explicit. 8222 bool Swap = false; 8223 auto DestReg = Inst.getOperand(0).getReg(); 8224 bool Transform = DestReg == Inst.getOperand(1).getReg(); 8225 if (!Transform && DestReg == Inst.getOperand(2).getReg()) { 8226 Transform = true; 8227 Swap = true; 8228 } 8229 if (!Transform || 8230 Inst.getOperand(5).getReg() != 0 || 8231 (static_cast<ARMOperand &>(*Operands[3]).isToken() && 8232 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) 8233 break; 8234 MCInst TmpInst; 8235 TmpInst.setOpcode(ARM::tADDhirr); 8236 TmpInst.addOperand(Inst.getOperand(0)); 8237 TmpInst.addOperand(Inst.getOperand(0)); 8238 TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2)); 8239 TmpInst.addOperand(Inst.getOperand(3)); 8240 TmpInst.addOperand(Inst.getOperand(4)); 8241 Inst = TmpInst; 8242 return true; 8243 } 8244 case ARM::tADDrSP: { 8245 // If the non-SP source operand and the destination operand are not the 8246 // same, we need to use the 32-bit encoding if it's available. 8247 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 8248 Inst.setOpcode(ARM::t2ADDrr); 8249 Inst.addOperand(MCOperand::createReg(0)); // cc_out 8250 return true; 8251 } 8252 break; 8253 } 8254 case ARM::tB: 8255 // A Thumb conditional branch outside of an IT block is a tBcc. 8256 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { 8257 Inst.setOpcode(ARM::tBcc); 8258 return true; 8259 } 8260 break; 8261 case ARM::t2B: 8262 // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 8263 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ 8264 Inst.setOpcode(ARM::t2Bcc); 8265 return true; 8266 } 8267 break; 8268 case ARM::t2Bcc: 8269 // If the conditional is AL or we're in an IT block, we really want t2B. 8270 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { 8271 Inst.setOpcode(ARM::t2B); 8272 return true; 8273 } 8274 break; 8275 case ARM::tBcc: 8276 // If the conditional is AL, we really want tB. 8277 if (Inst.getOperand(1).getImm() == ARMCC::AL) { 8278 Inst.setOpcode(ARM::tB); 8279 return true; 8280 } 8281 break; 8282 case ARM::tLDMIA: { 8283 // If the register list contains any high registers, or if the writeback 8284 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 8285 // instead if we're in Thumb2. Otherwise, this should have generated 8286 // an error in validateInstruction(). 8287 unsigned Rn = Inst.getOperand(0).getReg(); 8288 bool hasWritebackToken = 8289 (static_cast<ARMOperand &>(*Operands[3]).isToken() && 8290 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); 8291 bool listContainsBase; 8292 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 8293 (!listContainsBase && !hasWritebackToken) || 8294 (listContainsBase && hasWritebackToken)) { 8295 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 8296 assert (isThumbTwo()); 8297 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 8298 // If we're switching to the updating version, we need to insert 8299 // the writeback tied operand. 8300 if (hasWritebackToken) 8301 Inst.insert(Inst.begin(), 8302 MCOperand::createReg(Inst.getOperand(0).getReg())); 8303 return true; 8304 } 8305 break; 8306 } 8307 case ARM::tSTMIA_UPD: { 8308 // If the register list contains any high registers, we need to use 8309 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 8310 // should have generated an error in validateInstruction(). 8311 unsigned Rn = Inst.getOperand(0).getReg(); 8312 bool listContainsBase; 8313 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 8314 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 8315 assert (isThumbTwo()); 8316 Inst.setOpcode(ARM::t2STMIA_UPD); 8317 return true; 8318 } 8319 break; 8320 } 8321 case ARM::tPOP: { 8322 bool listContainsBase; 8323 // If the register list contains any high registers, we need to use 8324 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 8325 // should have generated an error in validateInstruction(). 8326 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) 8327 return false; 8328 assert (isThumbTwo()); 8329 Inst.setOpcode(ARM::t2LDMIA_UPD); 8330 // Add the base register and writeback operands. 8331 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); 8332 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); 8333 return true; 8334 } 8335 case ARM::tPUSH: { 8336 bool listContainsBase; 8337 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) 8338 return false; 8339 assert (isThumbTwo()); 8340 Inst.setOpcode(ARM::t2STMDB_UPD); 8341 // Add the base register and writeback operands. 8342 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); 8343 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP)); 8344 return true; 8345 } 8346 case ARM::t2MOVi: { 8347 // If we can use the 16-bit encoding and the user didn't explicitly 8348 // request the 32-bit variant, transform it here. 8349 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 8350 (unsigned)Inst.getOperand(1).getImm() <= 255 && 8351 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && 8352 Inst.getOperand(4).getReg() == ARM::CPSR) || 8353 (inITBlock() && Inst.getOperand(4).getReg() == 0)) && 8354 (!static_cast<ARMOperand &>(*Operands[2]).isToken() || 8355 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) { 8356 // The operands aren't in the same order for tMOVi8... 8357 MCInst TmpInst; 8358 TmpInst.setOpcode(ARM::tMOVi8); 8359 TmpInst.addOperand(Inst.getOperand(0)); 8360 TmpInst.addOperand(Inst.getOperand(4)); 8361 TmpInst.addOperand(Inst.getOperand(1)); 8362 TmpInst.addOperand(Inst.getOperand(2)); 8363 TmpInst.addOperand(Inst.getOperand(3)); 8364 Inst = TmpInst; 8365 return true; 8366 } 8367 break; 8368 } 8369 case ARM::t2MOVr: { 8370 // If we can use the 16-bit encoding and the user didn't explicitly 8371 // request the 32-bit variant, transform it here. 8372 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 8373 isARMLowRegister(Inst.getOperand(1).getReg()) && 8374 Inst.getOperand(2).getImm() == ARMCC::AL && 8375 Inst.getOperand(4).getReg() == ARM::CPSR && 8376 (!static_cast<ARMOperand &>(*Operands[2]).isToken() || 8377 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) { 8378 // The operands aren't the same for tMOV[S]r... (no cc_out) 8379 MCInst TmpInst; 8380 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 8381 TmpInst.addOperand(Inst.getOperand(0)); 8382 TmpInst.addOperand(Inst.getOperand(1)); 8383 TmpInst.addOperand(Inst.getOperand(2)); 8384 TmpInst.addOperand(Inst.getOperand(3)); 8385 Inst = TmpInst; 8386 return true; 8387 } 8388 break; 8389 } 8390 case ARM::t2SXTH: 8391 case ARM::t2SXTB: 8392 case ARM::t2UXTH: 8393 case ARM::t2UXTB: { 8394 // If we can use the 16-bit encoding and the user didn't explicitly 8395 // request the 32-bit variant, transform it here. 8396 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 8397 isARMLowRegister(Inst.getOperand(1).getReg()) && 8398 Inst.getOperand(2).getImm() == 0 && 8399 (!static_cast<ARMOperand &>(*Operands[2]).isToken() || 8400 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) { 8401 unsigned NewOpc; 8402 switch (Inst.getOpcode()) { 8403 default: llvm_unreachable("Illegal opcode!"); 8404 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 8405 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 8406 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 8407 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; 8408 } 8409 // The operands aren't the same for thumb1 (no rotate operand). 8410 MCInst TmpInst; 8411 TmpInst.setOpcode(NewOpc); 8412 TmpInst.addOperand(Inst.getOperand(0)); 8413 TmpInst.addOperand(Inst.getOperand(1)); 8414 TmpInst.addOperand(Inst.getOperand(3)); 8415 TmpInst.addOperand(Inst.getOperand(4)); 8416 Inst = TmpInst; 8417 return true; 8418 } 8419 break; 8420 } 8421 case ARM::MOVsi: { 8422 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 8423 // rrx shifts and asr/lsr of #32 is encoded as 0 8424 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr) 8425 return false; 8426 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { 8427 // Shifting by zero is accepted as a vanilla 'MOVr' 8428 MCInst TmpInst; 8429 TmpInst.setOpcode(ARM::MOVr); 8430 TmpInst.addOperand(Inst.getOperand(0)); 8431 TmpInst.addOperand(Inst.getOperand(1)); 8432 TmpInst.addOperand(Inst.getOperand(3)); 8433 TmpInst.addOperand(Inst.getOperand(4)); 8434 TmpInst.addOperand(Inst.getOperand(5)); 8435 Inst = TmpInst; 8436 return true; 8437 } 8438 return false; 8439 } 8440 case ARM::ANDrsi: 8441 case ARM::ORRrsi: 8442 case ARM::EORrsi: 8443 case ARM::BICrsi: 8444 case ARM::SUBrsi: 8445 case ARM::ADDrsi: { 8446 unsigned newOpc; 8447 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); 8448 if (SOpc == ARM_AM::rrx) return false; 8449 switch (Inst.getOpcode()) { 8450 default: llvm_unreachable("unexpected opcode!"); 8451 case ARM::ANDrsi: newOpc = ARM::ANDrr; break; 8452 case ARM::ORRrsi: newOpc = ARM::ORRrr; break; 8453 case ARM::EORrsi: newOpc = ARM::EORrr; break; 8454 case ARM::BICrsi: newOpc = ARM::BICrr; break; 8455 case ARM::SUBrsi: newOpc = ARM::SUBrr; break; 8456 case ARM::ADDrsi: newOpc = ARM::ADDrr; break; 8457 } 8458 // If the shift is by zero, use the non-shifted instruction definition. 8459 // The exception is for right shifts, where 0 == 32 8460 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 && 8461 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) { 8462 MCInst TmpInst; 8463 TmpInst.setOpcode(newOpc); 8464 TmpInst.addOperand(Inst.getOperand(0)); 8465 TmpInst.addOperand(Inst.getOperand(1)); 8466 TmpInst.addOperand(Inst.getOperand(2)); 8467 TmpInst.addOperand(Inst.getOperand(4)); 8468 TmpInst.addOperand(Inst.getOperand(5)); 8469 TmpInst.addOperand(Inst.getOperand(6)); 8470 Inst = TmpInst; 8471 return true; 8472 } 8473 return false; 8474 } 8475 case ARM::ITasm: 8476 case ARM::t2IT: { 8477 // The mask bits for all but the first condition are represented as 8478 // the low bit of the condition code value implies 't'. We currently 8479 // always have 1 implies 't', so XOR toggle the bits if the low bit 8480 // of the condition code is zero. 8481 MCOperand &MO = Inst.getOperand(1); 8482 unsigned Mask = MO.getImm(); 8483 unsigned OrigMask = Mask; 8484 unsigned TZ = countTrailingZeros(Mask); 8485 if ((Inst.getOperand(0).getImm() & 1) == 0) { 8486 assert(Mask && TZ <= 3 && "illegal IT mask value!"); 8487 Mask ^= (0xE << TZ) & 0xF; 8488 } 8489 MO.setImm(Mask); 8490 8491 // Set up the IT block state according to the IT instruction we just 8492 // matched. 8493 assert(!inITBlock() && "nested IT blocks?!"); 8494 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); 8495 ITState.Mask = OrigMask; // Use the original mask, not the updated one. 8496 ITState.CurPosition = 0; 8497 ITState.FirstCond = true; 8498 break; 8499 } 8500 case ARM::t2LSLrr: 8501 case ARM::t2LSRrr: 8502 case ARM::t2ASRrr: 8503 case ARM::t2SBCrr: 8504 case ARM::t2RORrr: 8505 case ARM::t2BICrr: 8506 { 8507 // Assemblers should use the narrow encodings of these instructions when permissible. 8508 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 8509 isARMLowRegister(Inst.getOperand(2).getReg())) && 8510 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 8511 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 8512 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 8513 (!static_cast<ARMOperand &>(*Operands[3]).isToken() || 8514 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower( 8515 ".w"))) { 8516 unsigned NewOpc; 8517 switch (Inst.getOpcode()) { 8518 default: llvm_unreachable("unexpected opcode"); 8519 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break; 8520 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break; 8521 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break; 8522 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break; 8523 case ARM::t2RORrr: NewOpc = ARM::tROR; break; 8524 case ARM::t2BICrr: NewOpc = ARM::tBIC; break; 8525 } 8526 MCInst TmpInst; 8527 TmpInst.setOpcode(NewOpc); 8528 TmpInst.addOperand(Inst.getOperand(0)); 8529 TmpInst.addOperand(Inst.getOperand(5)); 8530 TmpInst.addOperand(Inst.getOperand(1)); 8531 TmpInst.addOperand(Inst.getOperand(2)); 8532 TmpInst.addOperand(Inst.getOperand(3)); 8533 TmpInst.addOperand(Inst.getOperand(4)); 8534 Inst = TmpInst; 8535 return true; 8536 } 8537 return false; 8538 } 8539 case ARM::t2ANDrr: 8540 case ARM::t2EORrr: 8541 case ARM::t2ADCrr: 8542 case ARM::t2ORRrr: 8543 { 8544 // Assemblers should use the narrow encodings of these instructions when permissible. 8545 // These instructions are special in that they are commutable, so shorter encodings 8546 // are available more often. 8547 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 8548 isARMLowRegister(Inst.getOperand(2).getReg())) && 8549 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || 8550 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && 8551 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 8552 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 8553 (!static_cast<ARMOperand &>(*Operands[3]).isToken() || 8554 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower( 8555 ".w"))) { 8556 unsigned NewOpc; 8557 switch (Inst.getOpcode()) { 8558 default: llvm_unreachable("unexpected opcode"); 8559 case ARM::t2ADCrr: NewOpc = ARM::tADC; break; 8560 case ARM::t2ANDrr: NewOpc = ARM::tAND; break; 8561 case ARM::t2EORrr: NewOpc = ARM::tEOR; break; 8562 case ARM::t2ORRrr: NewOpc = ARM::tORR; break; 8563 } 8564 MCInst TmpInst; 8565 TmpInst.setOpcode(NewOpc); 8566 TmpInst.addOperand(Inst.getOperand(0)); 8567 TmpInst.addOperand(Inst.getOperand(5)); 8568 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) { 8569 TmpInst.addOperand(Inst.getOperand(1)); 8570 TmpInst.addOperand(Inst.getOperand(2)); 8571 } else { 8572 TmpInst.addOperand(Inst.getOperand(2)); 8573 TmpInst.addOperand(Inst.getOperand(1)); 8574 } 8575 TmpInst.addOperand(Inst.getOperand(3)); 8576 TmpInst.addOperand(Inst.getOperand(4)); 8577 Inst = TmpInst; 8578 return true; 8579 } 8580 return false; 8581 } 8582 } 8583 return false; 8584 } 8585 8586 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 8587 // 16-bit thumb arithmetic instructions either require or preclude the 'S' 8588 // suffix depending on whether they're in an IT block or not. 8589 unsigned Opc = Inst.getOpcode(); 8590 const MCInstrDesc &MCID = MII.get(Opc); 8591 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 8592 assert(MCID.hasOptionalDef() && 8593 "optionally flag setting instruction missing optional def operand"); 8594 assert(MCID.NumOperands == Inst.getNumOperands() && 8595 "operand count mismatch!"); 8596 // Find the optional-def operand (cc_out). 8597 unsigned OpNo; 8598 for (OpNo = 0; 8599 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 8600 ++OpNo) 8601 ; 8602 // If we're parsing Thumb1, reject it completely. 8603 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 8604 return Match_MnemonicFail; 8605 // If we're parsing Thumb2, which form is legal depends on whether we're 8606 // in an IT block. 8607 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 8608 !inITBlock()) 8609 return Match_RequiresITBlock; 8610 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 8611 inITBlock()) 8612 return Match_RequiresNotITBlock; 8613 } 8614 // Some high-register supporting Thumb1 encodings only allow both registers 8615 // to be from r0-r7 when in Thumb2. 8616 else if (Opc == ARM::tADDhirr && isThumbOne() && !hasV6MOps() && 8617 isARMLowRegister(Inst.getOperand(1).getReg()) && 8618 isARMLowRegister(Inst.getOperand(2).getReg())) 8619 return Match_RequiresThumb2; 8620 // Others only require ARMv6 or later. 8621 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && 8622 isARMLowRegister(Inst.getOperand(0).getReg()) && 8623 isARMLowRegister(Inst.getOperand(1).getReg())) 8624 return Match_RequiresV6; 8625 return Match_Success; 8626 } 8627 8628 namespace llvm { 8629 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) { 8630 return true; // In an assembly source, no need to second-guess 8631 } 8632 } 8633 8634 static const char *getSubtargetFeatureName(uint64_t Val); 8635 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 8636 OperandVector &Operands, 8637 MCStreamer &Out, uint64_t &ErrorInfo, 8638 bool MatchingInlineAsm) { 8639 MCInst Inst; 8640 unsigned MatchResult; 8641 8642 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, 8643 MatchingInlineAsm); 8644 switch (MatchResult) { 8645 case Match_Success: 8646 // Context sensitive operand constraints aren't handled by the matcher, 8647 // so check them here. 8648 if (validateInstruction(Inst, Operands)) { 8649 // Still progress the IT block, otherwise one wrong condition causes 8650 // nasty cascading errors. 8651 forwardITPosition(); 8652 return true; 8653 } 8654 8655 { // processInstruction() updates inITBlock state, we need to save it away 8656 bool wasInITBlock = inITBlock(); 8657 8658 // Some instructions need post-processing to, for example, tweak which 8659 // encoding is selected. Loop on it while changes happen so the 8660 // individual transformations can chain off each other. E.g., 8661 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8) 8662 while (processInstruction(Inst, Operands, Out)) 8663 ; 8664 8665 // Only after the instruction is fully processed, we can validate it 8666 if (wasInITBlock && hasV8Ops() && isThumb() && 8667 !isV8EligibleForIT(&Inst)) { 8668 Warning(IDLoc, "deprecated instruction in IT block"); 8669 } 8670 } 8671 8672 // Only move forward at the very end so that everything in validate 8673 // and process gets a consistent answer about whether we're in an IT 8674 // block. 8675 forwardITPosition(); 8676 8677 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and 8678 // doesn't actually encode. 8679 if (Inst.getOpcode() == ARM::ITasm) 8680 return false; 8681 8682 Inst.setLoc(IDLoc); 8683 Out.EmitInstruction(Inst, STI); 8684 return false; 8685 case Match_MissingFeature: { 8686 assert(ErrorInfo && "Unknown missing feature!"); 8687 // Special case the error message for the very common case where only 8688 // a single subtarget feature is missing (Thumb vs. ARM, e.g.). 8689 std::string Msg = "instruction requires:"; 8690 uint64_t Mask = 1; 8691 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) { 8692 if (ErrorInfo & Mask) { 8693 Msg += " "; 8694 Msg += getSubtargetFeatureName(ErrorInfo & Mask); 8695 } 8696 Mask <<= 1; 8697 } 8698 return Error(IDLoc, Msg); 8699 } 8700 case Match_InvalidOperand: { 8701 SMLoc ErrorLoc = IDLoc; 8702 if (ErrorInfo != ~0ULL) { 8703 if (ErrorInfo >= Operands.size()) 8704 return Error(IDLoc, "too few operands for instruction"); 8705 8706 ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc(); 8707 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 8708 } 8709 8710 return Error(ErrorLoc, "invalid operand for instruction"); 8711 } 8712 case Match_MnemonicFail: 8713 return Error(IDLoc, "invalid instruction", 8714 ((ARMOperand &)*Operands[0]).getLocRange()); 8715 case Match_RequiresNotITBlock: 8716 return Error(IDLoc, "flag setting instruction only valid outside IT block"); 8717 case Match_RequiresITBlock: 8718 return Error(IDLoc, "instruction only valid inside IT block"); 8719 case Match_RequiresV6: 8720 return Error(IDLoc, "instruction variant requires ARMv6 or later"); 8721 case Match_RequiresThumb2: 8722 return Error(IDLoc, "instruction variant requires Thumb2"); 8723 case Match_ImmRange0_15: { 8724 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc(); 8725 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 8726 return Error(ErrorLoc, "immediate operand must be in the range [0,15]"); 8727 } 8728 case Match_ImmRange0_239: { 8729 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc(); 8730 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 8731 return Error(ErrorLoc, "immediate operand must be in the range [0,239]"); 8732 } 8733 case Match_AlignedMemoryRequiresNone: 8734 case Match_DupAlignedMemoryRequiresNone: 8735 case Match_AlignedMemoryRequires16: 8736 case Match_DupAlignedMemoryRequires16: 8737 case Match_AlignedMemoryRequires32: 8738 case Match_DupAlignedMemoryRequires32: 8739 case Match_AlignedMemoryRequires64: 8740 case Match_DupAlignedMemoryRequires64: 8741 case Match_AlignedMemoryRequires64or128: 8742 case Match_DupAlignedMemoryRequires64or128: 8743 case Match_AlignedMemoryRequires64or128or256: 8744 { 8745 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc(); 8746 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 8747 switch (MatchResult) { 8748 default: 8749 llvm_unreachable("Missing Match_Aligned type"); 8750 case Match_AlignedMemoryRequiresNone: 8751 case Match_DupAlignedMemoryRequiresNone: 8752 return Error(ErrorLoc, "alignment must be omitted"); 8753 case Match_AlignedMemoryRequires16: 8754 case Match_DupAlignedMemoryRequires16: 8755 return Error(ErrorLoc, "alignment must be 16 or omitted"); 8756 case Match_AlignedMemoryRequires32: 8757 case Match_DupAlignedMemoryRequires32: 8758 return Error(ErrorLoc, "alignment must be 32 or omitted"); 8759 case Match_AlignedMemoryRequires64: 8760 case Match_DupAlignedMemoryRequires64: 8761 return Error(ErrorLoc, "alignment must be 64 or omitted"); 8762 case Match_AlignedMemoryRequires64or128: 8763 case Match_DupAlignedMemoryRequires64or128: 8764 return Error(ErrorLoc, "alignment must be 64, 128 or omitted"); 8765 case Match_AlignedMemoryRequires64or128or256: 8766 return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted"); 8767 } 8768 } 8769 } 8770 8771 llvm_unreachable("Implement any new match types added!"); 8772 } 8773 8774 /// parseDirective parses the arm specific directives 8775 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 8776 const MCObjectFileInfo::Environment Format = 8777 getContext().getObjectFileInfo()->getObjectFileType(); 8778 bool IsMachO = Format == MCObjectFileInfo::IsMachO; 8779 bool IsCOFF = Format == MCObjectFileInfo::IsCOFF; 8780 8781 StringRef IDVal = DirectiveID.getIdentifier(); 8782 if (IDVal == ".word") 8783 return parseLiteralValues(4, DirectiveID.getLoc()); 8784 else if (IDVal == ".short" || IDVal == ".hword") 8785 return parseLiteralValues(2, DirectiveID.getLoc()); 8786 else if (IDVal == ".thumb") 8787 return parseDirectiveThumb(DirectiveID.getLoc()); 8788 else if (IDVal == ".arm") 8789 return parseDirectiveARM(DirectiveID.getLoc()); 8790 else if (IDVal == ".thumb_func") 8791 return parseDirectiveThumbFunc(DirectiveID.getLoc()); 8792 else if (IDVal == ".code") 8793 return parseDirectiveCode(DirectiveID.getLoc()); 8794 else if (IDVal == ".syntax") 8795 return parseDirectiveSyntax(DirectiveID.getLoc()); 8796 else if (IDVal == ".unreq") 8797 return parseDirectiveUnreq(DirectiveID.getLoc()); 8798 else if (IDVal == ".fnend") 8799 return parseDirectiveFnEnd(DirectiveID.getLoc()); 8800 else if (IDVal == ".cantunwind") 8801 return parseDirectiveCantUnwind(DirectiveID.getLoc()); 8802 else if (IDVal == ".personality") 8803 return parseDirectivePersonality(DirectiveID.getLoc()); 8804 else if (IDVal == ".handlerdata") 8805 return parseDirectiveHandlerData(DirectiveID.getLoc()); 8806 else if (IDVal == ".setfp") 8807 return parseDirectiveSetFP(DirectiveID.getLoc()); 8808 else if (IDVal == ".pad") 8809 return parseDirectivePad(DirectiveID.getLoc()); 8810 else if (IDVal == ".save") 8811 return parseDirectiveRegSave(DirectiveID.getLoc(), false); 8812 else if (IDVal == ".vsave") 8813 return parseDirectiveRegSave(DirectiveID.getLoc(), true); 8814 else if (IDVal == ".ltorg" || IDVal == ".pool") 8815 return parseDirectiveLtorg(DirectiveID.getLoc()); 8816 else if (IDVal == ".even") 8817 return parseDirectiveEven(DirectiveID.getLoc()); 8818 else if (IDVal == ".personalityindex") 8819 return parseDirectivePersonalityIndex(DirectiveID.getLoc()); 8820 else if (IDVal == ".unwind_raw") 8821 return parseDirectiveUnwindRaw(DirectiveID.getLoc()); 8822 else if (IDVal == ".movsp") 8823 return parseDirectiveMovSP(DirectiveID.getLoc()); 8824 else if (IDVal == ".arch_extension") 8825 return parseDirectiveArchExtension(DirectiveID.getLoc()); 8826 else if (IDVal == ".align") 8827 return parseDirectiveAlign(DirectiveID.getLoc()); 8828 else if (IDVal == ".thumb_set") 8829 return parseDirectiveThumbSet(DirectiveID.getLoc()); 8830 8831 if (!IsMachO && !IsCOFF) { 8832 if (IDVal == ".arch") 8833 return parseDirectiveArch(DirectiveID.getLoc()); 8834 else if (IDVal == ".cpu") 8835 return parseDirectiveCPU(DirectiveID.getLoc()); 8836 else if (IDVal == ".eabi_attribute") 8837 return parseDirectiveEabiAttr(DirectiveID.getLoc()); 8838 else if (IDVal == ".fpu") 8839 return parseDirectiveFPU(DirectiveID.getLoc()); 8840 else if (IDVal == ".fnstart") 8841 return parseDirectiveFnStart(DirectiveID.getLoc()); 8842 else if (IDVal == ".inst") 8843 return parseDirectiveInst(DirectiveID.getLoc()); 8844 else if (IDVal == ".inst.n") 8845 return parseDirectiveInst(DirectiveID.getLoc(), 'n'); 8846 else if (IDVal == ".inst.w") 8847 return parseDirectiveInst(DirectiveID.getLoc(), 'w'); 8848 else if (IDVal == ".object_arch") 8849 return parseDirectiveObjectArch(DirectiveID.getLoc()); 8850 else if (IDVal == ".tlsdescseq") 8851 return parseDirectiveTLSDescSeq(DirectiveID.getLoc()); 8852 } 8853 8854 return true; 8855 } 8856 8857 /// parseLiteralValues 8858 /// ::= .hword expression [, expression]* 8859 /// ::= .short expression [, expression]* 8860 /// ::= .word expression [, expression]* 8861 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) { 8862 MCAsmParser &Parser = getParser(); 8863 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8864 for (;;) { 8865 const MCExpr *Value; 8866 if (getParser().parseExpression(Value)) { 8867 Parser.eatToEndOfStatement(); 8868 return false; 8869 } 8870 8871 getParser().getStreamer().EmitValue(Value, Size); 8872 8873 if (getLexer().is(AsmToken::EndOfStatement)) 8874 break; 8875 8876 // FIXME: Improve diagnostic. 8877 if (getLexer().isNot(AsmToken::Comma)) { 8878 Error(L, "unexpected token in directive"); 8879 return false; 8880 } 8881 Parser.Lex(); 8882 } 8883 } 8884 8885 Parser.Lex(); 8886 return false; 8887 } 8888 8889 /// parseDirectiveThumb 8890 /// ::= .thumb 8891 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 8892 MCAsmParser &Parser = getParser(); 8893 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8894 Error(L, "unexpected token in directive"); 8895 return false; 8896 } 8897 Parser.Lex(); 8898 8899 if (!hasThumb()) { 8900 Error(L, "target does not support Thumb mode"); 8901 return false; 8902 } 8903 8904 if (!isThumb()) 8905 SwitchMode(); 8906 8907 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 8908 return false; 8909 } 8910 8911 /// parseDirectiveARM 8912 /// ::= .arm 8913 bool ARMAsmParser::parseDirectiveARM(SMLoc L) { 8914 MCAsmParser &Parser = getParser(); 8915 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8916 Error(L, "unexpected token in directive"); 8917 return false; 8918 } 8919 Parser.Lex(); 8920 8921 if (!hasARM()) { 8922 Error(L, "target does not support ARM mode"); 8923 return false; 8924 } 8925 8926 if (isThumb()) 8927 SwitchMode(); 8928 8929 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 8930 return false; 8931 } 8932 8933 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) { 8934 if (NextSymbolIsThumb) { 8935 getParser().getStreamer().EmitThumbFunc(Symbol); 8936 NextSymbolIsThumb = false; 8937 } 8938 } 8939 8940 /// parseDirectiveThumbFunc 8941 /// ::= .thumbfunc symbol_name 8942 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 8943 MCAsmParser &Parser = getParser(); 8944 const auto Format = getContext().getObjectFileInfo()->getObjectFileType(); 8945 bool IsMachO = Format == MCObjectFileInfo::IsMachO; 8946 8947 // Darwin asm has (optionally) function name after .thumb_func direction 8948 // ELF doesn't 8949 if (IsMachO) { 8950 const AsmToken &Tok = Parser.getTok(); 8951 if (Tok.isNot(AsmToken::EndOfStatement)) { 8952 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) { 8953 Error(L, "unexpected token in .thumb_func directive"); 8954 return false; 8955 } 8956 8957 MCSymbol *Func = 8958 getParser().getContext().getOrCreateSymbol(Tok.getIdentifier()); 8959 getParser().getStreamer().EmitThumbFunc(Func); 8960 Parser.Lex(); // Consume the identifier token. 8961 return false; 8962 } 8963 } 8964 8965 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8966 Error(Parser.getTok().getLoc(), "unexpected token in directive"); 8967 Parser.eatToEndOfStatement(); 8968 return false; 8969 } 8970 8971 NextSymbolIsThumb = true; 8972 return false; 8973 } 8974 8975 /// parseDirectiveSyntax 8976 /// ::= .syntax unified | divided 8977 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 8978 MCAsmParser &Parser = getParser(); 8979 const AsmToken &Tok = Parser.getTok(); 8980 if (Tok.isNot(AsmToken::Identifier)) { 8981 Error(L, "unexpected token in .syntax directive"); 8982 return false; 8983 } 8984 8985 StringRef Mode = Tok.getString(); 8986 if (Mode == "unified" || Mode == "UNIFIED") { 8987 Parser.Lex(); 8988 } else if (Mode == "divided" || Mode == "DIVIDED") { 8989 Error(L, "'.syntax divided' arm asssembly not supported"); 8990 return false; 8991 } else { 8992 Error(L, "unrecognized syntax mode in .syntax directive"); 8993 return false; 8994 } 8995 8996 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8997 Error(Parser.getTok().getLoc(), "unexpected token in directive"); 8998 return false; 8999 } 9000 Parser.Lex(); 9001 9002 // TODO tell the MC streamer the mode 9003 // getParser().getStreamer().Emit???(); 9004 return false; 9005 } 9006 9007 /// parseDirectiveCode 9008 /// ::= .code 16 | 32 9009 bool ARMAsmParser::parseDirectiveCode(SMLoc L) { 9010 MCAsmParser &Parser = getParser(); 9011 const AsmToken &Tok = Parser.getTok(); 9012 if (Tok.isNot(AsmToken::Integer)) { 9013 Error(L, "unexpected token in .code directive"); 9014 return false; 9015 } 9016 int64_t Val = Parser.getTok().getIntVal(); 9017 if (Val != 16 && Val != 32) { 9018 Error(L, "invalid operand to .code directive"); 9019 return false; 9020 } 9021 Parser.Lex(); 9022 9023 if (getLexer().isNot(AsmToken::EndOfStatement)) { 9024 Error(Parser.getTok().getLoc(), "unexpected token in directive"); 9025 return false; 9026 } 9027 Parser.Lex(); 9028 9029 if (Val == 16) { 9030 if (!hasThumb()) { 9031 Error(L, "target does not support Thumb mode"); 9032 return false; 9033 } 9034 9035 if (!isThumb()) 9036 SwitchMode(); 9037 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 9038 } else { 9039 if (!hasARM()) { 9040 Error(L, "target does not support ARM mode"); 9041 return false; 9042 } 9043 9044 if (isThumb()) 9045 SwitchMode(); 9046 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 9047 } 9048 9049 return false; 9050 } 9051 9052 /// parseDirectiveReq 9053 /// ::= name .req registername 9054 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { 9055 MCAsmParser &Parser = getParser(); 9056 Parser.Lex(); // Eat the '.req' token. 9057 unsigned Reg; 9058 SMLoc SRegLoc, ERegLoc; 9059 if (ParseRegister(Reg, SRegLoc, ERegLoc)) { 9060 Parser.eatToEndOfStatement(); 9061 Error(SRegLoc, "register name expected"); 9062 return false; 9063 } 9064 9065 // Shouldn't be anything else. 9066 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { 9067 Parser.eatToEndOfStatement(); 9068 Error(Parser.getTok().getLoc(), "unexpected input in .req directive."); 9069 return false; 9070 } 9071 9072 Parser.Lex(); // Consume the EndOfStatement 9073 9074 if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg) { 9075 Error(SRegLoc, "redefinition of '" + Name + "' does not match original."); 9076 return false; 9077 } 9078 9079 return false; 9080 } 9081 9082 /// parseDirectiveUneq 9083 /// ::= .unreq registername 9084 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) { 9085 MCAsmParser &Parser = getParser(); 9086 if (Parser.getTok().isNot(AsmToken::Identifier)) { 9087 Parser.eatToEndOfStatement(); 9088 Error(L, "unexpected input in .unreq directive."); 9089 return false; 9090 } 9091 RegisterReqs.erase(Parser.getTok().getIdentifier().lower()); 9092 Parser.Lex(); // Eat the identifier. 9093 return false; 9094 } 9095 9096 /// parseDirectiveArch 9097 /// ::= .arch token 9098 bool ARMAsmParser::parseDirectiveArch(SMLoc L) { 9099 StringRef Arch = getParser().parseStringToEndOfStatement().trim(); 9100 9101 unsigned ID = ARMTargetParser::parseArch(Arch); 9102 9103 if (ID == ARM::AK_INVALID) { 9104 Error(L, "Unknown arch name"); 9105 return false; 9106 } 9107 9108 Triple T; 9109 STI.setDefaultFeatures(T.getARMCPUForArch(Arch)); 9110 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 9111 9112 getTargetStreamer().emitArch(ID); 9113 return false; 9114 } 9115 9116 /// parseDirectiveEabiAttr 9117 /// ::= .eabi_attribute int, int [, "str"] 9118 /// ::= .eabi_attribute Tag_name, int [, "str"] 9119 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { 9120 MCAsmParser &Parser = getParser(); 9121 int64_t Tag; 9122 SMLoc TagLoc; 9123 TagLoc = Parser.getTok().getLoc(); 9124 if (Parser.getTok().is(AsmToken::Identifier)) { 9125 StringRef Name = Parser.getTok().getIdentifier(); 9126 Tag = ARMBuildAttrs::AttrTypeFromString(Name); 9127 if (Tag == -1) { 9128 Error(TagLoc, "attribute name not recognised: " + Name); 9129 Parser.eatToEndOfStatement(); 9130 return false; 9131 } 9132 Parser.Lex(); 9133 } else { 9134 const MCExpr *AttrExpr; 9135 9136 TagLoc = Parser.getTok().getLoc(); 9137 if (Parser.parseExpression(AttrExpr)) { 9138 Parser.eatToEndOfStatement(); 9139 return false; 9140 } 9141 9142 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr); 9143 if (!CE) { 9144 Error(TagLoc, "expected numeric constant"); 9145 Parser.eatToEndOfStatement(); 9146 return false; 9147 } 9148 9149 Tag = CE->getValue(); 9150 } 9151 9152 if (Parser.getTok().isNot(AsmToken::Comma)) { 9153 Error(Parser.getTok().getLoc(), "comma expected"); 9154 Parser.eatToEndOfStatement(); 9155 return false; 9156 } 9157 Parser.Lex(); // skip comma 9158 9159 StringRef StringValue = ""; 9160 bool IsStringValue = false; 9161 9162 int64_t IntegerValue = 0; 9163 bool IsIntegerValue = false; 9164 9165 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name) 9166 IsStringValue = true; 9167 else if (Tag == ARMBuildAttrs::compatibility) { 9168 IsStringValue = true; 9169 IsIntegerValue = true; 9170 } else if (Tag < 32 || Tag % 2 == 0) 9171 IsIntegerValue = true; 9172 else if (Tag % 2 == 1) 9173 IsStringValue = true; 9174 else 9175 llvm_unreachable("invalid tag type"); 9176 9177 if (IsIntegerValue) { 9178 const MCExpr *ValueExpr; 9179 SMLoc ValueExprLoc = Parser.getTok().getLoc(); 9180 if (Parser.parseExpression(ValueExpr)) { 9181 Parser.eatToEndOfStatement(); 9182 return false; 9183 } 9184 9185 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr); 9186 if (!CE) { 9187 Error(ValueExprLoc, "expected numeric constant"); 9188 Parser.eatToEndOfStatement(); 9189 return false; 9190 } 9191 9192 IntegerValue = CE->getValue(); 9193 } 9194 9195 if (Tag == ARMBuildAttrs::compatibility) { 9196 if (Parser.getTok().isNot(AsmToken::Comma)) 9197 IsStringValue = false; 9198 if (Parser.getTok().isNot(AsmToken::Comma)) { 9199 Error(Parser.getTok().getLoc(), "comma expected"); 9200 Parser.eatToEndOfStatement(); 9201 return false; 9202 } else { 9203 Parser.Lex(); 9204 } 9205 } 9206 9207 if (IsStringValue) { 9208 if (Parser.getTok().isNot(AsmToken::String)) { 9209 Error(Parser.getTok().getLoc(), "bad string constant"); 9210 Parser.eatToEndOfStatement(); 9211 return false; 9212 } 9213 9214 StringValue = Parser.getTok().getStringContents(); 9215 Parser.Lex(); 9216 } 9217 9218 if (IsIntegerValue && IsStringValue) { 9219 assert(Tag == ARMBuildAttrs::compatibility); 9220 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue); 9221 } else if (IsIntegerValue) 9222 getTargetStreamer().emitAttribute(Tag, IntegerValue); 9223 else if (IsStringValue) 9224 getTargetStreamer().emitTextAttribute(Tag, StringValue); 9225 return false; 9226 } 9227 9228 /// parseDirectiveCPU 9229 /// ::= .cpu str 9230 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) { 9231 StringRef CPU = getParser().parseStringToEndOfStatement().trim(); 9232 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU); 9233 9234 // FIXME: This is using table-gen data, but should be moved to 9235 // ARMTargetParser once that is table-gen'd. 9236 if (!STI.isCPUStringValid(CPU)) { 9237 Error(L, "Unknown CPU name"); 9238 return false; 9239 } 9240 9241 STI.setDefaultFeatures(CPU); 9242 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 9243 9244 return false; 9245 } 9246 /// parseDirectiveFPU 9247 /// ::= .fpu str 9248 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) { 9249 SMLoc FPUNameLoc = getTok().getLoc(); 9250 StringRef FPU = getParser().parseStringToEndOfStatement().trim(); 9251 9252 unsigned ID = ARMTargetParser::parseFPU(FPU); 9253 std::vector<const char *> Features; 9254 if (!ARMTargetParser::getFPUFeatures(ID, Features)) { 9255 Error(FPUNameLoc, "Unknown FPU name"); 9256 return false; 9257 } 9258 9259 for (auto Feature : Features) 9260 STI.ApplyFeatureFlag(Feature); 9261 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 9262 9263 getTargetStreamer().emitFPU(ID); 9264 return false; 9265 } 9266 9267 /// parseDirectiveFnStart 9268 /// ::= .fnstart 9269 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) { 9270 if (UC.hasFnStart()) { 9271 Error(L, ".fnstart starts before the end of previous one"); 9272 UC.emitFnStartLocNotes(); 9273 return false; 9274 } 9275 9276 // Reset the unwind directives parser state 9277 UC.reset(); 9278 9279 getTargetStreamer().emitFnStart(); 9280 9281 UC.recordFnStart(L); 9282 return false; 9283 } 9284 9285 /// parseDirectiveFnEnd 9286 /// ::= .fnend 9287 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) { 9288 // Check the ordering of unwind directives 9289 if (!UC.hasFnStart()) { 9290 Error(L, ".fnstart must precede .fnend directive"); 9291 return false; 9292 } 9293 9294 // Reset the unwind directives parser state 9295 getTargetStreamer().emitFnEnd(); 9296 9297 UC.reset(); 9298 return false; 9299 } 9300 9301 /// parseDirectiveCantUnwind 9302 /// ::= .cantunwind 9303 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) { 9304 UC.recordCantUnwind(L); 9305 9306 // Check the ordering of unwind directives 9307 if (!UC.hasFnStart()) { 9308 Error(L, ".fnstart must precede .cantunwind directive"); 9309 return false; 9310 } 9311 if (UC.hasHandlerData()) { 9312 Error(L, ".cantunwind can't be used with .handlerdata directive"); 9313 UC.emitHandlerDataLocNotes(); 9314 return false; 9315 } 9316 if (UC.hasPersonality()) { 9317 Error(L, ".cantunwind can't be used with .personality directive"); 9318 UC.emitPersonalityLocNotes(); 9319 return false; 9320 } 9321 9322 getTargetStreamer().emitCantUnwind(); 9323 return false; 9324 } 9325 9326 /// parseDirectivePersonality 9327 /// ::= .personality name 9328 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) { 9329 MCAsmParser &Parser = getParser(); 9330 bool HasExistingPersonality = UC.hasPersonality(); 9331 9332 UC.recordPersonality(L); 9333 9334 // Check the ordering of unwind directives 9335 if (!UC.hasFnStart()) { 9336 Error(L, ".fnstart must precede .personality directive"); 9337 return false; 9338 } 9339 if (UC.cantUnwind()) { 9340 Error(L, ".personality can't be used with .cantunwind directive"); 9341 UC.emitCantUnwindLocNotes(); 9342 return false; 9343 } 9344 if (UC.hasHandlerData()) { 9345 Error(L, ".personality must precede .handlerdata directive"); 9346 UC.emitHandlerDataLocNotes(); 9347 return false; 9348 } 9349 if (HasExistingPersonality) { 9350 Parser.eatToEndOfStatement(); 9351 Error(L, "multiple personality directives"); 9352 UC.emitPersonalityLocNotes(); 9353 return false; 9354 } 9355 9356 // Parse the name of the personality routine 9357 if (Parser.getTok().isNot(AsmToken::Identifier)) { 9358 Parser.eatToEndOfStatement(); 9359 Error(L, "unexpected input in .personality directive."); 9360 return false; 9361 } 9362 StringRef Name(Parser.getTok().getIdentifier()); 9363 Parser.Lex(); 9364 9365 MCSymbol *PR = getParser().getContext().getOrCreateSymbol(Name); 9366 getTargetStreamer().emitPersonality(PR); 9367 return false; 9368 } 9369 9370 /// parseDirectiveHandlerData 9371 /// ::= .handlerdata 9372 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) { 9373 UC.recordHandlerData(L); 9374 9375 // Check the ordering of unwind directives 9376 if (!UC.hasFnStart()) { 9377 Error(L, ".fnstart must precede .personality directive"); 9378 return false; 9379 } 9380 if (UC.cantUnwind()) { 9381 Error(L, ".handlerdata can't be used with .cantunwind directive"); 9382 UC.emitCantUnwindLocNotes(); 9383 return false; 9384 } 9385 9386 getTargetStreamer().emitHandlerData(); 9387 return false; 9388 } 9389 9390 /// parseDirectiveSetFP 9391 /// ::= .setfp fpreg, spreg [, offset] 9392 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) { 9393 MCAsmParser &Parser = getParser(); 9394 // Check the ordering of unwind directives 9395 if (!UC.hasFnStart()) { 9396 Error(L, ".fnstart must precede .setfp directive"); 9397 return false; 9398 } 9399 if (UC.hasHandlerData()) { 9400 Error(L, ".setfp must precede .handlerdata directive"); 9401 return false; 9402 } 9403 9404 // Parse fpreg 9405 SMLoc FPRegLoc = Parser.getTok().getLoc(); 9406 int FPReg = tryParseRegister(); 9407 if (FPReg == -1) { 9408 Error(FPRegLoc, "frame pointer register expected"); 9409 return false; 9410 } 9411 9412 // Consume comma 9413 if (Parser.getTok().isNot(AsmToken::Comma)) { 9414 Error(Parser.getTok().getLoc(), "comma expected"); 9415 return false; 9416 } 9417 Parser.Lex(); // skip comma 9418 9419 // Parse spreg 9420 SMLoc SPRegLoc = Parser.getTok().getLoc(); 9421 int SPReg = tryParseRegister(); 9422 if (SPReg == -1) { 9423 Error(SPRegLoc, "stack pointer register expected"); 9424 return false; 9425 } 9426 9427 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) { 9428 Error(SPRegLoc, "register should be either $sp or the latest fp register"); 9429 return false; 9430 } 9431 9432 // Update the frame pointer register 9433 UC.saveFPReg(FPReg); 9434 9435 // Parse offset 9436 int64_t Offset = 0; 9437 if (Parser.getTok().is(AsmToken::Comma)) { 9438 Parser.Lex(); // skip comma 9439 9440 if (Parser.getTok().isNot(AsmToken::Hash) && 9441 Parser.getTok().isNot(AsmToken::Dollar)) { 9442 Error(Parser.getTok().getLoc(), "'#' expected"); 9443 return false; 9444 } 9445 Parser.Lex(); // skip hash token. 9446 9447 const MCExpr *OffsetExpr; 9448 SMLoc ExLoc = Parser.getTok().getLoc(); 9449 SMLoc EndLoc; 9450 if (getParser().parseExpression(OffsetExpr, EndLoc)) { 9451 Error(ExLoc, "malformed setfp offset"); 9452 return false; 9453 } 9454 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 9455 if (!CE) { 9456 Error(ExLoc, "setfp offset must be an immediate"); 9457 return false; 9458 } 9459 9460 Offset = CE->getValue(); 9461 } 9462 9463 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg), 9464 static_cast<unsigned>(SPReg), Offset); 9465 return false; 9466 } 9467 9468 /// parseDirective 9469 /// ::= .pad offset 9470 bool ARMAsmParser::parseDirectivePad(SMLoc L) { 9471 MCAsmParser &Parser = getParser(); 9472 // Check the ordering of unwind directives 9473 if (!UC.hasFnStart()) { 9474 Error(L, ".fnstart must precede .pad directive"); 9475 return false; 9476 } 9477 if (UC.hasHandlerData()) { 9478 Error(L, ".pad must precede .handlerdata directive"); 9479 return false; 9480 } 9481 9482 // Parse the offset 9483 if (Parser.getTok().isNot(AsmToken::Hash) && 9484 Parser.getTok().isNot(AsmToken::Dollar)) { 9485 Error(Parser.getTok().getLoc(), "'#' expected"); 9486 return false; 9487 } 9488 Parser.Lex(); // skip hash token. 9489 9490 const MCExpr *OffsetExpr; 9491 SMLoc ExLoc = Parser.getTok().getLoc(); 9492 SMLoc EndLoc; 9493 if (getParser().parseExpression(OffsetExpr, EndLoc)) { 9494 Error(ExLoc, "malformed pad offset"); 9495 return false; 9496 } 9497 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 9498 if (!CE) { 9499 Error(ExLoc, "pad offset must be an immediate"); 9500 return false; 9501 } 9502 9503 getTargetStreamer().emitPad(CE->getValue()); 9504 return false; 9505 } 9506 9507 /// parseDirectiveRegSave 9508 /// ::= .save { registers } 9509 /// ::= .vsave { registers } 9510 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) { 9511 // Check the ordering of unwind directives 9512 if (!UC.hasFnStart()) { 9513 Error(L, ".fnstart must precede .save or .vsave directives"); 9514 return false; 9515 } 9516 if (UC.hasHandlerData()) { 9517 Error(L, ".save or .vsave must precede .handlerdata directive"); 9518 return false; 9519 } 9520 9521 // RAII object to make sure parsed operands are deleted. 9522 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; 9523 9524 // Parse the register list 9525 if (parseRegisterList(Operands)) 9526 return false; 9527 ARMOperand &Op = (ARMOperand &)*Operands[0]; 9528 if (!IsVector && !Op.isRegList()) { 9529 Error(L, ".save expects GPR registers"); 9530 return false; 9531 } 9532 if (IsVector && !Op.isDPRRegList()) { 9533 Error(L, ".vsave expects DPR registers"); 9534 return false; 9535 } 9536 9537 getTargetStreamer().emitRegSave(Op.getRegList(), IsVector); 9538 return false; 9539 } 9540 9541 /// parseDirectiveInst 9542 /// ::= .inst opcode [, ...] 9543 /// ::= .inst.n opcode [, ...] 9544 /// ::= .inst.w opcode [, ...] 9545 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) { 9546 MCAsmParser &Parser = getParser(); 9547 int Width; 9548 9549 if (isThumb()) { 9550 switch (Suffix) { 9551 case 'n': 9552 Width = 2; 9553 break; 9554 case 'w': 9555 Width = 4; 9556 break; 9557 default: 9558 Parser.eatToEndOfStatement(); 9559 Error(Loc, "cannot determine Thumb instruction size, " 9560 "use inst.n/inst.w instead"); 9561 return false; 9562 } 9563 } else { 9564 if (Suffix) { 9565 Parser.eatToEndOfStatement(); 9566 Error(Loc, "width suffixes are invalid in ARM mode"); 9567 return false; 9568 } 9569 Width = 4; 9570 } 9571 9572 if (getLexer().is(AsmToken::EndOfStatement)) { 9573 Parser.eatToEndOfStatement(); 9574 Error(Loc, "expected expression following directive"); 9575 return false; 9576 } 9577 9578 for (;;) { 9579 const MCExpr *Expr; 9580 9581 if (getParser().parseExpression(Expr)) { 9582 Error(Loc, "expected expression"); 9583 return false; 9584 } 9585 9586 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr); 9587 if (!Value) { 9588 Error(Loc, "expected constant expression"); 9589 return false; 9590 } 9591 9592 switch (Width) { 9593 case 2: 9594 if (Value->getValue() > 0xffff) { 9595 Error(Loc, "inst.n operand is too big, use inst.w instead"); 9596 return false; 9597 } 9598 break; 9599 case 4: 9600 if (Value->getValue() > 0xffffffff) { 9601 Error(Loc, 9602 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big"); 9603 return false; 9604 } 9605 break; 9606 default: 9607 llvm_unreachable("only supported widths are 2 and 4"); 9608 } 9609 9610 getTargetStreamer().emitInst(Value->getValue(), Suffix); 9611 9612 if (getLexer().is(AsmToken::EndOfStatement)) 9613 break; 9614 9615 if (getLexer().isNot(AsmToken::Comma)) { 9616 Error(Loc, "unexpected token in directive"); 9617 return false; 9618 } 9619 9620 Parser.Lex(); 9621 } 9622 9623 Parser.Lex(); 9624 return false; 9625 } 9626 9627 /// parseDirectiveLtorg 9628 /// ::= .ltorg | .pool 9629 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) { 9630 getTargetStreamer().emitCurrentConstantPool(); 9631 return false; 9632 } 9633 9634 bool ARMAsmParser::parseDirectiveEven(SMLoc L) { 9635 const MCSection *Section = getStreamer().getCurrentSection().first; 9636 9637 if (getLexer().isNot(AsmToken::EndOfStatement)) { 9638 TokError("unexpected token in directive"); 9639 return false; 9640 } 9641 9642 if (!Section) { 9643 getStreamer().InitSections(false); 9644 Section = getStreamer().getCurrentSection().first; 9645 } 9646 9647 assert(Section && "must have section to emit alignment"); 9648 if (Section->UseCodeAlign()) 9649 getStreamer().EmitCodeAlignment(2); 9650 else 9651 getStreamer().EmitValueToAlignment(2); 9652 9653 return false; 9654 } 9655 9656 /// parseDirectivePersonalityIndex 9657 /// ::= .personalityindex index 9658 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) { 9659 MCAsmParser &Parser = getParser(); 9660 bool HasExistingPersonality = UC.hasPersonality(); 9661 9662 UC.recordPersonalityIndex(L); 9663 9664 if (!UC.hasFnStart()) { 9665 Parser.eatToEndOfStatement(); 9666 Error(L, ".fnstart must precede .personalityindex directive"); 9667 return false; 9668 } 9669 if (UC.cantUnwind()) { 9670 Parser.eatToEndOfStatement(); 9671 Error(L, ".personalityindex cannot be used with .cantunwind"); 9672 UC.emitCantUnwindLocNotes(); 9673 return false; 9674 } 9675 if (UC.hasHandlerData()) { 9676 Parser.eatToEndOfStatement(); 9677 Error(L, ".personalityindex must precede .handlerdata directive"); 9678 UC.emitHandlerDataLocNotes(); 9679 return false; 9680 } 9681 if (HasExistingPersonality) { 9682 Parser.eatToEndOfStatement(); 9683 Error(L, "multiple personality directives"); 9684 UC.emitPersonalityLocNotes(); 9685 return false; 9686 } 9687 9688 const MCExpr *IndexExpression; 9689 SMLoc IndexLoc = Parser.getTok().getLoc(); 9690 if (Parser.parseExpression(IndexExpression)) { 9691 Parser.eatToEndOfStatement(); 9692 return false; 9693 } 9694 9695 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression); 9696 if (!CE) { 9697 Parser.eatToEndOfStatement(); 9698 Error(IndexLoc, "index must be a constant number"); 9699 return false; 9700 } 9701 if (CE->getValue() < 0 || 9702 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) { 9703 Parser.eatToEndOfStatement(); 9704 Error(IndexLoc, "personality routine index should be in range [0-3]"); 9705 return false; 9706 } 9707 9708 getTargetStreamer().emitPersonalityIndex(CE->getValue()); 9709 return false; 9710 } 9711 9712 /// parseDirectiveUnwindRaw 9713 /// ::= .unwind_raw offset, opcode [, opcode...] 9714 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) { 9715 MCAsmParser &Parser = getParser(); 9716 if (!UC.hasFnStart()) { 9717 Parser.eatToEndOfStatement(); 9718 Error(L, ".fnstart must precede .unwind_raw directives"); 9719 return false; 9720 } 9721 9722 int64_t StackOffset; 9723 9724 const MCExpr *OffsetExpr; 9725 SMLoc OffsetLoc = getLexer().getLoc(); 9726 if (getLexer().is(AsmToken::EndOfStatement) || 9727 getParser().parseExpression(OffsetExpr)) { 9728 Error(OffsetLoc, "expected expression"); 9729 Parser.eatToEndOfStatement(); 9730 return false; 9731 } 9732 9733 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 9734 if (!CE) { 9735 Error(OffsetLoc, "offset must be a constant"); 9736 Parser.eatToEndOfStatement(); 9737 return false; 9738 } 9739 9740 StackOffset = CE->getValue(); 9741 9742 if (getLexer().isNot(AsmToken::Comma)) { 9743 Error(getLexer().getLoc(), "expected comma"); 9744 Parser.eatToEndOfStatement(); 9745 return false; 9746 } 9747 Parser.Lex(); 9748 9749 SmallVector<uint8_t, 16> Opcodes; 9750 for (;;) { 9751 const MCExpr *OE; 9752 9753 SMLoc OpcodeLoc = getLexer().getLoc(); 9754 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) { 9755 Error(OpcodeLoc, "expected opcode expression"); 9756 Parser.eatToEndOfStatement(); 9757 return false; 9758 } 9759 9760 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE); 9761 if (!OC) { 9762 Error(OpcodeLoc, "opcode value must be a constant"); 9763 Parser.eatToEndOfStatement(); 9764 return false; 9765 } 9766 9767 const int64_t Opcode = OC->getValue(); 9768 if (Opcode & ~0xff) { 9769 Error(OpcodeLoc, "invalid opcode"); 9770 Parser.eatToEndOfStatement(); 9771 return false; 9772 } 9773 9774 Opcodes.push_back(uint8_t(Opcode)); 9775 9776 if (getLexer().is(AsmToken::EndOfStatement)) 9777 break; 9778 9779 if (getLexer().isNot(AsmToken::Comma)) { 9780 Error(getLexer().getLoc(), "unexpected token in directive"); 9781 Parser.eatToEndOfStatement(); 9782 return false; 9783 } 9784 9785 Parser.Lex(); 9786 } 9787 9788 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes); 9789 9790 Parser.Lex(); 9791 return false; 9792 } 9793 9794 /// parseDirectiveTLSDescSeq 9795 /// ::= .tlsdescseq tls-variable 9796 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) { 9797 MCAsmParser &Parser = getParser(); 9798 9799 if (getLexer().isNot(AsmToken::Identifier)) { 9800 TokError("expected variable after '.tlsdescseq' directive"); 9801 Parser.eatToEndOfStatement(); 9802 return false; 9803 } 9804 9805 const MCSymbolRefExpr *SRE = 9806 MCSymbolRefExpr::create(Parser.getTok().getIdentifier(), 9807 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext()); 9808 Lex(); 9809 9810 if (getLexer().isNot(AsmToken::EndOfStatement)) { 9811 Error(Parser.getTok().getLoc(), "unexpected token"); 9812 Parser.eatToEndOfStatement(); 9813 return false; 9814 } 9815 9816 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE); 9817 return false; 9818 } 9819 9820 /// parseDirectiveMovSP 9821 /// ::= .movsp reg [, #offset] 9822 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) { 9823 MCAsmParser &Parser = getParser(); 9824 if (!UC.hasFnStart()) { 9825 Parser.eatToEndOfStatement(); 9826 Error(L, ".fnstart must precede .movsp directives"); 9827 return false; 9828 } 9829 if (UC.getFPReg() != ARM::SP) { 9830 Parser.eatToEndOfStatement(); 9831 Error(L, "unexpected .movsp directive"); 9832 return false; 9833 } 9834 9835 SMLoc SPRegLoc = Parser.getTok().getLoc(); 9836 int SPReg = tryParseRegister(); 9837 if (SPReg == -1) { 9838 Parser.eatToEndOfStatement(); 9839 Error(SPRegLoc, "register expected"); 9840 return false; 9841 } 9842 9843 if (SPReg == ARM::SP || SPReg == ARM::PC) { 9844 Parser.eatToEndOfStatement(); 9845 Error(SPRegLoc, "sp and pc are not permitted in .movsp directive"); 9846 return false; 9847 } 9848 9849 int64_t Offset = 0; 9850 if (Parser.getTok().is(AsmToken::Comma)) { 9851 Parser.Lex(); 9852 9853 if (Parser.getTok().isNot(AsmToken::Hash)) { 9854 Error(Parser.getTok().getLoc(), "expected #constant"); 9855 Parser.eatToEndOfStatement(); 9856 return false; 9857 } 9858 Parser.Lex(); 9859 9860 const MCExpr *OffsetExpr; 9861 SMLoc OffsetLoc = Parser.getTok().getLoc(); 9862 if (Parser.parseExpression(OffsetExpr)) { 9863 Parser.eatToEndOfStatement(); 9864 Error(OffsetLoc, "malformed offset expression"); 9865 return false; 9866 } 9867 9868 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 9869 if (!CE) { 9870 Parser.eatToEndOfStatement(); 9871 Error(OffsetLoc, "offset must be an immediate constant"); 9872 return false; 9873 } 9874 9875 Offset = CE->getValue(); 9876 } 9877 9878 getTargetStreamer().emitMovSP(SPReg, Offset); 9879 UC.saveFPReg(SPReg); 9880 9881 return false; 9882 } 9883 9884 /// parseDirectiveObjectArch 9885 /// ::= .object_arch name 9886 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) { 9887 MCAsmParser &Parser = getParser(); 9888 if (getLexer().isNot(AsmToken::Identifier)) { 9889 Error(getLexer().getLoc(), "unexpected token"); 9890 Parser.eatToEndOfStatement(); 9891 return false; 9892 } 9893 9894 StringRef Arch = Parser.getTok().getString(); 9895 SMLoc ArchLoc = Parser.getTok().getLoc(); 9896 getLexer().Lex(); 9897 9898 unsigned ID = ARMTargetParser::parseArch(Arch); 9899 9900 if (ID == ARM::AK_INVALID) { 9901 Error(ArchLoc, "unknown architecture '" + Arch + "'"); 9902 Parser.eatToEndOfStatement(); 9903 return false; 9904 } 9905 9906 getTargetStreamer().emitObjectArch(ID); 9907 9908 if (getLexer().isNot(AsmToken::EndOfStatement)) { 9909 Error(getLexer().getLoc(), "unexpected token"); 9910 Parser.eatToEndOfStatement(); 9911 } 9912 9913 return false; 9914 } 9915 9916 /// parseDirectiveAlign 9917 /// ::= .align 9918 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) { 9919 // NOTE: if this is not the end of the statement, fall back to the target 9920 // agnostic handling for this directive which will correctly handle this. 9921 if (getLexer().isNot(AsmToken::EndOfStatement)) 9922 return true; 9923 9924 // '.align' is target specifically handled to mean 2**2 byte alignment. 9925 if (getStreamer().getCurrentSection().first->UseCodeAlign()) 9926 getStreamer().EmitCodeAlignment(4, 0); 9927 else 9928 getStreamer().EmitValueToAlignment(4, 0, 1, 0); 9929 9930 return false; 9931 } 9932 9933 /// parseDirectiveThumbSet 9934 /// ::= .thumb_set name, value 9935 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) { 9936 MCAsmParser &Parser = getParser(); 9937 9938 StringRef Name; 9939 if (Parser.parseIdentifier(Name)) { 9940 TokError("expected identifier after '.thumb_set'"); 9941 Parser.eatToEndOfStatement(); 9942 return false; 9943 } 9944 9945 if (getLexer().isNot(AsmToken::Comma)) { 9946 TokError("expected comma after name '" + Name + "'"); 9947 Parser.eatToEndOfStatement(); 9948 return false; 9949 } 9950 Lex(); 9951 9952 MCSymbol *Sym; 9953 const MCExpr *Value; 9954 if (MCParserUtils::parseAssignmentExpression(Name, /* allow_redef */ true, 9955 Parser, Sym, Value)) 9956 return true; 9957 9958 getTargetStreamer().emitThumbSet(Sym, Value); 9959 return false; 9960 } 9961 9962 /// Force static initialization. 9963 extern "C" void LLVMInitializeARMAsmParser() { 9964 RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget); 9965 RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget); 9966 RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget); 9967 RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget); 9968 } 9969 9970 #define GET_REGISTER_MATCHER 9971 #define GET_SUBTARGET_FEATURE_NAME 9972 #define GET_MATCHER_IMPLEMENTATION 9973 #include "ARMGenAsmMatcher.inc" 9974 9975 // FIXME: This structure should be moved inside ARMTargetParser 9976 // when we start to table-generate them, and we can use the ARM 9977 // flags below, that were generated by table-gen. 9978 static const struct { 9979 const ARM::ArchExtKind Kind; 9980 const unsigned ArchCheck; 9981 const FeatureBitset Features; 9982 } Extensions[] = { 9983 { ARM::AEK_CRC, Feature_HasV8, {ARM::FeatureCRC} }, 9984 { ARM::AEK_CRYPTO, Feature_HasV8, 9985 {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} }, 9986 { ARM::AEK_FP, Feature_HasV8, {ARM::FeatureFPARMv8} }, 9987 { ARM::AEK_HWDIV, Feature_HasV7 | Feature_IsNotMClass, 9988 {ARM::FeatureHWDiv, ARM::FeatureHWDivARM} }, 9989 { ARM::AEK_MP, Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} }, 9990 { ARM::AEK_SIMD, Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} }, 9991 // FIXME: Also available in ARMv6-K 9992 { ARM::AEK_SEC, Feature_HasV7, {ARM::FeatureTrustZone} }, 9993 // FIXME: Only available in A-class, isel not predicated 9994 { ARM::AEK_VIRT, Feature_HasV7, {ARM::FeatureVirtualization} }, 9995 // FIXME: Unsupported extensions. 9996 { ARM::AEK_OS, Feature_None, {} }, 9997 { ARM::AEK_IWMMXT, Feature_None, {} }, 9998 { ARM::AEK_IWMMXT2, Feature_None, {} }, 9999 { ARM::AEK_MAVERICK, Feature_None, {} }, 10000 { ARM::AEK_XSCALE, Feature_None, {} }, 10001 }; 10002 10003 /// parseDirectiveArchExtension 10004 /// ::= .arch_extension [no]feature 10005 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) { 10006 MCAsmParser &Parser = getParser(); 10007 10008 if (getLexer().isNot(AsmToken::Identifier)) { 10009 Error(getLexer().getLoc(), "unexpected token"); 10010 Parser.eatToEndOfStatement(); 10011 return false; 10012 } 10013 10014 StringRef Name = Parser.getTok().getString(); 10015 SMLoc ExtLoc = Parser.getTok().getLoc(); 10016 getLexer().Lex(); 10017 10018 bool EnableFeature = true; 10019 if (Name.startswith_lower("no")) { 10020 EnableFeature = false; 10021 Name = Name.substr(2); 10022 } 10023 unsigned FeatureKind = ARMTargetParser::parseArchExt(Name); 10024 if (FeatureKind == ARM::AEK_INVALID) 10025 Error(ExtLoc, "unknown architectural extension: " + Name); 10026 10027 for (const auto &Extension : Extensions) { 10028 if (Extension.Kind != FeatureKind) 10029 continue; 10030 10031 if (Extension.Features.none()) 10032 report_fatal_error("unsupported architectural extension: " + Name); 10033 10034 if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) { 10035 Error(ExtLoc, "architectural extension '" + Name + "' is not " 10036 "allowed for the current base architecture"); 10037 return false; 10038 } 10039 10040 FeatureBitset ToggleFeatures = EnableFeature 10041 ? (~STI.getFeatureBits() & Extension.Features) 10042 : ( STI.getFeatureBits() & Extension.Features); 10043 10044 uint64_t Features = 10045 ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures)); 10046 setAvailableFeatures(Features); 10047 return false; 10048 } 10049 10050 Error(ExtLoc, "unknown architectural extension: " + Name); 10051 Parser.eatToEndOfStatement(); 10052 return false; 10053 } 10054 10055 // Define this matcher function after the auto-generated include so we 10056 // have the match class enum definitions. 10057 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, 10058 unsigned Kind) { 10059 ARMOperand &Op = static_cast<ARMOperand &>(AsmOp); 10060 // If the kind is a token for a literal immediate, check if our asm 10061 // operand matches. This is for InstAliases which have a fixed-value 10062 // immediate in the syntax. 10063 switch (Kind) { 10064 default: break; 10065 case MCK__35_0: 10066 if (Op.isImm()) 10067 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm())) 10068 if (CE->getValue() == 0) 10069 return Match_Success; 10070 break; 10071 case MCK_ModImm: 10072 if (Op.isImm()) { 10073 const MCExpr *SOExpr = Op.getImm(); 10074 int64_t Value; 10075 if (!SOExpr->evaluateAsAbsolute(Value)) 10076 return Match_Success; 10077 assert((Value >= INT32_MIN && Value <= UINT32_MAX) && 10078 "expression value must be representable in 32 bits"); 10079 } 10080 break; 10081 case MCK_GPRPair: 10082 if (Op.isReg() && 10083 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg())) 10084 return Match_Success; 10085 break; 10086 } 10087 return Match_InvalidOperand; 10088 } 10089