1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMTargetMachine.h" 14 #include "ARMMCAsmInfo.h" 15 #include "ARMFrameInfo.h" 16 #include "ARM.h" 17 #include "llvm/PassManager.h" 18 #include "llvm/CodeGen/Passes.h" 19 #include "llvm/Support/FormattedStream.h" 20 #include "llvm/Target/TargetOptions.h" 21 #include "llvm/Target/TargetRegistry.h" 22 using namespace llvm; 23 24 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) { 25 Triple TheTriple(TT); 26 switch (TheTriple.getOS()) { 27 case Triple::Darwin: 28 return new ARMMCAsmInfoDarwin(); 29 default: 30 return new ARMELFMCAsmInfo(); 31 } 32 } 33 34 extern "C" void LLVMInitializeARMTarget() { 35 // Register the target. 36 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget); 37 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget); 38 39 // Register the target asm info. 40 RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo); 41 RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo); 42 } 43 44 /// TargetMachine ctor - Create an ARM architecture model. 45 /// 46 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, 47 const std::string &TT, 48 const std::string &FS, 49 bool isThumb) 50 : LLVMTargetMachine(T, TT), 51 Subtarget(TT, FS, isThumb), 52 FrameInfo(Subtarget), 53 JITInfo(), 54 InstrItins(Subtarget.getInstrItineraryData()) { 55 DefRelocModel = getRelocationModel(); 56 } 57 58 ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT, 59 const std::string &FS) 60 : ARMBaseTargetMachine(T, TT, FS, false), InstrInfo(Subtarget), 61 DataLayout(Subtarget.isAPCS_ABI() ? 62 std::string("e-p:32:32-f64:32:32-i64:32:32-" 63 "v128:32:128-v64:32:64-n32") : 64 std::string("e-p:32:32-f64:64:64-i64:64:64-" 65 "v128:64:128-v64:64:64-n32")), 66 TLInfo(*this), 67 TSInfo(*this) { 68 if (!Subtarget.hasARMOps()) 69 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not " 70 "support ARM mode execution!"); 71 } 72 73 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT, 74 const std::string &FS) 75 : ARMBaseTargetMachine(T, TT, FS, true), 76 InstrInfo(Subtarget.hasThumb2() 77 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget)) 78 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))), 79 DataLayout(Subtarget.isAPCS_ABI() ? 80 std::string("e-p:32:32-f64:32:32-i64:32:32-" 81 "i16:16:32-i8:8:32-i1:8:32-" 82 "v128:32:128-v64:32:64-a:0:32-n32") : 83 std::string("e-p:32:32-f64:64:64-i64:64:64-" 84 "i16:16:32-i8:8:32-i1:8:32-" 85 "v128:64:128-v64:64:64-a:0:32-n32")), 86 TLInfo(*this), 87 TSInfo(*this) { 88 } 89 90 // Pass Pipeline Configuration 91 bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM, 92 CodeGenOpt::Level OptLevel) { 93 if (OptLevel != CodeGenOpt::None) 94 PM.add(createARMGlobalMergePass(getTargetLowering())); 95 96 return false; 97 } 98 99 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM, 100 CodeGenOpt::Level OptLevel) { 101 PM.add(createARMISelDag(*this, OptLevel)); 102 return false; 103 } 104 105 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM, 106 CodeGenOpt::Level OptLevel) { 107 if (Subtarget.hasNEON()) 108 PM.add(createNEONPreAllocPass()); 109 110 // FIXME: temporarily disabling load / store optimization pass for Thumb1. 111 if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) 112 PM.add(createARMLoadStoreOptimizationPass(true)); 113 114 return true; 115 } 116 117 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM, 118 CodeGenOpt::Level OptLevel) { 119 // FIXME: temporarily disabling load / store optimization pass for Thumb1. 120 if (OptLevel != CodeGenOpt::None) { 121 if (!Subtarget.isThumb1Only()) 122 PM.add(createARMLoadStoreOptimizationPass()); 123 if (Subtarget.hasNEON()) 124 PM.add(createNEONMoveFixPass()); 125 } 126 127 // Expand some pseudo instructions into multiple instructions to allow 128 // proper scheduling. 129 PM.add(createARMExpandPseudoPass()); 130 131 if (OptLevel != CodeGenOpt::None) { 132 if (!Subtarget.isThumb1Only()) 133 PM.add(createIfConverterPass()); 134 } 135 if (Subtarget.isThumb2()) 136 PM.add(createThumb2ITBlockPass()); 137 138 return true; 139 } 140 141 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM, 142 CodeGenOpt::Level OptLevel) { 143 if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb()) 144 PM.add(createThumb2SizeReductionPass()); 145 146 PM.add(createARMConstantIslandPass()); 147 return true; 148 } 149 150 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM, 151 CodeGenOpt::Level OptLevel, 152 JITCodeEmitter &JCE) { 153 // FIXME: Move this to TargetJITInfo! 154 if (DefRelocModel == Reloc::Default) 155 setRelocationModel(Reloc::Static); 156 157 // Machine code emitter pass for ARM. 158 PM.add(createARMJITCodeEmitterPass(*this, JCE)); 159 return false; 160 } 161