1//===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM VFP instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 15def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 16def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>; 17def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>, 18 SDTCisSameAs<1, 2>]>; 19 20def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>; 21def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>; 22def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>; 23def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>; 24def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>; 25def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>; 26def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>; 27def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>; 28 29 30//===----------------------------------------------------------------------===// 31// Operand Definitions. 32// 33 34// 8-bit floating-point immediate encodings. 35def FPImmOperand : AsmOperandClass { 36 let Name = "FPImm"; 37 let ParserMethod = "parseFPImm"; 38} 39 40def vfp_f32imm : Operand<f32>, 41 PatLeaf<(f32 fpimm), [{ 42 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1; 43 }], SDNodeXForm<fpimm, [{ 44 APFloat InVal = N->getValueAPF(); 45 uint32_t enc = ARM_AM::getFP32Imm(InVal); 46 return CurDAG->getTargetConstant(enc, MVT::i32); 47 }]>> { 48 let PrintMethod = "printFPImmOperand"; 49 let ParserMatchClass = FPImmOperand; 50} 51 52def vfp_f64imm : Operand<f64>, 53 PatLeaf<(f64 fpimm), [{ 54 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1; 55 }], SDNodeXForm<fpimm, [{ 56 APFloat InVal = N->getValueAPF(); 57 uint32_t enc = ARM_AM::getFP64Imm(InVal); 58 return CurDAG->getTargetConstant(enc, MVT::i32); 59 }]>> { 60 let PrintMethod = "printFPImmOperand"; 61 let ParserMatchClass = FPImmOperand; 62} 63 64def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 65 return cast<LoadSDNode>(N)->getAlignment() >= 4; 66}]>; 67 68def alignedstore32 : PatFrag<(ops node:$val, node:$ptr), 69 (store node:$val, node:$ptr), [{ 70 return cast<StoreSDNode>(N)->getAlignment() >= 4; 71}]>; 72 73// The VCVT to/from fixed-point instructions encode the 'fbits' operand 74// (the number of fixed bits) differently than it appears in the assembly 75// source. It's encoded as "Size - fbits" where Size is the size of the 76// fixed-point representation (32 or 16) and fbits is the value appearing 77// in the assembly source, an integer in [0,16] or (0,32], depending on size. 78def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; } 79def fbits32 : Operand<i32> { 80 let PrintMethod = "printFBits32"; 81 let ParserMatchClass = fbits32_asm_operand; 82} 83 84def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; } 85def fbits16 : Operand<i32> { 86 let PrintMethod = "printFBits16"; 87 let ParserMatchClass = fbits16_asm_operand; 88} 89 90//===----------------------------------------------------------------------===// 91// Load / store Instructions. 92// 93 94let canFoldAsLoad = 1, isReMaterializable = 1 in { 95 96def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), 97 IIC_fpLoad64, "vldr", "\t$Dd, $addr", 98 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>; 99 100def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr), 101 IIC_fpLoad32, "vldr", "\t$Sd, $addr", 102 [(set SPR:$Sd, (load addrmode5:$addr))]> { 103 // Some single precision VFP instructions may be executed on both NEON and VFP 104 // pipelines. 105 let D = VFPNeonDomain; 106} 107 108} // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in' 109 110def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr), 111 IIC_fpStore64, "vstr", "\t$Dd, $addr", 112 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>; 113 114def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr), 115 IIC_fpStore32, "vstr", "\t$Sd, $addr", 116 [(store SPR:$Sd, addrmode5:$addr)]> { 117 // Some single precision VFP instructions may be executed on both NEON and VFP 118 // pipelines. 119 let D = VFPNeonDomain; 120} 121 122//===----------------------------------------------------------------------===// 123// Load / store multiple Instructions. 124// 125 126multiclass vfp_ldst_mult<string asm, bit L_bit, 127 InstrItinClass itin, InstrItinClass itin_upd> { 128 // Double Precision 129 def DIA : 130 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 131 IndexModeNone, itin, 132 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { 133 let Inst{24-23} = 0b01; // Increment After 134 let Inst{21} = 0; // No writeback 135 let Inst{20} = L_bit; 136 } 137 def DIA_UPD : 138 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, 139 variable_ops), 140 IndexModeUpd, itin_upd, 141 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 142 let Inst{24-23} = 0b01; // Increment After 143 let Inst{21} = 1; // Writeback 144 let Inst{20} = L_bit; 145 } 146 def DDB_UPD : 147 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, 148 variable_ops), 149 IndexModeUpd, itin_upd, 150 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 151 let Inst{24-23} = 0b10; // Decrement Before 152 let Inst{21} = 1; // Writeback 153 let Inst{20} = L_bit; 154 } 155 156 // Single Precision 157 def SIA : 158 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops), 159 IndexModeNone, itin, 160 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { 161 let Inst{24-23} = 0b01; // Increment After 162 let Inst{21} = 0; // No writeback 163 let Inst{20} = L_bit; 164 165 // Some single precision VFP instructions may be executed on both NEON and 166 // VFP pipelines. 167 let D = VFPNeonDomain; 168 } 169 def SIA_UPD : 170 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, 171 variable_ops), 172 IndexModeUpd, itin_upd, 173 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 174 let Inst{24-23} = 0b01; // Increment After 175 let Inst{21} = 1; // Writeback 176 let Inst{20} = L_bit; 177 178 // Some single precision VFP instructions may be executed on both NEON and 179 // VFP pipelines. 180 let D = VFPNeonDomain; 181 } 182 def SDB_UPD : 183 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, 184 variable_ops), 185 IndexModeUpd, itin_upd, 186 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 187 let Inst{24-23} = 0b10; // Decrement Before 188 let Inst{21} = 1; // Writeback 189 let Inst{20} = L_bit; 190 191 // Some single precision VFP instructions may be executed on both NEON and 192 // VFP pipelines. 193 let D = VFPNeonDomain; 194 } 195} 196 197let neverHasSideEffects = 1 in { 198 199let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 200defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>; 201 202let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 203defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpStore_m, IIC_fpStore_mu>; 204 205} // neverHasSideEffects 206 207def : MnemonicAlias<"vldm", "vldmia">; 208def : MnemonicAlias<"vstm", "vstmia">; 209 210// FLDM/FSTM - Load / Store multiple single / double precision registers for 211// pre-ARMv6 cores. 212// These instructions are deprecated! 213def : VFP2MnemonicAlias<"fldmias", "vldmia">; 214def : VFP2MnemonicAlias<"fldmdbs", "vldmdb">; 215def : VFP2MnemonicAlias<"fldmeas", "vldmdb">; 216def : VFP2MnemonicAlias<"fldmfds", "vldmia">; 217def : VFP2MnemonicAlias<"fldmiad", "vldmia">; 218def : VFP2MnemonicAlias<"fldmdbd", "vldmdb">; 219def : VFP2MnemonicAlias<"fldmead", "vldmdb">; 220def : VFP2MnemonicAlias<"fldmfdd", "vldmia">; 221 222def : VFP2MnemonicAlias<"fstmias", "vstmia">; 223def : VFP2MnemonicAlias<"fstmdbs", "vstmdb">; 224def : VFP2MnemonicAlias<"fstmeas", "vstmia">; 225def : VFP2MnemonicAlias<"fstmfds", "vstmdb">; 226def : VFP2MnemonicAlias<"fstmiad", "vstmia">; 227def : VFP2MnemonicAlias<"fstmdbd", "vstmdb">; 228def : VFP2MnemonicAlias<"fstmead", "vstmia">; 229def : VFP2MnemonicAlias<"fstmfdd", "vstmdb">; 230 231def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>, 232 Requires<[HasVFP2]>; 233def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>, 234 Requires<[HasVFP2]>; 235def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>, 236 Requires<[HasVFP2]>; 237def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>, 238 Requires<[HasVFP2]>; 239defm : VFPDTAnyInstAlias<"vpush${p}", "$r", 240 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>; 241defm : VFPDTAnyInstAlias<"vpush${p}", "$r", 242 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>; 243defm : VFPDTAnyInstAlias<"vpop${p}", "$r", 244 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>; 245defm : VFPDTAnyInstAlias<"vpop${p}", "$r", 246 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>; 247 248// FLDMX, FSTMX - Load and store multiple unknown precision registers for 249// pre-armv6 cores. 250// These instruction are deprecated so we don't want them to get selected. 251multiclass vfp_ldstx_mult<string asm, bit L_bit> { 252 // Unknown precision 253 def XIA : 254 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 255 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> { 256 let Inst{24-23} = 0b01; // Increment After 257 let Inst{21} = 0; // No writeback 258 let Inst{20} = L_bit; 259 } 260 def XIA_UPD : 261 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 262 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 263 let Inst{24-23} = 0b01; // Increment After 264 let Inst{21} = 1; // Writeback 265 let Inst{20} = L_bit; 266 } 267 def XDB_UPD : 268 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 269 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 270 let Inst{24-23} = 0b10; // Decrement Before 271 let Inst{21} = 1; // Writeback 272 let Inst{20} = L_bit; 273 } 274} 275 276defm FLDM : vfp_ldstx_mult<"fldm", 1>; 277defm FSTM : vfp_ldstx_mult<"fstm", 0>; 278 279def : VFP2MnemonicAlias<"fldmeax", "fldmdbx">; 280def : VFP2MnemonicAlias<"fldmfdx", "fldmiax">; 281 282def : VFP2MnemonicAlias<"fstmeax", "fstmiax">; 283def : VFP2MnemonicAlias<"fstmfdx", "fstmdbx">; 284 285//===----------------------------------------------------------------------===// 286// FP Binary Operations. 287// 288 289let TwoOperandAliasConstraint = "$Dn = $Dd" in 290def VADDD : ADbI<0b11100, 0b11, 0, 0, 291 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 292 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm", 293 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>; 294 295let TwoOperandAliasConstraint = "$Sn = $Sd" in 296def VADDS : ASbIn<0b11100, 0b11, 0, 0, 297 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 298 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm", 299 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> { 300 // Some single precision VFP instructions may be executed on both NEON and 301 // VFP pipelines on A8. 302 let D = VFPNeonA8Domain; 303} 304 305let TwoOperandAliasConstraint = "$Dn = $Dd" in 306def VSUBD : ADbI<0b11100, 0b11, 1, 0, 307 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 308 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm", 309 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>; 310 311let TwoOperandAliasConstraint = "$Sn = $Sd" in 312def VSUBS : ASbIn<0b11100, 0b11, 1, 0, 313 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 314 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm", 315 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> { 316 // Some single precision VFP instructions may be executed on both NEON and 317 // VFP pipelines on A8. 318 let D = VFPNeonA8Domain; 319} 320 321let TwoOperandAliasConstraint = "$Dn = $Dd" in 322def VDIVD : ADbI<0b11101, 0b00, 0, 0, 323 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 324 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm", 325 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>; 326 327let TwoOperandAliasConstraint = "$Sn = $Sd" in 328def VDIVS : ASbI<0b11101, 0b00, 0, 0, 329 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 330 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm", 331 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>; 332 333let TwoOperandAliasConstraint = "$Dn = $Dd" in 334def VMULD : ADbI<0b11100, 0b10, 0, 0, 335 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 336 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm", 337 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>; 338 339let TwoOperandAliasConstraint = "$Sn = $Sd" in 340def VMULS : ASbIn<0b11100, 0b10, 0, 0, 341 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 342 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm", 343 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> { 344 // Some single precision VFP instructions may be executed on both NEON and 345 // VFP pipelines on A8. 346 let D = VFPNeonA8Domain; 347} 348 349def VNMULD : ADbI<0b11100, 0b10, 1, 0, 350 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 351 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm", 352 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>; 353 354def VNMULS : ASbI<0b11100, 0b10, 1, 0, 355 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 356 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm", 357 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> { 358 // Some single precision VFP instructions may be executed on both NEON and 359 // VFP pipelines on A8. 360 let D = VFPNeonA8Domain; 361} 362 363multiclass vsel_inst<string op, bits<2> opc, int CC> { 364 let DecoderNamespace = "VFPV8", PostEncoderMethod = "", 365 Uses = [CPSR], AddedComplexity = 4 in { 366 def S : ASbInp<0b11100, opc, 0, 367 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 368 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"), 369 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>, 370 Requires<[HasFPARMv8]>; 371 372 def D : ADbInp<0b11100, opc, 0, 373 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 374 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"), 375 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>, 376 Requires<[HasFPARMv8, HasDPVFP]>; 377 } 378} 379 380// The CC constants here match ARMCC::CondCodes. 381defm VSELGT : vsel_inst<"gt", 0b11, 12>; 382defm VSELGE : vsel_inst<"ge", 0b10, 10>; 383defm VSELEQ : vsel_inst<"eq", 0b00, 0>; 384defm VSELVS : vsel_inst<"vs", 0b01, 6>; 385 386multiclass vmaxmin_inst<string op, bit opc, SDNode SD> { 387 let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in { 388 def S : ASbInp<0b11101, 0b00, opc, 389 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 390 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"), 391 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>, 392 Requires<[HasFPARMv8]>; 393 394 def D : ADbInp<0b11101, 0b00, opc, 395 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 396 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"), 397 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>, 398 Requires<[HasFPARMv8, HasDPVFP]>; 399 } 400} 401 402defm VMAXNM : vmaxmin_inst<"vmaxnm", 0, ARMvmaxnm>; 403defm VMINNM : vmaxmin_inst<"vminnm", 1, ARMvminnm>; 404 405// Match reassociated forms only if not sign dependent rounding. 406def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)), 407 (VNMULD DPR:$a, DPR:$b)>, 408 Requires<[NoHonorSignDependentRounding,HasDPVFP]>; 409def : Pat<(fmul (fneg SPR:$a), SPR:$b), 410 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>; 411 412// These are encoded as unary instructions. 413let Defs = [FPSCR_NZCV] in { 414def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0, 415 (outs), (ins DPR:$Dd, DPR:$Dm), 416 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm", 417 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>; 418 419def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0, 420 (outs), (ins SPR:$Sd, SPR:$Sm), 421 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm", 422 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> { 423 // Some single precision VFP instructions may be executed on both NEON and 424 // VFP pipelines on A8. 425 let D = VFPNeonA8Domain; 426} 427 428// FIXME: Verify encoding after integrated assembler is working. 429def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, 430 (outs), (ins DPR:$Dd, DPR:$Dm), 431 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm", 432 [/* For disassembly only; pattern left blank */]>; 433 434def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, 435 (outs), (ins SPR:$Sd, SPR:$Sm), 436 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm", 437 [/* For disassembly only; pattern left blank */]> { 438 // Some single precision VFP instructions may be executed on both NEON and 439 // VFP pipelines on A8. 440 let D = VFPNeonA8Domain; 441} 442} // Defs = [FPSCR_NZCV] 443 444//===----------------------------------------------------------------------===// 445// FP Unary Operations. 446// 447 448def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0, 449 (outs DPR:$Dd), (ins DPR:$Dm), 450 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm", 451 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>; 452 453def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0, 454 (outs SPR:$Sd), (ins SPR:$Sm), 455 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm", 456 [(set SPR:$Sd, (fabs SPR:$Sm))]> { 457 // Some single precision VFP instructions may be executed on both NEON and 458 // VFP pipelines on A8. 459 let D = VFPNeonA8Domain; 460} 461 462let Defs = [FPSCR_NZCV] in { 463def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0, 464 (outs), (ins DPR:$Dd), 465 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0", 466 [(arm_cmpfp0 (f64 DPR:$Dd))]> { 467 let Inst{3-0} = 0b0000; 468 let Inst{5} = 0; 469} 470 471def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0, 472 (outs), (ins SPR:$Sd), 473 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0", 474 [(arm_cmpfp0 SPR:$Sd)]> { 475 let Inst{3-0} = 0b0000; 476 let Inst{5} = 0; 477 478 // Some single precision VFP instructions may be executed on both NEON and 479 // VFP pipelines on A8. 480 let D = VFPNeonA8Domain; 481} 482 483// FIXME: Verify encoding after integrated assembler is working. 484def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, 485 (outs), (ins DPR:$Dd), 486 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0", 487 [/* For disassembly only; pattern left blank */]> { 488 let Inst{3-0} = 0b0000; 489 let Inst{5} = 0; 490} 491 492def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0, 493 (outs), (ins SPR:$Sd), 494 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0", 495 [/* For disassembly only; pattern left blank */]> { 496 let Inst{3-0} = 0b0000; 497 let Inst{5} = 0; 498 499 // Some single precision VFP instructions may be executed on both NEON and 500 // VFP pipelines on A8. 501 let D = VFPNeonA8Domain; 502} 503} // Defs = [FPSCR_NZCV] 504 505def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0, 506 (outs DPR:$Dd), (ins SPR:$Sm), 507 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm", 508 [(set DPR:$Dd, (fextend SPR:$Sm))]> { 509 // Instruction operands. 510 bits<5> Dd; 511 bits<5> Sm; 512 513 // Encode instruction operands. 514 let Inst{3-0} = Sm{4-1}; 515 let Inst{5} = Sm{0}; 516 let Inst{15-12} = Dd{3-0}; 517 let Inst{22} = Dd{4}; 518} 519 520// Special case encoding: bits 11-8 is 0b1011. 521def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm, 522 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm", 523 [(set SPR:$Sd, (fround DPR:$Dm))]> { 524 // Instruction operands. 525 bits<5> Sd; 526 bits<5> Dm; 527 528 // Encode instruction operands. 529 let Inst{3-0} = Dm{3-0}; 530 let Inst{5} = Dm{4}; 531 let Inst{15-12} = Sd{4-1}; 532 let Inst{22} = Sd{0}; 533 534 let Inst{27-23} = 0b11101; 535 let Inst{21-16} = 0b110111; 536 let Inst{11-8} = 0b1011; 537 let Inst{7-6} = 0b11; 538 let Inst{4} = 0; 539 540 let Predicates = [HasVFP2, HasDPVFP]; 541} 542 543// Between half, single and double-precision. For disassembly only. 544 545// FIXME: Verify encoding after integrated assembler is working. 546def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), 547 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm", 548 [/* For disassembly only; pattern left blank */]>; 549 550def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), 551 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm", 552 [/* For disassembly only; pattern left blank */]>; 553 554def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), 555 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm", 556 [/* For disassembly only; pattern left blank */]>; 557 558def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), 559 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", 560 [/* For disassembly only; pattern left blank */]>; 561 562def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0, 563 (outs DPR:$Dd), (ins SPR:$Sm), 564 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm", 565 []>, Requires<[HasFPARMv8, HasDPVFP]> { 566 // Instruction operands. 567 bits<5> Sm; 568 569 // Encode instruction operands. 570 let Inst{3-0} = Sm{4-1}; 571 let Inst{5} = Sm{0}; 572} 573 574def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0, 575 (outs SPR:$Sd), (ins DPR:$Dm), 576 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm", 577 []>, Requires<[HasFPARMv8, HasDPVFP]> { 578 // Instruction operands. 579 bits<5> Sd; 580 bits<5> Dm; 581 582 // Encode instruction operands. 583 let Inst{3-0} = Dm{3-0}; 584 let Inst{5} = Dm{4}; 585 let Inst{15-12} = Sd{4-1}; 586 let Inst{22} = Sd{0}; 587} 588 589def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0, 590 (outs DPR:$Dd), (ins SPR:$Sm), 591 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm", 592 []>, Requires<[HasFPARMv8, HasDPVFP]> { 593 // Instruction operands. 594 bits<5> Sm; 595 596 // Encode instruction operands. 597 let Inst{3-0} = Sm{4-1}; 598 let Inst{5} = Sm{0}; 599} 600 601def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0, 602 (outs SPR:$Sd), (ins DPR:$Dm), 603 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm", 604 []>, Requires<[HasFPARMv8, HasDPVFP]> { 605 // Instruction operands. 606 bits<5> Sd; 607 bits<5> Dm; 608 609 // Encode instruction operands. 610 let Inst{15-12} = Sd{4-1}; 611 let Inst{22} = Sd{0}; 612 let Inst{3-0} = Dm{3-0}; 613 let Inst{5} = Dm{4}; 614} 615 616def : Pat<(fp_to_f16 SPR:$a), 617 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>; 618 619def : Pat<(fp_to_f16 (f64 DPR:$a)), 620 (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>; 621 622def : Pat<(f16_to_fp GPR:$a), 623 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>; 624 625def : Pat<(f64 (f16_to_fp GPR:$a)), 626 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>; 627 628 629multiclass vcvt_inst<string opc, bits<2> rm> { 630 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in { 631 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0, 632 (outs SPR:$Sd), (ins SPR:$Sm), 633 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"), 634 []>, Requires<[HasFPARMv8]> { 635 let Inst{17-16} = rm; 636 } 637 638 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0, 639 (outs SPR:$Sd), (ins SPR:$Sm), 640 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"), 641 []>, Requires<[HasFPARMv8]> { 642 let Inst{17-16} = rm; 643 } 644 645 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0, 646 (outs SPR:$Sd), (ins DPR:$Dm), 647 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"), 648 []>, Requires<[HasFPARMv8, HasDPVFP]> { 649 bits<5> Dm; 650 651 let Inst{17-16} = rm; 652 653 // Encode instruction operands 654 let Inst{3-0} = Dm{3-0}; 655 let Inst{5} = Dm{4}; 656 let Inst{8} = 1; 657 } 658 659 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0, 660 (outs SPR:$Sd), (ins DPR:$Dm), 661 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"), 662 []>, Requires<[HasFPARMv8, HasDPVFP]> { 663 bits<5> Dm; 664 665 let Inst{17-16} = rm; 666 667 // Encode instruction operands 668 let Inst{3-0} = Dm{3-0}; 669 let Inst{5} = Dm{4}; 670 let Inst{8} = 1; 671 } 672 } 673} 674 675defm VCVTA : vcvt_inst<"a", 0b00>; 676defm VCVTN : vcvt_inst<"n", 0b01>; 677defm VCVTP : vcvt_inst<"p", 0b10>; 678defm VCVTM : vcvt_inst<"m", 0b11>; 679 680def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, 681 (outs DPR:$Dd), (ins DPR:$Dm), 682 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", 683 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>; 684 685def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0, 686 (outs SPR:$Sd), (ins SPR:$Sm), 687 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm", 688 [(set SPR:$Sd, (fneg SPR:$Sm))]> { 689 // Some single precision VFP instructions may be executed on both NEON and 690 // VFP pipelines on A8. 691 let D = VFPNeonA8Domain; 692} 693 694multiclass vrint_inst_zrx<string opc, bit op, bit op2> { 695 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0, 696 (outs SPR:$Sd), (ins SPR:$Sm), 697 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm", 698 []>, Requires<[HasFPARMv8]> { 699 let Inst{7} = op2; 700 let Inst{16} = op; 701 } 702 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0, 703 (outs DPR:$Dd), (ins DPR:$Dm), 704 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm", 705 []>, Requires<[HasFPARMv8, HasDPVFP]> { 706 let Inst{7} = op2; 707 let Inst{16} = op; 708 } 709 710 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"), 711 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>, 712 Requires<[HasFPARMv8]>; 713 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"), 714 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>, 715 Requires<[HasFPARMv8,HasDPVFP]>; 716} 717 718defm VRINTZ : vrint_inst_zrx<"z", 0, 1>; 719defm VRINTR : vrint_inst_zrx<"r", 0, 0>; 720defm VRINTX : vrint_inst_zrx<"x", 1, 0>; 721 722multiclass vrint_inst_anpm<string opc, bits<2> rm> { 723 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in { 724 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0, 725 (outs SPR:$Sd), (ins SPR:$Sm), 726 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"), 727 []>, Requires<[HasFPARMv8]> { 728 let Inst{17-16} = rm; 729 } 730 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0, 731 (outs DPR:$Dd), (ins DPR:$Dm), 732 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"), 733 []>, Requires<[HasFPARMv8, HasDPVFP]> { 734 let Inst{17-16} = rm; 735 } 736 } 737 738 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"), 739 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>, 740 Requires<[HasFPARMv8]>; 741 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"), 742 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>, 743 Requires<[HasFPARMv8,HasDPVFP]>; 744} 745 746defm VRINTA : vrint_inst_anpm<"a", 0b00>; 747defm VRINTN : vrint_inst_anpm<"n", 0b01>; 748defm VRINTP : vrint_inst_anpm<"p", 0b10>; 749defm VRINTM : vrint_inst_anpm<"m", 0b11>; 750 751def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0, 752 (outs DPR:$Dd), (ins DPR:$Dm), 753 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm", 754 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>; 755 756def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0, 757 (outs SPR:$Sd), (ins SPR:$Sm), 758 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm", 759 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>; 760 761let neverHasSideEffects = 1 in { 762def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0, 763 (outs DPR:$Dd), (ins DPR:$Dm), 764 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>; 765 766def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0, 767 (outs SPR:$Sd), (ins SPR:$Sm), 768 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>; 769} // neverHasSideEffects 770 771//===----------------------------------------------------------------------===// 772// FP <-> GPR Copies. Int <-> FP Conversions. 773// 774 775def VMOVRS : AVConv2I<0b11100001, 0b1010, 776 (outs GPR:$Rt), (ins SPR:$Sn), 777 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn", 778 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> { 779 // Instruction operands. 780 bits<4> Rt; 781 bits<5> Sn; 782 783 // Encode instruction operands. 784 let Inst{19-16} = Sn{4-1}; 785 let Inst{7} = Sn{0}; 786 let Inst{15-12} = Rt; 787 788 let Inst{6-5} = 0b00; 789 let Inst{3-0} = 0b0000; 790 791 // Some single precision VFP instructions may be executed on both NEON and VFP 792 // pipelines. 793 let D = VFPNeonDomain; 794} 795 796// Bitcast i32 -> f32. NEON prefers to use VMOVDRR. 797def VMOVSR : AVConv4I<0b11100000, 0b1010, 798 (outs SPR:$Sn), (ins GPR:$Rt), 799 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt", 800 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>, 801 Requires<[HasVFP2, UseVMOVSR]> { 802 // Instruction operands. 803 bits<5> Sn; 804 bits<4> Rt; 805 806 // Encode instruction operands. 807 let Inst{19-16} = Sn{4-1}; 808 let Inst{7} = Sn{0}; 809 let Inst{15-12} = Rt; 810 811 let Inst{6-5} = 0b00; 812 let Inst{3-0} = 0b0000; 813 814 // Some single precision VFP instructions may be executed on both NEON and VFP 815 // pipelines. 816 let D = VFPNeonDomain; 817} 818 819let neverHasSideEffects = 1 in { 820def VMOVRRD : AVConv3I<0b11000101, 0b1011, 821 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm), 822 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm", 823 [/* FIXME: Can't write pattern for multiple result instr*/]> { 824 // Instruction operands. 825 bits<5> Dm; 826 bits<4> Rt; 827 bits<4> Rt2; 828 829 // Encode instruction operands. 830 let Inst{3-0} = Dm{3-0}; 831 let Inst{5} = Dm{4}; 832 let Inst{15-12} = Rt; 833 let Inst{19-16} = Rt2; 834 835 let Inst{7-6} = 0b00; 836 837 // Some single precision VFP instructions may be executed on both NEON and VFP 838 // pipelines. 839 let D = VFPNeonDomain; 840} 841 842def VMOVRRS : AVConv3I<0b11000101, 0b1010, 843 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2), 844 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2", 845 [/* For disassembly only; pattern left blank */]> { 846 bits<5> src1; 847 bits<4> Rt; 848 bits<4> Rt2; 849 850 // Encode instruction operands. 851 let Inst{3-0} = src1{4-1}; 852 let Inst{5} = src1{0}; 853 let Inst{15-12} = Rt; 854 let Inst{19-16} = Rt2; 855 856 let Inst{7-6} = 0b00; 857 858 // Some single precision VFP instructions may be executed on both NEON and VFP 859 // pipelines. 860 let D = VFPNeonDomain; 861 let DecoderMethod = "DecodeVMOVRRS"; 862} 863} // neverHasSideEffects 864 865// FMDHR: GPR -> SPR 866// FMDLR: GPR -> SPR 867 868def VMOVDRR : AVConv5I<0b11000100, 0b1011, 869 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2), 870 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2", 871 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> { 872 // Instruction operands. 873 bits<5> Dm; 874 bits<4> Rt; 875 bits<4> Rt2; 876 877 // Encode instruction operands. 878 let Inst{3-0} = Dm{3-0}; 879 let Inst{5} = Dm{4}; 880 let Inst{15-12} = Rt; 881 let Inst{19-16} = Rt2; 882 883 let Inst{7-6} = 0b00; 884 885 // Some single precision VFP instructions may be executed on both NEON and VFP 886 // pipelines. 887 let D = VFPNeonDomain; 888} 889 890let neverHasSideEffects = 1 in 891def VMOVSRR : AVConv5I<0b11000100, 0b1010, 892 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2), 893 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2", 894 [/* For disassembly only; pattern left blank */]> { 895 // Instruction operands. 896 bits<5> dst1; 897 bits<4> src1; 898 bits<4> src2; 899 900 // Encode instruction operands. 901 let Inst{3-0} = dst1{4-1}; 902 let Inst{5} = dst1{0}; 903 let Inst{15-12} = src1; 904 let Inst{19-16} = src2; 905 906 let Inst{7-6} = 0b00; 907 908 // Some single precision VFP instructions may be executed on both NEON and VFP 909 // pipelines. 910 let D = VFPNeonDomain; 911 912 let DecoderMethod = "DecodeVMOVSRR"; 913} 914 915// FMRDH: SPR -> GPR 916// FMRDL: SPR -> GPR 917// FMRRS: SPR -> GPR 918// FMRX: SPR system reg -> GPR 919// FMSRR: GPR -> SPR 920// FMXR: GPR -> VFP system reg 921 922 923// Int -> FP: 924 925class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 926 bits<4> opcod4, dag oops, dag iops, 927 InstrItinClass itin, string opc, string asm, 928 list<dag> pattern> 929 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 930 pattern> { 931 // Instruction operands. 932 bits<5> Dd; 933 bits<5> Sm; 934 935 // Encode instruction operands. 936 let Inst{3-0} = Sm{4-1}; 937 let Inst{5} = Sm{0}; 938 let Inst{15-12} = Dd{3-0}; 939 let Inst{22} = Dd{4}; 940 941 let Predicates = [HasVFP2, HasDPVFP]; 942} 943 944class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 945 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin, 946 string opc, string asm, list<dag> pattern> 947 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 948 pattern> { 949 // Instruction operands. 950 bits<5> Sd; 951 bits<5> Sm; 952 953 // Encode instruction operands. 954 let Inst{3-0} = Sm{4-1}; 955 let Inst{5} = Sm{0}; 956 let Inst{15-12} = Sd{4-1}; 957 let Inst{22} = Sd{0}; 958} 959 960def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, 961 (outs DPR:$Dd), (ins SPR:$Sm), 962 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm", 963 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> { 964 let Inst{7} = 1; // s32 965} 966 967def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, 968 (outs SPR:$Sd),(ins SPR:$Sm), 969 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm", 970 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> { 971 let Inst{7} = 1; // s32 972 973 // Some single precision VFP instructions may be executed on both NEON and 974 // VFP pipelines on A8. 975 let D = VFPNeonA8Domain; 976} 977 978def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, 979 (outs DPR:$Dd), (ins SPR:$Sm), 980 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm", 981 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> { 982 let Inst{7} = 0; // u32 983} 984 985def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, 986 (outs SPR:$Sd), (ins SPR:$Sm), 987 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm", 988 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> { 989 let Inst{7} = 0; // u32 990 991 // Some single precision VFP instructions may be executed on both NEON and 992 // VFP pipelines on A8. 993 let D = VFPNeonA8Domain; 994} 995 996// FP -> Int: 997 998class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 999 bits<4> opcod4, dag oops, dag iops, 1000 InstrItinClass itin, string opc, string asm, 1001 list<dag> pattern> 1002 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1003 pattern> { 1004 // Instruction operands. 1005 bits<5> Sd; 1006 bits<5> Dm; 1007 1008 // Encode instruction operands. 1009 let Inst{3-0} = Dm{3-0}; 1010 let Inst{5} = Dm{4}; 1011 let Inst{15-12} = Sd{4-1}; 1012 let Inst{22} = Sd{0}; 1013 1014 let Predicates = [HasVFP2, HasDPVFP]; 1015} 1016 1017class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1018 bits<4> opcod4, dag oops, dag iops, 1019 InstrItinClass itin, string opc, string asm, 1020 list<dag> pattern> 1021 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1022 pattern> { 1023 // Instruction operands. 1024 bits<5> Sd; 1025 bits<5> Sm; 1026 1027 // Encode instruction operands. 1028 let Inst{3-0} = Sm{4-1}; 1029 let Inst{5} = Sm{0}; 1030 let Inst{15-12} = Sd{4-1}; 1031 let Inst{22} = Sd{0}; 1032} 1033 1034// Always set Z bit in the instruction, i.e. "round towards zero" variants. 1035def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, 1036 (outs SPR:$Sd), (ins DPR:$Dm), 1037 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm", 1038 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> { 1039 let Inst{7} = 1; // Z bit 1040} 1041 1042def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, 1043 (outs SPR:$Sd), (ins SPR:$Sm), 1044 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm", 1045 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> { 1046 let Inst{7} = 1; // Z bit 1047 1048 // Some single precision VFP instructions may be executed on both NEON and 1049 // VFP pipelines on A8. 1050 let D = VFPNeonA8Domain; 1051} 1052 1053def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, 1054 (outs SPR:$Sd), (ins DPR:$Dm), 1055 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm", 1056 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> { 1057 let Inst{7} = 1; // Z bit 1058} 1059 1060def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, 1061 (outs SPR:$Sd), (ins SPR:$Sm), 1062 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm", 1063 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> { 1064 let Inst{7} = 1; // Z bit 1065 1066 // Some single precision VFP instructions may be executed on both NEON and 1067 // VFP pipelines on A8. 1068 let D = VFPNeonA8Domain; 1069} 1070 1071// And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR. 1072let Uses = [FPSCR] in { 1073// FIXME: Verify encoding after integrated assembler is working. 1074def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, 1075 (outs SPR:$Sd), (ins DPR:$Dm), 1076 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm", 1077 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{ 1078 let Inst{7} = 0; // Z bit 1079} 1080 1081def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, 1082 (outs SPR:$Sd), (ins SPR:$Sm), 1083 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm", 1084 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> { 1085 let Inst{7} = 0; // Z bit 1086} 1087 1088def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, 1089 (outs SPR:$Sd), (ins DPR:$Dm), 1090 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm", 1091 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{ 1092 let Inst{7} = 0; // Z bit 1093} 1094 1095def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, 1096 (outs SPR:$Sd), (ins SPR:$Sm), 1097 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm", 1098 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> { 1099 let Inst{7} = 0; // Z bit 1100} 1101} 1102 1103// Convert between floating-point and fixed-point 1104// Data type for fixed-point naming convention: 1105// S16 (U=0, sx=0) -> SH 1106// U16 (U=1, sx=0) -> UH 1107// S32 (U=0, sx=1) -> SL 1108// U32 (U=1, sx=1) -> UL 1109 1110let Constraints = "$a = $dst" in { 1111 1112// FP to Fixed-Point: 1113 1114// Single Precision register 1115class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, 1116 bit op5, dag oops, dag iops, InstrItinClass itin, 1117 string opc, string asm, list<dag> pattern> 1118 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>, 1119 Sched<[WriteCvtFP]> { 1120 bits<5> dst; 1121 // if dp_operation then UInt(D:Vd) else UInt(Vd:D); 1122 let Inst{22} = dst{0}; 1123 let Inst{15-12} = dst{4-1}; 1124} 1125 1126// Double Precision register 1127class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, 1128 bit op5, dag oops, dag iops, InstrItinClass itin, 1129 string opc, string asm, list<dag> pattern> 1130 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>, 1131 Sched<[WriteCvtFP]> { 1132 bits<5> dst; 1133 // if dp_operation then UInt(D:Vd) else UInt(Vd:D); 1134 let Inst{22} = dst{4}; 1135 let Inst{15-12} = dst{3-0}; 1136 1137 let Predicates = [HasVFP2, HasDPVFP]; 1138} 1139 1140def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0, 1141 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1142 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []> { 1143 // Some single precision VFP instructions may be executed on both NEON and 1144 // VFP pipelines on A8. 1145 let D = VFPNeonA8Domain; 1146} 1147 1148def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0, 1149 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1150 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []> { 1151 // Some single precision VFP instructions may be executed on both NEON and 1152 // VFP pipelines on A8. 1153 let D = VFPNeonA8Domain; 1154} 1155 1156def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1, 1157 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1158 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []> { 1159 // Some single precision VFP instructions may be executed on both NEON and 1160 // VFP pipelines on A8. 1161 let D = VFPNeonA8Domain; 1162} 1163 1164def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1, 1165 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1166 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []> { 1167 // Some single precision VFP instructions may be executed on both NEON and 1168 // VFP pipelines on A8. 1169 let D = VFPNeonA8Domain; 1170} 1171 1172def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0, 1173 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1174 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>; 1175 1176def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0, 1177 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1178 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>; 1179 1180def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1, 1181 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1182 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>; 1183 1184def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1, 1185 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1186 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>; 1187 1188// Fixed-Point to FP: 1189 1190def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0, 1191 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1192 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []> { 1193 // Some single precision VFP instructions may be executed on both NEON and 1194 // VFP pipelines on A8. 1195 let D = VFPNeonA8Domain; 1196} 1197 1198def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0, 1199 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1200 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []> { 1201 // Some single precision VFP instructions may be executed on both NEON and 1202 // VFP pipelines on A8. 1203 let D = VFPNeonA8Domain; 1204} 1205 1206def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1, 1207 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1208 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []> { 1209 // Some single precision VFP instructions may be executed on both NEON and 1210 // VFP pipelines on A8. 1211 let D = VFPNeonA8Domain; 1212} 1213 1214def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1, 1215 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1216 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []> { 1217 // Some single precision VFP instructions may be executed on both NEON and 1218 // VFP pipelines on A8. 1219 let D = VFPNeonA8Domain; 1220} 1221 1222def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0, 1223 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1224 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>; 1225 1226def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0, 1227 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1228 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>; 1229 1230def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1, 1231 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1232 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>; 1233 1234def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1, 1235 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1236 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>; 1237 1238} // End of 'let Constraints = "$a = $dst" in' 1239 1240//===----------------------------------------------------------------------===// 1241// FP Multiply-Accumulate Operations. 1242// 1243 1244def VMLAD : ADbI<0b11100, 0b00, 0, 0, 1245 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1246 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm", 1247 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1248 (f64 DPR:$Ddin)))]>, 1249 RegConstraint<"$Ddin = $Dd">, 1250 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1251 1252def VMLAS : ASbIn<0b11100, 0b00, 0, 0, 1253 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1254 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm", 1255 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), 1256 SPR:$Sdin))]>, 1257 RegConstraint<"$Sdin = $Sd">, 1258 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> { 1259 // Some single precision VFP instructions may be executed on both NEON and 1260 // VFP pipelines on A8. 1261 let D = VFPNeonA8Domain; 1262} 1263 1264def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1265 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 1266 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1267def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1268 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 1269 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>; 1270 1271def VMLSD : ADbI<0b11100, 0b00, 1, 0, 1272 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1273 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm", 1274 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1275 (f64 DPR:$Ddin)))]>, 1276 RegConstraint<"$Ddin = $Dd">, 1277 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1278 1279def VMLSS : ASbIn<0b11100, 0b00, 1, 0, 1280 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1281 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm", 1282 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1283 SPR:$Sdin))]>, 1284 RegConstraint<"$Sdin = $Sd">, 1285 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> { 1286 // Some single precision VFP instructions may be executed on both NEON and 1287 // VFP pipelines on A8. 1288 let D = VFPNeonA8Domain; 1289} 1290 1291def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1292 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, 1293 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1294def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1295 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, 1296 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>; 1297 1298def VNMLAD : ADbI<0b11100, 0b01, 1, 0, 1299 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1300 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm", 1301 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1302 (f64 DPR:$Ddin)))]>, 1303 RegConstraint<"$Ddin = $Dd">, 1304 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1305 1306def VNMLAS : ASbI<0b11100, 0b01, 1, 0, 1307 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1308 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm", 1309 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1310 SPR:$Sdin))]>, 1311 RegConstraint<"$Sdin = $Sd">, 1312 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> { 1313 // Some single precision VFP instructions may be executed on both NEON and 1314 // VFP pipelines on A8. 1315 let D = VFPNeonA8Domain; 1316} 1317 1318def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin), 1319 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 1320 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1321def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin), 1322 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 1323 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>; 1324 1325def VNMLSD : ADbI<0b11100, 0b01, 0, 0, 1326 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1327 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm", 1328 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1329 (f64 DPR:$Ddin)))]>, 1330 RegConstraint<"$Ddin = $Dd">, 1331 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1332 1333def VNMLSS : ASbI<0b11100, 0b01, 0, 0, 1334 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1335 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm", 1336 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, 1337 RegConstraint<"$Sdin = $Sd">, 1338 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> { 1339 // Some single precision VFP instructions may be executed on both NEON and 1340 // VFP pipelines on A8. 1341 let D = VFPNeonA8Domain; 1342} 1343 1344def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin), 1345 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>, 1346 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>; 1347def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), 1348 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>, 1349 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>; 1350 1351//===----------------------------------------------------------------------===// 1352// Fused FP Multiply-Accumulate Operations. 1353// 1354def VFMAD : ADbI<0b11101, 0b10, 0, 0, 1355 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1356 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm", 1357 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1358 (f64 DPR:$Ddin)))]>, 1359 RegConstraint<"$Ddin = $Dd">, 1360 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1361 1362def VFMAS : ASbIn<0b11101, 0b10, 0, 0, 1363 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1364 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm", 1365 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), 1366 SPR:$Sdin))]>, 1367 RegConstraint<"$Sdin = $Sd">, 1368 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> { 1369 // Some single precision VFP instructions may be executed on both NEON and 1370 // VFP pipelines. 1371} 1372 1373def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1374 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>, 1375 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1376def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1377 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>, 1378 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 1379 1380// Match @llvm.fma.* intrinsics 1381// (fma x, y, z) -> (vfms z, x, y) 1382def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)), 1383 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1384 Requires<[HasVFP4,HasDPVFP]>; 1385def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)), 1386 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1387 Requires<[HasVFP4]>; 1388 1389def VFMSD : ADbI<0b11101, 0b10, 1, 0, 1390 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1391 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm", 1392 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1393 (f64 DPR:$Ddin)))]>, 1394 RegConstraint<"$Ddin = $Dd">, 1395 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1396 1397def VFMSS : ASbIn<0b11101, 0b10, 1, 0, 1398 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1399 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm", 1400 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1401 SPR:$Sdin))]>, 1402 RegConstraint<"$Sdin = $Sd">, 1403 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> { 1404 // Some single precision VFP instructions may be executed on both NEON and 1405 // VFP pipelines. 1406} 1407 1408def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1409 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>, 1410 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1411def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1412 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>, 1413 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 1414 1415// Match @llvm.fma.* intrinsics 1416// (fma (fneg x), y, z) -> (vfms z, x, y) 1417def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)), 1418 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1419 Requires<[HasVFP4,HasDPVFP]>; 1420def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)), 1421 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1422 Requires<[HasVFP4]>; 1423// (fma x, (fneg y), z) -> (vfms z, x, y) 1424def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)), 1425 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1426 Requires<[HasVFP4,HasDPVFP]>; 1427def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)), 1428 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1429 Requires<[HasVFP4]>; 1430 1431def VFNMAD : ADbI<0b11101, 0b01, 1, 0, 1432 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1433 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm", 1434 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1435 (f64 DPR:$Ddin)))]>, 1436 RegConstraint<"$Ddin = $Dd">, 1437 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1438 1439def VFNMAS : ASbI<0b11101, 0b01, 1, 0, 1440 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1441 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm", 1442 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1443 SPR:$Sdin))]>, 1444 RegConstraint<"$Sdin = $Sd">, 1445 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> { 1446 // Some single precision VFP instructions may be executed on both NEON and 1447 // VFP pipelines. 1448} 1449 1450def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin), 1451 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>, 1452 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1453def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin), 1454 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>, 1455 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 1456 1457// Match @llvm.fma.* intrinsics 1458// (fneg (fma x, y, z)) -> (vfnma z, x, y) 1459def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))), 1460 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1461 Requires<[HasVFP4,HasDPVFP]>; 1462def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))), 1463 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1464 Requires<[HasVFP4]>; 1465// (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y) 1466def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))), 1467 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1468 Requires<[HasVFP4,HasDPVFP]>; 1469def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))), 1470 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1471 Requires<[HasVFP4]>; 1472 1473def VFNMSD : ADbI<0b11101, 0b01, 0, 0, 1474 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1475 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm", 1476 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1477 (f64 DPR:$Ddin)))]>, 1478 RegConstraint<"$Ddin = $Dd">, 1479 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1480 1481def VFNMSS : ASbI<0b11101, 0b01, 0, 0, 1482 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1483 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm", 1484 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, 1485 RegConstraint<"$Sdin = $Sd">, 1486 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> { 1487 // Some single precision VFP instructions may be executed on both NEON and 1488 // VFP pipelines. 1489} 1490 1491def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin), 1492 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>, 1493 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 1494def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), 1495 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>, 1496 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 1497 1498// Match @llvm.fma.* intrinsics 1499 1500// (fma x, y, (fneg z)) -> (vfnms z, x, y)) 1501def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))), 1502 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1503 Requires<[HasVFP4,HasDPVFP]>; 1504def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))), 1505 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1506 Requires<[HasVFP4]>; 1507// (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y) 1508def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))), 1509 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1510 Requires<[HasVFP4,HasDPVFP]>; 1511def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))), 1512 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1513 Requires<[HasVFP4]>; 1514// (fneg (fma x, (fneg y), z) -> (vfnms z, x, y) 1515def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))), 1516 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 1517 Requires<[HasVFP4,HasDPVFP]>; 1518def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))), 1519 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 1520 Requires<[HasVFP4]>; 1521 1522//===----------------------------------------------------------------------===// 1523// FP Conditional moves. 1524// 1525 1526let neverHasSideEffects = 1 in { 1527def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p), 1528 IIC_fpUNA64, 1529 [(set (f64 DPR:$Dd), 1530 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>, 1531 RegConstraint<"$Dn = $Dd">, Requires<[HasVFP2,HasDPVFP]>; 1532 1533def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p), 1534 IIC_fpUNA32, 1535 [(set (f32 SPR:$Sd), 1536 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>, 1537 RegConstraint<"$Sn = $Sd">, Requires<[HasVFP2]>; 1538} // neverHasSideEffects 1539 1540//===----------------------------------------------------------------------===// 1541// Move from VFP System Register to ARM core register. 1542// 1543 1544class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, 1545 list<dag> pattern>: 1546 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { 1547 1548 // Instruction operand. 1549 bits<4> Rt; 1550 1551 let Inst{27-20} = 0b11101111; 1552 let Inst{19-16} = opc19_16; 1553 let Inst{15-12} = Rt; 1554 let Inst{11-8} = 0b1010; 1555 let Inst{7} = 0; 1556 let Inst{6-5} = 0b00; 1557 let Inst{4} = 1; 1558 let Inst{3-0} = 0b0000; 1559} 1560 1561// APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags 1562// to APSR. 1563let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in 1564def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins), 1565 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>; 1566 1567// Application level FPSCR -> GPR 1568let hasSideEffects = 1, Uses = [FPSCR] in 1569def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins), 1570 "vmrs", "\t$Rt, fpscr", 1571 [(set GPR:$Rt, (int_arm_get_fpscr))]>; 1572 1573// System level FPEXC, FPSID -> GPR 1574let Uses = [FPSCR] in { 1575 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins), 1576 "vmrs", "\t$Rt, fpexc", []>; 1577 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins), 1578 "vmrs", "\t$Rt, fpsid", []>; 1579 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins), 1580 "vmrs", "\t$Rt, mvfr0", []>; 1581 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins), 1582 "vmrs", "\t$Rt, mvfr1", []>; 1583 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPR:$Rt), (ins), 1584 "vmrs", "\t$Rt, mvfr2", []>, Requires<[HasFPARMv8]>; 1585 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins), 1586 "vmrs", "\t$Rt, fpinst", []>; 1587 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins), 1588 "vmrs", "\t$Rt, fpinst2", []>; 1589} 1590 1591//===----------------------------------------------------------------------===// 1592// Move from ARM core register to VFP System Register. 1593// 1594 1595class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, 1596 list<dag> pattern>: 1597 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { 1598 1599 // Instruction operand. 1600 bits<4> src; 1601 1602 // Encode instruction operand. 1603 let Inst{15-12} = src; 1604 1605 let Inst{27-20} = 0b11101110; 1606 let Inst{19-16} = opc19_16; 1607 let Inst{11-8} = 0b1010; 1608 let Inst{7} = 0; 1609 let Inst{4} = 1; 1610} 1611 1612let Defs = [FPSCR] in { 1613 // Application level GPR -> FPSCR 1614 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src), 1615 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>; 1616 // System level GPR -> FPEXC 1617 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src), 1618 "vmsr", "\tfpexc, $src", []>; 1619 // System level GPR -> FPSID 1620 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src), 1621 "vmsr", "\tfpsid, $src", []>; 1622 1623 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPR:$src), 1624 "vmsr", "\tfpinst, $src", []>; 1625 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPR:$src), 1626 "vmsr", "\tfpinst2, $src", []>; 1627} 1628 1629//===----------------------------------------------------------------------===// 1630// Misc. 1631// 1632 1633// Materialize FP immediates. VFP3 only. 1634let isReMaterializable = 1 in { 1635def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm), 1636 VFPMiscFrm, IIC_fpUNA64, 1637 "vmov", ".f64\t$Dd, $imm", 1638 [(set DPR:$Dd, vfp_f64imm:$imm)]>, 1639 Requires<[HasVFP3,HasDPVFP]> { 1640 bits<5> Dd; 1641 bits<8> imm; 1642 1643 let Inst{27-23} = 0b11101; 1644 let Inst{22} = Dd{4}; 1645 let Inst{21-20} = 0b11; 1646 let Inst{19-16} = imm{7-4}; 1647 let Inst{15-12} = Dd{3-0}; 1648 let Inst{11-9} = 0b101; 1649 let Inst{8} = 1; // Double precision. 1650 let Inst{7-4} = 0b0000; 1651 let Inst{3-0} = imm{3-0}; 1652} 1653 1654def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm), 1655 VFPMiscFrm, IIC_fpUNA32, 1656 "vmov", ".f32\t$Sd, $imm", 1657 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> { 1658 bits<5> Sd; 1659 bits<8> imm; 1660 1661 let Inst{27-23} = 0b11101; 1662 let Inst{22} = Sd{0}; 1663 let Inst{21-20} = 0b11; 1664 let Inst{19-16} = imm{7-4}; 1665 let Inst{15-12} = Sd{4-1}; 1666 let Inst{11-9} = 0b101; 1667 let Inst{8} = 0; // Single precision. 1668 let Inst{7-4} = 0b0000; 1669 let Inst{3-0} = imm{3-0}; 1670} 1671} 1672 1673//===----------------------------------------------------------------------===// 1674// Assembler aliases. 1675// 1676// A few mnemonic aliases for pre-unifixed syntax. We don't guarantee to 1677// support them all, but supporting at least some of the basics is 1678// good to be friendly. 1679def : VFP2MnemonicAlias<"flds", "vldr">; 1680def : VFP2MnemonicAlias<"fldd", "vldr">; 1681def : VFP2MnemonicAlias<"fmrs", "vmov">; 1682def : VFP2MnemonicAlias<"fmsr", "vmov">; 1683def : VFP2MnemonicAlias<"fsqrts", "vsqrt">; 1684def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">; 1685def : VFP2MnemonicAlias<"fadds", "vadd.f32">; 1686def : VFP2MnemonicAlias<"faddd", "vadd.f64">; 1687def : VFP2MnemonicAlias<"fmrdd", "vmov">; 1688def : VFP2MnemonicAlias<"fmrds", "vmov">; 1689def : VFP2MnemonicAlias<"fmrrd", "vmov">; 1690def : VFP2MnemonicAlias<"fmdrr", "vmov">; 1691def : VFP2MnemonicAlias<"fmuls", "vmul.f32">; 1692def : VFP2MnemonicAlias<"fmuld", "vmul.f64">; 1693def : VFP2MnemonicAlias<"fnegs", "vneg.f32">; 1694def : VFP2MnemonicAlias<"fnegd", "vneg.f64">; 1695def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">; 1696def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">; 1697def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">; 1698def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">; 1699def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">; 1700def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">; 1701def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">; 1702def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">; 1703def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">; 1704def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">; 1705def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">; 1706def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">; 1707def : VFP2MnemonicAlias<"fsts", "vstr">; 1708def : VFP2MnemonicAlias<"fstd", "vstr">; 1709def : VFP2MnemonicAlias<"fmacd", "vmla.f64">; 1710def : VFP2MnemonicAlias<"fmacs", "vmla.f32">; 1711def : VFP2MnemonicAlias<"fcpys", "vmov.f32">; 1712def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">; 1713def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">; 1714def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">; 1715def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">; 1716def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">; 1717def : VFP2MnemonicAlias<"fmrx", "vmrs">; 1718def : VFP2MnemonicAlias<"fmxr", "vmsr">; 1719 1720// Be friendly and accept the old form of zero-compare 1721def : VFP2DPInstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>; 1722def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>; 1723 1724 1725def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>; 1726def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm", 1727 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>; 1728def : VFP2DPInstAlias<"faddd${p} $Dd, $Dn, $Dm", 1729 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>; 1730def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm", 1731 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>; 1732def : VFP2DPInstAlias<"fsubd${p} $Dd, $Dn, $Dm", 1733 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>; 1734 1735// No need for the size suffix on VSQRT. It's implied by the register classes. 1736def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>; 1737def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>; 1738 1739// VLDR/VSTR accept an optional type suffix. 1740def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr", 1741 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>; 1742def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr", 1743 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>; 1744def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr", 1745 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>; 1746def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr", 1747 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>; 1748 1749// VMOV can accept optional 32-bit or less data type suffix suffix. 1750def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn", 1751 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 1752def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn", 1753 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 1754def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn", 1755 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 1756def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt", 1757 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 1758def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt", 1759 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 1760def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt", 1761 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 1762 1763def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn", 1764 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>; 1765def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2", 1766 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>; 1767 1768// VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way 1769// VMOVD does. 1770def : VFP2InstAlias<"vmov${p} $Sd, $Sm", 1771 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>; 1772 1773// FCONSTD/FCONSTS alias for vmov.f64/vmov.f32 1774// These aliases provide added functionality over vmov.f instructions by 1775// allowing users to write assembly containing encoded floating point constants 1776// (e.g. #0x70 vs #1.0). Without these alises there is no way for the 1777// assembler to accept encoded fp constants (but the equivalent fp-literal is 1778// accepted directly by vmovf). 1779def : VFP3InstAlias<"fconstd${p} $Dd, $val", 1780 (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p)>; 1781def : VFP3InstAlias<"fconsts${p} $Sd, $val", 1782 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>; 1783