1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// ARM specific DAG Nodes. 16// 17 18// Type profiles. 19def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 21def SDT_ARMStructByVal : SDTypeProfile<0, 4, 22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 24 25def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 26 27def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 28 29def SDT_ARMCMov : SDTypeProfile<1, 3, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 31 SDTCisVT<3, i32>]>; 32 33def SDT_ARMBrcond : SDTypeProfile<0, 2, 34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 35 36def SDT_ARMBrJT : SDTypeProfile<0, 3, 37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 38 SDTCisVT<2, i32>]>; 39 40def SDT_ARMBr2JT : SDTypeProfile<0, 4, 41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 43 44def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, 45 [SDTCisVT<0, i32>, 46 SDTCisVT<1, i32>, SDTCisVT<2, i32>, 47 SDTCisVT<3, i32>, SDTCisVT<4, i32>, 48 SDTCisVT<5, OtherVT>]>; 49 50def SDT_ARMAnd : SDTypeProfile<1, 2, 51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 52 SDTCisVT<2, i32>]>; 53 54def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 55 56def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 58 59def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 60def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 61 SDTCisInt<2>]>; 62def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 63 64def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 65 66def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 67 SDTCisInt<1>]>; 68 69def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 70 71def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 73 74def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>; 75def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>; 76 77def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 78 [SDTCisSameAs<0, 2>, 79 SDTCisSameAs<0, 3>, 80 SDTCisInt<0>, SDTCisVT<1, i32>]>; 81 82// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR 83def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 84 [SDTCisSameAs<0, 2>, 85 SDTCisSameAs<0, 3>, 86 SDTCisInt<0>, 87 SDTCisVT<1, i32>, 88 SDTCisVT<4, i32>]>; 89 90def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>, 91 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 92 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >; 93def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>; 94def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>; 95 96// Node definitions. 97def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 98def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>; 99def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>; 100 101def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 102 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 103def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 104 [SDNPHasChain, SDNPSideEffect, 105 SDNPOptInGlue, SDNPOutGlue]>; 106def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" , 107 SDT_ARMStructByVal, 108 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 109 SDNPMayStore, SDNPMayLoad]>; 110 111def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 112 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 113 SDNPVariadic]>; 114def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 116 SDNPVariadic]>; 117def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 119 SDNPVariadic]>; 120 121def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 122 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 123def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall, 124 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 125def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 126 [SDNPInGlue]>; 127 128def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 129 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 130 131def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 132 [SDNPHasChain]>; 133def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 134 [SDNPHasChain]>; 135 136def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, 137 [SDNPHasChain]>; 138 139def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 140 [SDNPOutGlue]>; 141 142def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp, 143 [SDNPOutGlue]>; 144 145def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 146 [SDNPOutGlue, SDNPCommutative]>; 147 148def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 149 150def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 151def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 152def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; 153 154def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, 155 [SDNPCommutative]>; 156def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; 157def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; 158def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; 159 160def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 161def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", 162 SDT_ARMEH_SJLJ_Setjmp, 163 [SDNPHasChain, SDNPSideEffect]>; 164def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", 165 SDT_ARMEH_SJLJ_Longjmp, 166 [SDNPHasChain, SDNPSideEffect]>; 167 168def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, 169 [SDNPHasChain, SDNPSideEffect]>; 170def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH, 171 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 172 173def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>; 174 175def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, 176 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 177 178def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; 179 180def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>; 181def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>; 182 183//===----------------------------------------------------------------------===// 184// ARM Instruction Predicate Definitions. 185// 186def HasV4T : Predicate<"Subtarget->hasV4TOps()">, 187 AssemblerPredicate<"HasV4TOps", "armv4t">; 188def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; 189def HasV5T : Predicate<"Subtarget->hasV5TOps()">, 190 AssemblerPredicate<"HasV5TOps", "armv5t">; 191def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, 192 AssemblerPredicate<"HasV5TEOps", "armv5te">; 193def HasV6 : Predicate<"Subtarget->hasV6Ops()">, 194 AssemblerPredicate<"HasV6Ops", "armv6">; 195def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; 196def HasV6M : Predicate<"Subtarget->hasV6MOps()">, 197 AssemblerPredicate<"HasV6MOps", 198 "armv6m or armv6t2">; 199def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, 200 AssemblerPredicate<"HasV6T2Ops", "armv6t2">; 201def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; 202def HasV7 : Predicate<"Subtarget->hasV7Ops()">, 203 AssemblerPredicate<"HasV7Ops", "armv7">; 204def HasV8 : Predicate<"Subtarget->hasV8Ops()">, 205 AssemblerPredicate<"HasV8Ops", "armv8">; 206def PreV8 : Predicate<"!Subtarget->hasV8Ops()">, 207 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">; 208def NoVFP : Predicate<"!Subtarget->hasVFP2()">; 209def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, 210 AssemblerPredicate<"FeatureVFP2", "VFP2">; 211def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, 212 AssemblerPredicate<"FeatureVFP3", "VFP3">; 213def HasVFP4 : Predicate<"Subtarget->hasVFP4()">, 214 AssemblerPredicate<"FeatureVFP4", "VFP4">; 215def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">, 216 AssemblerPredicate<"!FeatureVFPOnlySP", 217 "double precision VFP">; 218def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, 219 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">; 220def HasNEON : Predicate<"Subtarget->hasNEON()">, 221 AssemblerPredicate<"FeatureNEON", "NEON">; 222def HasCrypto : Predicate<"Subtarget->hasCrypto()">, 223 AssemblerPredicate<"FeatureCrypto", "crypto">; 224def HasCRC : Predicate<"Subtarget->hasCRC()">, 225 AssemblerPredicate<"FeatureCRC", "crc">; 226def HasFP16 : Predicate<"Subtarget->hasFP16()">, 227 AssemblerPredicate<"FeatureFP16","half-float">; 228def HasDivide : Predicate<"Subtarget->hasDivide()">, 229 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">; 230def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">, 231 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">; 232def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">, 233 AssemblerPredicate<"FeatureT2XtPk", 234 "pack/extract">; 235def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">, 236 AssemblerPredicate<"FeatureDSPThumb2", 237 "thumb2-dsp">; 238def HasDB : Predicate<"Subtarget->hasDataBarrier()">, 239 AssemblerPredicate<"FeatureDB", 240 "data-barriers">; 241def HasMP : Predicate<"Subtarget->hasMPExtension()">, 242 AssemblerPredicate<"FeatureMP", 243 "mp-extensions">; 244def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">, 245 AssemblerPredicate<"FeatureTrustZone", 246 "TrustZone">; 247def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">; 248def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; 249def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; 250def IsThumb : Predicate<"Subtarget->isThumb()">, 251 AssemblerPredicate<"ModeThumb", "thumb">; 252def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; 253def IsThumb2 : Predicate<"Subtarget->isThumb2()">, 254 AssemblerPredicate<"ModeThumb,FeatureThumb2", 255 "thumb2">; 256def IsMClass : Predicate<"Subtarget->isMClass()">, 257 AssemblerPredicate<"FeatureMClass", "armv*m">; 258def IsNotMClass : Predicate<"!Subtarget->isMClass()">, 259 AssemblerPredicate<"!FeatureMClass", 260 "!armv*m">; 261def IsARM : Predicate<"!Subtarget->isThumb()">, 262 AssemblerPredicate<"!ModeThumb", "arm-mode">; 263def IsIOS : Predicate<"Subtarget->isTargetIOS()">; 264def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">; 265def IsMachO : Predicate<"Subtarget->isTargetMachO()">; 266def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">; 267def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 268def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">, 269 AssemblerPredicate<"FeatureNaClTrap", "NaCl">; 270def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">; 271 272// FIXME: Eventually this will be just "hasV6T2Ops". 273def UseMovt : Predicate<"Subtarget->useMovt(*MF)">; 274def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">; 275def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">; 276def UseMulOps : Predicate<"Subtarget->useMulOps()">; 277 278// Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available. 279// But only select them if more precision in FP computation is allowed. 280// Do not use them for Darwin platforms. 281def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion ==" 282 " FPOpFusion::Fast && " 283 " Subtarget->hasVFP4()) && " 284 "!Subtarget->isTargetDarwin()">; 285def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion ==" 286 " FPOpFusion::Fast &&" 287 " Subtarget->hasVFP4()) || " 288 "Subtarget->isTargetDarwin()">; 289 290// VGETLNi32 is microcoded on Swift - prefer VMOV. 291def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">; 292def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">; 293 294// VDUP.32 is microcoded on Swift - prefer VMOV. 295def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">; 296def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">; 297 298// Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as 299// this allows more effective execution domain optimization. See 300// setExecutionDomain(). 301def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">; 302def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">; 303 304def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">; 305def IsBE : Predicate<"getTargetLowering()->isBigEndian()">; 306 307//===----------------------------------------------------------------------===// 308// ARM Flag Definitions. 309 310class RegConstraint<string C> { 311 string Constraints = C; 312} 313 314//===----------------------------------------------------------------------===// 315// ARM specific transformation functions and pattern fragments. 316// 317 318// imm_neg_XFORM - Return the negation of an i32 immediate value. 319def imm_neg_XFORM : SDNodeXForm<imm, [{ 320 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32); 321}]>; 322 323// imm_not_XFORM - Return the complement of a i32 immediate value. 324def imm_not_XFORM : SDNodeXForm<imm, [{ 325 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32); 326}]>; 327 328/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 329def imm16_31 : ImmLeaf<i32, [{ 330 return (int32_t)Imm >= 16 && (int32_t)Imm < 32; 331}]>; 332 333def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; } 334def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 335 unsigned Value = -(unsigned)N->getZExtValue(); 336 return Value && ARM_AM::getSOImmVal(Value) != -1; 337 }], imm_neg_XFORM> { 338 let ParserMatchClass = so_imm_neg_asmoperand; 339} 340 341// Note: this pattern doesn't require an encoder method and such, as it's 342// only used on aliases (Pat<> and InstAlias<>). The actual encoding 343// is handled by the destination instructions, which use so_imm. 344def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; } 345def so_imm_not : Operand<i32>, PatLeaf<(imm), [{ 346 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; 347 }], imm_not_XFORM> { 348 let ParserMatchClass = so_imm_not_asmoperand; 349} 350 351// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 352def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 353 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; 354}]>; 355 356/// Split a 32-bit immediate into two 16 bit parts. 357def hi16 : SDNodeXForm<imm, [{ 358 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32); 359}]>; 360 361def lo16AllZero : PatLeaf<(i32 imm), [{ 362 // Returns true if all low 16-bits are 0. 363 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 364}], hi16>; 365 366class BinOpWithFlagFrag<dag res> : 367 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>; 368class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 369class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 370 371// An 'and' node with a single use. 372def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 373 return N->hasOneUse(); 374}]>; 375 376// An 'xor' node with a single use. 377def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{ 378 return N->hasOneUse(); 379}]>; 380 381// An 'fmul' node with a single use. 382def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{ 383 return N->hasOneUse(); 384}]>; 385 386// An 'fadd' node which checks for single non-hazardous use. 387def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{ 388 return hasNoVMLxHazardUse(N); 389}]>; 390 391// An 'fsub' node which checks for single non-hazardous use. 392def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{ 393 return hasNoVMLxHazardUse(N); 394}]>; 395 396//===----------------------------------------------------------------------===// 397// Operand Definitions. 398// 399 400// Immediate operands with a shared generic asm render method. 401class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; } 402 403// Branch target. 404// FIXME: rename brtarget to t2_brtarget 405def brtarget : Operand<OtherVT> { 406 let EncoderMethod = "getBranchTargetOpValue"; 407 let OperandType = "OPERAND_PCREL"; 408 let DecoderMethod = "DecodeT2BROperand"; 409} 410 411// FIXME: get rid of this one? 412def uncondbrtarget : Operand<OtherVT> { 413 let EncoderMethod = "getUnconditionalBranchTargetOpValue"; 414 let OperandType = "OPERAND_PCREL"; 415} 416 417// Branch target for ARM. Handles conditional/unconditional 418def br_target : Operand<OtherVT> { 419 let EncoderMethod = "getARMBranchTargetOpValue"; 420 let OperandType = "OPERAND_PCREL"; 421} 422 423// Call target. 424// FIXME: rename bltarget to t2_bl_target? 425def bltarget : Operand<i32> { 426 // Encoded the same as branch targets. 427 let EncoderMethod = "getBranchTargetOpValue"; 428 let OperandType = "OPERAND_PCREL"; 429} 430 431// Call target for ARM. Handles conditional/unconditional 432// FIXME: rename bl_target to t2_bltarget? 433def bl_target : Operand<i32> { 434 let EncoderMethod = "getARMBLTargetOpValue"; 435 let OperandType = "OPERAND_PCREL"; 436} 437 438def blx_target : Operand<i32> { 439 let EncoderMethod = "getARMBLXTargetOpValue"; 440 let OperandType = "OPERAND_PCREL"; 441} 442 443// A list of registers separated by comma. Used by load/store multiple. 444def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } 445def reglist : Operand<i32> { 446 let EncoderMethod = "getRegisterListOpValue"; 447 let ParserMatchClass = RegListAsmOperand; 448 let PrintMethod = "printRegisterList"; 449 let DecoderMethod = "DecodeRegListOperand"; 450} 451 452def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">; 453 454def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; } 455def dpr_reglist : Operand<i32> { 456 let EncoderMethod = "getRegisterListOpValue"; 457 let ParserMatchClass = DPRRegListAsmOperand; 458 let PrintMethod = "printRegisterList"; 459 let DecoderMethod = "DecodeDPRRegListOperand"; 460} 461 462def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; } 463def spr_reglist : Operand<i32> { 464 let EncoderMethod = "getRegisterListOpValue"; 465 let ParserMatchClass = SPRRegListAsmOperand; 466 let PrintMethod = "printRegisterList"; 467 let DecoderMethod = "DecodeSPRRegListOperand"; 468} 469 470// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 471def cpinst_operand : Operand<i32> { 472 let PrintMethod = "printCPInstOperand"; 473} 474 475// Local PC labels. 476def pclabel : Operand<i32> { 477 let PrintMethod = "printPCLabel"; 478} 479 480// ADR instruction labels. 481def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; } 482def adrlabel : Operand<i32> { 483 let EncoderMethod = "getAdrLabelOpValue"; 484 let ParserMatchClass = AdrLabelAsmOperand; 485 let PrintMethod = "printAdrLabelOperand<0>"; 486} 487 488def neon_vcvt_imm32 : Operand<i32> { 489 let EncoderMethod = "getNEONVcvtImm32OpValue"; 490 let DecoderMethod = "DecodeVCVTImmOperand"; 491} 492 493// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. 494def rot_imm_XFORM: SDNodeXForm<imm, [{ 495 switch (N->getZExtValue()){ 496 default: llvm_unreachable(nullptr); 497 case 0: return CurDAG->getTargetConstant(0, MVT::i32); 498 case 8: return CurDAG->getTargetConstant(1, MVT::i32); 499 case 16: return CurDAG->getTargetConstant(2, MVT::i32); 500 case 24: return CurDAG->getTargetConstant(3, MVT::i32); 501 } 502}]>; 503def RotImmAsmOperand : AsmOperandClass { 504 let Name = "RotImm"; 505 let ParserMethod = "parseRotImm"; 506} 507def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ 508 int32_t v = N->getZExtValue(); 509 return v == 8 || v == 16 || v == 24; }], 510 rot_imm_XFORM> { 511 let PrintMethod = "printRotImmOperand"; 512 let ParserMatchClass = RotImmAsmOperand; 513} 514 515// shift_imm: An integer that encodes a shift amount and the type of shift 516// (asr or lsl). The 6-bit immediate encodes as: 517// {5} 0 ==> lsl 518// 1 asr 519// {4-0} imm5 shift amount. 520// asr #32 encoded as imm5 == 0. 521def ShifterImmAsmOperand : AsmOperandClass { 522 let Name = "ShifterImm"; 523 let ParserMethod = "parseShifterImm"; 524} 525def shift_imm : Operand<i32> { 526 let PrintMethod = "printShiftImmOperand"; 527 let ParserMatchClass = ShifterImmAsmOperand; 528} 529 530// shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm. 531def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } 532def so_reg_reg : Operand<i32>, // reg reg imm 533 ComplexPattern<i32, 3, "SelectRegShifterOperand", 534 [shl, srl, sra, rotr]> { 535 let EncoderMethod = "getSORegRegOpValue"; 536 let PrintMethod = "printSORegRegOperand"; 537 let DecoderMethod = "DecodeSORegRegOperand"; 538 let ParserMatchClass = ShiftedRegAsmOperand; 539 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); 540} 541 542def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } 543def so_reg_imm : Operand<i32>, // reg imm 544 ComplexPattern<i32, 2, "SelectImmShifterOperand", 545 [shl, srl, sra, rotr]> { 546 let EncoderMethod = "getSORegImmOpValue"; 547 let PrintMethod = "printSORegImmOperand"; 548 let DecoderMethod = "DecodeSORegImmOperand"; 549 let ParserMatchClass = ShiftedImmAsmOperand; 550 let MIOperandInfo = (ops GPR, i32imm); 551} 552 553// FIXME: Does this need to be distinct from so_reg? 554def shift_so_reg_reg : Operand<i32>, // reg reg imm 555 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand", 556 [shl,srl,sra,rotr]> { 557 let EncoderMethod = "getSORegRegOpValue"; 558 let PrintMethod = "printSORegRegOperand"; 559 let DecoderMethod = "DecodeSORegRegOperand"; 560 let ParserMatchClass = ShiftedRegAsmOperand; 561 let MIOperandInfo = (ops GPR, GPR, i32imm); 562} 563 564// FIXME: Does this need to be distinct from so_reg? 565def shift_so_reg_imm : Operand<i32>, // reg reg imm 566 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 567 [shl,srl,sra,rotr]> { 568 let EncoderMethod = "getSORegImmOpValue"; 569 let PrintMethod = "printSORegImmOperand"; 570 let DecoderMethod = "DecodeSORegImmOperand"; 571 let ParserMatchClass = ShiftedImmAsmOperand; 572 let MIOperandInfo = (ops GPR, i32imm); 573} 574 575 576// so_imm - Match a 32-bit shifter_operand immediate operand, which is an 577// 8-bit immediate rotated by an arbitrary number of bits. 578def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; } 579def so_imm : Operand<i32>, ImmLeaf<i32, [{ 580 return ARM_AM::getSOImmVal(Imm) != -1; 581 }]> { 582 let EncoderMethod = "getSOImmOpValue"; 583 let ParserMatchClass = SOImmAsmOperand; 584 let DecoderMethod = "DecodeSOImmOperand"; 585} 586 587// Break so_imm's up into two pieces. This handles immediates with up to 16 588// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to 589// get the first/second pieces. 590def so_imm2part : PatLeaf<(imm), [{ 591 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 592}]>; 593 594/// arm_i32imm - True for +V6T2, or true only if so_imm2part is true. 595/// 596def arm_i32imm : PatLeaf<(imm), [{ 597 if (Subtarget->useMovt(*MF)) 598 return true; 599 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 600}]>; 601 602/// imm0_1 predicate - Immediate in the range [0,1]. 603def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; } 604def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; } 605 606/// imm0_3 predicate - Immediate in the range [0,3]. 607def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; } 608def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; } 609 610/// imm0_7 predicate - Immediate in the range [0,7]. 611def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; } 612def imm0_7 : Operand<i32>, ImmLeaf<i32, [{ 613 return Imm >= 0 && Imm < 8; 614}]> { 615 let ParserMatchClass = Imm0_7AsmOperand; 616} 617 618/// imm8 predicate - Immediate is exactly 8. 619def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; } 620def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> { 621 let ParserMatchClass = Imm8AsmOperand; 622} 623 624/// imm16 predicate - Immediate is exactly 16. 625def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; } 626def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> { 627 let ParserMatchClass = Imm16AsmOperand; 628} 629 630/// imm32 predicate - Immediate is exactly 32. 631def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; } 632def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> { 633 let ParserMatchClass = Imm32AsmOperand; 634} 635 636/// imm1_7 predicate - Immediate in the range [1,7]. 637def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; } 638def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> { 639 let ParserMatchClass = Imm1_7AsmOperand; 640} 641 642/// imm1_15 predicate - Immediate in the range [1,15]. 643def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; } 644def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> { 645 let ParserMatchClass = Imm1_15AsmOperand; 646} 647 648/// imm1_31 predicate - Immediate in the range [1,31]. 649def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; } 650def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> { 651 let ParserMatchClass = Imm1_31AsmOperand; 652} 653 654/// imm0_15 predicate - Immediate in the range [0,15]. 655def Imm0_15AsmOperand: ImmAsmOperand { 656 let Name = "Imm0_15"; 657 let DiagnosticType = "ImmRange0_15"; 658} 659def imm0_15 : Operand<i32>, ImmLeaf<i32, [{ 660 return Imm >= 0 && Imm < 16; 661}]> { 662 let ParserMatchClass = Imm0_15AsmOperand; 663} 664 665/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 666def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; } 667def imm0_31 : Operand<i32>, ImmLeaf<i32, [{ 668 return Imm >= 0 && Imm < 32; 669}]> { 670 let ParserMatchClass = Imm0_31AsmOperand; 671} 672 673/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32]. 674def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; } 675def imm0_32 : Operand<i32>, ImmLeaf<i32, [{ 676 return Imm >= 0 && Imm < 32; 677}]> { 678 let ParserMatchClass = Imm0_32AsmOperand; 679} 680 681/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63]. 682def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; } 683def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ 684 return Imm >= 0 && Imm < 64; 685}]> { 686 let ParserMatchClass = Imm0_63AsmOperand; 687} 688 689/// imm0_239 predicate - Immediate in the range [0,239]. 690def Imm0_239AsmOperand : ImmAsmOperand { 691 let Name = "Imm0_239"; 692 let DiagnosticType = "ImmRange0_239"; 693} 694def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> { 695 let ParserMatchClass = Imm0_239AsmOperand; 696} 697 698/// imm0_255 predicate - Immediate in the range [0,255]. 699def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; } 700def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 701 let ParserMatchClass = Imm0_255AsmOperand; 702} 703 704/// imm0_65535 - An immediate is in the range [0.65535]. 705def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; } 706def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{ 707 return Imm >= 0 && Imm < 65536; 708}]> { 709 let ParserMatchClass = Imm0_65535AsmOperand; 710} 711 712// imm0_65535_neg - An immediate whose negative value is in the range [0.65535]. 713def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{ 714 return -Imm >= 0 && -Imm < 65536; 715}]>; 716 717// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference 718// a relocatable expression. 719// 720// FIXME: This really needs a Thumb version separate from the ARM version. 721// While the range is the same, and can thus use the same match class, 722// the encoding is different so it should have a different encoder method. 723def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; } 724def imm0_65535_expr : Operand<i32> { 725 let EncoderMethod = "getHiLo16ImmOpValue"; 726 let ParserMatchClass = Imm0_65535ExprAsmOperand; 727} 728 729def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; } 730def imm256_65535_expr : Operand<i32> { 731 let ParserMatchClass = Imm256_65535ExprAsmOperand; 732} 733 734/// imm24b - True if the 32-bit immediate is encodable in 24 bits. 735def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; } 736def imm24b : Operand<i32>, ImmLeaf<i32, [{ 737 return Imm >= 0 && Imm <= 0xffffff; 738}]> { 739 let ParserMatchClass = Imm24bitAsmOperand; 740} 741 742 743/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 744/// e.g., 0xf000ffff 745def BitfieldAsmOperand : AsmOperandClass { 746 let Name = "Bitfield"; 747 let ParserMethod = "parseBitfield"; 748} 749 750def bf_inv_mask_imm : Operand<i32>, 751 PatLeaf<(imm), [{ 752 return ARM::isBitFieldInvertedMask(N->getZExtValue()); 753}] > { 754 let EncoderMethod = "getBitfieldInvertedMaskOpValue"; 755 let PrintMethod = "printBitfieldInvMaskImmOperand"; 756 let DecoderMethod = "DecodeBitfieldMaskOperand"; 757 let ParserMatchClass = BitfieldAsmOperand; 758} 759 760def imm1_32_XFORM: SDNodeXForm<imm, [{ 761 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32); 762}]>; 763def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; } 764def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ 765 uint64_t Imm = N->getZExtValue(); 766 return Imm > 0 && Imm <= 32; 767 }], 768 imm1_32_XFORM> { 769 let PrintMethod = "printImmPlusOneOperand"; 770 let ParserMatchClass = Imm1_32AsmOperand; 771} 772 773def imm1_16_XFORM: SDNodeXForm<imm, [{ 774 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32); 775}]>; 776def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; } 777def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }], 778 imm1_16_XFORM> { 779 let PrintMethod = "printImmPlusOneOperand"; 780 let ParserMatchClass = Imm1_16AsmOperand; 781} 782 783// Define ARM specific addressing modes. 784// addrmode_imm12 := reg +/- imm12 785// 786def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; } 787class AddrMode_Imm12 : Operand<i32>, 788 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> { 789 // 12-bit immediate operand. Note that instructions using this encode 790 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other 791 // immediate values are as normal. 792 793 let EncoderMethod = "getAddrModeImm12OpValue"; 794 let DecoderMethod = "DecodeAddrModeImm12Operand"; 795 let ParserMatchClass = MemImm12OffsetAsmOperand; 796 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 797} 798 799def addrmode_imm12 : AddrMode_Imm12 { 800 let PrintMethod = "printAddrModeImm12Operand<false>"; 801} 802 803def addrmode_imm12_pre : AddrMode_Imm12 { 804 let PrintMethod = "printAddrModeImm12Operand<true>"; 805} 806 807// ldst_so_reg := reg +/- reg shop imm 808// 809def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; } 810def ldst_so_reg : Operand<i32>, 811 ComplexPattern<i32, 3, "SelectLdStSOReg", []> { 812 let EncoderMethod = "getLdStSORegOpValue"; 813 // FIXME: Simplify the printer 814 let PrintMethod = "printAddrMode2Operand"; 815 let DecoderMethod = "DecodeSORegMemOperand"; 816 let ParserMatchClass = MemRegOffsetAsmOperand; 817 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); 818} 819 820// postidx_imm8 := +/- [0,255] 821// 822// 9 bit value: 823// {8} 1 is imm8 is non-negative. 0 otherwise. 824// {7-0} [0,255] imm8 value. 825def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; } 826def postidx_imm8 : Operand<i32> { 827 let PrintMethod = "printPostIdxImm8Operand"; 828 let ParserMatchClass = PostIdxImm8AsmOperand; 829 let MIOperandInfo = (ops i32imm); 830} 831 832// postidx_imm8s4 := +/- [0,1020] 833// 834// 9 bit value: 835// {8} 1 is imm8 is non-negative. 0 otherwise. 836// {7-0} [0,255] imm8 value, scaled by 4. 837def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; } 838def postidx_imm8s4 : Operand<i32> { 839 let PrintMethod = "printPostIdxImm8s4Operand"; 840 let ParserMatchClass = PostIdxImm8s4AsmOperand; 841 let MIOperandInfo = (ops i32imm); 842} 843 844 845// postidx_reg := +/- reg 846// 847def PostIdxRegAsmOperand : AsmOperandClass { 848 let Name = "PostIdxReg"; 849 let ParserMethod = "parsePostIdxReg"; 850} 851def postidx_reg : Operand<i32> { 852 let EncoderMethod = "getPostIdxRegOpValue"; 853 let DecoderMethod = "DecodePostIdxReg"; 854 let PrintMethod = "printPostIdxRegOperand"; 855 let ParserMatchClass = PostIdxRegAsmOperand; 856 let MIOperandInfo = (ops GPRnopc, i32imm); 857} 858 859 860// addrmode2 := reg +/- imm12 861// := reg +/- reg shop imm 862// 863// FIXME: addrmode2 should be refactored the rest of the way to always 864// use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg). 865def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; } 866def addrmode2 : Operand<i32>, 867 ComplexPattern<i32, 3, "SelectAddrMode2", []> { 868 let EncoderMethod = "getAddrMode2OpValue"; 869 let PrintMethod = "printAddrMode2Operand"; 870 let ParserMatchClass = AddrMode2AsmOperand; 871 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 872} 873 874def PostIdxRegShiftedAsmOperand : AsmOperandClass { 875 let Name = "PostIdxRegShifted"; 876 let ParserMethod = "parsePostIdxReg"; 877} 878def am2offset_reg : Operand<i32>, 879 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg", 880 [], [SDNPWantRoot]> { 881 let EncoderMethod = "getAddrMode2OffsetOpValue"; 882 let PrintMethod = "printAddrMode2OffsetOperand"; 883 // When using this for assembly, it's always as a post-index offset. 884 let ParserMatchClass = PostIdxRegShiftedAsmOperand; 885 let MIOperandInfo = (ops GPRnopc, i32imm); 886} 887 888// FIXME: am2offset_imm should only need the immediate, not the GPR. Having 889// the GPR is purely vestigal at this point. 890def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; } 891def am2offset_imm : Operand<i32>, 892 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm", 893 [], [SDNPWantRoot]> { 894 let EncoderMethod = "getAddrMode2OffsetOpValue"; 895 let PrintMethod = "printAddrMode2OffsetOperand"; 896 let ParserMatchClass = AM2OffsetImmAsmOperand; 897 let MIOperandInfo = (ops GPRnopc, i32imm); 898} 899 900 901// addrmode3 := reg +/- reg 902// addrmode3 := reg +/- imm8 903// 904// FIXME: split into imm vs. reg versions. 905def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; } 906class AddrMode3 : Operand<i32>, 907 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 908 let EncoderMethod = "getAddrMode3OpValue"; 909 let ParserMatchClass = AddrMode3AsmOperand; 910 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 911} 912 913def addrmode3 : AddrMode3 914{ 915 let PrintMethod = "printAddrMode3Operand<false>"; 916} 917 918def addrmode3_pre : AddrMode3 919{ 920 let PrintMethod = "printAddrMode3Operand<true>"; 921} 922 923// FIXME: split into imm vs. reg versions. 924// FIXME: parser method to handle +/- register. 925def AM3OffsetAsmOperand : AsmOperandClass { 926 let Name = "AM3Offset"; 927 let ParserMethod = "parseAM3Offset"; 928} 929def am3offset : Operand<i32>, 930 ComplexPattern<i32, 2, "SelectAddrMode3Offset", 931 [], [SDNPWantRoot]> { 932 let EncoderMethod = "getAddrMode3OffsetOpValue"; 933 let PrintMethod = "printAddrMode3OffsetOperand"; 934 let ParserMatchClass = AM3OffsetAsmOperand; 935 let MIOperandInfo = (ops GPR, i32imm); 936} 937 938// ldstm_mode := {ia, ib, da, db} 939// 940def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> { 941 let EncoderMethod = "getLdStmModeOpValue"; 942 let PrintMethod = "printLdStmModeOperand"; 943} 944 945// addrmode5 := reg +/- imm8*4 946// 947def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; } 948class AddrMode5 : Operand<i32>, 949 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 950 let EncoderMethod = "getAddrMode5OpValue"; 951 let DecoderMethod = "DecodeAddrMode5Operand"; 952 let ParserMatchClass = AddrMode5AsmOperand; 953 let MIOperandInfo = (ops GPR:$base, i32imm); 954} 955 956def addrmode5 : AddrMode5 { 957 let PrintMethod = "printAddrMode5Operand<false>"; 958} 959 960def addrmode5_pre : AddrMode5 { 961 let PrintMethod = "printAddrMode5Operand<true>"; 962} 963 964// addrmode6 := reg with optional alignment 965// 966def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; } 967def addrmode6 : Operand<i32>, 968 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 969 let PrintMethod = "printAddrMode6Operand"; 970 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 971 let EncoderMethod = "getAddrMode6AddressOpValue"; 972 let DecoderMethod = "DecodeAddrMode6Operand"; 973 let ParserMatchClass = AddrMode6AsmOperand; 974} 975 976def am6offset : Operand<i32>, 977 ComplexPattern<i32, 1, "SelectAddrMode6Offset", 978 [], [SDNPWantRoot]> { 979 let PrintMethod = "printAddrMode6OffsetOperand"; 980 let MIOperandInfo = (ops GPR); 981 let EncoderMethod = "getAddrMode6OffsetOpValue"; 982 let DecoderMethod = "DecodeGPRRegisterClass"; 983} 984 985// Special version of addrmode6 to handle alignment encoding for VST1/VLD1 986// (single element from one lane) for size 32. 987def addrmode6oneL32 : Operand<i32>, 988 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 989 let PrintMethod = "printAddrMode6Operand"; 990 let MIOperandInfo = (ops GPR:$addr, i32imm); 991 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue"; 992} 993 994// Base class for addrmode6 with specific alignment restrictions. 995class AddrMode6Align : Operand<i32>, 996 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 997 let PrintMethod = "printAddrMode6Operand"; 998 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 999 let EncoderMethod = "getAddrMode6AddressOpValue"; 1000 let DecoderMethod = "DecodeAddrMode6Operand"; 1001} 1002 1003// Special version of addrmode6 to handle no allowed alignment encoding for 1004// VLD/VST instructions and checking the alignment is not specified. 1005def AddrMode6AlignNoneAsmOperand : AsmOperandClass { 1006 let Name = "AlignedMemoryNone"; 1007 let DiagnosticType = "AlignedMemoryRequiresNone"; 1008} 1009def addrmode6alignNone : AddrMode6Align { 1010 // The alignment specifier can only be omitted. 1011 let ParserMatchClass = AddrMode6AlignNoneAsmOperand; 1012} 1013 1014// Special version of addrmode6 to handle 16-bit alignment encoding for 1015// VLD/VST instructions and checking the alignment value. 1016def AddrMode6Align16AsmOperand : AsmOperandClass { 1017 let Name = "AlignedMemory16"; 1018 let DiagnosticType = "AlignedMemoryRequires16"; 1019} 1020def addrmode6align16 : AddrMode6Align { 1021 // The alignment specifier can only be 16 or omitted. 1022 let ParserMatchClass = AddrMode6Align16AsmOperand; 1023} 1024 1025// Special version of addrmode6 to handle 32-bit alignment encoding for 1026// VLD/VST instructions and checking the alignment value. 1027def AddrMode6Align32AsmOperand : AsmOperandClass { 1028 let Name = "AlignedMemory32"; 1029 let DiagnosticType = "AlignedMemoryRequires32"; 1030} 1031def addrmode6align32 : AddrMode6Align { 1032 // The alignment specifier can only be 32 or omitted. 1033 let ParserMatchClass = AddrMode6Align32AsmOperand; 1034} 1035 1036// Special version of addrmode6 to handle 64-bit alignment encoding for 1037// VLD/VST instructions and checking the alignment value. 1038def AddrMode6Align64AsmOperand : AsmOperandClass { 1039 let Name = "AlignedMemory64"; 1040 let DiagnosticType = "AlignedMemoryRequires64"; 1041} 1042def addrmode6align64 : AddrMode6Align { 1043 // The alignment specifier can only be 64 or omitted. 1044 let ParserMatchClass = AddrMode6Align64AsmOperand; 1045} 1046 1047// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1048// for VLD/VST instructions and checking the alignment value. 1049def AddrMode6Align64or128AsmOperand : AsmOperandClass { 1050 let Name = "AlignedMemory64or128"; 1051 let DiagnosticType = "AlignedMemoryRequires64or128"; 1052} 1053def addrmode6align64or128 : AddrMode6Align { 1054 // The alignment specifier can only be 64, 128 or omitted. 1055 let ParserMatchClass = AddrMode6Align64or128AsmOperand; 1056} 1057 1058// Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment 1059// encoding for VLD/VST instructions and checking the alignment value. 1060def AddrMode6Align64or128or256AsmOperand : AsmOperandClass { 1061 let Name = "AlignedMemory64or128or256"; 1062 let DiagnosticType = "AlignedMemoryRequires64or128or256"; 1063} 1064def addrmode6align64or128or256 : AddrMode6Align { 1065 // The alignment specifier can only be 64, 128, 256 or omitted. 1066 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand; 1067} 1068 1069// Special version of addrmode6 to handle alignment encoding for VLD-dup 1070// instructions, specifically VLD4-dup. 1071def addrmode6dup : Operand<i32>, 1072 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1073 let PrintMethod = "printAddrMode6Operand"; 1074 let MIOperandInfo = (ops GPR:$addr, i32imm); 1075 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1076 // FIXME: This is close, but not quite right. The alignment specifier is 1077 // different. 1078 let ParserMatchClass = AddrMode6AsmOperand; 1079} 1080 1081// Base class for addrmode6dup with specific alignment restrictions. 1082class AddrMode6DupAlign : Operand<i32>, 1083 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1084 let PrintMethod = "printAddrMode6Operand"; 1085 let MIOperandInfo = (ops GPR:$addr, i32imm); 1086 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1087} 1088 1089// Special version of addrmode6 to handle no allowed alignment encoding for 1090// VLD-dup instruction and checking the alignment is not specified. 1091def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass { 1092 let Name = "DupAlignedMemoryNone"; 1093 let DiagnosticType = "DupAlignedMemoryRequiresNone"; 1094} 1095def addrmode6dupalignNone : AddrMode6DupAlign { 1096 // The alignment specifier can only be omitted. 1097 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand; 1098} 1099 1100// Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup 1101// instruction and checking the alignment value. 1102def AddrMode6dupAlign16AsmOperand : AsmOperandClass { 1103 let Name = "DupAlignedMemory16"; 1104 let DiagnosticType = "DupAlignedMemoryRequires16"; 1105} 1106def addrmode6dupalign16 : AddrMode6DupAlign { 1107 // The alignment specifier can only be 16 or omitted. 1108 let ParserMatchClass = AddrMode6dupAlign16AsmOperand; 1109} 1110 1111// Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup 1112// instruction and checking the alignment value. 1113def AddrMode6dupAlign32AsmOperand : AsmOperandClass { 1114 let Name = "DupAlignedMemory32"; 1115 let DiagnosticType = "DupAlignedMemoryRequires32"; 1116} 1117def addrmode6dupalign32 : AddrMode6DupAlign { 1118 // The alignment specifier can only be 32 or omitted. 1119 let ParserMatchClass = AddrMode6dupAlign32AsmOperand; 1120} 1121 1122// Special version of addrmode6 to handle 64-bit alignment encoding for VLD 1123// instructions and checking the alignment value. 1124def AddrMode6dupAlign64AsmOperand : AsmOperandClass { 1125 let Name = "DupAlignedMemory64"; 1126 let DiagnosticType = "DupAlignedMemoryRequires64"; 1127} 1128def addrmode6dupalign64 : AddrMode6DupAlign { 1129 // The alignment specifier can only be 64 or omitted. 1130 let ParserMatchClass = AddrMode6dupAlign64AsmOperand; 1131} 1132 1133// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1134// for VLD instructions and checking the alignment value. 1135def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass { 1136 let Name = "DupAlignedMemory64or128"; 1137 let DiagnosticType = "DupAlignedMemoryRequires64or128"; 1138} 1139def addrmode6dupalign64or128 : AddrMode6DupAlign { 1140 // The alignment specifier can only be 64, 128 or omitted. 1141 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand; 1142} 1143 1144// addrmodepc := pc + reg 1145// 1146def addrmodepc : Operand<i32>, 1147 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 1148 let PrintMethod = "printAddrModePCOperand"; 1149 let MIOperandInfo = (ops GPR, i32imm); 1150} 1151 1152// addr_offset_none := reg 1153// 1154def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; } 1155def addr_offset_none : Operand<i32>, 1156 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> { 1157 let PrintMethod = "printAddrMode7Operand"; 1158 let DecoderMethod = "DecodeAddrMode7Operand"; 1159 let ParserMatchClass = MemNoOffsetAsmOperand; 1160 let MIOperandInfo = (ops GPR:$base); 1161} 1162 1163def nohash_imm : Operand<i32> { 1164 let PrintMethod = "printNoHashImmediate"; 1165} 1166 1167def CoprocNumAsmOperand : AsmOperandClass { 1168 let Name = "CoprocNum"; 1169 let ParserMethod = "parseCoprocNumOperand"; 1170} 1171def p_imm : Operand<i32> { 1172 let PrintMethod = "printPImmediate"; 1173 let ParserMatchClass = CoprocNumAsmOperand; 1174 let DecoderMethod = "DecodeCoprocessor"; 1175} 1176 1177def CoprocRegAsmOperand : AsmOperandClass { 1178 let Name = "CoprocReg"; 1179 let ParserMethod = "parseCoprocRegOperand"; 1180} 1181def c_imm : Operand<i32> { 1182 let PrintMethod = "printCImmediate"; 1183 let ParserMatchClass = CoprocRegAsmOperand; 1184} 1185def CoprocOptionAsmOperand : AsmOperandClass { 1186 let Name = "CoprocOption"; 1187 let ParserMethod = "parseCoprocOptionOperand"; 1188} 1189def coproc_option_imm : Operand<i32> { 1190 let PrintMethod = "printCoprocOptionImm"; 1191 let ParserMatchClass = CoprocOptionAsmOperand; 1192} 1193 1194//===----------------------------------------------------------------------===// 1195 1196include "ARMInstrFormats.td" 1197 1198//===----------------------------------------------------------------------===// 1199// Multiclass helpers... 1200// 1201 1202/// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a 1203/// binop that produces a value. 1204let TwoOperandAliasConstraint = "$Rn = $Rd" in 1205multiclass AsI1_bin_irs<bits<4> opcod, string opc, 1206 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1207 PatFrag opnode, bit Commutable = 0> { 1208 // The register-immediate version is re-materializable. This is useful 1209 // in particular for taking the address of a local. 1210 let isReMaterializable = 1 in { 1211 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, 1212 iii, opc, "\t$Rd, $Rn, $imm", 1213 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>, 1214 Sched<[WriteALU, ReadALU]> { 1215 bits<4> Rd; 1216 bits<4> Rn; 1217 bits<12> imm; 1218 let Inst{25} = 1; 1219 let Inst{19-16} = Rn; 1220 let Inst{15-12} = Rd; 1221 let Inst{11-0} = imm; 1222 } 1223 } 1224 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1225 iir, opc, "\t$Rd, $Rn, $Rm", 1226 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 1227 Sched<[WriteALU, ReadALU, ReadALU]> { 1228 bits<4> Rd; 1229 bits<4> Rn; 1230 bits<4> Rm; 1231 let Inst{25} = 0; 1232 let isCommutable = Commutable; 1233 let Inst{19-16} = Rn; 1234 let Inst{15-12} = Rd; 1235 let Inst{11-4} = 0b00000000; 1236 let Inst{3-0} = Rm; 1237 } 1238 1239 def rsi : AsI1<opcod, (outs GPR:$Rd), 1240 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1241 iis, opc, "\t$Rd, $Rn, $shift", 1242 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>, 1243 Sched<[WriteALUsi, ReadALU]> { 1244 bits<4> Rd; 1245 bits<4> Rn; 1246 bits<12> shift; 1247 let Inst{25} = 0; 1248 let Inst{19-16} = Rn; 1249 let Inst{15-12} = Rd; 1250 let Inst{11-5} = shift{11-5}; 1251 let Inst{4} = 0; 1252 let Inst{3-0} = shift{3-0}; 1253 } 1254 1255 def rsr : AsI1<opcod, (outs GPR:$Rd), 1256 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1257 iis, opc, "\t$Rd, $Rn, $shift", 1258 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>, 1259 Sched<[WriteALUsr, ReadALUsr]> { 1260 bits<4> Rd; 1261 bits<4> Rn; 1262 bits<12> shift; 1263 let Inst{25} = 0; 1264 let Inst{19-16} = Rn; 1265 let Inst{15-12} = Rd; 1266 let Inst{11-8} = shift{11-8}; 1267 let Inst{7} = 0; 1268 let Inst{6-5} = shift{6-5}; 1269 let Inst{4} = 1; 1270 let Inst{3-0} = shift{3-0}; 1271 } 1272} 1273 1274/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are 1275/// reversed. The 'rr' form is only defined for the disassembler; for codegen 1276/// it is equivalent to the AsI1_bin_irs counterpart. 1277let TwoOperandAliasConstraint = "$Rn = $Rd" in 1278multiclass AsI1_rbin_irs<bits<4> opcod, string opc, 1279 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1280 PatFrag opnode, bit Commutable = 0> { 1281 // The register-immediate version is re-materializable. This is useful 1282 // in particular for taking the address of a local. 1283 let isReMaterializable = 1 in { 1284 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, 1285 iii, opc, "\t$Rd, $Rn, $imm", 1286 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>, 1287 Sched<[WriteALU, ReadALU]> { 1288 bits<4> Rd; 1289 bits<4> Rn; 1290 bits<12> imm; 1291 let Inst{25} = 1; 1292 let Inst{19-16} = Rn; 1293 let Inst{15-12} = Rd; 1294 let Inst{11-0} = imm; 1295 } 1296 } 1297 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1298 iir, opc, "\t$Rd, $Rn, $Rm", 1299 [/* pattern left blank */]>, 1300 Sched<[WriteALU, ReadALU, ReadALU]> { 1301 bits<4> Rd; 1302 bits<4> Rn; 1303 bits<4> Rm; 1304 let Inst{11-4} = 0b00000000; 1305 let Inst{25} = 0; 1306 let Inst{3-0} = Rm; 1307 let Inst{15-12} = Rd; 1308 let Inst{19-16} = Rn; 1309 } 1310 1311 def rsi : AsI1<opcod, (outs GPR:$Rd), 1312 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1313 iis, opc, "\t$Rd, $Rn, $shift", 1314 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>, 1315 Sched<[WriteALUsi, ReadALU]> { 1316 bits<4> Rd; 1317 bits<4> Rn; 1318 bits<12> shift; 1319 let Inst{25} = 0; 1320 let Inst{19-16} = Rn; 1321 let Inst{15-12} = Rd; 1322 let Inst{11-5} = shift{11-5}; 1323 let Inst{4} = 0; 1324 let Inst{3-0} = shift{3-0}; 1325 } 1326 1327 def rsr : AsI1<opcod, (outs GPR:$Rd), 1328 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1329 iis, opc, "\t$Rd, $Rn, $shift", 1330 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>, 1331 Sched<[WriteALUsr, ReadALUsr]> { 1332 bits<4> Rd; 1333 bits<4> Rn; 1334 bits<12> shift; 1335 let Inst{25} = 0; 1336 let Inst{19-16} = Rn; 1337 let Inst{15-12} = Rd; 1338 let Inst{11-8} = shift{11-8}; 1339 let Inst{7} = 0; 1340 let Inst{6-5} = shift{6-5}; 1341 let Inst{4} = 1; 1342 let Inst{3-0} = shift{3-0}; 1343 } 1344} 1345 1346/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default. 1347/// 1348/// These opcodes will be converted to the real non-S opcodes by 1349/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand. 1350let hasPostISelHook = 1, Defs = [CPSR] in { 1351multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 1352 InstrItinClass iis, PatFrag opnode, 1353 bit Commutable = 0> { 1354 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p), 1355 4, iii, 1356 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>, 1357 Sched<[WriteALU, ReadALU]>; 1358 1359 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p), 1360 4, iir, 1361 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>, 1362 Sched<[WriteALU, ReadALU, ReadALU]> { 1363 let isCommutable = Commutable; 1364 } 1365 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1366 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1367 4, iis, 1368 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1369 so_reg_imm:$shift))]>, 1370 Sched<[WriteALUsi, ReadALU]>; 1371 1372 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1373 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1374 4, iis, 1375 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1376 so_reg_reg:$shift))]>, 1377 Sched<[WriteALUSsr, ReadALUsr]>; 1378} 1379} 1380 1381/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG 1382/// operands are reversed. 1383let hasPostISelHook = 1, Defs = [CPSR] in { 1384multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir, 1385 InstrItinClass iis, PatFrag opnode, 1386 bit Commutable = 0> { 1387 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p), 1388 4, iii, 1389 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>, 1390 Sched<[WriteALU, ReadALU]>; 1391 1392 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1393 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1394 4, iis, 1395 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, 1396 GPR:$Rn))]>, 1397 Sched<[WriteALUsi, ReadALU]>; 1398 1399 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1400 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1401 4, iis, 1402 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, 1403 GPR:$Rn))]>, 1404 Sched<[WriteALUSsr, ReadALUsr]>; 1405} 1406} 1407 1408/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 1409/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 1410/// a explicit result, only implicitly set CPSR. 1411let isCompare = 1, Defs = [CPSR] in { 1412multiclass AI1_cmp_irs<bits<4> opcod, string opc, 1413 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1414 PatFrag opnode, bit Commutable = 0> { 1415 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii, 1416 opc, "\t$Rn, $imm", 1417 [(opnode GPR:$Rn, so_imm:$imm)]>, 1418 Sched<[WriteCMP, ReadALU]> { 1419 bits<4> Rn; 1420 bits<12> imm; 1421 let Inst{25} = 1; 1422 let Inst{20} = 1; 1423 let Inst{19-16} = Rn; 1424 let Inst{15-12} = 0b0000; 1425 let Inst{11-0} = imm; 1426 1427 let Unpredictable{15-12} = 0b1111; 1428 } 1429 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, 1430 opc, "\t$Rn, $Rm", 1431 [(opnode GPR:$Rn, GPR:$Rm)]>, 1432 Sched<[WriteCMP, ReadALU, ReadALU]> { 1433 bits<4> Rn; 1434 bits<4> Rm; 1435 let isCommutable = Commutable; 1436 let Inst{25} = 0; 1437 let Inst{20} = 1; 1438 let Inst{19-16} = Rn; 1439 let Inst{15-12} = 0b0000; 1440 let Inst{11-4} = 0b00000000; 1441 let Inst{3-0} = Rm; 1442 1443 let Unpredictable{15-12} = 0b1111; 1444 } 1445 def rsi : AI1<opcod, (outs), 1446 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis, 1447 opc, "\t$Rn, $shift", 1448 [(opnode GPR:$Rn, so_reg_imm:$shift)]>, 1449 Sched<[WriteCMPsi, ReadALU]> { 1450 bits<4> Rn; 1451 bits<12> shift; 1452 let Inst{25} = 0; 1453 let Inst{20} = 1; 1454 let Inst{19-16} = Rn; 1455 let Inst{15-12} = 0b0000; 1456 let Inst{11-5} = shift{11-5}; 1457 let Inst{4} = 0; 1458 let Inst{3-0} = shift{3-0}; 1459 1460 let Unpredictable{15-12} = 0b1111; 1461 } 1462 def rsr : AI1<opcod, (outs), 1463 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, 1464 opc, "\t$Rn, $shift", 1465 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>, 1466 Sched<[WriteCMPsr, ReadALU]> { 1467 bits<4> Rn; 1468 bits<12> shift; 1469 let Inst{25} = 0; 1470 let Inst{20} = 1; 1471 let Inst{19-16} = Rn; 1472 let Inst{15-12} = 0b0000; 1473 let Inst{11-8} = shift{11-8}; 1474 let Inst{7} = 0; 1475 let Inst{6-5} = shift{6-5}; 1476 let Inst{4} = 1; 1477 let Inst{3-0} = shift{3-0}; 1478 1479 let Unpredictable{15-12} = 0b1111; 1480 } 1481 1482} 1483} 1484 1485/// AI_ext_rrot - A unary operation with two forms: one whose operand is a 1486/// register and one whose operand is a register rotated by 8/16/24. 1487/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 1488class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> 1489 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1490 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1491 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1492 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1493 bits<4> Rd; 1494 bits<4> Rm; 1495 bits<2> rot; 1496 let Inst{19-16} = 0b1111; 1497 let Inst{15-12} = Rd; 1498 let Inst{11-10} = rot; 1499 let Inst{3-0} = Rm; 1500} 1501 1502class AI_ext_rrot_np<bits<8> opcod, string opc> 1503 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1504 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>, 1505 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1506 bits<2> rot; 1507 let Inst{19-16} = 0b1111; 1508 let Inst{11-10} = rot; 1509 } 1510 1511/// AI_exta_rrot - A binary operation with two forms: one whose operand is a 1512/// register and one whose operand is a register rotated by 8/16/24. 1513class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> 1514 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1515 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", 1516 [(set GPRnopc:$Rd, (opnode GPR:$Rn, 1517 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1518 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1519 bits<4> Rd; 1520 bits<4> Rm; 1521 bits<4> Rn; 1522 bits<2> rot; 1523 let Inst{19-16} = Rn; 1524 let Inst{15-12} = Rd; 1525 let Inst{11-10} = rot; 1526 let Inst{9-4} = 0b000111; 1527 let Inst{3-0} = Rm; 1528} 1529 1530class AI_exta_rrot_np<bits<8> opcod, string opc> 1531 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1532 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1533 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1534 bits<4> Rn; 1535 bits<2> rot; 1536 let Inst{19-16} = Rn; 1537 let Inst{11-10} = rot; 1538} 1539 1540/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 1541let TwoOperandAliasConstraint = "$Rn = $Rd" in 1542multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, 1543 bit Commutable = 0> { 1544 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1545 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), 1546 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1547 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>, 1548 Requires<[IsARM]>, 1549 Sched<[WriteALU, ReadALU]> { 1550 bits<4> Rd; 1551 bits<4> Rn; 1552 bits<12> imm; 1553 let Inst{25} = 1; 1554 let Inst{15-12} = Rd; 1555 let Inst{19-16} = Rn; 1556 let Inst{11-0} = imm; 1557 } 1558 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1559 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1560 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, 1561 Requires<[IsARM]>, 1562 Sched<[WriteALU, ReadALU, ReadALU]> { 1563 bits<4> Rd; 1564 bits<4> Rn; 1565 bits<4> Rm; 1566 let Inst{11-4} = 0b00000000; 1567 let Inst{25} = 0; 1568 let isCommutable = Commutable; 1569 let Inst{3-0} = Rm; 1570 let Inst{15-12} = Rd; 1571 let Inst{19-16} = Rn; 1572 } 1573 def rsi : AsI1<opcod, (outs GPR:$Rd), 1574 (ins GPR:$Rn, so_reg_imm:$shift), 1575 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1576 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, 1577 Requires<[IsARM]>, 1578 Sched<[WriteALUsi, ReadALU]> { 1579 bits<4> Rd; 1580 bits<4> Rn; 1581 bits<12> shift; 1582 let Inst{25} = 0; 1583 let Inst{19-16} = Rn; 1584 let Inst{15-12} = Rd; 1585 let Inst{11-5} = shift{11-5}; 1586 let Inst{4} = 0; 1587 let Inst{3-0} = shift{3-0}; 1588 } 1589 def rsr : AsI1<opcod, (outs GPRnopc:$Rd), 1590 (ins GPRnopc:$Rn, so_reg_reg:$shift), 1591 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1592 [(set GPRnopc:$Rd, CPSR, 1593 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, 1594 Requires<[IsARM]>, 1595 Sched<[WriteALUsr, ReadALUsr]> { 1596 bits<4> Rd; 1597 bits<4> Rn; 1598 bits<12> shift; 1599 let Inst{25} = 0; 1600 let Inst{19-16} = Rn; 1601 let Inst{15-12} = Rd; 1602 let Inst{11-8} = shift{11-8}; 1603 let Inst{7} = 0; 1604 let Inst{6-5} = shift{6-5}; 1605 let Inst{4} = 1; 1606 let Inst{3-0} = shift{3-0}; 1607 } 1608 } 1609} 1610 1611/// AI1_rsc_irs - Define instructions and patterns for rsc 1612let TwoOperandAliasConstraint = "$Rn = $Rd" in 1613multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> { 1614 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1615 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), 1616 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1617 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>, 1618 Requires<[IsARM]>, 1619 Sched<[WriteALU, ReadALU]> { 1620 bits<4> Rd; 1621 bits<4> Rn; 1622 bits<12> imm; 1623 let Inst{25} = 1; 1624 let Inst{15-12} = Rd; 1625 let Inst{19-16} = Rn; 1626 let Inst{11-0} = imm; 1627 } 1628 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1629 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1630 [/* pattern left blank */]>, 1631 Sched<[WriteALU, ReadALU, ReadALU]> { 1632 bits<4> Rd; 1633 bits<4> Rn; 1634 bits<4> Rm; 1635 let Inst{11-4} = 0b00000000; 1636 let Inst{25} = 0; 1637 let Inst{3-0} = Rm; 1638 let Inst{15-12} = Rd; 1639 let Inst{19-16} = Rn; 1640 } 1641 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), 1642 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1643 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>, 1644 Requires<[IsARM]>, 1645 Sched<[WriteALUsi, ReadALU]> { 1646 bits<4> Rd; 1647 bits<4> Rn; 1648 bits<12> shift; 1649 let Inst{25} = 0; 1650 let Inst{19-16} = Rn; 1651 let Inst{15-12} = Rd; 1652 let Inst{11-5} = shift{11-5}; 1653 let Inst{4} = 0; 1654 let Inst{3-0} = shift{3-0}; 1655 } 1656 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), 1657 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1658 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>, 1659 Requires<[IsARM]>, 1660 Sched<[WriteALUsr, ReadALUsr]> { 1661 bits<4> Rd; 1662 bits<4> Rn; 1663 bits<12> shift; 1664 let Inst{25} = 0; 1665 let Inst{19-16} = Rn; 1666 let Inst{15-12} = Rd; 1667 let Inst{11-8} = shift{11-8}; 1668 let Inst{7} = 0; 1669 let Inst{6-5} = shift{6-5}; 1670 let Inst{4} = 1; 1671 let Inst{3-0} = shift{3-0}; 1672 } 1673 } 1674} 1675 1676let canFoldAsLoad = 1, isReMaterializable = 1 in { 1677multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii, 1678 InstrItinClass iir, PatFrag opnode> { 1679 // Note: We use the complex addrmode_imm12 rather than just an input 1680 // GPR and a constrained immediate so that we can use this to match 1681 // frame index references and avoid matching constant pool references. 1682 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1683 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1684 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { 1685 bits<4> Rt; 1686 bits<17> addr; 1687 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1688 let Inst{19-16} = addr{16-13}; // Rn 1689 let Inst{15-12} = Rt; 1690 let Inst{11-0} = addr{11-0}; // imm12 1691 } 1692 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift), 1693 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1694 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { 1695 bits<4> Rt; 1696 bits<17> shift; 1697 let shift{4} = 0; // Inst{4} = 0 1698 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1699 let Inst{19-16} = shift{16-13}; // Rn 1700 let Inst{15-12} = Rt; 1701 let Inst{11-0} = shift{11-0}; 1702 } 1703} 1704} 1705 1706let canFoldAsLoad = 1, isReMaterializable = 1 in { 1707multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii, 1708 InstrItinClass iir, PatFrag opnode> { 1709 // Note: We use the complex addrmode_imm12 rather than just an input 1710 // GPR and a constrained immediate so that we can use this to match 1711 // frame index references and avoid matching constant pool references. 1712 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), 1713 (ins addrmode_imm12:$addr), 1714 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1715 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> { 1716 bits<4> Rt; 1717 bits<17> addr; 1718 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1719 let Inst{19-16} = addr{16-13}; // Rn 1720 let Inst{15-12} = Rt; 1721 let Inst{11-0} = addr{11-0}; // imm12 1722 } 1723 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), 1724 (ins ldst_so_reg:$shift), 1725 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1726 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> { 1727 bits<4> Rt; 1728 bits<17> shift; 1729 let shift{4} = 0; // Inst{4} = 0 1730 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1731 let Inst{19-16} = shift{16-13}; // Rn 1732 let Inst{15-12} = Rt; 1733 let Inst{11-0} = shift{11-0}; 1734 } 1735} 1736} 1737 1738 1739multiclass AI_str1<bit isByte, string opc, InstrItinClass iii, 1740 InstrItinClass iir, PatFrag opnode> { 1741 // Note: We use the complex addrmode_imm12 rather than just an input 1742 // GPR and a constrained immediate so that we can use this to match 1743 // frame index references and avoid matching constant pool references. 1744 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1745 (ins GPR:$Rt, addrmode_imm12:$addr), 1746 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1747 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> { 1748 bits<4> Rt; 1749 bits<17> addr; 1750 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1751 let Inst{19-16} = addr{16-13}; // Rn 1752 let Inst{15-12} = Rt; 1753 let Inst{11-0} = addr{11-0}; // imm12 1754 } 1755 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift), 1756 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1757 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { 1758 bits<4> Rt; 1759 bits<17> shift; 1760 let shift{4} = 0; // Inst{4} = 0 1761 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1762 let Inst{19-16} = shift{16-13}; // Rn 1763 let Inst{15-12} = Rt; 1764 let Inst{11-0} = shift{11-0}; 1765 } 1766} 1767 1768multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii, 1769 InstrItinClass iir, PatFrag opnode> { 1770 // Note: We use the complex addrmode_imm12 rather than just an input 1771 // GPR and a constrained immediate so that we can use this to match 1772 // frame index references and avoid matching constant pool references. 1773 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1774 (ins GPRnopc:$Rt, addrmode_imm12:$addr), 1775 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1776 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> { 1777 bits<4> Rt; 1778 bits<17> addr; 1779 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1780 let Inst{19-16} = addr{16-13}; // Rn 1781 let Inst{15-12} = Rt; 1782 let Inst{11-0} = addr{11-0}; // imm12 1783 } 1784 def rs : AI2ldst<0b011, 0, isByte, (outs), 1785 (ins GPRnopc:$Rt, ldst_so_reg:$shift), 1786 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1787 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> { 1788 bits<4> Rt; 1789 bits<17> shift; 1790 let shift{4} = 0; // Inst{4} = 0 1791 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1792 let Inst{19-16} = shift{16-13}; // Rn 1793 let Inst{15-12} = Rt; 1794 let Inst{11-0} = shift{11-0}; 1795 } 1796} 1797 1798 1799//===----------------------------------------------------------------------===// 1800// Instructions 1801//===----------------------------------------------------------------------===// 1802 1803//===----------------------------------------------------------------------===// 1804// Miscellaneous Instructions. 1805// 1806 1807/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 1808/// the function. The first operand is the ID# for this instruction, the second 1809/// is the index into the MachineConstantPool that this is, the third is the 1810/// size in bytes of this constant pool entry. 1811let neverHasSideEffects = 1, isNotDuplicable = 1 in 1812def CONSTPOOL_ENTRY : 1813PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1814 i32imm:$size), NoItinerary, []>; 1815 1816// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 1817// from removing one half of the matched pairs. That breaks PEI, which assumes 1818// these will always be in pairs, and asserts if it finds otherwise. Better way? 1819let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 1820def ADJCALLSTACKUP : 1821PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, 1822 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 1823 1824def ADJCALLSTACKDOWN : 1825PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary, 1826 [(ARMcallseq_start timm:$amt)]>; 1827} 1828 1829def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary, 1830 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>, 1831 Requires<[IsARM, HasV6]> { 1832 bits<8> imm; 1833 let Inst{27-8} = 0b00110010000011110000; 1834 let Inst{7-0} = imm; 1835} 1836 1837def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1838def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1839def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1840def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1841def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1842def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>; 1843 1844def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", 1845 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> { 1846 bits<4> Rd; 1847 bits<4> Rn; 1848 bits<4> Rm; 1849 let Inst{3-0} = Rm; 1850 let Inst{15-12} = Rd; 1851 let Inst{19-16} = Rn; 1852 let Inst{27-20} = 0b01101000; 1853 let Inst{7-4} = 0b1011; 1854 let Inst{11-8} = 0b1111; 1855 let Unpredictable{11-8} = 0b1111; 1856} 1857 1858// The 16-bit operand $val can be used by a debugger to store more information 1859// about the breakpoint. 1860def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 1861 "bkpt", "\t$val", []>, Requires<[IsARM]> { 1862 bits<16> val; 1863 let Inst{3-0} = val{3-0}; 1864 let Inst{19-8} = val{15-4}; 1865 let Inst{27-20} = 0b00010010; 1866 let Inst{31-28} = 0xe; // AL 1867 let Inst{7-4} = 0b0111; 1868} 1869// default immediate for breakpoint mnemonic 1870def : InstAlias<"bkpt", (BKPT 0)>, Requires<[IsARM]>; 1871 1872def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 1873 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> { 1874 bits<16> val; 1875 let Inst{3-0} = val{3-0}; 1876 let Inst{19-8} = val{15-4}; 1877 let Inst{27-20} = 0b00010000; 1878 let Inst{31-28} = 0xe; // AL 1879 let Inst{7-4} = 0b0111; 1880} 1881 1882// Change Processor State 1883// FIXME: We should use InstAlias to handle the optional operands. 1884class CPS<dag iops, string asm_ops> 1885 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops), 1886 []>, Requires<[IsARM]> { 1887 bits<2> imod; 1888 bits<3> iflags; 1889 bits<5> mode; 1890 bit M; 1891 1892 let Inst{31-28} = 0b1111; 1893 let Inst{27-20} = 0b00010000; 1894 let Inst{19-18} = imod; 1895 let Inst{17} = M; // Enabled if mode is set; 1896 let Inst{16-9} = 0b00000000; 1897 let Inst{8-6} = iflags; 1898 let Inst{5} = 0; 1899 let Inst{4-0} = mode; 1900} 1901 1902let DecoderMethod = "DecodeCPSInstruction" in { 1903let M = 1 in 1904 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), 1905 "$imod\t$iflags, $mode">; 1906let mode = 0, M = 0 in 1907 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; 1908 1909let imod = 0, iflags = 0, M = 1 in 1910 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; 1911} 1912 1913// Preload signals the memory system of possible future data/instruction access. 1914multiclass APreLoad<bits<1> read, bits<1> data, string opc> { 1915 1916 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm, 1917 IIC_Preload, !strconcat(opc, "\t$addr"), 1918 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>, 1919 Sched<[WritePreLd]> { 1920 bits<4> Rt; 1921 bits<17> addr; 1922 let Inst{31-26} = 0b111101; 1923 let Inst{25} = 0; // 0 for immediate form 1924 let Inst{24} = data; 1925 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1926 let Inst{22} = read; 1927 let Inst{21-20} = 0b01; 1928 let Inst{19-16} = addr{16-13}; // Rn 1929 let Inst{15-12} = 0b1111; 1930 let Inst{11-0} = addr{11-0}; // imm12 1931 } 1932 1933 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, 1934 !strconcat(opc, "\t$shift"), 1935 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>, 1936 Sched<[WritePreLd]> { 1937 bits<17> shift; 1938 let Inst{31-26} = 0b111101; 1939 let Inst{25} = 1; // 1 for register form 1940 let Inst{24} = data; 1941 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1942 let Inst{22} = read; 1943 let Inst{21-20} = 0b01; 1944 let Inst{19-16} = shift{16-13}; // Rn 1945 let Inst{15-12} = 0b1111; 1946 let Inst{11-0} = shift{11-0}; 1947 let Inst{4} = 0; 1948 } 1949} 1950 1951defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; 1952defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; 1953defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; 1954 1955def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, 1956 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> { 1957 bits<1> end; 1958 let Inst{31-10} = 0b1111000100000001000000; 1959 let Inst{9} = end; 1960 let Inst{8-0} = 0; 1961} 1962 1963def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 1964 []>, Requires<[IsARM, HasV7]> { 1965 bits<4> opt; 1966 let Inst{27-4} = 0b001100100000111100001111; 1967 let Inst{3-0} = opt; 1968} 1969 1970// A8.8.247 UDF - Undefined (Encoding A1) 1971def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary, 1972 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> { 1973 bits<16> imm16; 1974 let Inst{31-28} = 0b1110; // AL 1975 let Inst{27-25} = 0b011; 1976 let Inst{24-20} = 0b11111; 1977 let Inst{19-8} = imm16{15-4}; 1978 let Inst{7-4} = 0b1111; 1979 let Inst{3-0} = imm16{3-0}; 1980} 1981 1982/* 1983 * A5.4 Permanently UNDEFINED instructions. 1984 * 1985 * For most targets use UDF #65006, for which the OS will generate SIGTRAP. 1986 * Other UDF encodings generate SIGILL. 1987 * 1988 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb. 1989 * Encoding A1: 1990 * 1110 0111 1111 iiii iiii iiii 1111 iiii 1991 * Encoding T1: 1992 * 1101 1110 iiii iiii 1993 * It uses the following encoding: 1994 * 1110 0111 1111 1110 1101 1110 1111 0000 1995 * - In ARM: UDF #60896; 1996 * - In Thumb: UDF #254 followed by a branch-to-self. 1997 */ 1998let isBarrier = 1, isTerminator = 1 in 1999def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary, 2000 "trap", [(trap)]>, 2001 Requires<[IsARM,UseNaClTrap]> { 2002 let Inst = 0xe7fedef0; 2003} 2004let isBarrier = 1, isTerminator = 1 in 2005def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 2006 "trap", [(trap)]>, 2007 Requires<[IsARM,DontUseNaClTrap]> { 2008 let Inst = 0xe7ffdefe; 2009} 2010 2011// Address computation and loads and stores in PIC mode. 2012let isNotDuplicable = 1 in { 2013def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 2014 4, IIC_iALUr, 2015 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>, 2016 Sched<[WriteALU, ReadALU]>; 2017 2018let AddedComplexity = 10 in { 2019def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 2020 4, IIC_iLoad_r, 2021 [(set GPR:$dst, (load addrmodepc:$addr))]>; 2022 2023def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2024 4, IIC_iLoad_bh_r, 2025 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; 2026 2027def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2028 4, IIC_iLoad_bh_r, 2029 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; 2030 2031def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2032 4, IIC_iLoad_bh_r, 2033 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; 2034 2035def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2036 4, IIC_iLoad_bh_r, 2037 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; 2038} 2039let AddedComplexity = 10 in { 2040def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2041 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; 2042 2043def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2044 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, 2045 addrmodepc:$addr)]>; 2046 2047def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2048 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 2049} 2050} // isNotDuplicable = 1 2051 2052 2053// LEApcrel - Load a pc-relative address into a register without offending the 2054// assembler. 2055let neverHasSideEffects = 1, isReMaterializable = 1 in 2056// The 'adr' mnemonic encodes differently if the label is before or after 2057// the instruction. The {24-21} opcode bits are set by the fixup, as we don't 2058// know until then which form of the instruction will be used. 2059def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), 2060 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>, 2061 Sched<[WriteALU, ReadALU]> { 2062 bits<4> Rd; 2063 bits<14> label; 2064 let Inst{27-25} = 0b001; 2065 let Inst{24} = 0; 2066 let Inst{23-22} = label{13-12}; 2067 let Inst{21} = 0; 2068 let Inst{20} = 0; 2069 let Inst{19-16} = 0b1111; 2070 let Inst{15-12} = Rd; 2071 let Inst{11-0} = label{11-0}; 2072} 2073 2074let hasSideEffects = 1 in { 2075def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 2076 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2077 2078def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), 2079 (ins i32imm:$label, nohash_imm:$id, pred:$p), 2080 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2081} 2082 2083//===----------------------------------------------------------------------===// 2084// Control Flow Instructions. 2085// 2086 2087let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 2088 // ARMV4T and above 2089 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2090 "bx", "\tlr", [(ARMretflag)]>, 2091 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2092 let Inst{27-0} = 0b0001001011111111111100011110; 2093 } 2094 2095 // ARMV4 only 2096 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2097 "mov", "\tpc, lr", [(ARMretflag)]>, 2098 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> { 2099 let Inst{27-0} = 0b0001101000001111000000001110; 2100 } 2101 2102 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets 2103 // the user-space one). 2104 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p), 2105 4, IIC_Br, 2106 [(ARMintretflag imm:$offset)]>; 2107} 2108 2109// Indirect branches 2110let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 2111 // ARMV4T and above 2112 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 2113 [(brind GPR:$dst)]>, 2114 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2115 bits<4> dst; 2116 let Inst{31-4} = 0b1110000100101111111111110001; 2117 let Inst{3-0} = dst; 2118 } 2119 2120 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, 2121 "bx", "\t$dst", [/* pattern left blank */]>, 2122 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2123 bits<4> dst; 2124 let Inst{27-4} = 0b000100101111111111110001; 2125 let Inst{3-0} = dst; 2126 } 2127} 2128 2129// SP is marked as a use to prevent stack-pointer assignments that appear 2130// immediately before calls from potentially appearing dead. 2131let isCall = 1, 2132 // FIXME: Do we really need a non-predicated version? If so, it should 2133 // at least be a pseudo instruction expanding to the predicated version 2134 // at MC lowering time. 2135 Defs = [LR], Uses = [SP] in { 2136 def BL : ABXI<0b1011, (outs), (ins bl_target:$func), 2137 IIC_Br, "bl\t$func", 2138 [(ARMcall tglobaladdr:$func)]>, 2139 Requires<[IsARM]>, Sched<[WriteBrL]> { 2140 let Inst{31-28} = 0b1110; 2141 bits<24> func; 2142 let Inst{23-0} = func; 2143 let DecoderMethod = "DecodeBranchImmInstruction"; 2144 } 2145 2146 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func), 2147 IIC_Br, "bl", "\t$func", 2148 [(ARMcall_pred tglobaladdr:$func)]>, 2149 Requires<[IsARM]>, Sched<[WriteBrL]> { 2150 bits<24> func; 2151 let Inst{23-0} = func; 2152 let DecoderMethod = "DecodeBranchImmInstruction"; 2153 } 2154 2155 // ARMv5T and above 2156 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, 2157 IIC_Br, "blx\t$func", 2158 [(ARMcall GPR:$func)]>, 2159 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2160 bits<4> func; 2161 let Inst{31-4} = 0b1110000100101111111111110011; 2162 let Inst{3-0} = func; 2163 } 2164 2165 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm, 2166 IIC_Br, "blx", "\t$func", 2167 [(ARMcall_pred GPR:$func)]>, 2168 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2169 bits<4> func; 2170 let Inst{27-4} = 0b000100101111111111110011; 2171 let Inst{3-0} = func; 2172 } 2173 2174 // ARMv4T 2175 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 2176 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2177 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2178 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>; 2179 2180 // ARMv4 2181 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2182 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2183 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 2184 2185 // mov lr, pc; b if callee is marked noreturn to avoid confusing the 2186 // return stack predictor. 2187 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func), 2188 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, 2189 Requires<[IsARM]>, Sched<[WriteBr]>; 2190} 2191 2192let isBranch = 1, isTerminator = 1 in { 2193 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 2194 // a two-value operand where a dag node expects two operands. :( 2195 def Bcc : ABI<0b1010, (outs), (ins br_target:$target), 2196 IIC_Br, "b", "\t$target", 2197 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>, 2198 Sched<[WriteBr]> { 2199 bits<24> target; 2200 let Inst{23-0} = target; 2201 let DecoderMethod = "DecodeBranchImmInstruction"; 2202 } 2203 2204 let isBarrier = 1 in { 2205 // B is "predicable" since it's just a Bcc with an 'always' condition. 2206 let isPredicable = 1 in 2207 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly 2208 // should be sufficient. 2209 // FIXME: Is B really a Barrier? That doesn't seem right. 2210 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br, 2211 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>, 2212 Sched<[WriteBr]>; 2213 2214 let isNotDuplicable = 1, isIndirectBranch = 1 in { 2215 def BR_JTr : ARMPseudoInst<(outs), 2216 (ins GPR:$target, i32imm:$jt, i32imm:$id), 2217 0, IIC_Br, 2218 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>, 2219 Sched<[WriteBr]>; 2220 // FIXME: This shouldn't use the generic "addrmode2," but rather be split 2221 // into i12 and rs suffixed versions. 2222 def BR_JTm : ARMPseudoInst<(outs), 2223 (ins addrmode2:$target, i32imm:$jt, i32imm:$id), 2224 0, IIC_Br, 2225 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, 2226 imm:$id)]>, Sched<[WriteBrTbl]>; 2227 def BR_JTadd : ARMPseudoInst<(outs), 2228 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id), 2229 0, IIC_Br, 2230 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, 2231 imm:$id)]>, Sched<[WriteBrTbl]>; 2232 } // isNotDuplicable = 1, isIndirectBranch = 1 2233 } // isBarrier = 1 2234 2235} 2236 2237// BLX (immediate) 2238def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary, 2239 "blx\t$target", []>, 2240 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2241 let Inst{31-25} = 0b1111101; 2242 bits<25> target; 2243 let Inst{23-0} = target{24-1}; 2244 let Inst{24} = target{0}; 2245} 2246 2247// Branch and Exchange Jazelle 2248def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2249 [/* pattern left blank */]>, Sched<[WriteBr]> { 2250 bits<4> func; 2251 let Inst{23-20} = 0b0010; 2252 let Inst{19-8} = 0xfff; 2253 let Inst{7-4} = 0b0010; 2254 let Inst{3-0} = func; 2255} 2256 2257// Tail calls. 2258 2259let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 2260 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>, 2261 Sched<[WriteBr]>; 2262 2263 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>, 2264 Sched<[WriteBr]>; 2265 2266 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst), 2267 4, IIC_Br, [], 2268 (Bcc br_target:$dst, (ops 14, zero_reg))>, 2269 Requires<[IsARM]>, Sched<[WriteBr]>; 2270 2271 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst), 2272 4, IIC_Br, [], 2273 (BX GPR:$dst)>, Sched<[WriteBr]>, 2274 Requires<[IsARM]>; 2275} 2276 2277// Secure Monitor Call is a system instruction. 2278def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 2279 []>, Requires<[IsARM, HasTrustZone]> { 2280 bits<4> opt; 2281 let Inst{23-4} = 0b01100000000000000111; 2282 let Inst{3-0} = opt; 2283} 2284 2285// Supervisor Call (Software Interrupt) 2286let isCall = 1, Uses = [SP] in { 2287def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>, 2288 Sched<[WriteBr]> { 2289 bits<24> svc; 2290 let Inst{23-0} = svc; 2291} 2292} 2293 2294// Store Return State 2295class SRSI<bit wb, string asm> 2296 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm, 2297 NoItinerary, asm, "", []> { 2298 bits<5> mode; 2299 let Inst{31-28} = 0b1111; 2300 let Inst{27-25} = 0b100; 2301 let Inst{22} = 1; 2302 let Inst{21} = wb; 2303 let Inst{20} = 0; 2304 let Inst{19-16} = 0b1101; // SP 2305 let Inst{15-5} = 0b00000101000; 2306 let Inst{4-0} = mode; 2307} 2308 2309def SRSDA : SRSI<0, "srsda\tsp, $mode"> { 2310 let Inst{24-23} = 0; 2311} 2312def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> { 2313 let Inst{24-23} = 0; 2314} 2315def SRSDB : SRSI<0, "srsdb\tsp, $mode"> { 2316 let Inst{24-23} = 0b10; 2317} 2318def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> { 2319 let Inst{24-23} = 0b10; 2320} 2321def SRSIA : SRSI<0, "srsia\tsp, $mode"> { 2322 let Inst{24-23} = 0b01; 2323} 2324def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> { 2325 let Inst{24-23} = 0b01; 2326} 2327def SRSIB : SRSI<0, "srsib\tsp, $mode"> { 2328 let Inst{24-23} = 0b11; 2329} 2330def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { 2331 let Inst{24-23} = 0b11; 2332} 2333 2334def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>; 2335def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>; 2336 2337def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>; 2338def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>; 2339 2340def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>; 2341def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>; 2342 2343def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>; 2344def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>; 2345 2346// Return From Exception 2347class RFEI<bit wb, string asm> 2348 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, 2349 NoItinerary, asm, "", []> { 2350 bits<4> Rn; 2351 let Inst{31-28} = 0b1111; 2352 let Inst{27-25} = 0b100; 2353 let Inst{22} = 0; 2354 let Inst{21} = wb; 2355 let Inst{20} = 1; 2356 let Inst{19-16} = Rn; 2357 let Inst{15-0} = 0xa00; 2358} 2359 2360def RFEDA : RFEI<0, "rfeda\t$Rn"> { 2361 let Inst{24-23} = 0; 2362} 2363def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> { 2364 let Inst{24-23} = 0; 2365} 2366def RFEDB : RFEI<0, "rfedb\t$Rn"> { 2367 let Inst{24-23} = 0b10; 2368} 2369def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> { 2370 let Inst{24-23} = 0b10; 2371} 2372def RFEIA : RFEI<0, "rfeia\t$Rn"> { 2373 let Inst{24-23} = 0b01; 2374} 2375def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> { 2376 let Inst{24-23} = 0b01; 2377} 2378def RFEIB : RFEI<0, "rfeib\t$Rn"> { 2379 let Inst{24-23} = 0b11; 2380} 2381def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> { 2382 let Inst{24-23} = 0b11; 2383} 2384 2385//===----------------------------------------------------------------------===// 2386// Load / Store Instructions. 2387// 2388 2389// Load 2390 2391 2392defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, 2393 UnOpFrag<(load node:$Src)>>; 2394defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si, 2395 UnOpFrag<(zextloadi8 node:$Src)>>; 2396defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, 2397 BinOpFrag<(store node:$LHS, node:$RHS)>>; 2398defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si, 2399 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 2400 2401// Special LDR for loads from non-pc-relative constpools. 2402let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1, 2403 isReMaterializable = 1, isCodeGenOnly = 1 in 2404def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 2405 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", 2406 []> { 2407 bits<4> Rt; 2408 bits<17> addr; 2409 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2410 let Inst{19-16} = 0b1111; 2411 let Inst{15-12} = Rt; 2412 let Inst{11-0} = addr{11-0}; // imm12 2413} 2414 2415// Loads with zero extension 2416def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2417 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", 2418 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; 2419 2420// Loads with sign extension 2421def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2422 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", 2423 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; 2424 2425def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2426 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", 2427 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; 2428 2429let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { 2430 // Load doubleword 2431 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr), 2432 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>, 2433 Requires<[IsARM, HasV5TE]>; 2434} 2435 2436def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2437 NoItinerary, "lda", "\t$Rt, $addr", []>; 2438def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2439 NoItinerary, "ldab", "\t$Rt, $addr", []>; 2440def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2441 NoItinerary, "ldah", "\t$Rt, $addr", []>; 2442 2443// Indexed loads 2444multiclass AI2_ldridx<bit isByte, string opc, 2445 InstrItinClass iii, InstrItinClass iir> { 2446 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2447 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii, 2448 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2449 bits<17> addr; 2450 let Inst{25} = 0; 2451 let Inst{23} = addr{12}; 2452 let Inst{19-16} = addr{16-13}; 2453 let Inst{11-0} = addr{11-0}; 2454 let DecoderMethod = "DecodeLDRPreImm"; 2455 } 2456 2457 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2458 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir, 2459 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2460 bits<17> addr; 2461 let Inst{25} = 1; 2462 let Inst{23} = addr{12}; 2463 let Inst{19-16} = addr{16-13}; 2464 let Inst{11-0} = addr{11-0}; 2465 let Inst{4} = 0; 2466 let DecoderMethod = "DecodeLDRPreReg"; 2467 } 2468 2469 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2470 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2471 IndexModePost, LdFrm, iir, 2472 opc, "\t$Rt, $addr, $offset", 2473 "$addr.base = $Rn_wb", []> { 2474 // {12} isAdd 2475 // {11-0} imm12/Rm 2476 bits<14> offset; 2477 bits<4> addr; 2478 let Inst{25} = 1; 2479 let Inst{23} = offset{12}; 2480 let Inst{19-16} = addr; 2481 let Inst{11-0} = offset{11-0}; 2482 let Inst{4} = 0; 2483 2484 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2485 } 2486 2487 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2488 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2489 IndexModePost, LdFrm, iii, 2490 opc, "\t$Rt, $addr, $offset", 2491 "$addr.base = $Rn_wb", []> { 2492 // {12} isAdd 2493 // {11-0} imm12/Rm 2494 bits<14> offset; 2495 bits<4> addr; 2496 let Inst{25} = 0; 2497 let Inst{23} = offset{12}; 2498 let Inst{19-16} = addr; 2499 let Inst{11-0} = offset{11-0}; 2500 2501 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2502 } 2503 2504} 2505 2506let mayLoad = 1, neverHasSideEffects = 1 in { 2507// FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or 2508// IIC_iLoad_siu depending on whether it the offset register is shifted. 2509defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>; 2510defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>; 2511} 2512 2513multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> { 2514 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2515 (ins addrmode3_pre:$addr), IndexModePre, 2516 LdMiscFrm, itin, 2517 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2518 bits<14> addr; 2519 let Inst{23} = addr{8}; // U bit 2520 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2521 let Inst{19-16} = addr{12-9}; // Rn 2522 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2523 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2524 let DecoderMethod = "DecodeAddrMode3Instruction"; 2525 } 2526 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2527 (ins addr_offset_none:$addr, am3offset:$offset), 2528 IndexModePost, LdMiscFrm, itin, 2529 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2530 []> { 2531 bits<10> offset; 2532 bits<4> addr; 2533 let Inst{23} = offset{8}; // U bit 2534 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2535 let Inst{19-16} = addr; 2536 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2537 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2538 let DecoderMethod = "DecodeAddrMode3Instruction"; 2539 } 2540} 2541 2542let mayLoad = 1, neverHasSideEffects = 1 in { 2543defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; 2544defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; 2545defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; 2546let hasExtraDefRegAllocReq = 1 in { 2547def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2548 (ins addrmode3_pre:$addr), IndexModePre, 2549 LdMiscFrm, IIC_iLoad_d_ru, 2550 "ldrd", "\t$Rt, $Rt2, $addr!", 2551 "$addr.base = $Rn_wb", []> { 2552 bits<14> addr; 2553 let Inst{23} = addr{8}; // U bit 2554 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2555 let Inst{19-16} = addr{12-9}; // Rn 2556 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2557 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2558 let DecoderMethod = "DecodeAddrMode3Instruction"; 2559} 2560def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2561 (ins addr_offset_none:$addr, am3offset:$offset), 2562 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, 2563 "ldrd", "\t$Rt, $Rt2, $addr, $offset", 2564 "$addr.base = $Rn_wb", []> { 2565 bits<10> offset; 2566 bits<4> addr; 2567 let Inst{23} = offset{8}; // U bit 2568 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2569 let Inst{19-16} = addr; 2570 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2571 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2572 let DecoderMethod = "DecodeAddrMode3Instruction"; 2573} 2574} // hasExtraDefRegAllocReq = 1 2575} // mayLoad = 1, neverHasSideEffects = 1 2576 2577// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT. 2578let mayLoad = 1, neverHasSideEffects = 1 in { 2579def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2580 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2581 IndexModePost, LdFrm, IIC_iLoad_ru, 2582 "ldrt", "\t$Rt, $addr, $offset", 2583 "$addr.base = $Rn_wb", []> { 2584 // {12} isAdd 2585 // {11-0} imm12/Rm 2586 bits<14> offset; 2587 bits<4> addr; 2588 let Inst{25} = 1; 2589 let Inst{23} = offset{12}; 2590 let Inst{21} = 1; // overwrite 2591 let Inst{19-16} = addr; 2592 let Inst{11-5} = offset{11-5}; 2593 let Inst{4} = 0; 2594 let Inst{3-0} = offset{3-0}; 2595 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2596} 2597 2598def LDRT_POST_IMM 2599 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2600 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2601 IndexModePost, LdFrm, IIC_iLoad_ru, 2602 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2603 // {12} isAdd 2604 // {11-0} imm12/Rm 2605 bits<14> offset; 2606 bits<4> addr; 2607 let Inst{25} = 0; 2608 let Inst{23} = offset{12}; 2609 let Inst{21} = 1; // overwrite 2610 let Inst{19-16} = addr; 2611 let Inst{11-0} = offset{11-0}; 2612 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2613} 2614 2615def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2616 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2617 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2618 "ldrbt", "\t$Rt, $addr, $offset", 2619 "$addr.base = $Rn_wb", []> { 2620 // {12} isAdd 2621 // {11-0} imm12/Rm 2622 bits<14> offset; 2623 bits<4> addr; 2624 let Inst{25} = 1; 2625 let Inst{23} = offset{12}; 2626 let Inst{21} = 1; // overwrite 2627 let Inst{19-16} = addr; 2628 let Inst{11-5} = offset{11-5}; 2629 let Inst{4} = 0; 2630 let Inst{3-0} = offset{3-0}; 2631 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2632} 2633 2634def LDRBT_POST_IMM 2635 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2636 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2637 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2638 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2639 // {12} isAdd 2640 // {11-0} imm12/Rm 2641 bits<14> offset; 2642 bits<4> addr; 2643 let Inst{25} = 0; 2644 let Inst{23} = offset{12}; 2645 let Inst{21} = 1; // overwrite 2646 let Inst{19-16} = addr; 2647 let Inst{11-0} = offset{11-0}; 2648 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2649} 2650 2651multiclass AI3ldrT<bits<4> op, string opc> { 2652 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb), 2653 (ins addr_offset_none:$addr, postidx_imm8:$offset), 2654 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2655 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2656 bits<9> offset; 2657 let Inst{23} = offset{8}; 2658 let Inst{22} = 1; 2659 let Inst{11-8} = offset{7-4}; 2660 let Inst{3-0} = offset{3-0}; 2661 } 2662 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb), 2663 (ins addr_offset_none:$addr, postidx_reg:$Rm), 2664 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2665 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2666 bits<5> Rm; 2667 let Inst{23} = Rm{4}; 2668 let Inst{22} = 0; 2669 let Inst{11-8} = 0; 2670 let Unpredictable{11-8} = 0b1111; 2671 let Inst{3-0} = Rm{3-0}; 2672 let DecoderMethod = "DecodeLDR"; 2673 } 2674} 2675 2676defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">; 2677defm LDRHT : AI3ldrT<0b1011, "ldrht">; 2678defm LDRSHT : AI3ldrT<0b1111, "ldrsht">; 2679} 2680 2681def LDRT_POST 2682 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2683 (outs GPR:$Rt)>; 2684 2685def LDRBT_POST 2686 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2687 (outs GPR:$Rt)>; 2688 2689// Store 2690 2691// Stores with truncate 2692def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, 2693 IIC_iStore_bh_r, "strh", "\t$Rt, $addr", 2694 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; 2695 2696// Store doubleword 2697let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { 2698 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr), 2699 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>, 2700 Requires<[IsARM, HasV5TE]> { 2701 let Inst{21} = 0; 2702 } 2703} 2704 2705// Indexed stores 2706multiclass AI2_stridx<bit isByte, string opc, 2707 InstrItinClass iii, InstrItinClass iir> { 2708 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2709 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre, 2710 StFrm, iii, 2711 opc, "\t$Rt, $addr!", 2712 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2713 bits<17> addr; 2714 let Inst{25} = 0; 2715 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2716 let Inst{19-16} = addr{16-13}; // Rn 2717 let Inst{11-0} = addr{11-0}; // imm12 2718 let DecoderMethod = "DecodeSTRPreImm"; 2719 } 2720 2721 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2722 (ins GPR:$Rt, ldst_so_reg:$addr), 2723 IndexModePre, StFrm, iir, 2724 opc, "\t$Rt, $addr!", 2725 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2726 bits<17> addr; 2727 let Inst{25} = 1; 2728 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2729 let Inst{19-16} = addr{16-13}; // Rn 2730 let Inst{11-0} = addr{11-0}; 2731 let Inst{4} = 0; // Inst{4} = 0 2732 let DecoderMethod = "DecodeSTRPreReg"; 2733 } 2734 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2735 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2736 IndexModePost, StFrm, iir, 2737 opc, "\t$Rt, $addr, $offset", 2738 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2739 // {12} isAdd 2740 // {11-0} imm12/Rm 2741 bits<14> offset; 2742 bits<4> addr; 2743 let Inst{25} = 1; 2744 let Inst{23} = offset{12}; 2745 let Inst{19-16} = addr; 2746 let Inst{11-0} = offset{11-0}; 2747 let Inst{4} = 0; 2748 2749 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2750 } 2751 2752 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2753 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2754 IndexModePost, StFrm, iii, 2755 opc, "\t$Rt, $addr, $offset", 2756 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2757 // {12} isAdd 2758 // {11-0} imm12/Rm 2759 bits<14> offset; 2760 bits<4> addr; 2761 let Inst{25} = 0; 2762 let Inst{23} = offset{12}; 2763 let Inst{19-16} = addr; 2764 let Inst{11-0} = offset{11-0}; 2765 2766 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2767 } 2768} 2769 2770let mayStore = 1, neverHasSideEffects = 1 in { 2771// FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or 2772// IIC_iStore_siu depending on whether it the offset register is shifted. 2773defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>; 2774defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>; 2775} 2776 2777def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2778 am2offset_reg:$offset), 2779 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr, 2780 am2offset_reg:$offset)>; 2781def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2782 am2offset_imm:$offset), 2783 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2784 am2offset_imm:$offset)>; 2785def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2786 am2offset_reg:$offset), 2787 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, 2788 am2offset_reg:$offset)>; 2789def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2790 am2offset_imm:$offset), 2791 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2792 am2offset_imm:$offset)>; 2793 2794// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 2795// put the patterns on the instruction definitions directly as ISel wants 2796// the address base and offset to be separate operands, not a single 2797// complex operand like we represent the instructions themselves. The 2798// pseudos map between the two. 2799let usesCustomInserter = 1, 2800 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 2801def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2802 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 2803 4, IIC_iStore_ru, 2804 [(set GPR:$Rn_wb, 2805 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 2806def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2807 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 2808 4, IIC_iStore_ru, 2809 [(set GPR:$Rn_wb, 2810 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 2811def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2812 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 2813 4, IIC_iStore_ru, 2814 [(set GPR:$Rn_wb, 2815 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 2816def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2817 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 2818 4, IIC_iStore_ru, 2819 [(set GPR:$Rn_wb, 2820 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 2821def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2822 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p), 2823 4, IIC_iStore_ru, 2824 [(set GPR:$Rn_wb, 2825 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>; 2826} 2827 2828 2829 2830def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), 2831 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre, 2832 StMiscFrm, IIC_iStore_bh_ru, 2833 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2834 bits<14> addr; 2835 let Inst{23} = addr{8}; // U bit 2836 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2837 let Inst{19-16} = addr{12-9}; // Rn 2838 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2839 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2840 let DecoderMethod = "DecodeAddrMode3Instruction"; 2841} 2842 2843def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), 2844 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset), 2845 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, 2846 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2847 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, 2848 addr_offset_none:$addr, 2849 am3offset:$offset))]> { 2850 bits<10> offset; 2851 bits<4> addr; 2852 let Inst{23} = offset{8}; // U bit 2853 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2854 let Inst{19-16} = addr; 2855 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2856 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2857 let DecoderMethod = "DecodeAddrMode3Instruction"; 2858} 2859 2860let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { 2861def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), 2862 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr), 2863 IndexModePre, StMiscFrm, IIC_iStore_d_ru, 2864 "strd", "\t$Rt, $Rt2, $addr!", 2865 "$addr.base = $Rn_wb", []> { 2866 bits<14> addr; 2867 let Inst{23} = addr{8}; // U bit 2868 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2869 let Inst{19-16} = addr{12-9}; // Rn 2870 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2871 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2872 let DecoderMethod = "DecodeAddrMode3Instruction"; 2873} 2874 2875def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), 2876 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, 2877 am3offset:$offset), 2878 IndexModePost, StMiscFrm, IIC_iStore_d_ru, 2879 "strd", "\t$Rt, $Rt2, $addr, $offset", 2880 "$addr.base = $Rn_wb", []> { 2881 bits<10> offset; 2882 bits<4> addr; 2883 let Inst{23} = offset{8}; // U bit 2884 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2885 let Inst{19-16} = addr; 2886 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2887 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2888 let DecoderMethod = "DecodeAddrMode3Instruction"; 2889} 2890} // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 2891 2892// STRT, STRBT, and STRHT 2893 2894def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 2895 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2896 IndexModePost, StFrm, IIC_iStore_bh_ru, 2897 "strbt", "\t$Rt, $addr, $offset", 2898 "$addr.base = $Rn_wb", []> { 2899 // {12} isAdd 2900 // {11-0} imm12/Rm 2901 bits<14> offset; 2902 bits<4> addr; 2903 let Inst{25} = 1; 2904 let Inst{23} = offset{12}; 2905 let Inst{21} = 1; // overwrite 2906 let Inst{19-16} = addr; 2907 let Inst{11-5} = offset{11-5}; 2908 let Inst{4} = 0; 2909 let Inst{3-0} = offset{3-0}; 2910 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2911} 2912 2913def STRBT_POST_IMM 2914 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 2915 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2916 IndexModePost, StFrm, IIC_iStore_bh_ru, 2917 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2918 // {12} isAdd 2919 // {11-0} imm12/Rm 2920 bits<14> offset; 2921 bits<4> addr; 2922 let Inst{25} = 0; 2923 let Inst{23} = offset{12}; 2924 let Inst{21} = 1; // overwrite 2925 let Inst{19-16} = addr; 2926 let Inst{11-0} = offset{11-0}; 2927 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2928} 2929 2930def STRBT_POST 2931 : ARMAsmPseudo<"strbt${q} $Rt, $addr", 2932 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 2933 2934let mayStore = 1, neverHasSideEffects = 1 in { 2935def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 2936 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2937 IndexModePost, StFrm, IIC_iStore_ru, 2938 "strt", "\t$Rt, $addr, $offset", 2939 "$addr.base = $Rn_wb", []> { 2940 // {12} isAdd 2941 // {11-0} imm12/Rm 2942 bits<14> offset; 2943 bits<4> addr; 2944 let Inst{25} = 1; 2945 let Inst{23} = offset{12}; 2946 let Inst{21} = 1; // overwrite 2947 let Inst{19-16} = addr; 2948 let Inst{11-5} = offset{11-5}; 2949 let Inst{4} = 0; 2950 let Inst{3-0} = offset{3-0}; 2951 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2952} 2953 2954def STRT_POST_IMM 2955 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 2956 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2957 IndexModePost, StFrm, IIC_iStore_ru, 2958 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2959 // {12} isAdd 2960 // {11-0} imm12/Rm 2961 bits<14> offset; 2962 bits<4> addr; 2963 let Inst{25} = 0; 2964 let Inst{23} = offset{12}; 2965 let Inst{21} = 1; // overwrite 2966 let Inst{19-16} = addr; 2967 let Inst{11-0} = offset{11-0}; 2968 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2969} 2970} 2971 2972def STRT_POST 2973 : ARMAsmPseudo<"strt${q} $Rt, $addr", 2974 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 2975 2976multiclass AI3strT<bits<4> op, string opc> { 2977 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 2978 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset), 2979 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 2980 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2981 bits<9> offset; 2982 let Inst{23} = offset{8}; 2983 let Inst{22} = 1; 2984 let Inst{11-8} = offset{7-4}; 2985 let Inst{3-0} = offset{3-0}; 2986 } 2987 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 2988 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm), 2989 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 2990 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2991 bits<5> Rm; 2992 let Inst{23} = Rm{4}; 2993 let Inst{22} = 0; 2994 let Inst{11-8} = 0; 2995 let Inst{3-0} = Rm{3-0}; 2996 } 2997} 2998 2999 3000defm STRHT : AI3strT<0b1011, "strht">; 3001 3002def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3003 NoItinerary, "stl", "\t$Rt, $addr", []>; 3004def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3005 NoItinerary, "stlb", "\t$Rt, $addr", []>; 3006def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3007 NoItinerary, "stlh", "\t$Rt, $addr", []>; 3008 3009//===----------------------------------------------------------------------===// 3010// Load / store multiple Instructions. 3011// 3012 3013multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f, 3014 InstrItinClass itin, InstrItinClass itin_upd> { 3015 // IA is the default, so no need for an explicit suffix on the 3016 // mnemonic here. Without it is the canonical spelling. 3017 def IA : 3018 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3019 IndexModeNone, f, itin, 3020 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> { 3021 let Inst{24-23} = 0b01; // Increment After 3022 let Inst{22} = P_bit; 3023 let Inst{21} = 0; // No writeback 3024 let Inst{20} = L_bit; 3025 } 3026 def IA_UPD : 3027 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3028 IndexModeUpd, f, itin_upd, 3029 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3030 let Inst{24-23} = 0b01; // Increment After 3031 let Inst{22} = P_bit; 3032 let Inst{21} = 1; // Writeback 3033 let Inst{20} = L_bit; 3034 3035 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3036 } 3037 def DA : 3038 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3039 IndexModeNone, f, itin, 3040 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> { 3041 let Inst{24-23} = 0b00; // Decrement After 3042 let Inst{22} = P_bit; 3043 let Inst{21} = 0; // No writeback 3044 let Inst{20} = L_bit; 3045 } 3046 def DA_UPD : 3047 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3048 IndexModeUpd, f, itin_upd, 3049 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3050 let Inst{24-23} = 0b00; // Decrement After 3051 let Inst{22} = P_bit; 3052 let Inst{21} = 1; // Writeback 3053 let Inst{20} = L_bit; 3054 3055 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3056 } 3057 def DB : 3058 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3059 IndexModeNone, f, itin, 3060 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> { 3061 let Inst{24-23} = 0b10; // Decrement Before 3062 let Inst{22} = P_bit; 3063 let Inst{21} = 0; // No writeback 3064 let Inst{20} = L_bit; 3065 } 3066 def DB_UPD : 3067 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3068 IndexModeUpd, f, itin_upd, 3069 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3070 let Inst{24-23} = 0b10; // Decrement Before 3071 let Inst{22} = P_bit; 3072 let Inst{21} = 1; // Writeback 3073 let Inst{20} = L_bit; 3074 3075 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3076 } 3077 def IB : 3078 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3079 IndexModeNone, f, itin, 3080 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> { 3081 let Inst{24-23} = 0b11; // Increment Before 3082 let Inst{22} = P_bit; 3083 let Inst{21} = 0; // No writeback 3084 let Inst{20} = L_bit; 3085 } 3086 def IB_UPD : 3087 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3088 IndexModeUpd, f, itin_upd, 3089 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3090 let Inst{24-23} = 0b11; // Increment Before 3091 let Inst{22} = P_bit; 3092 let Inst{21} = 1; // Writeback 3093 let Inst{20} = L_bit; 3094 3095 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3096 } 3097} 3098 3099let neverHasSideEffects = 1 in { 3100 3101let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3102defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m, 3103 IIC_iLoad_mu>; 3104 3105let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3106defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m, 3107 IIC_iStore_mu>; 3108 3109} // neverHasSideEffects 3110 3111// FIXME: remove when we have a way to marking a MI with these properties. 3112// FIXME: Should pc be an implicit operand like PICADD, etc? 3113let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 3114 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 3115def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 3116 reglist:$regs, variable_ops), 3117 4, IIC_iLoad_mBr, [], 3118 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 3119 RegConstraint<"$Rn = $wb">; 3120 3121let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3122defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m, 3123 IIC_iLoad_mu>; 3124 3125let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3126defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m, 3127 IIC_iStore_mu>; 3128 3129 3130 3131//===----------------------------------------------------------------------===// 3132// Move Instructions. 3133// 3134 3135let neverHasSideEffects = 1 in 3136def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, 3137 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3138 bits<4> Rd; 3139 bits<4> Rm; 3140 3141 let Inst{19-16} = 0b0000; 3142 let Inst{11-4} = 0b00000000; 3143 let Inst{25} = 0; 3144 let Inst{3-0} = Rm; 3145 let Inst{15-12} = Rd; 3146} 3147 3148// A version for the smaller set of tail call registers. 3149let neverHasSideEffects = 1 in 3150def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 3151 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3152 bits<4> Rd; 3153 bits<4> Rm; 3154 3155 let Inst{11-4} = 0b00000000; 3156 let Inst{25} = 0; 3157 let Inst{3-0} = Rm; 3158 let Inst{15-12} = Rd; 3159} 3160 3161def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), 3162 DPSoRegRegFrm, IIC_iMOVsr, 3163 "mov", "\t$Rd, $src", 3164 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP, 3165 Sched<[WriteALU]> { 3166 bits<4> Rd; 3167 bits<12> src; 3168 let Inst{15-12} = Rd; 3169 let Inst{19-16} = 0b0000; 3170 let Inst{11-8} = src{11-8}; 3171 let Inst{7} = 0; 3172 let Inst{6-5} = src{6-5}; 3173 let Inst{4} = 1; 3174 let Inst{3-0} = src{3-0}; 3175 let Inst{25} = 0; 3176} 3177 3178def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src), 3179 DPSoRegImmFrm, IIC_iMOVsr, 3180 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>, 3181 UnaryDP, Sched<[WriteALU]> { 3182 bits<4> Rd; 3183 bits<12> src; 3184 let Inst{15-12} = Rd; 3185 let Inst{19-16} = 0b0000; 3186 let Inst{11-5} = src{11-5}; 3187 let Inst{4} = 0; 3188 let Inst{3-0} = src{3-0}; 3189 let Inst{25} = 0; 3190} 3191 3192let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3193def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi, 3194 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP, 3195 Sched<[WriteALU]> { 3196 bits<4> Rd; 3197 bits<12> imm; 3198 let Inst{25} = 1; 3199 let Inst{15-12} = Rd; 3200 let Inst{19-16} = 0b0000; 3201 let Inst{11-0} = imm; 3202} 3203 3204let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3205def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), 3206 DPFrm, IIC_iMOVi, 3207 "movw", "\t$Rd, $imm", 3208 [(set GPR:$Rd, imm0_65535:$imm)]>, 3209 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> { 3210 bits<4> Rd; 3211 bits<16> imm; 3212 let Inst{15-12} = Rd; 3213 let Inst{11-0} = imm{11-0}; 3214 let Inst{19-16} = imm{15-12}; 3215 let Inst{20} = 0; 3216 let Inst{25} = 1; 3217 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3218} 3219 3220def : InstAlias<"mov${p} $Rd, $imm", 3221 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>, 3222 Requires<[IsARM]>; 3223 3224def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3225 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3226 Sched<[WriteALU]>; 3227 3228let Constraints = "$src = $Rd" in { 3229def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd), 3230 (ins GPR:$src, imm0_65535_expr:$imm), 3231 DPFrm, IIC_iMOVi, 3232 "movt", "\t$Rd, $imm", 3233 [(set GPRnopc:$Rd, 3234 (or (and GPR:$src, 0xffff), 3235 lo16AllZero:$imm))]>, UnaryDP, 3236 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> { 3237 bits<4> Rd; 3238 bits<16> imm; 3239 let Inst{15-12} = Rd; 3240 let Inst{11-0} = imm{11-0}; 3241 let Inst{19-16} = imm{15-12}; 3242 let Inst{20} = 0; 3243 let Inst{25} = 1; 3244 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3245} 3246 3247def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3248 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3249 Sched<[WriteALU]>; 3250 3251} // Constraints 3252 3253def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 3254 Requires<[IsARM, HasV6T2]>; 3255 3256let Uses = [CPSR] in 3257def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, 3258 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, 3259 Requires<[IsARM]>, Sched<[WriteALU]>; 3260 3261// These aren't really mov instructions, but we have to define them this way 3262// due to flag operands. 3263 3264let Defs = [CPSR] in { 3265def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3266 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, 3267 Sched<[WriteALU]>, Requires<[IsARM]>; 3268def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3269 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, 3270 Sched<[WriteALU]>, Requires<[IsARM]>; 3271} 3272 3273//===----------------------------------------------------------------------===// 3274// Extend Instructions. 3275// 3276 3277// Sign extenders 3278 3279def SXTB : AI_ext_rrot<0b01101010, 3280 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 3281def SXTH : AI_ext_rrot<0b01101011, 3282 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 3283 3284def SXTAB : AI_exta_rrot<0b01101010, 3285 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 3286def SXTAH : AI_exta_rrot<0b01101011, 3287 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 3288 3289def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; 3290 3291def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; 3292 3293// Zero extenders 3294 3295let AddedComplexity = 16 in { 3296def UXTB : AI_ext_rrot<0b01101110, 3297 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 3298def UXTH : AI_ext_rrot<0b01101111, 3299 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 3300def UXTB16 : AI_ext_rrot<0b01101100, 3301 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 3302 3303// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 3304// The transformation should probably be done as a combiner action 3305// instead so we can include a check for masking back in the upper 3306// eight bits of the source into the lower eight bits of the result. 3307//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 3308// (UXTB16r_rot GPR:$Src, 3)>; 3309def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 3310 (UXTB16 GPR:$Src, 1)>; 3311 3312def UXTAB : AI_exta_rrot<0b01101110, "uxtab", 3313 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 3314def UXTAH : AI_exta_rrot<0b01101111, "uxtah", 3315 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 3316} 3317 3318// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 3319def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; 3320 3321 3322def SBFX : I<(outs GPRnopc:$Rd), 3323 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3324 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3325 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3326 Requires<[IsARM, HasV6T2]> { 3327 bits<4> Rd; 3328 bits<4> Rn; 3329 bits<5> lsb; 3330 bits<5> width; 3331 let Inst{27-21} = 0b0111101; 3332 let Inst{6-4} = 0b101; 3333 let Inst{20-16} = width; 3334 let Inst{15-12} = Rd; 3335 let Inst{11-7} = lsb; 3336 let Inst{3-0} = Rn; 3337} 3338 3339def UBFX : I<(outs GPRnopc:$Rd), 3340 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3341 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3342 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3343 Requires<[IsARM, HasV6T2]> { 3344 bits<4> Rd; 3345 bits<4> Rn; 3346 bits<5> lsb; 3347 bits<5> width; 3348 let Inst{27-21} = 0b0111111; 3349 let Inst{6-4} = 0b101; 3350 let Inst{20-16} = width; 3351 let Inst{15-12} = Rd; 3352 let Inst{11-7} = lsb; 3353 let Inst{3-0} = Rn; 3354} 3355 3356//===----------------------------------------------------------------------===// 3357// Arithmetic Instructions. 3358// 3359 3360defm ADD : AsI1_bin_irs<0b0100, "add", 3361 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3362 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 3363defm SUB : AsI1_bin_irs<0b0010, "sub", 3364 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3365 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 3366 3367// ADD and SUB with 's' bit set. 3368// 3369// Currently, ADDS/SUBS are pseudo opcodes that exist only in the 3370// selection DAG. They are "lowered" to real ADD/SUB opcodes by 3371// AdjustInstrPostInstrSelection where we determine whether or not to 3372// set the "s" bit based on CPSR liveness. 3373// 3374// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen 3375// support for an optional CPSR definition that corresponds to the DAG 3376// node's second value. We can then eliminate the implicit def of CPSR. 3377defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3378 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>; 3379defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3380 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 3381 3382defm ADC : AI1_adde_sube_irs<0b0101, "adc", 3383 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>; 3384defm SBC : AI1_adde_sube_irs<0b0110, "sbc", 3385 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>; 3386 3387defm RSB : AsI1_rbin_irs<0b0011, "rsb", 3388 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3389 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 3390 3391// FIXME: Eliminate them if we can write def : Pat patterns which defines 3392// CPSR and the implicit def of CPSR is not needed. 3393defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3394 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 3395 3396defm RSC : AI1_rsc_irs<0b0111, "rsc", 3397 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>; 3398 3399// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 3400// The assume-no-carry-in form uses the negation of the input since add/sub 3401// assume opposite meanings of the carry flag (i.e., carry == !borrow). 3402// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 3403// details. 3404def : ARMPat<(add GPR:$src, so_imm_neg:$imm), 3405 (SUBri GPR:$src, so_imm_neg:$imm)>; 3406def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm), 3407 (SUBSri GPR:$src, so_imm_neg:$imm)>; 3408 3409def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm), 3410 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3411 Requires<[IsARM, HasV6T2]>; 3412def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm), 3413 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3414 Requires<[IsARM, HasV6T2]>; 3415 3416// The with-carry-in form matches bitwise not instead of the negation. 3417// Effectively, the inverse interpretation of the carry flag already accounts 3418// for part of the negation. 3419def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR), 3420 (SBCri GPR:$src, so_imm_not:$imm)>; 3421def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR), 3422 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>, 3423 Requires<[IsARM, HasV6T2]>; 3424 3425// Note: These are implemented in C++ code, because they have to generate 3426// ADD/SUBrs instructions, which use a complex pattern that a xform function 3427// cannot produce. 3428// (mul X, 2^n+1) -> (add (X << n), X) 3429// (mul X, 2^n-1) -> (rsb X, (X << n)) 3430 3431// ARM Arithmetic Instruction 3432// GPR:$dst = GPR:$a op GPR:$b 3433class AAI<bits<8> op27_20, bits<8> op11_4, string opc, 3434 list<dag> pattern = [], 3435 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), 3436 string asm = "\t$Rd, $Rn, $Rm"> 3437 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>, 3438 Sched<[WriteALU, ReadALU, ReadALU]> { 3439 bits<4> Rn; 3440 bits<4> Rd; 3441 bits<4> Rm; 3442 let Inst{27-20} = op27_20; 3443 let Inst{11-4} = op11_4; 3444 let Inst{19-16} = Rn; 3445 let Inst{15-12} = Rd; 3446 let Inst{3-0} = Rm; 3447 3448 let Unpredictable{11-8} = 0b1111; 3449} 3450 3451// Saturating add/subtract 3452 3453let DecoderMethod = "DecodeQADDInstruction" in 3454def QADD : AAI<0b00010000, 0b00000101, "qadd", 3455 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))], 3456 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">; 3457 3458def QSUB : AAI<0b00010010, 0b00000101, "qsub", 3459 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))], 3460 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">; 3461def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], 3462 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3463 "\t$Rd, $Rm, $Rn">; 3464def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], 3465 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3466 "\t$Rd, $Rm, $Rn">; 3467 3468def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">; 3469def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">; 3470def QASX : AAI<0b01100010, 0b11110011, "qasx">; 3471def QSAX : AAI<0b01100010, 0b11110101, "qsax">; 3472def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">; 3473def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">; 3474def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">; 3475def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">; 3476def UQASX : AAI<0b01100110, 0b11110011, "uqasx">; 3477def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">; 3478def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">; 3479def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">; 3480 3481// Signed/Unsigned add/subtract 3482 3483def SASX : AAI<0b01100001, 0b11110011, "sasx">; 3484def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">; 3485def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">; 3486def SSAX : AAI<0b01100001, 0b11110101, "ssax">; 3487def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">; 3488def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">; 3489def UASX : AAI<0b01100101, 0b11110011, "uasx">; 3490def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">; 3491def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">; 3492def USAX : AAI<0b01100101, 0b11110101, "usax">; 3493def USUB16 : AAI<0b01100101, 0b11110111, "usub16">; 3494def USUB8 : AAI<0b01100101, 0b11111111, "usub8">; 3495 3496// Signed/Unsigned halving add/subtract 3497 3498def SHASX : AAI<0b01100011, 0b11110011, "shasx">; 3499def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">; 3500def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">; 3501def SHSAX : AAI<0b01100011, 0b11110101, "shsax">; 3502def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">; 3503def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">; 3504def UHASX : AAI<0b01100111, 0b11110011, "uhasx">; 3505def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">; 3506def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">; 3507def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">; 3508def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">; 3509def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">; 3510 3511// Unsigned Sum of Absolute Differences [and Accumulate]. 3512 3513def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3514 MulFrm /* for convenience */, NoItinerary, "usad8", 3515 "\t$Rd, $Rn, $Rm", []>, 3516 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> { 3517 bits<4> Rd; 3518 bits<4> Rn; 3519 bits<4> Rm; 3520 let Inst{27-20} = 0b01111000; 3521 let Inst{15-12} = 0b1111; 3522 let Inst{7-4} = 0b0001; 3523 let Inst{19-16} = Rd; 3524 let Inst{11-8} = Rm; 3525 let Inst{3-0} = Rn; 3526} 3527def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3528 MulFrm /* for convenience */, NoItinerary, "usada8", 3529 "\t$Rd, $Rn, $Rm, $Ra", []>, 3530 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{ 3531 bits<4> Rd; 3532 bits<4> Rn; 3533 bits<4> Rm; 3534 bits<4> Ra; 3535 let Inst{27-20} = 0b01111000; 3536 let Inst{7-4} = 0b0001; 3537 let Inst{19-16} = Rd; 3538 let Inst{15-12} = Ra; 3539 let Inst{11-8} = Rm; 3540 let Inst{3-0} = Rn; 3541} 3542 3543// Signed/Unsigned saturate 3544 3545def SSAT : AI<(outs GPRnopc:$Rd), 3546 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3547 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> { 3548 bits<4> Rd; 3549 bits<5> sat_imm; 3550 bits<4> Rn; 3551 bits<8> sh; 3552 let Inst{27-21} = 0b0110101; 3553 let Inst{5-4} = 0b01; 3554 let Inst{20-16} = sat_imm; 3555 let Inst{15-12} = Rd; 3556 let Inst{11-7} = sh{4-0}; 3557 let Inst{6} = sh{5}; 3558 let Inst{3-0} = Rn; 3559} 3560 3561def SSAT16 : AI<(outs GPRnopc:$Rd), 3562 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm, 3563 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> { 3564 bits<4> Rd; 3565 bits<4> sat_imm; 3566 bits<4> Rn; 3567 let Inst{27-20} = 0b01101010; 3568 let Inst{11-4} = 0b11110011; 3569 let Inst{15-12} = Rd; 3570 let Inst{19-16} = sat_imm; 3571 let Inst{3-0} = Rn; 3572} 3573 3574def USAT : AI<(outs GPRnopc:$Rd), 3575 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3576 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> { 3577 bits<4> Rd; 3578 bits<5> sat_imm; 3579 bits<4> Rn; 3580 bits<8> sh; 3581 let Inst{27-21} = 0b0110111; 3582 let Inst{5-4} = 0b01; 3583 let Inst{15-12} = Rd; 3584 let Inst{11-7} = sh{4-0}; 3585 let Inst{6} = sh{5}; 3586 let Inst{20-16} = sat_imm; 3587 let Inst{3-0} = Rn; 3588} 3589 3590def USAT16 : AI<(outs GPRnopc:$Rd), 3591 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm, 3592 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> { 3593 bits<4> Rd; 3594 bits<4> sat_imm; 3595 bits<4> Rn; 3596 let Inst{27-20} = 0b01101110; 3597 let Inst{11-4} = 0b11110011; 3598 let Inst{15-12} = Rd; 3599 let Inst{19-16} = sat_imm; 3600 let Inst{3-0} = Rn; 3601} 3602 3603def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos), 3604 (SSAT imm:$pos, GPRnopc:$a, 0)>; 3605def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos), 3606 (USAT imm:$pos, GPRnopc:$a, 0)>; 3607 3608//===----------------------------------------------------------------------===// 3609// Bitwise Instructions. 3610// 3611 3612defm AND : AsI1_bin_irs<0b0000, "and", 3613 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3614 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; 3615defm ORR : AsI1_bin_irs<0b1100, "orr", 3616 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3617 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; 3618defm EOR : AsI1_bin_irs<0b0001, "eor", 3619 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3620 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; 3621defm BIC : AsI1_bin_irs<0b1110, "bic", 3622 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3623 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 3624 3625// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just 3626// like in the actual instruction encoding. The complexity of mapping the mask 3627// to the lsb/msb pair should be handled by ISel, not encapsulated in the 3628// instruction description. 3629def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), 3630 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3631 "bfc", "\t$Rd, $imm", "$src = $Rd", 3632 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 3633 Requires<[IsARM, HasV6T2]> { 3634 bits<4> Rd; 3635 bits<10> imm; 3636 let Inst{27-21} = 0b0111110; 3637 let Inst{6-0} = 0b0011111; 3638 let Inst{15-12} = Rd; 3639 let Inst{11-7} = imm{4-0}; // lsb 3640 let Inst{20-16} = imm{9-5}; // msb 3641} 3642 3643// A8.6.18 BFI - Bitfield insert (Encoding A1) 3644def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm), 3645 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3646 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", 3647 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, 3648 bf_inv_mask_imm:$imm))]>, 3649 Requires<[IsARM, HasV6T2]> { 3650 bits<4> Rd; 3651 bits<4> Rn; 3652 bits<10> imm; 3653 let Inst{27-21} = 0b0111110; 3654 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 3655 let Inst{15-12} = Rd; 3656 let Inst{11-7} = imm{4-0}; // lsb 3657 let Inst{20-16} = imm{9-5}; // width 3658 let Inst{3-0} = Rn; 3659} 3660 3661def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, 3662 "mvn", "\t$Rd, $Rm", 3663 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> { 3664 bits<4> Rd; 3665 bits<4> Rm; 3666 let Inst{25} = 0; 3667 let Inst{19-16} = 0b0000; 3668 let Inst{11-4} = 0b00000000; 3669 let Inst{15-12} = Rd; 3670 let Inst{3-0} = Rm; 3671} 3672def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), 3673 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3674 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP, 3675 Sched<[WriteALU]> { 3676 bits<4> Rd; 3677 bits<12> shift; 3678 let Inst{25} = 0; 3679 let Inst{19-16} = 0b0000; 3680 let Inst{15-12} = Rd; 3681 let Inst{11-5} = shift{11-5}; 3682 let Inst{4} = 0; 3683 let Inst{3-0} = shift{3-0}; 3684} 3685def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift), 3686 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3687 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP, 3688 Sched<[WriteALU]> { 3689 bits<4> Rd; 3690 bits<12> shift; 3691 let Inst{25} = 0; 3692 let Inst{19-16} = 0b0000; 3693 let Inst{15-12} = Rd; 3694 let Inst{11-8} = shift{11-8}; 3695 let Inst{7} = 0; 3696 let Inst{6-5} = shift{6-5}; 3697 let Inst{4} = 1; 3698 let Inst{3-0} = shift{3-0}; 3699} 3700let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3701def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, 3702 IIC_iMVNi, "mvn", "\t$Rd, $imm", 3703 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> { 3704 bits<4> Rd; 3705 bits<12> imm; 3706 let Inst{25} = 1; 3707 let Inst{19-16} = 0b0000; 3708 let Inst{15-12} = Rd; 3709 let Inst{11-0} = imm; 3710} 3711 3712def : ARMPat<(and GPR:$src, so_imm_not:$imm), 3713 (BICri GPR:$src, so_imm_not:$imm)>; 3714 3715//===----------------------------------------------------------------------===// 3716// Multiply Instructions. 3717// 3718class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3719 string opc, string asm, list<dag> pattern> 3720 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3721 bits<4> Rd; 3722 bits<4> Rm; 3723 bits<4> Rn; 3724 let Inst{19-16} = Rd; 3725 let Inst{11-8} = Rm; 3726 let Inst{3-0} = Rn; 3727} 3728class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3729 string opc, string asm, list<dag> pattern> 3730 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3731 bits<4> RdLo; 3732 bits<4> RdHi; 3733 bits<4> Rm; 3734 bits<4> Rn; 3735 let Inst{19-16} = RdHi; 3736 let Inst{15-12} = RdLo; 3737 let Inst{11-8} = Rm; 3738 let Inst{3-0} = Rn; 3739} 3740class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3741 string opc, string asm, list<dag> pattern> 3742 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3743 bits<4> RdLo; 3744 bits<4> RdHi; 3745 bits<4> Rm; 3746 bits<4> Rn; 3747 let Inst{19-16} = RdHi; 3748 let Inst{15-12} = RdLo; 3749 let Inst{11-8} = Rm; 3750 let Inst{3-0} = Rn; 3751} 3752 3753// FIXME: The v5 pseudos are only necessary for the additional Constraint 3754// property. Remove them when it's possible to add those properties 3755// on an individual MachineInstr, not just an instruction description. 3756let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in { 3757def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), 3758 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3759 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", 3760 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>, 3761 Requires<[IsARM, HasV6]> { 3762 let Inst{15-12} = 0b0000; 3763 let Unpredictable{15-12} = 0b1111; 3764} 3765 3766let Constraints = "@earlyclobber $Rd" in 3767def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, 3768 pred:$p, cc_out:$s), 3769 4, IIC_iMUL32, 3770 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))], 3771 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 3772 Requires<[IsARM, NoV6, UseMulOps]>; 3773} 3774 3775def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd), 3776 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra), 3777 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", 3778 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>, 3779 Requires<[IsARM, HasV6, UseMulOps]> { 3780 bits<4> Ra; 3781 let Inst{15-12} = Ra; 3782} 3783 3784let Constraints = "@earlyclobber $Rd" in 3785def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd), 3786 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 3787 pred:$p, cc_out:$s), 4, IIC_iMAC32, 3788 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))], 3789 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>, 3790 Requires<[IsARM, NoV6]>; 3791 3792def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3793 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", 3794 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, 3795 Requires<[IsARM, HasV6T2, UseMulOps]> { 3796 bits<4> Rd; 3797 bits<4> Rm; 3798 bits<4> Rn; 3799 bits<4> Ra; 3800 let Inst{19-16} = Rd; 3801 let Inst{15-12} = Ra; 3802 let Inst{11-8} = Rm; 3803 let Inst{3-0} = Rn; 3804} 3805 3806// Extra precision multiplies with low / high results 3807let neverHasSideEffects = 1 in { 3808let isCommutable = 1 in { 3809def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 3810 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 3811 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3812 Requires<[IsARM, HasV6]>; 3813 3814def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 3815 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 3816 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3817 Requires<[IsARM, HasV6]>; 3818 3819let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 3820def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3821 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 3822 4, IIC_iMUL64, [], 3823 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 3824 Requires<[IsARM, NoV6]>; 3825 3826def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3827 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 3828 4, IIC_iMUL64, [], 3829 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 3830 Requires<[IsARM, NoV6]>; 3831} 3832} 3833 3834// Multiply + accumulate 3835def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), 3836 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 3837 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3838 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>; 3839def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 3840 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 3841 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3842 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>; 3843 3844def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), 3845 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64, 3846 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3847 Requires<[IsARM, HasV6]> { 3848 bits<4> RdLo; 3849 bits<4> RdHi; 3850 bits<4> Rm; 3851 bits<4> Rn; 3852 let Inst{19-16} = RdHi; 3853 let Inst{15-12} = RdLo; 3854 let Inst{11-8} = Rm; 3855 let Inst{3-0} = Rn; 3856} 3857 3858let Constraints = 3859 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { 3860def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3861 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 3862 4, IIC_iMAC64, [], 3863 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 3864 pred:$p, cc_out:$s)>, 3865 Requires<[IsARM, NoV6]>; 3866def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3867 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 3868 4, IIC_iMAC64, [], 3869 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 3870 pred:$p, cc_out:$s)>, 3871 Requires<[IsARM, NoV6]>; 3872} 3873 3874} // neverHasSideEffects 3875 3876// Most significant word multiply 3877def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3878 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", 3879 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, 3880 Requires<[IsARM, HasV6]> { 3881 let Inst{15-12} = 0b1111; 3882} 3883 3884def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3885 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>, 3886 Requires<[IsARM, HasV6]> { 3887 let Inst{15-12} = 0b1111; 3888} 3889 3890def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), 3891 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3892 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", 3893 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 3894 Requires<[IsARM, HasV6, UseMulOps]>; 3895 3896def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), 3897 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3898 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>, 3899 Requires<[IsARM, HasV6]>; 3900 3901def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), 3902 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3903 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>, 3904 Requires<[IsARM, HasV6, UseMulOps]>; 3905 3906def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), 3907 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3908 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>, 3909 Requires<[IsARM, HasV6]>; 3910 3911multiclass AI_smul<string opc, PatFrag opnode> { 3912 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3913 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 3914 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16), 3915 (sext_inreg GPR:$Rm, i16)))]>, 3916 Requires<[IsARM, HasV5TE]>; 3917 3918 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3919 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 3920 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16), 3921 (sra GPR:$Rm, (i32 16))))]>, 3922 Requires<[IsARM, HasV5TE]>; 3923 3924 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3925 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 3926 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)), 3927 (sext_inreg GPR:$Rm, i16)))]>, 3928 Requires<[IsARM, HasV5TE]>; 3929 3930 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3931 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 3932 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)), 3933 (sra GPR:$Rm, (i32 16))))]>, 3934 Requires<[IsARM, HasV5TE]>; 3935 3936 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3937 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 3938 [(set GPR:$Rd, (sra (opnode GPR:$Rn, 3939 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>, 3940 Requires<[IsARM, HasV5TE]>; 3941 3942 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3943 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 3944 [(set GPR:$Rd, (sra (opnode GPR:$Rn, 3945 (sra GPR:$Rm, (i32 16))), (i32 16)))]>, 3946 Requires<[IsARM, HasV5TE]>; 3947} 3948 3949 3950multiclass AI_smla<string opc, PatFrag opnode> { 3951 let DecoderMethod = "DecodeSMLAInstruction" in { 3952 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd), 3953 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3954 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 3955 [(set GPRnopc:$Rd, (add GPR:$Ra, 3956 (opnode (sext_inreg GPRnopc:$Rn, i16), 3957 (sext_inreg GPRnopc:$Rm, i16))))]>, 3958 Requires<[IsARM, HasV5TE, UseMulOps]>; 3959 3960 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd), 3961 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3962 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 3963 [(set GPRnopc:$Rd, 3964 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16), 3965 (sra GPRnopc:$Rm, (i32 16)))))]>, 3966 Requires<[IsARM, HasV5TE, UseMulOps]>; 3967 3968 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd), 3969 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3970 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 3971 [(set GPRnopc:$Rd, 3972 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)), 3973 (sext_inreg GPRnopc:$Rm, i16))))]>, 3974 Requires<[IsARM, HasV5TE, UseMulOps]>; 3975 3976 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd), 3977 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3978 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 3979 [(set GPRnopc:$Rd, 3980 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)), 3981 (sra GPRnopc:$Rm, (i32 16)))))]>, 3982 Requires<[IsARM, HasV5TE, UseMulOps]>; 3983 3984 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd), 3985 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3986 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 3987 [(set GPRnopc:$Rd, 3988 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn, 3989 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>, 3990 Requires<[IsARM, HasV5TE, UseMulOps]>; 3991 3992 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd), 3993 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3994 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 3995 [(set GPRnopc:$Rd, 3996 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn, 3997 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>, 3998 Requires<[IsARM, HasV5TE, UseMulOps]>; 3999 } 4000} 4001 4002defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 4003defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 4004 4005// Halfword multiply accumulate long: SMLAL<x><y>. 4006def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4007 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4008 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4009 Requires<[IsARM, HasV5TE]>; 4010 4011def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4012 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4013 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4014 Requires<[IsARM, HasV5TE]>; 4015 4016def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4017 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4018 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4019 Requires<[IsARM, HasV5TE]>; 4020 4021def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4022 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4023 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4024 Requires<[IsARM, HasV5TE]>; 4025 4026// Helper class for AI_smld. 4027class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, 4028 InstrItinClass itin, string opc, string asm> 4029 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> { 4030 bits<4> Rn; 4031 bits<4> Rm; 4032 let Inst{27-23} = 0b01110; 4033 let Inst{22} = long; 4034 let Inst{21-20} = 0b00; 4035 let Inst{11-8} = Rm; 4036 let Inst{7} = 0; 4037 let Inst{6} = sub; 4038 let Inst{5} = swap; 4039 let Inst{4} = 1; 4040 let Inst{3-0} = Rn; 4041} 4042class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 4043 InstrItinClass itin, string opc, string asm> 4044 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4045 bits<4> Rd; 4046 let Inst{15-12} = 0b1111; 4047 let Inst{19-16} = Rd; 4048} 4049class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, 4050 InstrItinClass itin, string opc, string asm> 4051 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4052 bits<4> Ra; 4053 bits<4> Rd; 4054 let Inst{19-16} = Rd; 4055 let Inst{15-12} = Ra; 4056} 4057class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, 4058 InstrItinClass itin, string opc, string asm> 4059 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4060 bits<4> RdLo; 4061 bits<4> RdHi; 4062 let Inst{19-16} = RdHi; 4063 let Inst{15-12} = RdLo; 4064} 4065 4066multiclass AI_smld<bit sub, string opc> { 4067 4068 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd), 4069 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4070 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">; 4071 4072 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd), 4073 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4074 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">; 4075 4076 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4077 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary, 4078 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">; 4079 4080 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4081 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary, 4082 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">; 4083 4084} 4085 4086defm SMLA : AI_smld<0, "smla">; 4087defm SMLS : AI_smld<1, "smls">; 4088 4089multiclass AI_sdml<bit sub, string opc> { 4090 4091 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), 4092 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">; 4093 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm), 4094 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">; 4095} 4096 4097defm SMUA : AI_sdml<0, "smua">; 4098defm SMUS : AI_sdml<1, "smus">; 4099 4100//===----------------------------------------------------------------------===// 4101// Division Instructions (ARMv7-A with virtualization extension) 4102// 4103def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4104 "sdiv", "\t$Rd, $Rn, $Rm", 4105 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>, 4106 Requires<[IsARM, HasDivideInARM]>; 4107 4108def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4109 "udiv", "\t$Rd, $Rn, $Rm", 4110 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>, 4111 Requires<[IsARM, HasDivideInARM]>; 4112 4113//===----------------------------------------------------------------------===// 4114// Misc. Arithmetic Instructions. 4115// 4116 4117def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), 4118 IIC_iUNAr, "clz", "\t$Rd, $Rm", 4119 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>, 4120 Sched<[WriteALU]>; 4121 4122def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4123 IIC_iUNAr, "rbit", "\t$Rd, $Rm", 4124 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>, 4125 Requires<[IsARM, HasV6T2]>, 4126 Sched<[WriteALU]>; 4127 4128def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4129 IIC_iUNAr, "rev", "\t$Rd, $Rm", 4130 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>, 4131 Sched<[WriteALU]>; 4132 4133let AddedComplexity = 5 in 4134def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4135 IIC_iUNAr, "rev16", "\t$Rd, $Rm", 4136 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>, 4137 Requires<[IsARM, HasV6]>, 4138 Sched<[WriteALU]>; 4139 4140def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)), 4141 (REV16 (LDRH addrmode3:$addr))>; 4142def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr), 4143 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>; 4144 4145let AddedComplexity = 5 in 4146def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4147 IIC_iUNAr, "revsh", "\t$Rd, $Rm", 4148 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>, 4149 Requires<[IsARM, HasV6]>, 4150 Sched<[WriteALU]>; 4151 4152def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), 4153 (and (srl GPR:$Rm, (i32 8)), 0xFF)), 4154 (REVSH GPR:$Rm)>; 4155 4156def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd), 4157 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh), 4158 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 4159 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF), 4160 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 4161 0xFFFF0000)))]>, 4162 Requires<[IsARM, HasV6]>, 4163 Sched<[WriteALUsi, ReadALU]>; 4164 4165// Alternate cases for PKHBT where identities eliminate some nodes. 4166def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)), 4167 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>; 4168def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)), 4169 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>; 4170 4171// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 4172// will match the pattern below. 4173def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd), 4174 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh), 4175 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 4176 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000), 4177 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 4178 0xFFFF)))]>, 4179 Requires<[IsARM, HasV6]>, 4180 Sched<[WriteALUsi, ReadALU]>; 4181 4182// Alternate cases for PKHTB where identities eliminate some nodes. Note that 4183// a shift amount of 0 is *not legal* here, it is PKHBT instead. 4184// We also can not replace a srl (17..31) by an arithmetic shift we would use in 4185// pkhtb src1, src2, asr (17..31). 4186def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4187 (srl GPRnopc:$src2, imm16:$sh)), 4188 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>; 4189def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4190 (sra GPRnopc:$src2, imm16_31:$sh)), 4191 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>; 4192def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4193 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)), 4194 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>; 4195 4196//===----------------------------------------------------------------------===// 4197// CRC Instructions 4198// 4199// Polynomials: 4200// + CRC32{B,H,W} 0x04C11DB7 4201// + CRC32C{B,H,W} 0x1EDC6F41 4202// 4203 4204class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> 4205 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary, 4206 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm", 4207 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>, 4208 Requires<[IsARM, HasV8, HasCRC]> { 4209 bits<4> Rd; 4210 bits<4> Rn; 4211 bits<4> Rm; 4212 4213 let Inst{31-28} = 0b1110; 4214 let Inst{27-23} = 0b00010; 4215 let Inst{22-21} = sz; 4216 let Inst{20} = 0; 4217 let Inst{19-16} = Rn; 4218 let Inst{15-12} = Rd; 4219 let Inst{11-10} = 0b00; 4220 let Inst{9} = C; 4221 let Inst{8} = 0; 4222 let Inst{7-4} = 0b0100; 4223 let Inst{3-0} = Rm; 4224 4225 let Unpredictable{11-8} = 0b1101; 4226} 4227 4228def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>; 4229def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>; 4230def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>; 4231def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>; 4232def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>; 4233def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>; 4234 4235//===----------------------------------------------------------------------===// 4236// Comparison Instructions... 4237// 4238 4239defm CMP : AI1_cmp_irs<0b1010, "cmp", 4240 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, 4241 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 4242 4243// ARMcmpZ can re-use the above instruction definitions. 4244def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm), 4245 (CMPri GPR:$src, so_imm:$imm)>; 4246def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs), 4247 (CMPrr GPR:$src, GPR:$rhs)>; 4248def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs), 4249 (CMPrsi GPR:$src, so_reg_imm:$rhs)>; 4250def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs), 4251 (CMPrsr GPR:$src, so_reg_reg:$rhs)>; 4252 4253// CMN register-integer 4254let isCompare = 1, Defs = [CPSR] in { 4255def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi, 4256 "cmn", "\t$Rn, $imm", 4257 [(ARMcmn GPR:$Rn, so_imm:$imm)]>, 4258 Sched<[WriteCMP, ReadALU]> { 4259 bits<4> Rn; 4260 bits<12> imm; 4261 let Inst{25} = 1; 4262 let Inst{20} = 1; 4263 let Inst{19-16} = Rn; 4264 let Inst{15-12} = 0b0000; 4265 let Inst{11-0} = imm; 4266 4267 let Unpredictable{15-12} = 0b1111; 4268} 4269 4270// CMN register-register/shift 4271def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr, 4272 "cmn", "\t$Rn, $Rm", 4273 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4274 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { 4275 bits<4> Rn; 4276 bits<4> Rm; 4277 let isCommutable = 1; 4278 let Inst{25} = 0; 4279 let Inst{20} = 1; 4280 let Inst{19-16} = Rn; 4281 let Inst{15-12} = 0b0000; 4282 let Inst{11-4} = 0b00000000; 4283 let Inst{3-0} = Rm; 4284 4285 let Unpredictable{15-12} = 0b1111; 4286} 4287 4288def CMNzrsi : AI1<0b1011, (outs), 4289 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr, 4290 "cmn", "\t$Rn, $shift", 4291 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4292 GPR:$Rn, so_reg_imm:$shift)]>, 4293 Sched<[WriteCMPsi, ReadALU]> { 4294 bits<4> Rn; 4295 bits<12> shift; 4296 let Inst{25} = 0; 4297 let Inst{20} = 1; 4298 let Inst{19-16} = Rn; 4299 let Inst{15-12} = 0b0000; 4300 let Inst{11-5} = shift{11-5}; 4301 let Inst{4} = 0; 4302 let Inst{3-0} = shift{3-0}; 4303 4304 let Unpredictable{15-12} = 0b1111; 4305} 4306 4307def CMNzrsr : AI1<0b1011, (outs), 4308 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr, 4309 "cmn", "\t$Rn, $shift", 4310 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4311 GPRnopc:$Rn, so_reg_reg:$shift)]>, 4312 Sched<[WriteCMPsr, ReadALU]> { 4313 bits<4> Rn; 4314 bits<12> shift; 4315 let Inst{25} = 0; 4316 let Inst{20} = 1; 4317 let Inst{19-16} = Rn; 4318 let Inst{15-12} = 0b0000; 4319 let Inst{11-8} = shift{11-8}; 4320 let Inst{7} = 0; 4321 let Inst{6-5} = shift{6-5}; 4322 let Inst{4} = 1; 4323 let Inst{3-0} = shift{3-0}; 4324 4325 let Unpredictable{15-12} = 0b1111; 4326} 4327 4328} 4329 4330def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm), 4331 (CMNri GPR:$src, so_imm_neg:$imm)>; 4332 4333def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm), 4334 (CMNri GPR:$src, so_imm_neg:$imm)>; 4335 4336// Note that TST/TEQ don't set all the same flags that CMP does! 4337defm TST : AI1_cmp_irs<0b1000, "tst", 4338 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4339 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>; 4340defm TEQ : AI1_cmp_irs<0b1001, "teq", 4341 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4342 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>; 4343 4344// Pseudo i64 compares for some floating point compares. 4345let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, 4346 Defs = [CPSR] in { 4347def BCCi64 : PseudoInst<(outs), 4348 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), 4349 IIC_Br, 4350 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>, 4351 Sched<[WriteBr]>; 4352 4353def BCCZi64 : PseudoInst<(outs), 4354 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, 4355 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>, 4356 Sched<[WriteBr]>; 4357} // usesCustomInserter 4358 4359 4360// Conditional moves 4361let neverHasSideEffects = 1 in { 4362 4363let isCommutable = 1, isSelect = 1 in 4364def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), 4365 (ins GPR:$false, GPR:$Rm, cmovpred:$p), 4366 4, IIC_iCMOVr, 4367 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, 4368 cmovpred:$p))]>, 4369 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4370 4371def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd), 4372 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p), 4373 4, IIC_iCMOVsr, 4374 [(set GPR:$Rd, 4375 (ARMcmov GPR:$false, so_reg_imm:$shift, 4376 cmovpred:$p))]>, 4377 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4378def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd), 4379 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p), 4380 4, IIC_iCMOVsr, 4381 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, 4382 cmovpred:$p))]>, 4383 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4384 4385 4386let isMoveImm = 1 in 4387def MOVCCi16 4388 : ARMPseudoInst<(outs GPR:$Rd), 4389 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 4390 4, IIC_iMOVi, 4391 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm, 4392 cmovpred:$p))]>, 4393 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>, 4394 Sched<[WriteALU]>; 4395 4396let isMoveImm = 1 in 4397def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), 4398 (ins GPR:$false, so_imm:$imm, cmovpred:$p), 4399 4, IIC_iCMOVi, 4400 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, 4401 cmovpred:$p))]>, 4402 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4403 4404// Two instruction predicate mov immediate. 4405let isMoveImm = 1 in 4406def MOVCCi32imm 4407 : ARMPseudoInst<(outs GPR:$Rd), 4408 (ins GPR:$false, i32imm:$src, cmovpred:$p), 4409 8, IIC_iCMOVix2, 4410 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src, 4411 cmovpred:$p))]>, 4412 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; 4413 4414let isMoveImm = 1 in 4415def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), 4416 (ins GPR:$false, so_imm:$imm, cmovpred:$p), 4417 4, IIC_iCMOVi, 4418 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, 4419 cmovpred:$p))]>, 4420 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4421 4422} // neverHasSideEffects 4423 4424 4425//===----------------------------------------------------------------------===// 4426// Atomic operations intrinsics 4427// 4428 4429def MemBarrierOptOperand : AsmOperandClass { 4430 let Name = "MemBarrierOpt"; 4431 let ParserMethod = "parseMemBarrierOptOperand"; 4432} 4433def memb_opt : Operand<i32> { 4434 let PrintMethod = "printMemBOption"; 4435 let ParserMatchClass = MemBarrierOptOperand; 4436 let DecoderMethod = "DecodeMemBarrierOption"; 4437} 4438 4439def InstSyncBarrierOptOperand : AsmOperandClass { 4440 let Name = "InstSyncBarrierOpt"; 4441 let ParserMethod = "parseInstSyncBarrierOptOperand"; 4442} 4443def instsyncb_opt : Operand<i32> { 4444 let PrintMethod = "printInstSyncBOption"; 4445 let ParserMatchClass = InstSyncBarrierOptOperand; 4446 let DecoderMethod = "DecodeInstSyncBarrierOption"; 4447} 4448 4449// Memory barriers protect the atomic sequences 4450let hasSideEffects = 1 in { 4451def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4452 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, 4453 Requires<[IsARM, HasDB]> { 4454 bits<4> opt; 4455 let Inst{31-4} = 0xf57ff05; 4456 let Inst{3-0} = opt; 4457} 4458 4459def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4460 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, 4461 Requires<[IsARM, HasDB]> { 4462 bits<4> opt; 4463 let Inst{31-4} = 0xf57ff04; 4464 let Inst{3-0} = opt; 4465} 4466 4467// ISB has only full system option 4468def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary, 4469 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>, 4470 Requires<[IsARM, HasDB]> { 4471 bits<4> opt; 4472 let Inst{31-4} = 0xf57ff06; 4473 let Inst{3-0} = opt; 4474} 4475} 4476 4477let usesCustomInserter = 1, Defs = [CPSR] in { 4478 4479// Pseudo instruction that combines movs + predicated rsbmi 4480// to implement integer ABS 4481 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>; 4482} 4483 4484let usesCustomInserter = 1 in { 4485 def COPY_STRUCT_BYVAL_I32 : PseudoInst< 4486 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment), 4487 NoItinerary, 4488 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>; 4489} 4490 4491def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4492 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4493}]>; 4494 4495def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4496 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4497}]>; 4498 4499def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4500 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4501}]>; 4502 4503def strex_1 : PatFrag<(ops node:$val, node:$ptr), 4504 (int_arm_strex node:$val, node:$ptr), [{ 4505 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4506}]>; 4507 4508def strex_2 : PatFrag<(ops node:$val, node:$ptr), 4509 (int_arm_strex node:$val, node:$ptr), [{ 4510 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4511}]>; 4512 4513def strex_4 : PatFrag<(ops node:$val, node:$ptr), 4514 (int_arm_strex node:$val, node:$ptr), [{ 4515 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4516}]>; 4517 4518def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4519 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4520}]>; 4521 4522def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4523 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4524}]>; 4525 4526def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4527 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4528}]>; 4529 4530def stlex_1 : PatFrag<(ops node:$val, node:$ptr), 4531 (int_arm_stlex node:$val, node:$ptr), [{ 4532 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4533}]>; 4534 4535def stlex_2 : PatFrag<(ops node:$val, node:$ptr), 4536 (int_arm_stlex node:$val, node:$ptr), [{ 4537 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4538}]>; 4539 4540def stlex_4 : PatFrag<(ops node:$val, node:$ptr), 4541 (int_arm_stlex node:$val, node:$ptr), [{ 4542 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4543}]>; 4544 4545let mayLoad = 1 in { 4546def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4547 NoItinerary, "ldrexb", "\t$Rt, $addr", 4548 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; 4549def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4550 NoItinerary, "ldrexh", "\t$Rt, $addr", 4551 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>; 4552def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4553 NoItinerary, "ldrex", "\t$Rt, $addr", 4554 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>; 4555let hasExtraDefRegAllocReq = 1 in 4556def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4557 NoItinerary, "ldrexd", "\t$Rt, $addr", []> { 4558 let DecoderMethod = "DecodeDoubleRegLoad"; 4559} 4560 4561def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4562 NoItinerary, "ldaexb", "\t$Rt, $addr", 4563 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>; 4564def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4565 NoItinerary, "ldaexh", "\t$Rt, $addr", 4566 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>; 4567def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4568 NoItinerary, "ldaex", "\t$Rt, $addr", 4569 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>; 4570let hasExtraDefRegAllocReq = 1 in 4571def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4572 NoItinerary, "ldaexd", "\t$Rt, $addr", []> { 4573 let DecoderMethod = "DecodeDoubleRegLoad"; 4574} 4575} 4576 4577let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 4578def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4579 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", 4580 [(set GPR:$Rd, (strex_1 GPR:$Rt, 4581 addr_offset_none:$addr))]>; 4582def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4583 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", 4584 [(set GPR:$Rd, (strex_2 GPR:$Rt, 4585 addr_offset_none:$addr))]>; 4586def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4587 NoItinerary, "strex", "\t$Rd, $Rt, $addr", 4588 [(set GPR:$Rd, (strex_4 GPR:$Rt, 4589 addr_offset_none:$addr))]>; 4590let hasExtraSrcRegAllocReq = 1 in 4591def STREXD : AIstrex<0b01, (outs GPR:$Rd), 4592 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 4593 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { 4594 let DecoderMethod = "DecodeDoubleRegStore"; 4595} 4596def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4597 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr", 4598 [(set GPR:$Rd, 4599 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>; 4600def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4601 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr", 4602 [(set GPR:$Rd, 4603 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>; 4604def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4605 NoItinerary, "stlex", "\t$Rd, $Rt, $addr", 4606 [(set GPR:$Rd, 4607 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>; 4608let hasExtraSrcRegAllocReq = 1 in 4609def STLEXD : AIstlex<0b01, (outs GPR:$Rd), 4610 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 4611 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> { 4612 let DecoderMethod = "DecodeDoubleRegStore"; 4613} 4614} 4615 4616def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", 4617 [(int_arm_clrex)]>, 4618 Requires<[IsARM, HasV6]> { 4619 let Inst{31-0} = 0b11110101011111111111000000011111; 4620} 4621 4622def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 4623 (STREXB GPR:$Rt, addr_offset_none:$addr)>; 4624def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 4625 (STREXH GPR:$Rt, addr_offset_none:$addr)>; 4626 4627def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 4628 (STLEXB GPR:$Rt, addr_offset_none:$addr)>; 4629def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 4630 (STLEXH GPR:$Rt, addr_offset_none:$addr)>; 4631 4632class acquiring_load<PatFrag base> 4633 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 4634 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 4635 return Ordering == Acquire || Ordering == SequentiallyConsistent; 4636}]>; 4637 4638def atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 4639def atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 4640def atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 4641 4642class releasing_store<PatFrag base> 4643 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 4644 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 4645 return Ordering == Release || Ordering == SequentiallyConsistent; 4646}]>; 4647 4648def atomic_store_release_8 : releasing_store<atomic_store_8>; 4649def atomic_store_release_16 : releasing_store<atomic_store_16>; 4650def atomic_store_release_32 : releasing_store<atomic_store_32>; 4651 4652let AddedComplexity = 8 in { 4653 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>; 4654 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>; 4655 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>; 4656 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>; 4657 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>; 4658 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>; 4659} 4660 4661// SWP/SWPB are deprecated in V6/V7. 4662let mayLoad = 1, mayStore = 1 in { 4663def SWP : AIswp<0, (outs GPRnopc:$Rt), 4664 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>, 4665 Requires<[PreV8]>; 4666def SWPB: AIswp<1, (outs GPRnopc:$Rt), 4667 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>, 4668 Requires<[PreV8]>; 4669} 4670 4671//===----------------------------------------------------------------------===// 4672// Coprocessor Instructions. 4673// 4674 4675def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4676 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4677 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4678 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4679 imm:$CRm, imm:$opc2)]>, 4680 Requires<[PreV8]> { 4681 bits<4> opc1; 4682 bits<4> CRn; 4683 bits<4> CRd; 4684 bits<4> cop; 4685 bits<3> opc2; 4686 bits<4> CRm; 4687 4688 let Inst{3-0} = CRm; 4689 let Inst{4} = 0; 4690 let Inst{7-5} = opc2; 4691 let Inst{11-8} = cop; 4692 let Inst{15-12} = CRd; 4693 let Inst{19-16} = CRn; 4694 let Inst{23-20} = opc1; 4695} 4696 4697def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4698 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4699 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4700 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4701 imm:$CRm, imm:$opc2)]>, 4702 Requires<[PreV8]> { 4703 let Inst{31-28} = 0b1111; 4704 bits<4> opc1; 4705 bits<4> CRn; 4706 bits<4> CRd; 4707 bits<4> cop; 4708 bits<3> opc2; 4709 bits<4> CRm; 4710 4711 let Inst{3-0} = CRm; 4712 let Inst{4} = 0; 4713 let Inst{7-5} = opc2; 4714 let Inst{11-8} = cop; 4715 let Inst{15-12} = CRd; 4716 let Inst{19-16} = CRn; 4717 let Inst{23-20} = opc1; 4718} 4719 4720class ACI<dag oops, dag iops, string opc, string asm, 4721 IndexMode im = IndexModeNone> 4722 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 4723 opc, asm, "", []> { 4724 let Inst{27-25} = 0b110; 4725} 4726class ACInoP<dag oops, dag iops, string opc, string asm, 4727 IndexMode im = IndexModeNone> 4728 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 4729 opc, asm, "", []> { 4730 let Inst{31-28} = 0b1111; 4731 let Inst{27-25} = 0b110; 4732} 4733multiclass LdStCop<bit load, bit Dbit, string asm> { 4734 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4735 asm, "\t$cop, $CRd, $addr"> { 4736 bits<13> addr; 4737 bits<4> cop; 4738 bits<4> CRd; 4739 let Inst{24} = 1; // P = 1 4740 let Inst{23} = addr{8}; 4741 let Inst{22} = Dbit; 4742 let Inst{21} = 0; // W = 0 4743 let Inst{20} = load; 4744 let Inst{19-16} = addr{12-9}; 4745 let Inst{15-12} = CRd; 4746 let Inst{11-8} = cop; 4747 let Inst{7-0} = addr{7-0}; 4748 let DecoderMethod = "DecodeCopMemInstruction"; 4749 } 4750 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 4751 asm, "\t$cop, $CRd, $addr!", IndexModePre> { 4752 bits<13> addr; 4753 bits<4> cop; 4754 bits<4> CRd; 4755 let Inst{24} = 1; // P = 1 4756 let Inst{23} = addr{8}; 4757 let Inst{22} = Dbit; 4758 let Inst{21} = 1; // W = 1 4759 let Inst{20} = load; 4760 let Inst{19-16} = addr{12-9}; 4761 let Inst{15-12} = CRd; 4762 let Inst{11-8} = cop; 4763 let Inst{7-0} = addr{7-0}; 4764 let DecoderMethod = "DecodeCopMemInstruction"; 4765 } 4766 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4767 postidx_imm8s4:$offset), 4768 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> { 4769 bits<9> offset; 4770 bits<4> addr; 4771 bits<4> cop; 4772 bits<4> CRd; 4773 let Inst{24} = 0; // P = 0 4774 let Inst{23} = offset{8}; 4775 let Inst{22} = Dbit; 4776 let Inst{21} = 1; // W = 1 4777 let Inst{20} = load; 4778 let Inst{19-16} = addr; 4779 let Inst{15-12} = CRd; 4780 let Inst{11-8} = cop; 4781 let Inst{7-0} = offset{7-0}; 4782 let DecoderMethod = "DecodeCopMemInstruction"; 4783 } 4784 def _OPTION : ACI<(outs), 4785 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4786 coproc_option_imm:$option), 4787 asm, "\t$cop, $CRd, $addr, $option"> { 4788 bits<8> option; 4789 bits<4> addr; 4790 bits<4> cop; 4791 bits<4> CRd; 4792 let Inst{24} = 0; // P = 0 4793 let Inst{23} = 1; // U = 1 4794 let Inst{22} = Dbit; 4795 let Inst{21} = 0; // W = 0 4796 let Inst{20} = load; 4797 let Inst{19-16} = addr; 4798 let Inst{15-12} = CRd; 4799 let Inst{11-8} = cop; 4800 let Inst{7-0} = option; 4801 let DecoderMethod = "DecodeCopMemInstruction"; 4802 } 4803} 4804multiclass LdSt2Cop<bit load, bit Dbit, string asm> { 4805 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4806 asm, "\t$cop, $CRd, $addr"> { 4807 bits<13> addr; 4808 bits<4> cop; 4809 bits<4> CRd; 4810 let Inst{24} = 1; // P = 1 4811 let Inst{23} = addr{8}; 4812 let Inst{22} = Dbit; 4813 let Inst{21} = 0; // W = 0 4814 let Inst{20} = load; 4815 let Inst{19-16} = addr{12-9}; 4816 let Inst{15-12} = CRd; 4817 let Inst{11-8} = cop; 4818 let Inst{7-0} = addr{7-0}; 4819 let DecoderMethod = "DecodeCopMemInstruction"; 4820 } 4821 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 4822 asm, "\t$cop, $CRd, $addr!", IndexModePre> { 4823 bits<13> addr; 4824 bits<4> cop; 4825 bits<4> CRd; 4826 let Inst{24} = 1; // P = 1 4827 let Inst{23} = addr{8}; 4828 let Inst{22} = Dbit; 4829 let Inst{21} = 1; // W = 1 4830 let Inst{20} = load; 4831 let Inst{19-16} = addr{12-9}; 4832 let Inst{15-12} = CRd; 4833 let Inst{11-8} = cop; 4834 let Inst{7-0} = addr{7-0}; 4835 let DecoderMethod = "DecodeCopMemInstruction"; 4836 } 4837 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4838 postidx_imm8s4:$offset), 4839 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> { 4840 bits<9> offset; 4841 bits<4> addr; 4842 bits<4> cop; 4843 bits<4> CRd; 4844 let Inst{24} = 0; // P = 0 4845 let Inst{23} = offset{8}; 4846 let Inst{22} = Dbit; 4847 let Inst{21} = 1; // W = 1 4848 let Inst{20} = load; 4849 let Inst{19-16} = addr; 4850 let Inst{15-12} = CRd; 4851 let Inst{11-8} = cop; 4852 let Inst{7-0} = offset{7-0}; 4853 let DecoderMethod = "DecodeCopMemInstruction"; 4854 } 4855 def _OPTION : ACInoP<(outs), 4856 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4857 coproc_option_imm:$option), 4858 asm, "\t$cop, $CRd, $addr, $option"> { 4859 bits<8> option; 4860 bits<4> addr; 4861 bits<4> cop; 4862 bits<4> CRd; 4863 let Inst{24} = 0; // P = 0 4864 let Inst{23} = 1; // U = 1 4865 let Inst{22} = Dbit; 4866 let Inst{21} = 0; // W = 0 4867 let Inst{20} = load; 4868 let Inst{19-16} = addr; 4869 let Inst{15-12} = CRd; 4870 let Inst{11-8} = cop; 4871 let Inst{7-0} = option; 4872 let DecoderMethod = "DecodeCopMemInstruction"; 4873 } 4874} 4875 4876defm LDC : LdStCop <1, 0, "ldc">; 4877defm LDCL : LdStCop <1, 1, "ldcl">; 4878defm STC : LdStCop <0, 0, "stc">; 4879defm STCL : LdStCop <0, 1, "stcl">; 4880defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>; 4881defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>; 4882defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>; 4883defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>; 4884 4885//===----------------------------------------------------------------------===// 4886// Move between coprocessor and ARM core register. 4887// 4888 4889class MovRCopro<string opc, bit direction, dag oops, dag iops, 4890 list<dag> pattern> 4891 : ABI<0b1110, oops, iops, NoItinerary, opc, 4892 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> { 4893 let Inst{20} = direction; 4894 let Inst{4} = 1; 4895 4896 bits<4> Rt; 4897 bits<4> cop; 4898 bits<3> opc1; 4899 bits<3> opc2; 4900 bits<4> CRm; 4901 bits<4> CRn; 4902 4903 let Inst{15-12} = Rt; 4904 let Inst{11-8} = cop; 4905 let Inst{23-21} = opc1; 4906 let Inst{7-5} = opc2; 4907 let Inst{3-0} = CRm; 4908 let Inst{19-16} = CRn; 4909} 4910 4911def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, 4912 (outs), 4913 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4914 c_imm:$CRm, imm0_7:$opc2), 4915 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4916 imm:$CRm, imm:$opc2)]>, 4917 ComplexDeprecationPredicate<"MCR">; 4918def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 4919 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4920 c_imm:$CRm, 0, pred:$p)>; 4921def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, 4922 (outs GPRwithAPSR:$Rt), 4923 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 4924 imm0_7:$opc2), []>; 4925def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 4926 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4927 c_imm:$CRm, 0, pred:$p)>; 4928 4929def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 4930 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 4931 4932class MovRCopro2<string opc, bit direction, dag oops, dag iops, 4933 list<dag> pattern> 4934 : ABXI<0b1110, oops, iops, NoItinerary, 4935 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { 4936 let Inst{31-24} = 0b11111110; 4937 let Inst{20} = direction; 4938 let Inst{4} = 1; 4939 4940 bits<4> Rt; 4941 bits<4> cop; 4942 bits<3> opc1; 4943 bits<3> opc2; 4944 bits<4> CRm; 4945 bits<4> CRn; 4946 4947 let Inst{15-12} = Rt; 4948 let Inst{11-8} = cop; 4949 let Inst{23-21} = opc1; 4950 let Inst{7-5} = opc2; 4951 let Inst{3-0} = CRm; 4952 let Inst{19-16} = CRn; 4953} 4954 4955def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, 4956 (outs), 4957 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4958 c_imm:$CRm, imm0_7:$opc2), 4959 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4960 imm:$CRm, imm:$opc2)]>, 4961 Requires<[PreV8]>; 4962def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm", 4963 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4964 c_imm:$CRm, 0)>; 4965def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, 4966 (outs GPRwithAPSR:$Rt), 4967 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 4968 imm0_7:$opc2), []>, 4969 Requires<[PreV8]>; 4970def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm", 4971 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4972 c_imm:$CRm, 0)>; 4973 4974def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, 4975 imm:$CRm, imm:$opc2), 4976 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 4977 4978class MovRRCopro<string opc, bit direction, list<dag> pattern = []> 4979 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4980 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), 4981 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> { 4982 let Inst{23-21} = 0b010; 4983 let Inst{20} = direction; 4984 4985 bits<4> Rt; 4986 bits<4> Rt2; 4987 bits<4> cop; 4988 bits<4> opc1; 4989 bits<4> CRm; 4990 4991 let Inst{15-12} = Rt; 4992 let Inst{19-16} = Rt2; 4993 let Inst{11-8} = cop; 4994 let Inst{7-4} = opc1; 4995 let Inst{3-0} = CRm; 4996} 4997 4998def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */, 4999 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt, 5000 GPRnopc:$Rt2, imm:$CRm)]>; 5001def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>; 5002 5003class MovRRCopro2<string opc, bit direction, list<dag> pattern = []> 5004 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5005 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary, 5006 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>, 5007 Requires<[PreV8]> { 5008 let Inst{31-28} = 0b1111; 5009 let Inst{23-21} = 0b010; 5010 let Inst{20} = direction; 5011 5012 bits<4> Rt; 5013 bits<4> Rt2; 5014 bits<4> cop; 5015 bits<4> opc1; 5016 bits<4> CRm; 5017 5018 let Inst{15-12} = Rt; 5019 let Inst{19-16} = Rt2; 5020 let Inst{11-8} = cop; 5021 let Inst{7-4} = opc1; 5022 let Inst{3-0} = CRm; 5023 5024 let DecoderMethod = "DecodeMRRC2"; 5025} 5026 5027def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */, 5028 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt, 5029 GPRnopc:$Rt2, imm:$CRm)]>; 5030def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>; 5031 5032//===----------------------------------------------------------------------===// 5033// Move between special register and ARM core register 5034// 5035 5036// Move to ARM core register from Special Register 5037def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5038 "mrs", "\t$Rd, apsr", []> { 5039 bits<4> Rd; 5040 let Inst{23-16} = 0b00001111; 5041 let Unpredictable{19-17} = 0b111; 5042 5043 let Inst{15-12} = Rd; 5044 5045 let Inst{11-0} = 0b000000000000; 5046 let Unpredictable{11-0} = 0b110100001111; 5047} 5048 5049def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>, 5050 Requires<[IsARM]>; 5051 5052// The MRSsys instruction is the MRS instruction from the ARM ARM, 5053// section B9.3.9, with the R bit set to 1. 5054def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5055 "mrs", "\t$Rd, spsr", []> { 5056 bits<4> Rd; 5057 let Inst{23-16} = 0b01001111; 5058 let Unpredictable{19-16} = 0b1111; 5059 5060 let Inst{15-12} = Rd; 5061 5062 let Inst{11-0} = 0b000000000000; 5063 let Unpredictable{11-0} = 0b110100001111; 5064} 5065 5066// Move from ARM core register to Special Register 5067// 5068// No need to have both system and application versions, the encodings are the 5069// same and the assembly parser has no way to distinguish between them. The mask 5070// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains 5071// the mask with the fields to be accessed in the special register. 5072def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, 5073 "msr", "\t$mask, $Rn", []> { 5074 bits<5> mask; 5075 bits<4> Rn; 5076 5077 let Inst{23} = 0; 5078 let Inst{22} = mask{4}; // R bit 5079 let Inst{21-20} = 0b10; 5080 let Inst{19-16} = mask{3-0}; 5081 let Inst{15-12} = 0b1111; 5082 let Inst{11-4} = 0b00000000; 5083 let Inst{3-0} = Rn; 5084} 5085 5086def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary, 5087 "msr", "\t$mask, $a", []> { 5088 bits<5> mask; 5089 bits<12> a; 5090 5091 let Inst{23} = 0; 5092 let Inst{22} = mask{4}; // R bit 5093 let Inst{21-20} = 0b10; 5094 let Inst{19-16} = mask{3-0}; 5095 let Inst{15-12} = 0b1111; 5096 let Inst{11-0} = a; 5097} 5098 5099// Dynamic stack allocation yields a _chkstk for Windows targets. These calls 5100// are needed to probe the stack when allocating more than 5101// 4k bytes in one go. Touching the stack at 4K increments is necessary to 5102// ensure that the guard pages used by the OS virtual memory manager are 5103// allocated in correct sequence. 5104// The main point of having separate instruction are extra unmodelled effects 5105// (compared to ordinary calls) like stack pointer change. 5106 5107def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone, 5108 [SDNPHasChain, SDNPSideEffect]>; 5109let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in 5110 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>; 5111 5112//===----------------------------------------------------------------------===// 5113// TLS Instructions 5114// 5115 5116// __aeabi_read_tp preserves the registers r1-r3. 5117// This is a pseudo inst so that we can get the encoding right, 5118// complete with fixup for the aeabi_read_tp function. 5119// TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern 5120// is defined in "ARMInstrThumb.td". 5121let isCall = 1, 5122 Defs = [R0, R12, LR, CPSR], Uses = [SP] in { 5123 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br, 5124 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>; 5125} 5126 5127//===----------------------------------------------------------------------===// 5128// SJLJ Exception handling intrinsics 5129// eh_sjlj_setjmp() is an instruction sequence to store the return 5130// address and save #0 in R0 for the non-longjmp case. 5131// Since by its nature we may be coming from some other function to get 5132// here, and we're using the stack frame for the containing function to 5133// save/restore registers, we can't keep anything live in regs across 5134// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 5135// when we get here from a longjmp(). We force everything out of registers 5136// except for our own input by listing the relevant registers in Defs. By 5137// doing so, we also cause the prologue/epilogue code to actively preserve 5138// all of the callee-saved resgisters, which is exactly what we want. 5139// A constant value is passed in $val, and we use the location as a scratch. 5140// 5141// These are pseudo-instructions and are lowered to individual MC-insts, so 5142// no encoding information is necessary. 5143let Defs = 5144 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 5145 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], 5146 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5147 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5148 NoItinerary, 5149 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5150 Requires<[IsARM, HasVFP2]>; 5151} 5152 5153let Defs = 5154 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 5155 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5156 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5157 NoItinerary, 5158 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5159 Requires<[IsARM, NoVFP]>; 5160} 5161 5162// FIXME: Non-IOS version(s) 5163let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, 5164 Defs = [ R7, LR, SP ] in { 5165def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), 5166 NoItinerary, 5167 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 5168 Requires<[IsARM, IsIOS]>; 5169} 5170 5171// eh.sjlj.dispatchsetup pseudo-instruction. 5172// This pseudo is used for both ARM and Thumb. Any differences are handled when 5173// the pseudo is expanded (which happens before any passes that need the 5174// instruction size). 5175let isBarrier = 1 in 5176def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 5177 5178 5179//===----------------------------------------------------------------------===// 5180// Non-Instruction Patterns 5181// 5182 5183// ARMv4 indirect branch using (MOVr PC, dst) 5184let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 5185 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), 5186 4, IIC_Br, [(brind GPR:$dst)], 5187 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5188 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5189 5190// Large immediate handling. 5191 5192// 32-bit immediate using two piece so_imms or movw + movt. 5193// This is a single pseudo instruction, the benefit is that it can be remat'd 5194// as a single unit instead of having to handle reg inputs. 5195// FIXME: Remove this when we can do generalized remat. 5196let isReMaterializable = 1, isMoveImm = 1 in 5197def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 5198 [(set GPR:$dst, (arm_i32imm:$src))]>, 5199 Requires<[IsARM]>; 5200 5201def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i, 5202 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>, 5203 Requires<[IsARM, DontUseMovt]>; 5204 5205// Pseudo instruction that combines movw + movt + add pc (if PIC). 5206// It also makes it possible to rematerialize the instructions. 5207// FIXME: Remove this when we can do generalized remat and when machine licm 5208// can properly the instructions. 5209let isReMaterializable = 1 in { 5210def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5211 IIC_iMOVix2addpc, 5212 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 5213 Requires<[IsARM, UseMovt]>; 5214 5215def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5216 IIC_iLoadiALU, 5217 [(set GPR:$dst, 5218 (ARMWrapperPIC tglobaladdr:$addr))]>, 5219 Requires<[IsARM, DontUseMovt]>; 5220 5221def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5222 NoItinerary, 5223 [(set GPR:$dst, 5224 (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5225 Requires<[IsARM, DontUseMovt]>; 5226 5227let AddedComplexity = 10 in 5228def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5229 IIC_iMOVix2ld, 5230 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5231 Requires<[IsARM, UseMovt]>; 5232} // isReMaterializable 5233 5234// ConstantPool, GlobalAddress, and JumpTable 5235def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 5236def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 5237 Requires<[IsARM, UseMovt]>; 5238def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id), 5239 (LEApcrelJT tjumptable:$dst, imm:$id)>; 5240 5241// TODO: add,sub,and, 3-instr forms? 5242 5243// Tail calls. These patterns also apply to Thumb mode. 5244def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>; 5245def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>; 5246def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>; 5247 5248// Direct calls 5249def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 5250def : ARMPat<(ARMcall_nolink texternalsym:$func), 5251 (BMOVPCB_CALL texternalsym:$func)>; 5252 5253// zextload i1 -> zextload i8 5254def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5255def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5256 5257// extload -> zextload 5258def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5259def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5260def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5261def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5262 5263def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 5264 5265def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 5266def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 5267 5268// smul* and smla* 5269def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5270 (sra (shl GPR:$b, (i32 16)), (i32 16))), 5271 (SMULBB GPR:$a, GPR:$b)>; 5272def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 5273 (SMULBB GPR:$a, GPR:$b)>; 5274def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5275 (sra GPR:$b, (i32 16))), 5276 (SMULBT GPR:$a, GPR:$b)>; 5277def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))), 5278 (SMULBT GPR:$a, GPR:$b)>; 5279def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), 5280 (sra (shl GPR:$b, (i32 16)), (i32 16))), 5281 (SMULTB GPR:$a, GPR:$b)>; 5282def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b), 5283 (SMULTB GPR:$a, GPR:$b)>; 5284def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), 5285 (i32 16)), 5286 (SMULWB GPR:$a, GPR:$b)>; 5287def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)), 5288 (SMULWB GPR:$a, GPR:$b)>; 5289 5290def : ARMV5MOPat<(add GPR:$acc, 5291 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5292 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 5293 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5294def : ARMV5MOPat<(add GPR:$acc, 5295 (mul sext_16_node:$a, sext_16_node:$b)), 5296 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5297def : ARMV5MOPat<(add GPR:$acc, 5298 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5299 (sra GPR:$b, (i32 16)))), 5300 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5301def : ARMV5MOPat<(add GPR:$acc, 5302 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))), 5303 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5304def : ARMV5MOPat<(add GPR:$acc, 5305 (mul (sra GPR:$a, (i32 16)), 5306 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 5307 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5308def : ARMV5MOPat<(add GPR:$acc, 5309 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)), 5310 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5311def : ARMV5MOPat<(add GPR:$acc, 5312 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), 5313 (i32 16))), 5314 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 5315def : ARMV5MOPat<(add GPR:$acc, 5316 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))), 5317 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 5318 5319 5320// Pre-v7 uses MCR for synchronization barriers. 5321def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, 5322 Requires<[IsARM, HasV6]>; 5323 5324// SXT/UXT with no rotate 5325let AddedComplexity = 16 in { 5326def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; 5327def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; 5328def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; 5329def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), 5330 (UXTAB GPR:$Rn, GPR:$Rm, 0)>; 5331def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), 5332 (UXTAH GPR:$Rn, GPR:$Rm, 0)>; 5333} 5334 5335def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; 5336def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; 5337 5338def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)), 5339 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>; 5340def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), 5341 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; 5342 5343// Atomic load/store patterns 5344def : ARMPat<(atomic_load_8 ldst_so_reg:$src), 5345 (LDRBrs ldst_so_reg:$src)>; 5346def : ARMPat<(atomic_load_8 addrmode_imm12:$src), 5347 (LDRBi12 addrmode_imm12:$src)>; 5348def : ARMPat<(atomic_load_16 addrmode3:$src), 5349 (LDRH addrmode3:$src)>; 5350def : ARMPat<(atomic_load_32 ldst_so_reg:$src), 5351 (LDRrs ldst_so_reg:$src)>; 5352def : ARMPat<(atomic_load_32 addrmode_imm12:$src), 5353 (LDRi12 addrmode_imm12:$src)>; 5354def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), 5355 (STRBrs GPR:$val, ldst_so_reg:$ptr)>; 5356def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), 5357 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; 5358def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), 5359 (STRH GPR:$val, addrmode3:$ptr)>; 5360def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), 5361 (STRrs GPR:$val, ldst_so_reg:$ptr)>; 5362def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), 5363 (STRi12 GPR:$val, addrmode_imm12:$ptr)>; 5364 5365 5366//===----------------------------------------------------------------------===// 5367// Thumb Support 5368// 5369 5370include "ARMInstrThumb.td" 5371 5372//===----------------------------------------------------------------------===// 5373// Thumb2 Support 5374// 5375 5376include "ARMInstrThumb2.td" 5377 5378//===----------------------------------------------------------------------===// 5379// Floating Point Support 5380// 5381 5382include "ARMInstrVFP.td" 5383 5384//===----------------------------------------------------------------------===// 5385// Advanced SIMD (NEON) Support 5386// 5387 5388include "ARMInstrNEON.td" 5389 5390//===----------------------------------------------------------------------===// 5391// Assembler aliases 5392// 5393 5394// Memory barriers 5395def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>; 5396def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>; 5397def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>; 5398 5399// System instructions 5400def : MnemonicAlias<"swi", "svc">; 5401 5402// Load / Store Multiple 5403def : MnemonicAlias<"ldmfd", "ldm">; 5404def : MnemonicAlias<"ldmia", "ldm">; 5405def : MnemonicAlias<"ldmea", "ldmdb">; 5406def : MnemonicAlias<"stmfd", "stmdb">; 5407def : MnemonicAlias<"stmia", "stm">; 5408def : MnemonicAlias<"stmea", "stm">; 5409 5410// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the 5411// shift amount is zero (i.e., unspecified). 5412def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 5413 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>, 5414 Requires<[IsARM, HasV6]>; 5415def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 5416 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>, 5417 Requires<[IsARM, HasV6]>; 5418 5419// PUSH/POP aliases for STM/LDM 5420def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; 5421def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; 5422 5423// SSAT/USAT optional shift operand. 5424def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 5425 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5426def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", 5427 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5428 5429 5430// Extend instruction optional rotate operand. 5431def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", 5432 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5433def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", 5434 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5435def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 5436 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5437def : ARMInstAlias<"sxtb${p} $Rd, $Rm", 5438 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5439def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", 5440 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5441def : ARMInstAlias<"sxth${p} $Rd, $Rm", 5442 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5443 5444def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", 5445 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5446def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", 5447 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5448def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 5449 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5450def : ARMInstAlias<"uxtb${p} $Rd, $Rm", 5451 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5452def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", 5453 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5454def : ARMInstAlias<"uxth${p} $Rd, $Rm", 5455 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5456 5457 5458// RFE aliases 5459def : MnemonicAlias<"rfefa", "rfeda">; 5460def : MnemonicAlias<"rfeea", "rfedb">; 5461def : MnemonicAlias<"rfefd", "rfeia">; 5462def : MnemonicAlias<"rfeed", "rfeib">; 5463def : MnemonicAlias<"rfe", "rfeia">; 5464 5465// SRS aliases 5466def : MnemonicAlias<"srsfa", "srsib">; 5467def : MnemonicAlias<"srsea", "srsia">; 5468def : MnemonicAlias<"srsfd", "srsdb">; 5469def : MnemonicAlias<"srsed", "srsda">; 5470def : MnemonicAlias<"srs", "srsia">; 5471 5472// QSAX == QSUBADDX 5473def : MnemonicAlias<"qsubaddx", "qsax">; 5474// SASX == SADDSUBX 5475def : MnemonicAlias<"saddsubx", "sasx">; 5476// SHASX == SHADDSUBX 5477def : MnemonicAlias<"shaddsubx", "shasx">; 5478// SHSAX == SHSUBADDX 5479def : MnemonicAlias<"shsubaddx", "shsax">; 5480// SSAX == SSUBADDX 5481def : MnemonicAlias<"ssubaddx", "ssax">; 5482// UASX == UADDSUBX 5483def : MnemonicAlias<"uaddsubx", "uasx">; 5484// UHASX == UHADDSUBX 5485def : MnemonicAlias<"uhaddsubx", "uhasx">; 5486// UHSAX == UHSUBADDX 5487def : MnemonicAlias<"uhsubaddx", "uhsax">; 5488// UQASX == UQADDSUBX 5489def : MnemonicAlias<"uqaddsubx", "uqasx">; 5490// UQSAX == UQSUBADDX 5491def : MnemonicAlias<"uqsubaddx", "uqsax">; 5492// USAX == USUBADDX 5493def : MnemonicAlias<"usubaddx", "usax">; 5494 5495// "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like 5496// for isel. 5497def : ARMInstAlias<"mov${s}${p} $Rd, $imm", 5498 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>; 5499def : ARMInstAlias<"mvn${s}${p} $Rd, $imm", 5500 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>; 5501// Same for AND <--> BIC 5502def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm", 5503 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm, 5504 pred:$p, cc_out:$s)>; 5505def : ARMInstAlias<"bic${s}${p} $Rdn, $imm", 5506 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm, 5507 pred:$p, cc_out:$s)>; 5508def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm", 5509 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm, 5510 pred:$p, cc_out:$s)>; 5511def : ARMInstAlias<"and${s}${p} $Rdn, $imm", 5512 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm, 5513 pred:$p, cc_out:$s)>; 5514 5515// Likewise, "add Rd, so_imm_neg" -> sub 5516def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm", 5517 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>; 5518def : ARMInstAlias<"add${s}${p} $Rd, $imm", 5519 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>; 5520// Same for CMP <--> CMN via so_imm_neg 5521def : ARMInstAlias<"cmp${p} $Rd, $imm", 5522 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>; 5523def : ARMInstAlias<"cmn${p} $Rd, $imm", 5524 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>; 5525 5526// The shifter forms of the MOV instruction are aliased to the ASR, LSL, 5527// LSR, ROR, and RRX instructions. 5528// FIXME: We need C++ parser hooks to map the alias to the MOV 5529// encoding. It seems we should be able to do that sort of thing 5530// in tblgen, but it could get ugly. 5531let TwoOperandAliasConstraint = "$Rm = $Rd" in { 5532def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", 5533 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 5534 cc_out:$s)>; 5535def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm", 5536 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 5537 cc_out:$s)>; 5538def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", 5539 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 5540 cc_out:$s)>; 5541def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", 5542 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 5543 cc_out:$s)>; 5544} 5545def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", 5546 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>; 5547let TwoOperandAliasConstraint = "$Rn = $Rd" in { 5548def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", 5549 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5550 cc_out:$s)>; 5551def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm", 5552 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5553 cc_out:$s)>; 5554def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm", 5555 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5556 cc_out:$s)>; 5557def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm", 5558 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5559 cc_out:$s)>; 5560} 5561 5562// "neg" is and alias for "rsb rd, rn, #0" 5563def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", 5564 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; 5565 5566// Pre-v6, 'mov r0, r0' was used as a NOP encoding. 5567def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>, 5568 Requires<[IsARM, NoV6]>; 5569 5570// MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but 5571// the instruction definitions need difference constraints pre-v6. 5572// Use these aliases for the assembly parsing on pre-v6. 5573def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm", 5574 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 5575 Requires<[IsARM, NoV6]>; 5576def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra", 5577 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 5578 pred:$p, cc_out:$s)>, 5579 Requires<[IsARM, NoV6]>; 5580def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5581 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5582 Requires<[IsARM, NoV6]>; 5583def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5584 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5585 Requires<[IsARM, NoV6]>; 5586def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5587 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5588 Requires<[IsARM, NoV6]>; 5589def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5590 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5591 Requires<[IsARM, NoV6]>; 5592 5593// 'it' blocks in ARM mode just validate the predicates. The IT itself 5594// is discarded. 5595def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>, 5596 ComplexDeprecationPredicate<"IT">; 5597