1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // the post-regalloc scheduling pass.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "ARM.h"
18 #include "ARMBaseInstrInfo.h"
19 #include "ARMBaseRegisterInfo.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMSubtarget.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/CodeGen/LivePhysRegs.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineInstrBundle.h"
29 #include "llvm/IR/GlobalValue.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
32 #include "llvm/Target/TargetFrameLowering.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "arm-pseudo"
38 
39 static cl::opt<bool>
40 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
41                 cl::desc("Verify machine code after expanding ARM pseudos"));
42 
43 namespace {
44   class ARMExpandPseudo : public MachineFunctionPass {
45   public:
46     static char ID;
47     ARMExpandPseudo() : MachineFunctionPass(ID) {}
48 
49     const ARMBaseInstrInfo *TII;
50     const TargetRegisterInfo *TRI;
51     const ARMSubtarget *STI;
52     ARMFunctionInfo *AFI;
53 
54     bool runOnMachineFunction(MachineFunction &Fn) override;
55 
56     MachineFunctionProperties getRequiredProperties() const override {
57       return MachineFunctionProperties().set(
58           MachineFunctionProperties::Property::NoVRegs);
59     }
60 
61     StringRef getPassName() const override {
62       return "ARM pseudo instruction expansion pass";
63     }
64 
65   private:
66     void TransferImpOps(MachineInstr &OldMI,
67                         MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
68     bool ExpandMI(MachineBasicBlock &MBB,
69                   MachineBasicBlock::iterator MBBI,
70                   MachineBasicBlock::iterator &NextMBBI);
71     bool ExpandMBB(MachineBasicBlock &MBB);
72     void ExpandVLD(MachineBasicBlock::iterator &MBBI);
73     void ExpandVST(MachineBasicBlock::iterator &MBBI);
74     void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
75     void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
76                     unsigned Opc, bool IsExt);
77     void ExpandMOV32BitImm(MachineBasicBlock &MBB,
78                            MachineBasicBlock::iterator &MBBI);
79     bool ExpandCMP_SWAP(MachineBasicBlock &MBB,
80                         MachineBasicBlock::iterator MBBI, unsigned LdrexOp,
81                         unsigned StrexOp, unsigned UxtOp,
82                         MachineBasicBlock::iterator &NextMBBI);
83 
84     bool ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
85                            MachineBasicBlock::iterator MBBI,
86                            MachineBasicBlock::iterator &NextMBBI);
87   };
88   char ARMExpandPseudo::ID = 0;
89 }
90 
91 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
92 /// the instructions created from the expansion.
93 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
94                                      MachineInstrBuilder &UseMI,
95                                      MachineInstrBuilder &DefMI) {
96   const MCInstrDesc &Desc = OldMI.getDesc();
97   for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
98        i != e; ++i) {
99     const MachineOperand &MO = OldMI.getOperand(i);
100     assert(MO.isReg() && MO.getReg());
101     if (MO.isUse())
102       UseMI.add(MO);
103     else
104       DefMI.add(MO);
105   }
106 }
107 
108 namespace {
109   // Constants for register spacing in NEON load/store instructions.
110   // For quad-register load-lane and store-lane pseudo instructors, the
111   // spacing is initially assumed to be EvenDblSpc, and that is changed to
112   // OddDblSpc depending on the lane number operand.
113   enum NEONRegSpacing {
114     SingleSpc,
115     EvenDblSpc,
116     OddDblSpc
117   };
118 
119   // Entries for NEON load/store information table.  The table is sorted by
120   // PseudoOpc for fast binary-search lookups.
121   struct NEONLdStTableEntry {
122     uint16_t PseudoOpc;
123     uint16_t RealOpc;
124     bool IsLoad;
125     bool isUpdating;
126     bool hasWritebackOperand;
127     uint8_t RegSpacing; // One of type NEONRegSpacing
128     uint8_t NumRegs; // D registers loaded or stored
129     uint8_t RegElts; // elements per D register; used for lane ops
130     // FIXME: Temporary flag to denote whether the real instruction takes
131     // a single register (like the encoding) or all of the registers in
132     // the list (like the asm syntax and the isel DAG). When all definitions
133     // are converted to take only the single encoded register, this will
134     // go away.
135     bool copyAllListRegs;
136 
137     // Comparison methods for binary search of the table.
138     bool operator<(const NEONLdStTableEntry &TE) const {
139       return PseudoOpc < TE.PseudoOpc;
140     }
141     friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
142       return TE.PseudoOpc < PseudoOpc;
143     }
144     friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
145                                                 const NEONLdStTableEntry &TE) {
146       return PseudoOpc < TE.PseudoOpc;
147     }
148   };
149 }
150 
151 static const NEONLdStTableEntry NEONLdStTable[] = {
152 { ARM::VLD1LNq16Pseudo,     ARM::VLD1LNd16,     true, false, false, EvenDblSpc, 1, 4 ,true},
153 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true,  EvenDblSpc, 1, 4 ,true},
154 { ARM::VLD1LNq32Pseudo,     ARM::VLD1LNd32,     true, false, false, EvenDblSpc, 1, 2 ,true},
155 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true,  EvenDblSpc, 1, 2 ,true},
156 { ARM::VLD1LNq8Pseudo,      ARM::VLD1LNd8,      true, false, false, EvenDblSpc, 1, 8 ,true},
157 { ARM::VLD1LNq8Pseudo_UPD,  ARM::VLD1LNd8_UPD, true, true, true,  EvenDblSpc, 1, 8 ,true},
158 
159 { ARM::VLD1d64QPseudo,      ARM::VLD1d64Q,     true,  false, false, SingleSpc,  4, 1 ,false},
160 { ARM::VLD1d64QPseudoWB_fixed,  ARM::VLD1d64Qwb_fixed,   true,  true, false, SingleSpc,  4, 1 ,false},
161 { ARM::VLD1d64TPseudo,      ARM::VLD1d64T,     true,  false, false, SingleSpc,  3, 1 ,false},
162 { ARM::VLD1d64TPseudoWB_fixed,  ARM::VLD1d64Twb_fixed,   true,  true, false, SingleSpc,  3, 1 ,false},
163 
164 { ARM::VLD2LNd16Pseudo,     ARM::VLD2LNd16,     true, false, false, SingleSpc,  2, 4 ,true},
165 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true,  SingleSpc,  2, 4 ,true},
166 { ARM::VLD2LNd32Pseudo,     ARM::VLD2LNd32,     true, false, false, SingleSpc,  2, 2 ,true},
167 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true,  SingleSpc,  2, 2 ,true},
168 { ARM::VLD2LNd8Pseudo,      ARM::VLD2LNd8,      true, false, false, SingleSpc,  2, 8 ,true},
169 { ARM::VLD2LNd8Pseudo_UPD,  ARM::VLD2LNd8_UPD, true, true, true,  SingleSpc,  2, 8 ,true},
170 { ARM::VLD2LNq16Pseudo,     ARM::VLD2LNq16,     true, false, false, EvenDblSpc, 2, 4 ,true},
171 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true,  EvenDblSpc, 2, 4 ,true},
172 { ARM::VLD2LNq32Pseudo,     ARM::VLD2LNq32,     true, false, false, EvenDblSpc, 2, 2 ,true},
173 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true,  EvenDblSpc, 2, 2 ,true},
174 
175 { ARM::VLD2q16Pseudo,       ARM::VLD2q16,      true,  false, false, SingleSpc,  4, 4 ,false},
176 { ARM::VLD2q16PseudoWB_fixed,   ARM::VLD2q16wb_fixed, true, true, false,  SingleSpc,  4, 4 ,false},
177 { ARM::VLD2q16PseudoWB_register,   ARM::VLD2q16wb_register, true, true, true,  SingleSpc,  4, 4 ,false},
178 { ARM::VLD2q32Pseudo,       ARM::VLD2q32,      true,  false, false, SingleSpc,  4, 2 ,false},
179 { ARM::VLD2q32PseudoWB_fixed,   ARM::VLD2q32wb_fixed, true, true, false,  SingleSpc,  4, 2 ,false},
180 { ARM::VLD2q32PseudoWB_register,   ARM::VLD2q32wb_register, true, true, true,  SingleSpc,  4, 2 ,false},
181 { ARM::VLD2q8Pseudo,        ARM::VLD2q8,       true,  false, false, SingleSpc,  4, 8 ,false},
182 { ARM::VLD2q8PseudoWB_fixed,    ARM::VLD2q8wb_fixed, true, true, false,  SingleSpc,  4, 8 ,false},
183 { ARM::VLD2q8PseudoWB_register,    ARM::VLD2q8wb_register, true, true, true,  SingleSpc,  4, 8 ,false},
184 
185 { ARM::VLD3DUPd16Pseudo,     ARM::VLD3DUPd16,     true, false, false, SingleSpc, 3, 4,true},
186 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true,  SingleSpc, 3, 4,true},
187 { ARM::VLD3DUPd32Pseudo,     ARM::VLD3DUPd32,     true, false, false, SingleSpc, 3, 2,true},
188 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true,  SingleSpc, 3, 2,true},
189 { ARM::VLD3DUPd8Pseudo,      ARM::VLD3DUPd8,      true, false, false, SingleSpc, 3, 8,true},
190 { ARM::VLD3DUPd8Pseudo_UPD,  ARM::VLD3DUPd8_UPD, true, true, true,  SingleSpc, 3, 8,true},
191 
192 { ARM::VLD3LNd16Pseudo,     ARM::VLD3LNd16,     true, false, false, SingleSpc,  3, 4 ,true},
193 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true,  SingleSpc,  3, 4 ,true},
194 { ARM::VLD3LNd32Pseudo,     ARM::VLD3LNd32,     true, false, false, SingleSpc,  3, 2 ,true},
195 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true,  SingleSpc,  3, 2 ,true},
196 { ARM::VLD3LNd8Pseudo,      ARM::VLD3LNd8,      true, false, false, SingleSpc,  3, 8 ,true},
197 { ARM::VLD3LNd8Pseudo_UPD,  ARM::VLD3LNd8_UPD, true, true, true,  SingleSpc,  3, 8 ,true},
198 { ARM::VLD3LNq16Pseudo,     ARM::VLD3LNq16,     true, false, false, EvenDblSpc, 3, 4 ,true},
199 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true,  EvenDblSpc, 3, 4 ,true},
200 { ARM::VLD3LNq32Pseudo,     ARM::VLD3LNq32,     true, false, false, EvenDblSpc, 3, 2 ,true},
201 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true,  EvenDblSpc, 3, 2 ,true},
202 
203 { ARM::VLD3d16Pseudo,       ARM::VLD3d16,      true,  false, false, SingleSpc,  3, 4 ,true},
204 { ARM::VLD3d16Pseudo_UPD,   ARM::VLD3d16_UPD, true, true, true,  SingleSpc,  3, 4 ,true},
205 { ARM::VLD3d32Pseudo,       ARM::VLD3d32,      true,  false, false, SingleSpc,  3, 2 ,true},
206 { ARM::VLD3d32Pseudo_UPD,   ARM::VLD3d32_UPD, true, true, true,  SingleSpc,  3, 2 ,true},
207 { ARM::VLD3d8Pseudo,        ARM::VLD3d8,       true,  false, false, SingleSpc,  3, 8 ,true},
208 { ARM::VLD3d8Pseudo_UPD,    ARM::VLD3d8_UPD, true, true, true,  SingleSpc,  3, 8 ,true},
209 
210 { ARM::VLD3q16Pseudo_UPD,    ARM::VLD3q16_UPD, true, true, true,  EvenDblSpc, 3, 4 ,true},
211 { ARM::VLD3q16oddPseudo,     ARM::VLD3q16,     true,  false, false, OddDblSpc,  3, 4 ,true},
212 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true,  OddDblSpc,  3, 4 ,true},
213 { ARM::VLD3q32Pseudo_UPD,    ARM::VLD3q32_UPD, true, true, true,  EvenDblSpc, 3, 2 ,true},
214 { ARM::VLD3q32oddPseudo,     ARM::VLD3q32,     true,  false, false, OddDblSpc,  3, 2 ,true},
215 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true,  OddDblSpc,  3, 2 ,true},
216 { ARM::VLD3q8Pseudo_UPD,     ARM::VLD3q8_UPD, true, true, true,  EvenDblSpc, 3, 8 ,true},
217 { ARM::VLD3q8oddPseudo,      ARM::VLD3q8,      true,  false, false, OddDblSpc,  3, 8 ,true},
218 { ARM::VLD3q8oddPseudo_UPD,  ARM::VLD3q8_UPD, true, true, true,  OddDblSpc,  3, 8 ,true},
219 
220 { ARM::VLD4DUPd16Pseudo,     ARM::VLD4DUPd16,     true, false, false, SingleSpc, 4, 4,true},
221 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true,  SingleSpc, 4, 4,true},
222 { ARM::VLD4DUPd32Pseudo,     ARM::VLD4DUPd32,     true, false, false, SingleSpc, 4, 2,true},
223 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true,  SingleSpc, 4, 2,true},
224 { ARM::VLD4DUPd8Pseudo,      ARM::VLD4DUPd8,      true, false, false, SingleSpc, 4, 8,true},
225 { ARM::VLD4DUPd8Pseudo_UPD,  ARM::VLD4DUPd8_UPD, true, true, true,  SingleSpc, 4, 8,true},
226 
227 { ARM::VLD4LNd16Pseudo,     ARM::VLD4LNd16,     true, false, false, SingleSpc,  4, 4 ,true},
228 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true,  SingleSpc,  4, 4 ,true},
229 { ARM::VLD4LNd32Pseudo,     ARM::VLD4LNd32,     true, false, false, SingleSpc,  4, 2 ,true},
230 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true,  SingleSpc,  4, 2 ,true},
231 { ARM::VLD4LNd8Pseudo,      ARM::VLD4LNd8,      true, false, false, SingleSpc,  4, 8 ,true},
232 { ARM::VLD4LNd8Pseudo_UPD,  ARM::VLD4LNd8_UPD, true, true, true,  SingleSpc,  4, 8 ,true},
233 { ARM::VLD4LNq16Pseudo,     ARM::VLD4LNq16,     true, false, false, EvenDblSpc, 4, 4 ,true},
234 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true,  EvenDblSpc, 4, 4 ,true},
235 { ARM::VLD4LNq32Pseudo,     ARM::VLD4LNq32,     true, false, false, EvenDblSpc, 4, 2 ,true},
236 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true,  EvenDblSpc, 4, 2 ,true},
237 
238 { ARM::VLD4d16Pseudo,       ARM::VLD4d16,      true,  false, false, SingleSpc,  4, 4 ,true},
239 { ARM::VLD4d16Pseudo_UPD,   ARM::VLD4d16_UPD, true, true, true,  SingleSpc,  4, 4 ,true},
240 { ARM::VLD4d32Pseudo,       ARM::VLD4d32,      true,  false, false, SingleSpc,  4, 2 ,true},
241 { ARM::VLD4d32Pseudo_UPD,   ARM::VLD4d32_UPD, true, true, true,  SingleSpc,  4, 2 ,true},
242 { ARM::VLD4d8Pseudo,        ARM::VLD4d8,       true,  false, false, SingleSpc,  4, 8 ,true},
243 { ARM::VLD4d8Pseudo_UPD,    ARM::VLD4d8_UPD, true, true, true,  SingleSpc,  4, 8 ,true},
244 
245 { ARM::VLD4q16Pseudo_UPD,    ARM::VLD4q16_UPD, true, true, true,  EvenDblSpc, 4, 4 ,true},
246 { ARM::VLD4q16oddPseudo,     ARM::VLD4q16,     true,  false, false, OddDblSpc,  4, 4 ,true},
247 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true,  OddDblSpc,  4, 4 ,true},
248 { ARM::VLD4q32Pseudo_UPD,    ARM::VLD4q32_UPD, true, true, true,  EvenDblSpc, 4, 2 ,true},
249 { ARM::VLD4q32oddPseudo,     ARM::VLD4q32,     true,  false, false, OddDblSpc,  4, 2 ,true},
250 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true,  OddDblSpc,  4, 2 ,true},
251 { ARM::VLD4q8Pseudo_UPD,     ARM::VLD4q8_UPD, true, true, true,  EvenDblSpc, 4, 8 ,true},
252 { ARM::VLD4q8oddPseudo,      ARM::VLD4q8,      true,  false, false, OddDblSpc,  4, 8 ,true},
253 { ARM::VLD4q8oddPseudo_UPD,  ARM::VLD4q8_UPD, true, true, true,  OddDblSpc,  4, 8 ,true},
254 
255 { ARM::VST1LNq16Pseudo,     ARM::VST1LNd16,    false, false, false, EvenDblSpc, 1, 4 ,true},
256 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true,  EvenDblSpc, 1, 4 ,true},
257 { ARM::VST1LNq32Pseudo,     ARM::VST1LNd32,    false, false, false, EvenDblSpc, 1, 2 ,true},
258 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true,  EvenDblSpc, 1, 2 ,true},
259 { ARM::VST1LNq8Pseudo,      ARM::VST1LNd8,     false, false, false, EvenDblSpc, 1, 8 ,true},
260 { ARM::VST1LNq8Pseudo_UPD,  ARM::VST1LNd8_UPD, false, true, true,  EvenDblSpc, 1, 8 ,true},
261 
262 { ARM::VST1d64QPseudo,      ARM::VST1d64Q,     false, false, false, SingleSpc,  4, 1 ,false},
263 { ARM::VST1d64QPseudoWB_fixed,  ARM::VST1d64Qwb_fixed, false, true, false,  SingleSpc,  4, 1 ,false},
264 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true,  SingleSpc,  4, 1 ,false},
265 { ARM::VST1d64TPseudo,      ARM::VST1d64T,     false, false, false, SingleSpc,  3, 1 ,false},
266 { ARM::VST1d64TPseudoWB_fixed,  ARM::VST1d64Twb_fixed, false, true, false,  SingleSpc,  3, 1 ,false},
267 { ARM::VST1d64TPseudoWB_register,  ARM::VST1d64Twb_register, false, true, true,  SingleSpc,  3, 1 ,false},
268 
269 { ARM::VST2LNd16Pseudo,     ARM::VST2LNd16,     false, false, false, SingleSpc, 2, 4 ,true},
270 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true,  SingleSpc, 2, 4 ,true},
271 { ARM::VST2LNd32Pseudo,     ARM::VST2LNd32,     false, false, false, SingleSpc, 2, 2 ,true},
272 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true,  SingleSpc, 2, 2 ,true},
273 { ARM::VST2LNd8Pseudo,      ARM::VST2LNd8,      false, false, false, SingleSpc, 2, 8 ,true},
274 { ARM::VST2LNd8Pseudo_UPD,  ARM::VST2LNd8_UPD, false, true, true,  SingleSpc, 2, 8 ,true},
275 { ARM::VST2LNq16Pseudo,     ARM::VST2LNq16,     false, false, false, EvenDblSpc, 2, 4,true},
276 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true,  EvenDblSpc, 2, 4,true},
277 { ARM::VST2LNq32Pseudo,     ARM::VST2LNq32,     false, false, false, EvenDblSpc, 2, 2,true},
278 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true,  EvenDblSpc, 2, 2,true},
279 
280 { ARM::VST2q16Pseudo,       ARM::VST2q16,      false, false, false, SingleSpc,  4, 4 ,false},
281 { ARM::VST2q16PseudoWB_fixed,   ARM::VST2q16wb_fixed, false, true, false,  SingleSpc,  4, 4 ,false},
282 { ARM::VST2q16PseudoWB_register,   ARM::VST2q16wb_register, false, true, true,  SingleSpc,  4, 4 ,false},
283 { ARM::VST2q32Pseudo,       ARM::VST2q32,      false, false, false, SingleSpc,  4, 2 ,false},
284 { ARM::VST2q32PseudoWB_fixed,   ARM::VST2q32wb_fixed, false, true, false,  SingleSpc,  4, 2 ,false},
285 { ARM::VST2q32PseudoWB_register,   ARM::VST2q32wb_register, false, true, true,  SingleSpc,  4, 2 ,false},
286 { ARM::VST2q8Pseudo,        ARM::VST2q8,       false, false, false, SingleSpc,  4, 8 ,false},
287 { ARM::VST2q8PseudoWB_fixed,    ARM::VST2q8wb_fixed, false, true, false,  SingleSpc,  4, 8 ,false},
288 { ARM::VST2q8PseudoWB_register,    ARM::VST2q8wb_register, false, true, true,  SingleSpc,  4, 8 ,false},
289 
290 { ARM::VST3LNd16Pseudo,     ARM::VST3LNd16,     false, false, false, SingleSpc, 3, 4 ,true},
291 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true,  SingleSpc, 3, 4 ,true},
292 { ARM::VST3LNd32Pseudo,     ARM::VST3LNd32,     false, false, false, SingleSpc, 3, 2 ,true},
293 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true,  SingleSpc, 3, 2 ,true},
294 { ARM::VST3LNd8Pseudo,      ARM::VST3LNd8,      false, false, false, SingleSpc, 3, 8 ,true},
295 { ARM::VST3LNd8Pseudo_UPD,  ARM::VST3LNd8_UPD, false, true, true,  SingleSpc, 3, 8 ,true},
296 { ARM::VST3LNq16Pseudo,     ARM::VST3LNq16,     false, false, false, EvenDblSpc, 3, 4,true},
297 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true,  EvenDblSpc, 3, 4,true},
298 { ARM::VST3LNq32Pseudo,     ARM::VST3LNq32,     false, false, false, EvenDblSpc, 3, 2,true},
299 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true,  EvenDblSpc, 3, 2,true},
300 
301 { ARM::VST3d16Pseudo,       ARM::VST3d16,      false, false, false, SingleSpc,  3, 4 ,true},
302 { ARM::VST3d16Pseudo_UPD,   ARM::VST3d16_UPD, false, true, true,  SingleSpc,  3, 4 ,true},
303 { ARM::VST3d32Pseudo,       ARM::VST3d32,      false, false, false, SingleSpc,  3, 2 ,true},
304 { ARM::VST3d32Pseudo_UPD,   ARM::VST3d32_UPD, false, true, true,  SingleSpc,  3, 2 ,true},
305 { ARM::VST3d8Pseudo,        ARM::VST3d8,       false, false, false, SingleSpc,  3, 8 ,true},
306 { ARM::VST3d8Pseudo_UPD,    ARM::VST3d8_UPD, false, true, true,  SingleSpc,  3, 8 ,true},
307 
308 { ARM::VST3q16Pseudo_UPD,    ARM::VST3q16_UPD, false, true, true,  EvenDblSpc, 3, 4 ,true},
309 { ARM::VST3q16oddPseudo,     ARM::VST3q16,     false, false, false, OddDblSpc,  3, 4 ,true},
310 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true,  OddDblSpc,  3, 4 ,true},
311 { ARM::VST3q32Pseudo_UPD,    ARM::VST3q32_UPD, false, true, true,  EvenDblSpc, 3, 2 ,true},
312 { ARM::VST3q32oddPseudo,     ARM::VST3q32,     false, false, false, OddDblSpc,  3, 2 ,true},
313 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true,  OddDblSpc,  3, 2 ,true},
314 { ARM::VST3q8Pseudo_UPD,     ARM::VST3q8_UPD, false, true, true,  EvenDblSpc, 3, 8 ,true},
315 { ARM::VST3q8oddPseudo,      ARM::VST3q8,      false, false, false, OddDblSpc,  3, 8 ,true},
316 { ARM::VST3q8oddPseudo_UPD,  ARM::VST3q8_UPD, false, true, true,  OddDblSpc,  3, 8 ,true},
317 
318 { ARM::VST4LNd16Pseudo,     ARM::VST4LNd16,     false, false, false, SingleSpc, 4, 4 ,true},
319 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true,  SingleSpc, 4, 4 ,true},
320 { ARM::VST4LNd32Pseudo,     ARM::VST4LNd32,     false, false, false, SingleSpc, 4, 2 ,true},
321 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true,  SingleSpc, 4, 2 ,true},
322 { ARM::VST4LNd8Pseudo,      ARM::VST4LNd8,      false, false, false, SingleSpc, 4, 8 ,true},
323 { ARM::VST4LNd8Pseudo_UPD,  ARM::VST4LNd8_UPD, false, true, true,  SingleSpc, 4, 8 ,true},
324 { ARM::VST4LNq16Pseudo,     ARM::VST4LNq16,     false, false, false, EvenDblSpc, 4, 4,true},
325 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true,  EvenDblSpc, 4, 4,true},
326 { ARM::VST4LNq32Pseudo,     ARM::VST4LNq32,     false, false, false, EvenDblSpc, 4, 2,true},
327 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true,  EvenDblSpc, 4, 2,true},
328 
329 { ARM::VST4d16Pseudo,       ARM::VST4d16,      false, false, false, SingleSpc,  4, 4 ,true},
330 { ARM::VST4d16Pseudo_UPD,   ARM::VST4d16_UPD, false, true, true,  SingleSpc,  4, 4 ,true},
331 { ARM::VST4d32Pseudo,       ARM::VST4d32,      false, false, false, SingleSpc,  4, 2 ,true},
332 { ARM::VST4d32Pseudo_UPD,   ARM::VST4d32_UPD, false, true, true,  SingleSpc,  4, 2 ,true},
333 { ARM::VST4d8Pseudo,        ARM::VST4d8,       false, false, false, SingleSpc,  4, 8 ,true},
334 { ARM::VST4d8Pseudo_UPD,    ARM::VST4d8_UPD, false, true, true,  SingleSpc,  4, 8 ,true},
335 
336 { ARM::VST4q16Pseudo_UPD,    ARM::VST4q16_UPD, false, true, true,  EvenDblSpc, 4, 4 ,true},
337 { ARM::VST4q16oddPseudo,     ARM::VST4q16,     false, false, false, OddDblSpc,  4, 4 ,true},
338 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true,  OddDblSpc,  4, 4 ,true},
339 { ARM::VST4q32Pseudo_UPD,    ARM::VST4q32_UPD, false, true, true,  EvenDblSpc, 4, 2 ,true},
340 { ARM::VST4q32oddPseudo,     ARM::VST4q32,     false, false, false, OddDblSpc,  4, 2 ,true},
341 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true,  OddDblSpc,  4, 2 ,true},
342 { ARM::VST4q8Pseudo_UPD,     ARM::VST4q8_UPD, false, true, true,  EvenDblSpc, 4, 8 ,true},
343 { ARM::VST4q8oddPseudo,      ARM::VST4q8,      false, false, false, OddDblSpc,  4, 8 ,true},
344 { ARM::VST4q8oddPseudo_UPD,  ARM::VST4q8_UPD, false, true, true,  OddDblSpc,  4, 8 ,true}
345 };
346 
347 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
348 /// load or store pseudo instruction.
349 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
350 #ifndef NDEBUG
351   // Make sure the table is sorted.
352   static bool TableChecked = false;
353   if (!TableChecked) {
354     assert(std::is_sorted(std::begin(NEONLdStTable), std::end(NEONLdStTable)) &&
355            "NEONLdStTable is not sorted!");
356     TableChecked = true;
357   }
358 #endif
359 
360   auto I = std::lower_bound(std::begin(NEONLdStTable),
361                             std::end(NEONLdStTable), Opcode);
362   if (I != std::end(NEONLdStTable) && I->PseudoOpc == Opcode)
363     return I;
364   return nullptr;
365 }
366 
367 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
368 /// corresponding to the specified register spacing.  Not all of the results
369 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
370 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
371                         const TargetRegisterInfo *TRI, unsigned &D0,
372                         unsigned &D1, unsigned &D2, unsigned &D3) {
373   if (RegSpc == SingleSpc) {
374     D0 = TRI->getSubReg(Reg, ARM::dsub_0);
375     D1 = TRI->getSubReg(Reg, ARM::dsub_1);
376     D2 = TRI->getSubReg(Reg, ARM::dsub_2);
377     D3 = TRI->getSubReg(Reg, ARM::dsub_3);
378   } else if (RegSpc == EvenDblSpc) {
379     D0 = TRI->getSubReg(Reg, ARM::dsub_0);
380     D1 = TRI->getSubReg(Reg, ARM::dsub_2);
381     D2 = TRI->getSubReg(Reg, ARM::dsub_4);
382     D3 = TRI->getSubReg(Reg, ARM::dsub_6);
383   } else {
384     assert(RegSpc == OddDblSpc && "unknown register spacing");
385     D0 = TRI->getSubReg(Reg, ARM::dsub_1);
386     D1 = TRI->getSubReg(Reg, ARM::dsub_3);
387     D2 = TRI->getSubReg(Reg, ARM::dsub_5);
388     D3 = TRI->getSubReg(Reg, ARM::dsub_7);
389   }
390 }
391 
392 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
393 /// operands to real VLD instructions with D register operands.
394 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
395   MachineInstr &MI = *MBBI;
396   MachineBasicBlock &MBB = *MI.getParent();
397 
398   const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
399   assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
400   NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
401   unsigned NumRegs = TableEntry->NumRegs;
402 
403   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
404                                     TII->get(TableEntry->RealOpc));
405   unsigned OpIdx = 0;
406 
407   bool DstIsDead = MI.getOperand(OpIdx).isDead();
408   unsigned DstReg = MI.getOperand(OpIdx++).getReg();
409   unsigned D0, D1, D2, D3;
410   GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
411   MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
412   if (NumRegs > 1 && TableEntry->copyAllListRegs)
413     MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
414   if (NumRegs > 2 && TableEntry->copyAllListRegs)
415     MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
416   if (NumRegs > 3 && TableEntry->copyAllListRegs)
417     MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
418 
419   if (TableEntry->isUpdating)
420     MIB.add(MI.getOperand(OpIdx++));
421 
422   // Copy the addrmode6 operands.
423   MIB.add(MI.getOperand(OpIdx++));
424   MIB.add(MI.getOperand(OpIdx++));
425   // Copy the am6offset operand.
426   if (TableEntry->hasWritebackOperand)
427     MIB.add(MI.getOperand(OpIdx++));
428 
429   // For an instruction writing double-spaced subregs, the pseudo instruction
430   // has an extra operand that is a use of the super-register.  Record the
431   // operand index and skip over it.
432   unsigned SrcOpIdx = 0;
433   if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
434     SrcOpIdx = OpIdx++;
435 
436   // Copy the predicate operands.
437   MIB.add(MI.getOperand(OpIdx++));
438   MIB.add(MI.getOperand(OpIdx++));
439 
440   // Copy the super-register source operand used for double-spaced subregs over
441   // to the new instruction as an implicit operand.
442   if (SrcOpIdx != 0) {
443     MachineOperand MO = MI.getOperand(SrcOpIdx);
444     MO.setImplicit(true);
445     MIB.add(MO);
446   }
447   // Add an implicit def for the super-register.
448   MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
449   TransferImpOps(MI, MIB, MIB);
450 
451   // Transfer memoperands.
452   MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
453 
454   MI.eraseFromParent();
455 }
456 
457 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
458 /// operands to real VST instructions with D register operands.
459 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
460   MachineInstr &MI = *MBBI;
461   MachineBasicBlock &MBB = *MI.getParent();
462 
463   const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
464   assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
465   NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
466   unsigned NumRegs = TableEntry->NumRegs;
467 
468   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
469                                     TII->get(TableEntry->RealOpc));
470   unsigned OpIdx = 0;
471   if (TableEntry->isUpdating)
472     MIB.add(MI.getOperand(OpIdx++));
473 
474   // Copy the addrmode6 operands.
475   MIB.add(MI.getOperand(OpIdx++));
476   MIB.add(MI.getOperand(OpIdx++));
477   // Copy the am6offset operand.
478   if (TableEntry->hasWritebackOperand)
479     MIB.add(MI.getOperand(OpIdx++));
480 
481   bool SrcIsKill = MI.getOperand(OpIdx).isKill();
482   bool SrcIsUndef = MI.getOperand(OpIdx).isUndef();
483   unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
484   unsigned D0, D1, D2, D3;
485   GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
486   MIB.addReg(D0, getUndefRegState(SrcIsUndef));
487   if (NumRegs > 1 && TableEntry->copyAllListRegs)
488     MIB.addReg(D1, getUndefRegState(SrcIsUndef));
489   if (NumRegs > 2 && TableEntry->copyAllListRegs)
490     MIB.addReg(D2, getUndefRegState(SrcIsUndef));
491   if (NumRegs > 3 && TableEntry->copyAllListRegs)
492     MIB.addReg(D3, getUndefRegState(SrcIsUndef));
493 
494   // Copy the predicate operands.
495   MIB.add(MI.getOperand(OpIdx++));
496   MIB.add(MI.getOperand(OpIdx++));
497 
498   if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg.
499     MIB->addRegisterKilled(SrcReg, TRI, true);
500   else if (!SrcIsUndef)
501     MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
502   TransferImpOps(MI, MIB, MIB);
503 
504   // Transfer memoperands.
505   MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
506 
507   MI.eraseFromParent();
508 }
509 
510 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
511 /// register operands to real instructions with D register operands.
512 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
513   MachineInstr &MI = *MBBI;
514   MachineBasicBlock &MBB = *MI.getParent();
515 
516   const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
517   assert(TableEntry && "NEONLdStTable lookup failed");
518   NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
519   unsigned NumRegs = TableEntry->NumRegs;
520   unsigned RegElts = TableEntry->RegElts;
521 
522   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
523                                     TII->get(TableEntry->RealOpc));
524   unsigned OpIdx = 0;
525   // The lane operand is always the 3rd from last operand, before the 2
526   // predicate operands.
527   unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
528 
529   // Adjust the lane and spacing as needed for Q registers.
530   assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
531   if (RegSpc == EvenDblSpc && Lane >= RegElts) {
532     RegSpc = OddDblSpc;
533     Lane -= RegElts;
534   }
535   assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
536 
537   unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
538   unsigned DstReg = 0;
539   bool DstIsDead = false;
540   if (TableEntry->IsLoad) {
541     DstIsDead = MI.getOperand(OpIdx).isDead();
542     DstReg = MI.getOperand(OpIdx++).getReg();
543     GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
544     MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
545     if (NumRegs > 1)
546       MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
547     if (NumRegs > 2)
548       MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
549     if (NumRegs > 3)
550       MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
551   }
552 
553   if (TableEntry->isUpdating)
554     MIB.add(MI.getOperand(OpIdx++));
555 
556   // Copy the addrmode6 operands.
557   MIB.add(MI.getOperand(OpIdx++));
558   MIB.add(MI.getOperand(OpIdx++));
559   // Copy the am6offset operand.
560   if (TableEntry->hasWritebackOperand)
561     MIB.add(MI.getOperand(OpIdx++));
562 
563   // Grab the super-register source.
564   MachineOperand MO = MI.getOperand(OpIdx++);
565   if (!TableEntry->IsLoad)
566     GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
567 
568   // Add the subregs as sources of the new instruction.
569   unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
570                        getKillRegState(MO.isKill()));
571   MIB.addReg(D0, SrcFlags);
572   if (NumRegs > 1)
573     MIB.addReg(D1, SrcFlags);
574   if (NumRegs > 2)
575     MIB.addReg(D2, SrcFlags);
576   if (NumRegs > 3)
577     MIB.addReg(D3, SrcFlags);
578 
579   // Add the lane number operand.
580   MIB.addImm(Lane);
581   OpIdx += 1;
582 
583   // Copy the predicate operands.
584   MIB.add(MI.getOperand(OpIdx++));
585   MIB.add(MI.getOperand(OpIdx++));
586 
587   // Copy the super-register source to be an implicit source.
588   MO.setImplicit(true);
589   MIB.add(MO);
590   if (TableEntry->IsLoad)
591     // Add an implicit def for the super-register.
592     MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
593   TransferImpOps(MI, MIB, MIB);
594   // Transfer memoperands.
595   MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
596   MI.eraseFromParent();
597 }
598 
599 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
600 /// register operands to real instructions with D register operands.
601 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
602                                  unsigned Opc, bool IsExt) {
603   MachineInstr &MI = *MBBI;
604   MachineBasicBlock &MBB = *MI.getParent();
605 
606   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
607   unsigned OpIdx = 0;
608 
609   // Transfer the destination register operand.
610   MIB.add(MI.getOperand(OpIdx++));
611   if (IsExt)
612     MIB.add(MI.getOperand(OpIdx++));
613 
614   bool SrcIsKill = MI.getOperand(OpIdx).isKill();
615   unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
616   unsigned D0, D1, D2, D3;
617   GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
618   MIB.addReg(D0);
619 
620   // Copy the other source register operand.
621   MIB.add(MI.getOperand(OpIdx++));
622 
623   // Copy the predicate operands.
624   MIB.add(MI.getOperand(OpIdx++));
625   MIB.add(MI.getOperand(OpIdx++));
626 
627   // Add an implicit kill and use for the super-reg.
628   MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
629   TransferImpOps(MI, MIB, MIB);
630   MI.eraseFromParent();
631 }
632 
633 static bool IsAnAddressOperand(const MachineOperand &MO) {
634   // This check is overly conservative.  Unless we are certain that the machine
635   // operand is not a symbol reference, we return that it is a symbol reference.
636   // This is important as the load pair may not be split up Windows.
637   switch (MO.getType()) {
638   case MachineOperand::MO_Register:
639   case MachineOperand::MO_Immediate:
640   case MachineOperand::MO_CImmediate:
641   case MachineOperand::MO_FPImmediate:
642     return false;
643   case MachineOperand::MO_MachineBasicBlock:
644     return true;
645   case MachineOperand::MO_FrameIndex:
646     return false;
647   case MachineOperand::MO_ConstantPoolIndex:
648   case MachineOperand::MO_TargetIndex:
649   case MachineOperand::MO_JumpTableIndex:
650   case MachineOperand::MO_ExternalSymbol:
651   case MachineOperand::MO_GlobalAddress:
652   case MachineOperand::MO_BlockAddress:
653     return true;
654   case MachineOperand::MO_RegisterMask:
655   case MachineOperand::MO_RegisterLiveOut:
656     return false;
657   case MachineOperand::MO_Metadata:
658   case MachineOperand::MO_MCSymbol:
659     return true;
660   case MachineOperand::MO_CFIIndex:
661     return false;
662   case MachineOperand::MO_IntrinsicID:
663   case MachineOperand::MO_Predicate:
664     llvm_unreachable("should not exist post-isel");
665   }
666   llvm_unreachable("unhandled machine operand type");
667 }
668 
669 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
670                                         MachineBasicBlock::iterator &MBBI) {
671   MachineInstr &MI = *MBBI;
672   unsigned Opcode = MI.getOpcode();
673   unsigned PredReg = 0;
674   ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
675   unsigned DstReg = MI.getOperand(0).getReg();
676   bool DstIsDead = MI.getOperand(0).isDead();
677   bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
678   const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
679   bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO);
680   MachineInstrBuilder LO16, HI16;
681 
682   if (!STI->hasV6T2Ops() &&
683       (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
684     // FIXME Windows CE supports older ARM CPUs
685     assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+");
686 
687     // Expand into a movi + orr.
688     LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
689     HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
690       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
691       .addReg(DstReg);
692 
693     assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
694     unsigned ImmVal = (unsigned)MO.getImm();
695     unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
696     unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
697     LO16 = LO16.addImm(SOImmValV1);
698     HI16 = HI16.addImm(SOImmValV2);
699     LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
700     HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
701     LO16.addImm(Pred).addReg(PredReg).add(condCodeOp());
702     HI16.addImm(Pred).addReg(PredReg).add(condCodeOp());
703     TransferImpOps(MI, LO16, HI16);
704     MI.eraseFromParent();
705     return;
706   }
707 
708   unsigned LO16Opc = 0;
709   unsigned HI16Opc = 0;
710   if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
711     LO16Opc = ARM::t2MOVi16;
712     HI16Opc = ARM::t2MOVTi16;
713   } else {
714     LO16Opc = ARM::MOVi16;
715     HI16Opc = ARM::MOVTi16;
716   }
717 
718   LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
719   HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
720     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
721     .addReg(DstReg);
722 
723   switch (MO.getType()) {
724   case MachineOperand::MO_Immediate: {
725     unsigned Imm = MO.getImm();
726     unsigned Lo16 = Imm & 0xffff;
727     unsigned Hi16 = (Imm >> 16) & 0xffff;
728     LO16 = LO16.addImm(Lo16);
729     HI16 = HI16.addImm(Hi16);
730     break;
731   }
732   case MachineOperand::MO_ExternalSymbol: {
733     const char *ES = MO.getSymbolName();
734     unsigned TF = MO.getTargetFlags();
735     LO16 = LO16.addExternalSymbol(ES, TF | ARMII::MO_LO16);
736     HI16 = HI16.addExternalSymbol(ES, TF | ARMII::MO_HI16);
737     break;
738   }
739   default: {
740     const GlobalValue *GV = MO.getGlobal();
741     unsigned TF = MO.getTargetFlags();
742     LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
743     HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
744     break;
745   }
746   }
747 
748   LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
749   HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
750   LO16.addImm(Pred).addReg(PredReg);
751   HI16.addImm(Pred).addReg(PredReg);
752 
753   if (RequiresBundling)
754     finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator());
755 
756   TransferImpOps(MI, LO16, HI16);
757   MI.eraseFromParent();
758 }
759 
760 /// Expand a CMP_SWAP pseudo-inst to an ldrex/strex loop as simply as
761 /// possible. This only gets used at -O0 so we don't care about efficiency of
762 /// the generated code.
763 bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
764                                      MachineBasicBlock::iterator MBBI,
765                                      unsigned LdrexOp, unsigned StrexOp,
766                                      unsigned UxtOp,
767                                      MachineBasicBlock::iterator &NextMBBI) {
768   bool IsThumb = STI->isThumb();
769   MachineInstr &MI = *MBBI;
770   DebugLoc DL = MI.getDebugLoc();
771   const MachineOperand &Dest = MI.getOperand(0);
772   unsigned TempReg = MI.getOperand(1).getReg();
773   // Duplicating undef operands into 2 instructions does not guarantee the same
774   // value on both; However undef should be replaced by xzr anyway.
775   assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
776   unsigned AddrReg = MI.getOperand(2).getReg();
777   unsigned DesiredReg = MI.getOperand(3).getReg();
778   unsigned NewReg = MI.getOperand(4).getReg();
779 
780   MachineFunction *MF = MBB.getParent();
781   auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
782   auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
783   auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
784 
785   MF->insert(++MBB.getIterator(), LoadCmpBB);
786   MF->insert(++LoadCmpBB->getIterator(), StoreBB);
787   MF->insert(++StoreBB->getIterator(), DoneBB);
788 
789   if (UxtOp) {
790     MachineInstrBuilder MIB =
791         BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg)
792             .addReg(DesiredReg, RegState::Kill);
793     if (!IsThumb)
794       MIB.addImm(0);
795     MIB.add(predOps(ARMCC::AL));
796   }
797 
798   // .Lloadcmp:
799   //     ldrex rDest, [rAddr]
800   //     cmp rDest, rDesired
801   //     bne .Ldone
802 
803   MachineInstrBuilder MIB;
804   MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg());
805   MIB.addReg(AddrReg);
806   if (LdrexOp == ARM::t2LDREX)
807     MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset.
808   MIB.add(predOps(ARMCC::AL));
809 
810   unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
811   BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
812       .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
813       .addReg(DesiredReg)
814       .add(predOps(ARMCC::AL));
815   unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
816   BuildMI(LoadCmpBB, DL, TII->get(Bcc))
817       .addMBB(DoneBB)
818       .addImm(ARMCC::NE)
819       .addReg(ARM::CPSR, RegState::Kill);
820   LoadCmpBB->addSuccessor(DoneBB);
821   LoadCmpBB->addSuccessor(StoreBB);
822 
823   // .Lstore:
824   //     strex rTempReg, rNew, [rAddr]
825   //     cmp rTempReg, #0
826   //     bne .Lloadcmp
827   MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg)
828     .addReg(NewReg)
829     .addReg(AddrReg);
830   if (StrexOp == ARM::t2STREX)
831     MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset.
832   MIB.add(predOps(ARMCC::AL));
833 
834   unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
835   BuildMI(StoreBB, DL, TII->get(CMPri))
836       .addReg(TempReg, RegState::Kill)
837       .addImm(0)
838       .add(predOps(ARMCC::AL));
839   BuildMI(StoreBB, DL, TII->get(Bcc))
840       .addMBB(LoadCmpBB)
841       .addImm(ARMCC::NE)
842       .addReg(ARM::CPSR, RegState::Kill);
843   StoreBB->addSuccessor(LoadCmpBB);
844   StoreBB->addSuccessor(DoneBB);
845 
846   DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
847   DoneBB->transferSuccessors(&MBB);
848 
849   MBB.addSuccessor(LoadCmpBB);
850 
851   NextMBBI = MBB.end();
852   MI.eraseFromParent();
853 
854   // Recompute livein lists.
855   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
856   LivePhysRegs LiveRegs;
857   computeLiveIns(LiveRegs, MRI, *DoneBB);
858   computeLiveIns(LiveRegs, MRI, *StoreBB);
859   computeLiveIns(LiveRegs, MRI, *LoadCmpBB);
860   // Do an extra pass around the loop to get loop carried registers right.
861   StoreBB->clearLiveIns();
862   computeLiveIns(LiveRegs, MRI, *StoreBB);
863   LoadCmpBB->clearLiveIns();
864   computeLiveIns(LiveRegs, MRI, *LoadCmpBB);
865 
866   return true;
867 }
868 
869 /// ARM's ldrexd/strexd take a consecutive register pair (represented as a
870 /// single GPRPair register), Thumb's take two separate registers so we need to
871 /// extract the subregs from the pair.
872 static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg,
873                                 unsigned Flags, bool IsThumb,
874                                 const TargetRegisterInfo *TRI) {
875   if (IsThumb) {
876     unsigned RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0);
877     unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1);
878     MIB.addReg(RegLo, Flags | getKillRegState(Reg.isDead()));
879     MIB.addReg(RegHi, Flags | getKillRegState(Reg.isDead()));
880   } else
881     MIB.addReg(Reg.getReg(), Flags | getKillRegState(Reg.isDead()));
882 }
883 
884 /// Expand a 64-bit CMP_SWAP to an ldrexd/strexd loop.
885 bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
886                                         MachineBasicBlock::iterator MBBI,
887                                         MachineBasicBlock::iterator &NextMBBI) {
888   bool IsThumb = STI->isThumb();
889   MachineInstr &MI = *MBBI;
890   DebugLoc DL = MI.getDebugLoc();
891   MachineOperand &Dest = MI.getOperand(0);
892   unsigned TempReg = MI.getOperand(1).getReg();
893   // Duplicating undef operands into 2 instructions does not guarantee the same
894   // value on both; However undef should be replaced by xzr anyway.
895   assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
896   unsigned AddrReg = MI.getOperand(2).getReg();
897   unsigned DesiredReg = MI.getOperand(3).getReg();
898   MachineOperand New = MI.getOperand(4);
899   New.setIsKill(false);
900 
901   unsigned DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0);
902   unsigned DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1);
903   unsigned DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0);
904   unsigned DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1);
905 
906   MachineFunction *MF = MBB.getParent();
907   auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
908   auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
909   auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
910 
911   MF->insert(++MBB.getIterator(), LoadCmpBB);
912   MF->insert(++LoadCmpBB->getIterator(), StoreBB);
913   MF->insert(++StoreBB->getIterator(), DoneBB);
914 
915   // .Lloadcmp:
916   //     ldrexd rDestLo, rDestHi, [rAddr]
917   //     cmp rDestLo, rDesiredLo
918   //     sbcs rTempReg<dead>, rDestHi, rDesiredHi
919   //     bne .Ldone
920   unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD;
921   MachineInstrBuilder MIB;
922   MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD));
923   addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI);
924   MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
925 
926   unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
927   BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
928       .addReg(DestLo, getKillRegState(Dest.isDead()))
929       .addReg(DesiredLo)
930       .add(predOps(ARMCC::AL));
931 
932   BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
933       .addReg(DestHi, getKillRegState(Dest.isDead()))
934       .addReg(DesiredHi)
935       .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
936 
937   unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
938   BuildMI(LoadCmpBB, DL, TII->get(Bcc))
939       .addMBB(DoneBB)
940       .addImm(ARMCC::NE)
941       .addReg(ARM::CPSR, RegState::Kill);
942   LoadCmpBB->addSuccessor(DoneBB);
943   LoadCmpBB->addSuccessor(StoreBB);
944 
945   // .Lstore:
946   //     strexd rTempReg, rNewLo, rNewHi, [rAddr]
947   //     cmp rTempReg, #0
948   //     bne .Lloadcmp
949   unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD;
950   MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg);
951   addExclusiveRegPair(MIB, New, 0, IsThumb, TRI);
952   MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
953 
954   unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
955   BuildMI(StoreBB, DL, TII->get(CMPri))
956       .addReg(TempReg, RegState::Kill)
957       .addImm(0)
958       .add(predOps(ARMCC::AL));
959   BuildMI(StoreBB, DL, TII->get(Bcc))
960       .addMBB(LoadCmpBB)
961       .addImm(ARMCC::NE)
962       .addReg(ARM::CPSR, RegState::Kill);
963   StoreBB->addSuccessor(LoadCmpBB);
964   StoreBB->addSuccessor(DoneBB);
965 
966   DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
967   DoneBB->transferSuccessors(&MBB);
968 
969   MBB.addSuccessor(LoadCmpBB);
970 
971   NextMBBI = MBB.end();
972   MI.eraseFromParent();
973 
974   // Recompute livein lists.
975   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
976   LivePhysRegs LiveRegs;
977   computeLiveIns(LiveRegs, MRI, *DoneBB);
978   computeLiveIns(LiveRegs, MRI, *StoreBB);
979   computeLiveIns(LiveRegs, MRI, *LoadCmpBB);
980   // Do an extra pass around the loop to get loop carried registers right.
981   StoreBB->clearLiveIns();
982   computeLiveIns(LiveRegs, MRI, *StoreBB);
983   LoadCmpBB->clearLiveIns();
984   computeLiveIns(LiveRegs, MRI, *LoadCmpBB);
985 
986   return true;
987 }
988 
989 
990 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
991                                MachineBasicBlock::iterator MBBI,
992                                MachineBasicBlock::iterator &NextMBBI) {
993   MachineInstr &MI = *MBBI;
994   unsigned Opcode = MI.getOpcode();
995   switch (Opcode) {
996     default:
997       return false;
998 
999     case ARM::TCRETURNdi:
1000     case ARM::TCRETURNri: {
1001       MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
1002       assert(MBBI->isReturn() &&
1003              "Can only insert epilog into returning blocks");
1004       unsigned RetOpcode = MBBI->getOpcode();
1005       DebugLoc dl = MBBI->getDebugLoc();
1006       const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
1007           MBB.getParent()->getSubtarget().getInstrInfo());
1008 
1009       // Tail call return: adjust the stack pointer and jump to callee.
1010       MBBI = MBB.getLastNonDebugInstr();
1011       MachineOperand &JumpTarget = MBBI->getOperand(0);
1012 
1013       // Jump to label or value in register.
1014       if (RetOpcode == ARM::TCRETURNdi) {
1015         unsigned TCOpcode =
1016             STI->isThumb()
1017                 ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND)
1018                 : ARM::TAILJMPd;
1019         MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
1020         if (JumpTarget.isGlobal())
1021           MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1022                                JumpTarget.getTargetFlags());
1023         else {
1024           assert(JumpTarget.isSymbol());
1025           MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1026                                 JumpTarget.getTargetFlags());
1027         }
1028 
1029         // Add the default predicate in Thumb mode.
1030         if (STI->isThumb())
1031           MIB.add(predOps(ARMCC::AL));
1032       } else if (RetOpcode == ARM::TCRETURNri) {
1033         BuildMI(MBB, MBBI, dl,
1034                 TII.get(STI->isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr))
1035             .addReg(JumpTarget.getReg(), RegState::Kill);
1036       }
1037 
1038       auto NewMI = std::prev(MBBI);
1039       for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
1040         NewMI->addOperand(MBBI->getOperand(i));
1041 
1042       // Delete the pseudo instruction TCRETURN.
1043       MBB.erase(MBBI);
1044       MBBI = NewMI;
1045       return true;
1046     }
1047     case ARM::VMOVScc:
1048     case ARM::VMOVDcc: {
1049       unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
1050       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
1051               MI.getOperand(1).getReg())
1052           .add(MI.getOperand(2))
1053           .addImm(MI.getOperand(3).getImm()) // 'pred'
1054           .add(MI.getOperand(4));
1055 
1056       MI.eraseFromParent();
1057       return true;
1058     }
1059     case ARM::t2MOVCCr:
1060     case ARM::MOVCCr: {
1061       unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
1062       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1063               MI.getOperand(1).getReg())
1064           .add(MI.getOperand(2))
1065           .addImm(MI.getOperand(3).getImm()) // 'pred'
1066           .add(MI.getOperand(4))
1067           .add(condCodeOp()); // 's' bit
1068 
1069       MI.eraseFromParent();
1070       return true;
1071     }
1072     case ARM::MOVCCsi: {
1073       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1074               (MI.getOperand(1).getReg()))
1075           .add(MI.getOperand(2))
1076           .addImm(MI.getOperand(3).getImm())
1077           .addImm(MI.getOperand(4).getImm()) // 'pred'
1078           .add(MI.getOperand(5))
1079           .add(condCodeOp()); // 's' bit
1080 
1081       MI.eraseFromParent();
1082       return true;
1083     }
1084     case ARM::MOVCCsr: {
1085       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
1086               (MI.getOperand(1).getReg()))
1087           .add(MI.getOperand(2))
1088           .add(MI.getOperand(3))
1089           .addImm(MI.getOperand(4).getImm())
1090           .addImm(MI.getOperand(5).getImm()) // 'pred'
1091           .add(MI.getOperand(6))
1092           .add(condCodeOp()); // 's' bit
1093 
1094       MI.eraseFromParent();
1095       return true;
1096     }
1097     case ARM::t2MOVCCi16:
1098     case ARM::MOVCCi16: {
1099       unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
1100       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1101               MI.getOperand(1).getReg())
1102           .addImm(MI.getOperand(2).getImm())
1103           .addImm(MI.getOperand(3).getImm()) // 'pred'
1104           .add(MI.getOperand(4));
1105       MI.eraseFromParent();
1106       return true;
1107     }
1108     case ARM::t2MOVCCi:
1109     case ARM::MOVCCi: {
1110       unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
1111       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1112               MI.getOperand(1).getReg())
1113           .addImm(MI.getOperand(2).getImm())
1114           .addImm(MI.getOperand(3).getImm()) // 'pred'
1115           .add(MI.getOperand(4))
1116           .add(condCodeOp()); // 's' bit
1117 
1118       MI.eraseFromParent();
1119       return true;
1120     }
1121     case ARM::t2MVNCCi:
1122     case ARM::MVNCCi: {
1123       unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
1124       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1125               MI.getOperand(1).getReg())
1126           .addImm(MI.getOperand(2).getImm())
1127           .addImm(MI.getOperand(3).getImm()) // 'pred'
1128           .add(MI.getOperand(4))
1129           .add(condCodeOp()); // 's' bit
1130 
1131       MI.eraseFromParent();
1132       return true;
1133     }
1134     case ARM::t2MOVCClsl:
1135     case ARM::t2MOVCClsr:
1136     case ARM::t2MOVCCasr:
1137     case ARM::t2MOVCCror: {
1138       unsigned NewOpc;
1139       switch (Opcode) {
1140       case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
1141       case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
1142       case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
1143       case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
1144       default: llvm_unreachable("unexpeced conditional move");
1145       }
1146       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1147               MI.getOperand(1).getReg())
1148           .add(MI.getOperand(2))
1149           .addImm(MI.getOperand(3).getImm())
1150           .addImm(MI.getOperand(4).getImm()) // 'pred'
1151           .add(MI.getOperand(5))
1152           .add(condCodeOp()); // 's' bit
1153       MI.eraseFromParent();
1154       return true;
1155     }
1156     case ARM::Int_eh_sjlj_dispatchsetup: {
1157       MachineFunction &MF = *MI.getParent()->getParent();
1158       const ARMBaseInstrInfo *AII =
1159         static_cast<const ARMBaseInstrInfo*>(TII);
1160       const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
1161       // For functions using a base pointer, we rematerialize it (via the frame
1162       // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
1163       // for us. Otherwise, expand to nothing.
1164       if (RI.hasBasePointer(MF)) {
1165         int32_t NumBytes = AFI->getFramePtrSpillOffset();
1166         unsigned FramePtr = RI.getFrameRegister(MF);
1167         assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
1168                "base pointer without frame pointer?");
1169 
1170         if (AFI->isThumb2Function()) {
1171           emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1172                                  FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
1173         } else if (AFI->isThumbFunction()) {
1174           emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1175                                     FramePtr, -NumBytes, *TII, RI);
1176         } else {
1177           emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1178                                   FramePtr, -NumBytes, ARMCC::AL, 0,
1179                                   *TII);
1180         }
1181         // If there's dynamic realignment, adjust for it.
1182         if (RI.needsStackRealignment(MF)) {
1183           MachineFrameInfo &MFI = MF.getFrameInfo();
1184           unsigned MaxAlign = MFI.getMaxAlignment();
1185           assert (!AFI->isThumb1OnlyFunction());
1186           // Emit bic r6, r6, MaxAlign
1187           assert(MaxAlign <= 256 && "The BIC instruction cannot encode "
1188                                     "immediates larger than 256 with all lower "
1189                                     "bits set.");
1190           unsigned bicOpc = AFI->isThumbFunction() ?
1191             ARM::t2BICri : ARM::BICri;
1192           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6)
1193               .addReg(ARM::R6, RegState::Kill)
1194               .addImm(MaxAlign - 1)
1195               .add(predOps(ARMCC::AL))
1196               .add(condCodeOp());
1197         }
1198 
1199       }
1200       MI.eraseFromParent();
1201       return true;
1202     }
1203 
1204     case ARM::MOVsrl_flag:
1205     case ARM::MOVsra_flag: {
1206       // These are just fancy MOVs instructions.
1207       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1208               MI.getOperand(0).getReg())
1209           .add(MI.getOperand(1))
1210           .addImm(ARM_AM::getSORegOpc(
1211               (Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1))
1212           .add(predOps(ARMCC::AL))
1213           .addReg(ARM::CPSR, RegState::Define);
1214       MI.eraseFromParent();
1215       return true;
1216     }
1217     case ARM::RRX: {
1218       // This encodes as "MOVs Rd, Rm, rrx
1219       MachineInstrBuilder MIB =
1220           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1221                   MI.getOperand(0).getReg())
1222               .add(MI.getOperand(1))
1223               .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))
1224               .add(predOps(ARMCC::AL))
1225               .add(condCodeOp());
1226       TransferImpOps(MI, MIB, MIB);
1227       MI.eraseFromParent();
1228       return true;
1229     }
1230     case ARM::tTPsoft:
1231     case ARM::TPsoft: {
1232       const bool Thumb = Opcode == ARM::tTPsoft;
1233 
1234       MachineInstrBuilder MIB;
1235       if (STI->genLongCalls()) {
1236         MachineFunction *MF = MBB.getParent();
1237         MachineConstantPool *MCP = MF->getConstantPool();
1238         unsigned PCLabelID = AFI->createPICLabelUId();
1239         MachineConstantPoolValue *CPV =
1240             ARMConstantPoolSymbol::Create(MF->getFunction()->getContext(),
1241                                           "__aeabi_read_tp", PCLabelID, 0);
1242         unsigned Reg = MI.getOperand(0).getReg();
1243         MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1244                       TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg)
1245                   .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
1246         if (!Thumb)
1247           MIB.addImm(0);
1248         MIB.add(predOps(ARMCC::AL));
1249 
1250         MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1251                       TII->get(Thumb ? ARM::tBLXr : ARM::BLX));
1252         if (Thumb)
1253           MIB.add(predOps(ARMCC::AL));
1254         MIB.addReg(Reg, RegState::Kill);
1255       } else {
1256         MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1257                       TII->get(Thumb ? ARM::tBL : ARM::BL));
1258         if (Thumb)
1259           MIB.add(predOps(ARMCC::AL));
1260         MIB.addExternalSymbol("__aeabi_read_tp", 0);
1261       }
1262 
1263       MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1264       TransferImpOps(MI, MIB, MIB);
1265       MI.eraseFromParent();
1266       return true;
1267     }
1268     case ARM::tLDRpci_pic:
1269     case ARM::t2LDRpci_pic: {
1270       unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
1271         ? ARM::tLDRpci : ARM::t2LDRpci;
1272       unsigned DstReg = MI.getOperand(0).getReg();
1273       bool DstIsDead = MI.getOperand(0).isDead();
1274       MachineInstrBuilder MIB1 =
1275           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewLdOpc), DstReg)
1276               .add(MI.getOperand(1))
1277               .add(predOps(ARMCC::AL));
1278       MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1279       MachineInstrBuilder MIB2 =
1280           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD))
1281               .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1282               .addReg(DstReg)
1283               .add(MI.getOperand(2));
1284       TransferImpOps(MI, MIB1, MIB2);
1285       MI.eraseFromParent();
1286       return true;
1287     }
1288 
1289     case ARM::LDRLIT_ga_abs:
1290     case ARM::LDRLIT_ga_pcrel:
1291     case ARM::LDRLIT_ga_pcrel_ldr:
1292     case ARM::tLDRLIT_ga_abs:
1293     case ARM::tLDRLIT_ga_pcrel: {
1294       unsigned DstReg = MI.getOperand(0).getReg();
1295       bool DstIsDead = MI.getOperand(0).isDead();
1296       const MachineOperand &MO1 = MI.getOperand(1);
1297       const GlobalValue *GV = MO1.getGlobal();
1298       bool IsARM =
1299           Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs;
1300       bool IsPIC =
1301           Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
1302       unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
1303       unsigned PICAddOpc =
1304           IsARM
1305               ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1306               : ARM::tPICADD;
1307 
1308       // We need a new const-pool entry to load from.
1309       MachineConstantPool *MCP = MBB.getParent()->getConstantPool();
1310       unsigned ARMPCLabelIndex = 0;
1311       MachineConstantPoolValue *CPV;
1312 
1313       if (IsPIC) {
1314         unsigned PCAdj = IsARM ? 8 : 4;
1315         ARMPCLabelIndex = AFI->createPICLabelUId();
1316         CPV = ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex,
1317                                               ARMCP::CPValue, PCAdj);
1318       } else
1319         CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier);
1320 
1321       MachineInstrBuilder MIB =
1322           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg)
1323             .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
1324       if (IsARM)
1325         MIB.addImm(0);
1326       MIB.add(predOps(ARMCC::AL));
1327 
1328       if (IsPIC) {
1329         MachineInstrBuilder MIB =
1330           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc))
1331             .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1332             .addReg(DstReg)
1333             .addImm(ARMPCLabelIndex);
1334 
1335         if (IsARM)
1336           MIB.add(predOps(ARMCC::AL));
1337       }
1338 
1339       MI.eraseFromParent();
1340       return true;
1341     }
1342     case ARM::MOV_ga_pcrel:
1343     case ARM::MOV_ga_pcrel_ldr:
1344     case ARM::t2MOV_ga_pcrel: {
1345       // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
1346       unsigned LabelId = AFI->createPICLabelUId();
1347       unsigned DstReg = MI.getOperand(0).getReg();
1348       bool DstIsDead = MI.getOperand(0).isDead();
1349       const MachineOperand &MO1 = MI.getOperand(1);
1350       const GlobalValue *GV = MO1.getGlobal();
1351       unsigned TF = MO1.getTargetFlags();
1352       bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
1353       unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
1354       unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
1355       unsigned LO16TF = TF | ARMII::MO_LO16;
1356       unsigned HI16TF = TF | ARMII::MO_HI16;
1357       unsigned PICAddOpc = isARM
1358         ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1359         : ARM::tPICADD;
1360       MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1361                                          TII->get(LO16Opc), DstReg)
1362         .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
1363         .addImm(LabelId);
1364 
1365       BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg)
1366         .addReg(DstReg)
1367         .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
1368         .addImm(LabelId);
1369 
1370       MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1371                                          TII->get(PICAddOpc))
1372         .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1373         .addReg(DstReg).addImm(LabelId);
1374       if (isARM) {
1375         MIB3.add(predOps(ARMCC::AL));
1376         if (Opcode == ARM::MOV_ga_pcrel_ldr)
1377           MIB3->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1378       }
1379       TransferImpOps(MI, MIB1, MIB3);
1380       MI.eraseFromParent();
1381       return true;
1382     }
1383 
1384     case ARM::MOVi32imm:
1385     case ARM::MOVCCi32imm:
1386     case ARM::t2MOVi32imm:
1387     case ARM::t2MOVCCi32imm:
1388       ExpandMOV32BitImm(MBB, MBBI);
1389       return true;
1390 
1391     case ARM::SUBS_PC_LR: {
1392       MachineInstrBuilder MIB =
1393           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
1394               .addReg(ARM::LR)
1395               .add(MI.getOperand(0))
1396               .add(MI.getOperand(1))
1397               .add(MI.getOperand(2))
1398               .addReg(ARM::CPSR, RegState::Undef);
1399       TransferImpOps(MI, MIB, MIB);
1400       MI.eraseFromParent();
1401       return true;
1402     }
1403     case ARM::VLDMQIA: {
1404       unsigned NewOpc = ARM::VLDMDIA;
1405       MachineInstrBuilder MIB =
1406         BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1407       unsigned OpIdx = 0;
1408 
1409       // Grab the Q register destination.
1410       bool DstIsDead = MI.getOperand(OpIdx).isDead();
1411       unsigned DstReg = MI.getOperand(OpIdx++).getReg();
1412 
1413       // Copy the source register.
1414       MIB.add(MI.getOperand(OpIdx++));
1415 
1416       // Copy the predicate operands.
1417       MIB.add(MI.getOperand(OpIdx++));
1418       MIB.add(MI.getOperand(OpIdx++));
1419 
1420       // Add the destination operands (D subregs).
1421       unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1422       unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1423       MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
1424         .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
1425 
1426       // Add an implicit def for the super-register.
1427       MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
1428       TransferImpOps(MI, MIB, MIB);
1429       MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1430       MI.eraseFromParent();
1431       return true;
1432     }
1433 
1434     case ARM::VSTMQIA: {
1435       unsigned NewOpc = ARM::VSTMDIA;
1436       MachineInstrBuilder MIB =
1437         BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1438       unsigned OpIdx = 0;
1439 
1440       // Grab the Q register source.
1441       bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1442       unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
1443 
1444       // Copy the destination register.
1445       MIB.add(MI.getOperand(OpIdx++));
1446 
1447       // Copy the predicate operands.
1448       MIB.add(MI.getOperand(OpIdx++));
1449       MIB.add(MI.getOperand(OpIdx++));
1450 
1451       // Add the source operands (D subregs).
1452       unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1453       unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1454       MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0)
1455          .addReg(D1, SrcIsKill ? RegState::Kill : 0);
1456 
1457       if (SrcIsKill)      // Add an implicit kill for the Q register.
1458         MIB->addRegisterKilled(SrcReg, TRI, true);
1459 
1460       TransferImpOps(MI, MIB, MIB);
1461       MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1462       MI.eraseFromParent();
1463       return true;
1464     }
1465 
1466     case ARM::VLD2q8Pseudo:
1467     case ARM::VLD2q16Pseudo:
1468     case ARM::VLD2q32Pseudo:
1469     case ARM::VLD2q8PseudoWB_fixed:
1470     case ARM::VLD2q16PseudoWB_fixed:
1471     case ARM::VLD2q32PseudoWB_fixed:
1472     case ARM::VLD2q8PseudoWB_register:
1473     case ARM::VLD2q16PseudoWB_register:
1474     case ARM::VLD2q32PseudoWB_register:
1475     case ARM::VLD3d8Pseudo:
1476     case ARM::VLD3d16Pseudo:
1477     case ARM::VLD3d32Pseudo:
1478     case ARM::VLD1d64TPseudo:
1479     case ARM::VLD1d64TPseudoWB_fixed:
1480     case ARM::VLD3d8Pseudo_UPD:
1481     case ARM::VLD3d16Pseudo_UPD:
1482     case ARM::VLD3d32Pseudo_UPD:
1483     case ARM::VLD3q8Pseudo_UPD:
1484     case ARM::VLD3q16Pseudo_UPD:
1485     case ARM::VLD3q32Pseudo_UPD:
1486     case ARM::VLD3q8oddPseudo:
1487     case ARM::VLD3q16oddPseudo:
1488     case ARM::VLD3q32oddPseudo:
1489     case ARM::VLD3q8oddPseudo_UPD:
1490     case ARM::VLD3q16oddPseudo_UPD:
1491     case ARM::VLD3q32oddPseudo_UPD:
1492     case ARM::VLD4d8Pseudo:
1493     case ARM::VLD4d16Pseudo:
1494     case ARM::VLD4d32Pseudo:
1495     case ARM::VLD1d64QPseudo:
1496     case ARM::VLD1d64QPseudoWB_fixed:
1497     case ARM::VLD4d8Pseudo_UPD:
1498     case ARM::VLD4d16Pseudo_UPD:
1499     case ARM::VLD4d32Pseudo_UPD:
1500     case ARM::VLD4q8Pseudo_UPD:
1501     case ARM::VLD4q16Pseudo_UPD:
1502     case ARM::VLD4q32Pseudo_UPD:
1503     case ARM::VLD4q8oddPseudo:
1504     case ARM::VLD4q16oddPseudo:
1505     case ARM::VLD4q32oddPseudo:
1506     case ARM::VLD4q8oddPseudo_UPD:
1507     case ARM::VLD4q16oddPseudo_UPD:
1508     case ARM::VLD4q32oddPseudo_UPD:
1509     case ARM::VLD3DUPd8Pseudo:
1510     case ARM::VLD3DUPd16Pseudo:
1511     case ARM::VLD3DUPd32Pseudo:
1512     case ARM::VLD3DUPd8Pseudo_UPD:
1513     case ARM::VLD3DUPd16Pseudo_UPD:
1514     case ARM::VLD3DUPd32Pseudo_UPD:
1515     case ARM::VLD4DUPd8Pseudo:
1516     case ARM::VLD4DUPd16Pseudo:
1517     case ARM::VLD4DUPd32Pseudo:
1518     case ARM::VLD4DUPd8Pseudo_UPD:
1519     case ARM::VLD4DUPd16Pseudo_UPD:
1520     case ARM::VLD4DUPd32Pseudo_UPD:
1521       ExpandVLD(MBBI);
1522       return true;
1523 
1524     case ARM::VST2q8Pseudo:
1525     case ARM::VST2q16Pseudo:
1526     case ARM::VST2q32Pseudo:
1527     case ARM::VST2q8PseudoWB_fixed:
1528     case ARM::VST2q16PseudoWB_fixed:
1529     case ARM::VST2q32PseudoWB_fixed:
1530     case ARM::VST2q8PseudoWB_register:
1531     case ARM::VST2q16PseudoWB_register:
1532     case ARM::VST2q32PseudoWB_register:
1533     case ARM::VST3d8Pseudo:
1534     case ARM::VST3d16Pseudo:
1535     case ARM::VST3d32Pseudo:
1536     case ARM::VST1d64TPseudo:
1537     case ARM::VST3d8Pseudo_UPD:
1538     case ARM::VST3d16Pseudo_UPD:
1539     case ARM::VST3d32Pseudo_UPD:
1540     case ARM::VST1d64TPseudoWB_fixed:
1541     case ARM::VST1d64TPseudoWB_register:
1542     case ARM::VST3q8Pseudo_UPD:
1543     case ARM::VST3q16Pseudo_UPD:
1544     case ARM::VST3q32Pseudo_UPD:
1545     case ARM::VST3q8oddPseudo:
1546     case ARM::VST3q16oddPseudo:
1547     case ARM::VST3q32oddPseudo:
1548     case ARM::VST3q8oddPseudo_UPD:
1549     case ARM::VST3q16oddPseudo_UPD:
1550     case ARM::VST3q32oddPseudo_UPD:
1551     case ARM::VST4d8Pseudo:
1552     case ARM::VST4d16Pseudo:
1553     case ARM::VST4d32Pseudo:
1554     case ARM::VST1d64QPseudo:
1555     case ARM::VST4d8Pseudo_UPD:
1556     case ARM::VST4d16Pseudo_UPD:
1557     case ARM::VST4d32Pseudo_UPD:
1558     case ARM::VST1d64QPseudoWB_fixed:
1559     case ARM::VST1d64QPseudoWB_register:
1560     case ARM::VST4q8Pseudo_UPD:
1561     case ARM::VST4q16Pseudo_UPD:
1562     case ARM::VST4q32Pseudo_UPD:
1563     case ARM::VST4q8oddPseudo:
1564     case ARM::VST4q16oddPseudo:
1565     case ARM::VST4q32oddPseudo:
1566     case ARM::VST4q8oddPseudo_UPD:
1567     case ARM::VST4q16oddPseudo_UPD:
1568     case ARM::VST4q32oddPseudo_UPD:
1569       ExpandVST(MBBI);
1570       return true;
1571 
1572     case ARM::VLD1LNq8Pseudo:
1573     case ARM::VLD1LNq16Pseudo:
1574     case ARM::VLD1LNq32Pseudo:
1575     case ARM::VLD1LNq8Pseudo_UPD:
1576     case ARM::VLD1LNq16Pseudo_UPD:
1577     case ARM::VLD1LNq32Pseudo_UPD:
1578     case ARM::VLD2LNd8Pseudo:
1579     case ARM::VLD2LNd16Pseudo:
1580     case ARM::VLD2LNd32Pseudo:
1581     case ARM::VLD2LNq16Pseudo:
1582     case ARM::VLD2LNq32Pseudo:
1583     case ARM::VLD2LNd8Pseudo_UPD:
1584     case ARM::VLD2LNd16Pseudo_UPD:
1585     case ARM::VLD2LNd32Pseudo_UPD:
1586     case ARM::VLD2LNq16Pseudo_UPD:
1587     case ARM::VLD2LNq32Pseudo_UPD:
1588     case ARM::VLD3LNd8Pseudo:
1589     case ARM::VLD3LNd16Pseudo:
1590     case ARM::VLD3LNd32Pseudo:
1591     case ARM::VLD3LNq16Pseudo:
1592     case ARM::VLD3LNq32Pseudo:
1593     case ARM::VLD3LNd8Pseudo_UPD:
1594     case ARM::VLD3LNd16Pseudo_UPD:
1595     case ARM::VLD3LNd32Pseudo_UPD:
1596     case ARM::VLD3LNq16Pseudo_UPD:
1597     case ARM::VLD3LNq32Pseudo_UPD:
1598     case ARM::VLD4LNd8Pseudo:
1599     case ARM::VLD4LNd16Pseudo:
1600     case ARM::VLD4LNd32Pseudo:
1601     case ARM::VLD4LNq16Pseudo:
1602     case ARM::VLD4LNq32Pseudo:
1603     case ARM::VLD4LNd8Pseudo_UPD:
1604     case ARM::VLD4LNd16Pseudo_UPD:
1605     case ARM::VLD4LNd32Pseudo_UPD:
1606     case ARM::VLD4LNq16Pseudo_UPD:
1607     case ARM::VLD4LNq32Pseudo_UPD:
1608     case ARM::VST1LNq8Pseudo:
1609     case ARM::VST1LNq16Pseudo:
1610     case ARM::VST1LNq32Pseudo:
1611     case ARM::VST1LNq8Pseudo_UPD:
1612     case ARM::VST1LNq16Pseudo_UPD:
1613     case ARM::VST1LNq32Pseudo_UPD:
1614     case ARM::VST2LNd8Pseudo:
1615     case ARM::VST2LNd16Pseudo:
1616     case ARM::VST2LNd32Pseudo:
1617     case ARM::VST2LNq16Pseudo:
1618     case ARM::VST2LNq32Pseudo:
1619     case ARM::VST2LNd8Pseudo_UPD:
1620     case ARM::VST2LNd16Pseudo_UPD:
1621     case ARM::VST2LNd32Pseudo_UPD:
1622     case ARM::VST2LNq16Pseudo_UPD:
1623     case ARM::VST2LNq32Pseudo_UPD:
1624     case ARM::VST3LNd8Pseudo:
1625     case ARM::VST3LNd16Pseudo:
1626     case ARM::VST3LNd32Pseudo:
1627     case ARM::VST3LNq16Pseudo:
1628     case ARM::VST3LNq32Pseudo:
1629     case ARM::VST3LNd8Pseudo_UPD:
1630     case ARM::VST3LNd16Pseudo_UPD:
1631     case ARM::VST3LNd32Pseudo_UPD:
1632     case ARM::VST3LNq16Pseudo_UPD:
1633     case ARM::VST3LNq32Pseudo_UPD:
1634     case ARM::VST4LNd8Pseudo:
1635     case ARM::VST4LNd16Pseudo:
1636     case ARM::VST4LNd32Pseudo:
1637     case ARM::VST4LNq16Pseudo:
1638     case ARM::VST4LNq32Pseudo:
1639     case ARM::VST4LNd8Pseudo_UPD:
1640     case ARM::VST4LNd16Pseudo_UPD:
1641     case ARM::VST4LNd32Pseudo_UPD:
1642     case ARM::VST4LNq16Pseudo_UPD:
1643     case ARM::VST4LNq32Pseudo_UPD:
1644       ExpandLaneOp(MBBI);
1645       return true;
1646 
1647     case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
1648     case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
1649     case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
1650     case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
1651 
1652     case ARM::CMP_SWAP_8:
1653       if (STI->isThumb())
1654         return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB,
1655                               ARM::tUXTB, NextMBBI);
1656       else
1657         return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB,
1658                               ARM::UXTB, NextMBBI);
1659     case ARM::CMP_SWAP_16:
1660       if (STI->isThumb())
1661         return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH,
1662                               ARM::tUXTH, NextMBBI);
1663       else
1664         return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH,
1665                               ARM::UXTH, NextMBBI);
1666     case ARM::CMP_SWAP_32:
1667       if (STI->isThumb())
1668         return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0,
1669                               NextMBBI);
1670       else
1671         return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI);
1672 
1673     case ARM::CMP_SWAP_64:
1674       return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI);
1675   }
1676 }
1677 
1678 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
1679   bool Modified = false;
1680 
1681   MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1682   while (MBBI != E) {
1683     MachineBasicBlock::iterator NMBBI = std::next(MBBI);
1684     Modified |= ExpandMI(MBB, MBBI, NMBBI);
1685     MBBI = NMBBI;
1686   }
1687 
1688   return Modified;
1689 }
1690 
1691 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1692   STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
1693   TII = STI->getInstrInfo();
1694   TRI = STI->getRegisterInfo();
1695   AFI = MF.getInfo<ARMFunctionInfo>();
1696 
1697   bool Modified = false;
1698   for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
1699        ++MFI)
1700     Modified |= ExpandMBB(*MFI);
1701   if (VerifyARMPseudo)
1702     MF.verify(this, "After expanding ARM pseudo instructions.");
1703   return Modified;
1704 }
1705 
1706 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1707 /// expansion pass.
1708 FunctionPass *llvm::createARMExpandPseudoPass() {
1709   return new ARMExpandPseudo();
1710 }
1711