1 //===- ARCExpandPseudosPass - ARC expand pseudo loads -----------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass expands stores with large offsets into an appropriate sequence.
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARC.h"
14 #include "ARCInstrInfo.h"
15 #include "ARCRegisterInfo.h"
16 #include "ARCSubtarget.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 
22 using namespace llvm;
23 
24 #define DEBUG_TYPE "arc-expand-pseudos"
25 
26 namespace {
27 
28 class ARCExpandPseudos : public MachineFunctionPass {
29 public:
30   static char ID;
31   ARCExpandPseudos() : MachineFunctionPass(ID) {}
32 
33   bool runOnMachineFunction(MachineFunction &Fn) override;
34 
35   StringRef getPassName() const override { return "ARC Expand Pseudos"; }
36 
37 private:
38   void ExpandStore(MachineFunction &, MachineBasicBlock::iterator);
39 
40   const ARCInstrInfo *TII;
41 };
42 
43 char ARCExpandPseudos::ID = 0;
44 
45 } // end anonymous namespace
46 
47 static unsigned getMappedOp(unsigned PseudoOp) {
48   switch (PseudoOp) {
49   case ARC::ST_FAR:
50     return ARC::ST_rs9;
51   case ARC::STH_FAR:
52     return ARC::STH_rs9;
53   case ARC::STB_FAR:
54     return ARC::STB_rs9;
55   default:
56     llvm_unreachable("Unhandled pseudo op.");
57   }
58 }
59 
60 void ARCExpandPseudos::ExpandStore(MachineFunction &MF,
61                                    MachineBasicBlock::iterator SII) {
62   MachineInstr &SI = *SII;
63   unsigned AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass);
64   unsigned AddOpc =
65       isUInt<6>(SI.getOperand(2).getImm()) ? ARC::ADD_rru6 : ARC::ADD_rrlimm;
66   BuildMI(*SI.getParent(), SI, SI.getDebugLoc(), TII->get(AddOpc), AddrReg)
67       .addReg(SI.getOperand(1).getReg())
68       .addImm(SI.getOperand(2).getImm());
69   BuildMI(*SI.getParent(), SI, SI.getDebugLoc(),
70           TII->get(getMappedOp(SI.getOpcode())))
71       .addReg(SI.getOperand(0).getReg())
72       .addReg(AddrReg)
73       .addImm(0);
74   SI.eraseFromParent();
75 }
76 
77 bool ARCExpandPseudos::runOnMachineFunction(MachineFunction &MF) {
78   const ARCSubtarget *STI = &MF.getSubtarget<ARCSubtarget>();
79   TII = STI->getInstrInfo();
80   bool ExpandedStore = false;
81   for (auto &MBB : MF) {
82     MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
83     while (MBBI != E) {
84       MachineBasicBlock::iterator NMBBI = std::next(MBBI);
85       switch (MBBI->getOpcode()) {
86       case ARC::ST_FAR:
87       case ARC::STH_FAR:
88       case ARC::STB_FAR:
89         ExpandStore(MF, MBBI);
90         ExpandedStore = true;
91         break;
92       default:
93         break;
94       }
95       MBBI = NMBBI;
96     }
97   }
98   return ExpandedStore;
99 }
100 
101 FunctionPass *llvm::createARCExpandPseudosPass() {
102   return new ARCExpandPseudos();
103 }
104