1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
12 
13 #include "AMDGPU.h"
14 #include "AMDKernelCodeT.h"
15 #include "SIDefines.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/IR/CallingConv.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/Support/Compiler.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include <cstdint>
22 #include <string>
23 #include <utility>
24 
25 namespace llvm {
26 
27 class Argument;
28 class FeatureBitset;
29 class Function;
30 class GlobalValue;
31 class MachineMemOperand;
32 class MCContext;
33 class MCRegisterClass;
34 class MCRegisterInfo;
35 class MCSection;
36 class MCSubtargetInfo;
37 class Triple;
38 
39 namespace AMDGPU {
40 namespace IsaInfo {
41 
42 enum {
43   // The closed Vulkan driver sets 96, which limits the wave count to 8 but
44   // doesn't spill SGPRs as much as when 80 is set.
45   FIXED_NUM_SGPRS_FOR_INIT_BUG = 96
46 };
47 
48 /// \brief Instruction set architecture version.
49 struct IsaVersion {
50   unsigned Major;
51   unsigned Minor;
52   unsigned Stepping;
53 };
54 
55 /// \returns Isa version for given subtarget \p Features.
56 IsaVersion getIsaVersion(const FeatureBitset &Features);
57 
58 /// \brief Streams isa version string for given subtarget \p STI into \p Stream.
59 void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream);
60 
61 /// \returns True if given subtarget \p Features support code object version 3,
62 /// false otherwise.
63 bool hasCodeObjectV3(const FeatureBitset &Features);
64 
65 /// \returns Wavefront size for given subtarget \p Features.
66 unsigned getWavefrontSize(const FeatureBitset &Features);
67 
68 /// \returns Local memory size in bytes for given subtarget \p Features.
69 unsigned getLocalMemorySize(const FeatureBitset &Features);
70 
71 /// \returns Number of execution units per compute unit for given subtarget \p
72 /// Features.
73 unsigned getEUsPerCU(const FeatureBitset &Features);
74 
75 /// \returns Maximum number of work groups per compute unit for given subtarget
76 /// \p Features and limited by given \p FlatWorkGroupSize.
77 unsigned getMaxWorkGroupsPerCU(const FeatureBitset &Features,
78                                unsigned FlatWorkGroupSize);
79 
80 /// \returns Maximum number of waves per compute unit for given subtarget \p
81 /// Features without any kind of limitation.
82 unsigned getMaxWavesPerCU(const FeatureBitset &Features);
83 
84 /// \returns Maximum number of waves per compute unit for given subtarget \p
85 /// Features and limited by given \p FlatWorkGroupSize.
86 unsigned getMaxWavesPerCU(const FeatureBitset &Features,
87                           unsigned FlatWorkGroupSize);
88 
89 /// \returns Minimum number of waves per execution unit for given subtarget \p
90 /// Features.
91 unsigned getMinWavesPerEU(const FeatureBitset &Features);
92 
93 /// \returns Maximum number of waves per execution unit for given subtarget \p
94 /// Features without any kind of limitation.
95 unsigned getMaxWavesPerEU(const FeatureBitset &Features);
96 
97 /// \returns Maximum number of waves per execution unit for given subtarget \p
98 /// Features and limited by given \p FlatWorkGroupSize.
99 unsigned getMaxWavesPerEU(const FeatureBitset &Features,
100                           unsigned FlatWorkGroupSize);
101 
102 /// \returns Minimum flat work group size for given subtarget \p Features.
103 unsigned getMinFlatWorkGroupSize(const FeatureBitset &Features);
104 
105 /// \returns Maximum flat work group size for given subtarget \p Features.
106 unsigned getMaxFlatWorkGroupSize(const FeatureBitset &Features);
107 
108 /// \returns Number of waves per work group for given subtarget \p Features and
109 /// limited by given \p FlatWorkGroupSize.
110 unsigned getWavesPerWorkGroup(const FeatureBitset &Features,
111                               unsigned FlatWorkGroupSize);
112 
113 /// \returns SGPR allocation granularity for given subtarget \p Features.
114 unsigned getSGPRAllocGranule(const FeatureBitset &Features);
115 
116 /// \returns SGPR encoding granularity for given subtarget \p Features.
117 unsigned getSGPREncodingGranule(const FeatureBitset &Features);
118 
119 /// \returns Total number of SGPRs for given subtarget \p Features.
120 unsigned getTotalNumSGPRs(const FeatureBitset &Features);
121 
122 /// \returns Addressable number of SGPRs for given subtarget \p Features.
123 unsigned getAddressableNumSGPRs(const FeatureBitset &Features);
124 
125 /// \returns Minimum number of SGPRs that meets the given number of waves per
126 /// execution unit requirement for given subtarget \p Features.
127 unsigned getMinNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
128 
129 /// \returns Maximum number of SGPRs that meets the given number of waves per
130 /// execution unit requirement for given subtarget \p Features.
131 unsigned getMaxNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU,
132                         bool Addressable);
133 
134 /// \returns VGPR allocation granularity for given subtarget \p Features.
135 unsigned getVGPRAllocGranule(const FeatureBitset &Features);
136 
137 /// \returns VGPR encoding granularity for given subtarget \p Features.
138 unsigned getVGPREncodingGranule(const FeatureBitset &Features);
139 
140 /// \returns Total number of VGPRs for given subtarget \p Features.
141 unsigned getTotalNumVGPRs(const FeatureBitset &Features);
142 
143 /// \returns Addressable number of VGPRs for given subtarget \p Features.
144 unsigned getAddressableNumVGPRs(const FeatureBitset &Features);
145 
146 /// \returns Minimum number of VGPRs that meets given number of waves per
147 /// execution unit requirement for given subtarget \p Features.
148 unsigned getMinNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
149 
150 /// \returns Maximum number of VGPRs that meets given number of waves per
151 /// execution unit requirement for given subtarget \p Features.
152 unsigned getMaxNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
153 
154 } // end namespace IsaInfo
155 
156 LLVM_READONLY
157 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
158 
159 LLVM_READONLY
160 int getMaskedMIMGOp(const MCInstrInfo &MII,
161                     unsigned Opc, unsigned NewChannels);
162 LLVM_READONLY
163 int getMCOpcode(uint16_t Opcode, unsigned Gen);
164 
165 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
166                                const FeatureBitset &Features);
167 
168 bool isGroupSegment(const GlobalValue *GV);
169 bool isGlobalSegment(const GlobalValue *GV);
170 bool isReadOnlySegment(const GlobalValue *GV);
171 
172 /// \returns True if constants should be emitted to .text section for given
173 /// target triple \p TT, false otherwise.
174 bool shouldEmitConstantsToTextSection(const Triple &TT);
175 
176 /// \returns Integer value requested using \p F's \p Name attribute.
177 ///
178 /// \returns \p Default if attribute is not present.
179 ///
180 /// \returns \p Default and emits error if requested value cannot be converted
181 /// to integer.
182 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
183 
184 /// \returns A pair of integer values requested using \p F's \p Name attribute
185 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
186 /// is false).
187 ///
188 /// \returns \p Default if attribute is not present.
189 ///
190 /// \returns \p Default and emits error if one of the requested values cannot be
191 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
192 /// not present.
193 std::pair<int, int> getIntegerPairAttribute(const Function &F,
194                                             StringRef Name,
195                                             std::pair<int, int> Default,
196                                             bool OnlyFirstRequired = false);
197 
198 /// \returns Vmcnt bit mask for given isa \p Version.
199 unsigned getVmcntBitMask(const IsaInfo::IsaVersion &Version);
200 
201 /// \returns Expcnt bit mask for given isa \p Version.
202 unsigned getExpcntBitMask(const IsaInfo::IsaVersion &Version);
203 
204 /// \returns Lgkmcnt bit mask for given isa \p Version.
205 unsigned getLgkmcntBitMask(const IsaInfo::IsaVersion &Version);
206 
207 /// \returns Waitcnt bit mask for given isa \p Version.
208 unsigned getWaitcntBitMask(const IsaInfo::IsaVersion &Version);
209 
210 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
211 unsigned decodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
212 
213 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
214 unsigned decodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
215 
216 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
217 unsigned decodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
218 
219 /// \brief Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
220 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
221 /// \p Lgkmcnt respectively.
222 ///
223 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
224 ///     \p Vmcnt = \p Waitcnt[3:0]                      (pre-gfx9 only)
225 ///     \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14]  (gfx9+ only)
226 ///     \p Expcnt = \p Waitcnt[6:4]
227 ///     \p Lgkmcnt = \p Waitcnt[11:8]
228 void decodeWaitcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
229                    unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
230 
231 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
232 unsigned encodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
233                      unsigned Vmcnt);
234 
235 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
236 unsigned encodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
237                       unsigned Expcnt);
238 
239 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
240 unsigned encodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
241                        unsigned Lgkmcnt);
242 
243 /// \brief Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
244 /// \p Version.
245 ///
246 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
247 ///     Waitcnt[3:0]   = \p Vmcnt       (pre-gfx9 only)
248 ///     Waitcnt[3:0]   = \p Vmcnt[3:0]  (gfx9+ only)
249 ///     Waitcnt[6:4]   = \p Expcnt
250 ///     Waitcnt[11:8]  = \p Lgkmcnt
251 ///     Waitcnt[15:14] = \p Vmcnt[5:4]  (gfx9+ only)
252 ///
253 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
254 /// isa \p Version.
255 unsigned encodeWaitcnt(const IsaInfo::IsaVersion &Version,
256                        unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
257 
258 unsigned getInitialPSInputAddr(const Function &F);
259 
260 LLVM_READNONE
261 bool isShader(CallingConv::ID CC);
262 
263 LLVM_READNONE
264 bool isCompute(CallingConv::ID CC);
265 
266 LLVM_READNONE
267 bool isEntryFunctionCC(CallingConv::ID CC);
268 
269 // FIXME: Remove this when calling conventions cleaned up
270 LLVM_READNONE
271 inline bool isKernel(CallingConv::ID CC) {
272   switch (CC) {
273   case CallingConv::AMDGPU_KERNEL:
274   case CallingConv::SPIR_KERNEL:
275     return true;
276   default:
277     return false;
278   }
279 }
280 
281 bool isSI(const MCSubtargetInfo &STI);
282 bool isCI(const MCSubtargetInfo &STI);
283 bool isVI(const MCSubtargetInfo &STI);
284 bool isGFX9(const MCSubtargetInfo &STI);
285 
286 /// \brief Is Reg - scalar register
287 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
288 
289 /// \brief Is there any intersection between registers
290 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
291 
292 /// If \p Reg is a pseudo reg, return the correct hardware register given
293 /// \p STI otherwise return \p Reg.
294 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
295 
296 /// \brief Convert hardware register \p Reg to a pseudo register
297 LLVM_READNONE
298 unsigned mc2PseudoReg(unsigned Reg);
299 
300 /// \brief Can this operand also contain immediate values?
301 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
302 
303 /// \brief Is this floating-point operand?
304 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
305 
306 /// \brief Does this opearnd support only inlinable literals?
307 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
308 
309 /// \brief Get the size in bits of a register from the register class \p RC.
310 unsigned getRegBitWidth(unsigned RCID);
311 
312 /// \brief Get the size in bits of a register from the register class \p RC.
313 unsigned getRegBitWidth(const MCRegisterClass &RC);
314 
315 /// \brief Get size of register operand
316 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
317                            unsigned OpNo);
318 
319 LLVM_READNONE
320 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
321   switch (OpInfo.OperandType) {
322   case AMDGPU::OPERAND_REG_IMM_INT32:
323   case AMDGPU::OPERAND_REG_IMM_FP32:
324   case AMDGPU::OPERAND_REG_INLINE_C_INT32:
325   case AMDGPU::OPERAND_REG_INLINE_C_FP32:
326     return 4;
327 
328   case AMDGPU::OPERAND_REG_IMM_INT64:
329   case AMDGPU::OPERAND_REG_IMM_FP64:
330   case AMDGPU::OPERAND_REG_INLINE_C_INT64:
331   case AMDGPU::OPERAND_REG_INLINE_C_FP64:
332     return 8;
333 
334   case AMDGPU::OPERAND_REG_IMM_INT16:
335   case AMDGPU::OPERAND_REG_IMM_FP16:
336   case AMDGPU::OPERAND_REG_INLINE_C_INT16:
337   case AMDGPU::OPERAND_REG_INLINE_C_FP16:
338   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
339   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
340     return 2;
341 
342   default:
343     llvm_unreachable("unhandled operand type");
344   }
345 }
346 
347 LLVM_READNONE
348 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
349   return getOperandSize(Desc.OpInfo[OpNo]);
350 }
351 
352 /// \brief Is this literal inlinable
353 LLVM_READNONE
354 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
355 
356 LLVM_READNONE
357 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
358 
359 LLVM_READNONE
360 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
361 
362 LLVM_READNONE
363 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
364 
365 bool isArgPassedInSGPR(const Argument *Arg);
366 
367 /// \returns The encoding that will be used for \p ByteOffset in the SMRD
368 /// offset field.
369 int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
370 
371 /// \returns true if this offset is small enough to fit in the SMRD
372 /// offset field.  \p ByteOffset should be the offset in bytes and
373 /// not the encoded offset.
374 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
375 
376 } // end namespace AMDGPU
377 } // end namespace llvm
378 
379 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
380