1 //===-- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA ---*- C++ -*--===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// This file contains declaration for AMDGPU ISA disassembler
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17 #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
18 
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
21 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
22 #include "llvm/MC/MCDisassembler/MCSymbolizer.h"
23 #include <algorithm>
24 #include <cstdint>
25 #include <memory>
26 
27 namespace llvm {
28 
29 class MCContext;
30 class MCInst;
31 class MCOperand;
32 class MCSubtargetInfo;
33 class Twine;
34 
35 //===----------------------------------------------------------------------===//
36 // AMDGPUDisassembler
37 //===----------------------------------------------------------------------===//
38 
39 class AMDGPUDisassembler : public MCDisassembler {
40 private:
41   mutable ArrayRef<uint8_t> Bytes;
42   mutable uint32_t Literal;
43   mutable bool HasLiteral;
44 
45 public:
46   AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
47     MCDisassembler(STI, Ctx) {}
48 
49   ~AMDGPUDisassembler() override = default;
50 
51   DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
52                               ArrayRef<uint8_t> Bytes, uint64_t Address,
53                               raw_ostream &WS, raw_ostream &CS) const override;
54 
55   const char* getRegClassName(unsigned RegClassID) const;
56 
57   MCOperand createRegOperand(unsigned int RegId) const;
58   MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
59   MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
60 
61   MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
62 
63   DecodeStatus tryDecodeInst(const uint8_t* Table,
64                               MCInst &MI,
65                               uint64_t Inst,
66                               uint64_t Address) const;
67 
68   DecodeStatus convertSDWAInst(MCInst &MI) const;
69 
70   MCOperand decodeOperand_VGPR_32(unsigned Val) const;
71   MCOperand decodeOperand_VS_32(unsigned Val) const;
72   MCOperand decodeOperand_VS_64(unsigned Val) const;
73   MCOperand decodeOperand_VS_128(unsigned Val) const;
74   MCOperand decodeOperand_VSrc16(unsigned Val) const;
75   MCOperand decodeOperand_VSrcV216(unsigned Val) const;
76 
77   MCOperand decodeOperand_VReg_64(unsigned Val) const;
78   MCOperand decodeOperand_VReg_96(unsigned Val) const;
79   MCOperand decodeOperand_VReg_128(unsigned Val) const;
80 
81   MCOperand decodeOperand_SReg_32(unsigned Val) const;
82   MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const;
83   MCOperand decodeOperand_SReg_64(unsigned Val) const;
84   MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const;
85   MCOperand decodeOperand_SReg_128(unsigned Val) const;
86   MCOperand decodeOperand_SReg_256(unsigned Val) const;
87   MCOperand decodeOperand_SReg_512(unsigned Val) const;
88 
89   enum OpWidthTy {
90     OPW32,
91     OPW64,
92     OPW128,
93     OPW16,
94     OPWV216,
95     OPW_LAST_,
96     OPW_FIRST_ = OPW32
97   };
98 
99   unsigned getVgprClassId(const OpWidthTy Width) const;
100   unsigned getSgprClassId(const OpWidthTy Width) const;
101   unsigned getTtmpClassId(const OpWidthTy Width) const;
102 
103   static MCOperand decodeIntImmed(unsigned Imm);
104   static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm);
105   MCOperand decodeLiteralConstant() const;
106 
107   MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const;
108   MCOperand decodeSpecialReg32(unsigned Val) const;
109   MCOperand decodeSpecialReg64(unsigned Val) const;
110 
111   MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const;
112   MCOperand decodeSDWASrc16(unsigned Val) const;
113   MCOperand decodeSDWASrc32(unsigned Val) const;
114   MCOperand decodeSDWAVopcDst(unsigned Val) const;
115 };
116 
117 //===----------------------------------------------------------------------===//
118 // AMDGPUSymbolizer
119 //===----------------------------------------------------------------------===//
120 
121 class AMDGPUSymbolizer : public MCSymbolizer {
122 private:
123   void *DisInfo;
124 
125 public:
126   AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
127                    void *disInfo)
128                    : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
129 
130   bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
131                                 int64_t Value, uint64_t Address,
132                                 bool IsBranch, uint64_t Offset,
133                                 uint64_t InstSize) override;
134 
135   void tryAddingPcLoadReferenceComment(raw_ostream &cStream,
136                                        int64_t Value,
137                                        uint64_t Address) override;
138 };
139 
140 } // end namespace llvm
141 
142 #endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
143