1 //===-- AMDGPUTargetTransformInfo.h - AMDGPU specific TTI -------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// AMDGPU target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
14 ///
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
19 
20 #include "AMDGPU.h"
21 #include "AMDGPUTargetMachine.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/BasicTTIImpl.h"
24 
25 namespace llvm {
26 class AMDGPUTargetLowering;
27 
28 class AMDGPUTTIImpl final : public BasicTTIImplBase<AMDGPUTTIImpl> {
29   typedef BasicTTIImplBase<AMDGPUTTIImpl> BaseT;
30   typedef TargetTransformInfo TTI;
31   friend BaseT;
32 
33   const AMDGPUSubtarget *ST;
34   const AMDGPUTargetLowering *TLI;
35   bool IsGraphicsShader;
36 
37   const AMDGPUSubtarget *getST() const { return ST; }
38   const AMDGPUTargetLowering *getTLI() const { return TLI; }
39 
40 
41   static inline int getFullRateInstrCost() {
42     return TargetTransformInfo::TCC_Basic;
43   }
44 
45   static inline int getHalfRateInstrCost() {
46     return 2 * TargetTransformInfo::TCC_Basic;
47   }
48 
49   // TODO: The size is usually 8 bytes, but takes 4x as many cycles. Maybe
50   // should be 2 or 4.
51   static inline int getQuarterRateInstrCost() {
52     return 3 * TargetTransformInfo::TCC_Basic;
53   }
54 
55    // On some parts, normal fp64 operations are half rate, and others
56    // quarter. This also applies to some integer operations.
57   inline int get64BitInstrCost() const {
58     return ST->hasHalfRate64Ops() ?
59       getHalfRateInstrCost() : getQuarterRateInstrCost();
60   }
61 
62 public:
63   explicit AMDGPUTTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
64     : BaseT(TM, F.getParent()->getDataLayout()),
65       ST(TM->getSubtargetImpl(F)),
66       TLI(ST->getTargetLowering()),
67       IsGraphicsShader(AMDGPU::isShader(F.getCallingConv())) {}
68 
69   bool hasBranchDivergence() { return true; }
70 
71   void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
72                                TTI::UnrollingPreferences &UP);
73 
74   TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) {
75     assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
76     return TTI::PSK_FastHardware;
77   }
78 
79   unsigned getHardwareNumberOfRegisters(bool Vector) const;
80   unsigned getNumberOfRegisters(bool Vector) const;
81   unsigned getRegisterBitWidth(bool Vector) const ;
82   unsigned getMinVectorRegisterBitWidth() const;
83   unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
84 
85   bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes,
86                                   unsigned Alignment,
87                                   unsigned AddrSpace) const;
88   bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
89                                    unsigned Alignment,
90                                    unsigned AddrSpace) const;
91   bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
92                                     unsigned Alignment,
93                                     unsigned AddrSpace) const;
94 
95   unsigned getMaxInterleaveFactor(unsigned VF);
96 
97   int getArithmeticInstrCost(
98     unsigned Opcode, Type *Ty,
99     TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
100     TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
101     TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
102     TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
103     ArrayRef<const Value *> Args = ArrayRef<const Value *>());
104 
105   unsigned getCFInstrCost(unsigned Opcode);
106 
107   int getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index);
108   bool isSourceOfDivergence(const Value *V) const;
109   bool isAlwaysUniform(const Value *V) const;
110 
111   unsigned getFlatAddressSpace() const {
112     // Don't bother running InferAddressSpaces pass on graphics shaders which
113     // don't use flat addressing.
114     if (IsGraphicsShader)
115       return -1;
116     return ST->hasFlatAddressSpace() ?
117       ST->getAMDGPUAS().FLAT_ADDRESS : ST->getAMDGPUAS().UNKNOWN_ADDRESS_SPACE;
118   }
119 
120   unsigned getVectorSplitCost() { return 0; }
121 
122   unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
123                           Type *SubTp);
124 };
125 
126 } // end namespace llvm
127 
128 #endif
129