1 //===-- AMDGPUSubtarget.cpp - AMDGPU Subtarget Information ----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Implements the AMDGPU specific subclass of TargetSubtarget.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUSubtarget.h"
16 #include "R600ISelLowering.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineScheduler.h"
19 #include "SIFrameLowering.h"
20 #include "SIISelLowering.h"
21 #include "SIInstrInfo.h"
22 #include "SIMachineFunctionInfo.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/CodeGen/MachineScheduler.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "amdgpu-subtarget"
29 
30 #define GET_SUBTARGETINFO_ENUM
31 #define GET_SUBTARGETINFO_TARGET_DESC
32 #define GET_SUBTARGETINFO_CTOR
33 #include "AMDGPUGenSubtargetInfo.inc"
34 
35 AMDGPUSubtarget &
36 AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT,
37                                                  StringRef GPU, StringRef FS) {
38   // Determine default and user-specified characteristics
39   // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be
40   // enabled, but some instructions do not respect them and they run at the
41   // double precision rate, so don't enable by default.
42   //
43   // We want to be able to turn these off, but making this a subtarget feature
44   // for SI has the unhelpful behavior that it unsets everything else if you
45   // disable it.
46 
47   SmallString<256> FullFS("+promote-alloca,+fp64-denormals,");
48   if (isAmdHsaOS()) // Turn on FlatForGlobal for HSA.
49     FullFS += "+flat-for-global,";
50   FullFS += FS;
51 
52   if (GPU == "" && TT.getArch() == Triple::amdgcn)
53     GPU = "SI";
54 
55   ParseSubtargetFeatures(GPU, FullFS);
56 
57   // FIXME: I don't think think Evergreen has any useful support for
58   // denormals, but should be checked. Should we issue a warning somewhere
59   // if someone tries to enable these?
60   if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
61     FP32Denormals = false;
62     FP64Denormals = false;
63   }
64   return *this;
65 }
66 
67 AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
68                                  TargetMachine &TM)
69     : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false),
70       DumpCode(false), R600ALUInst(false), HasVertexCache(false),
71       TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
72       FP64Denormals(false), FP32Denormals(false), FastFMAF32(false),
73       CaymanISA(false), FlatAddressSpace(false), FlatForGlobal(false),
74       EnableIRStructurizer(true), EnablePromoteAlloca(false), EnableIfCvt(true),
75       EnableLoadStoreOpt(false), EnableUnsafeDSOffsetFolding(false),
76       EnableXNACK(false),
77       WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
78       EnableVGPRSpilling(false), SGPRInitBug(false), IsGCN(false),
79       GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), LDSBankCount(0),
80       IsaVersion(ISAVersion0_0_0), EnableHugeScratchBuffer(false),
81       EnableSIScheduler(false), FrameLowering(nullptr),
82       InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) {
83 
84   initializeSubtargetDependencies(TT, GPU, FS);
85 
86   const unsigned MaxStackAlign = 64 * 16; // Maximum stack alignment (long16)
87 
88   if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
89     InstrInfo.reset(new R600InstrInfo(*this));
90     TLInfo.reset(new R600TargetLowering(TM, *this));
91 
92     // FIXME: Should have R600 specific FrameLowering
93     FrameLowering.reset(new AMDGPUFrameLowering(
94                           TargetFrameLowering::StackGrowsUp,
95                           MaxStackAlign,
96                           0));
97   } else {
98     InstrInfo.reset(new SIInstrInfo(*this));
99     TLInfo.reset(new SITargetLowering(TM, *this));
100     FrameLowering.reset(new SIFrameLowering(
101                           TargetFrameLowering::StackGrowsUp,
102                           MaxStackAlign,
103                           0));
104   }
105 }
106 
107 unsigned AMDGPUSubtarget::getStackEntrySize() const {
108   assert(getGeneration() <= NORTHERN_ISLANDS);
109   switch(getWavefrontSize()) {
110   case 16:
111     return 8;
112   case 32:
113     return hasCaymanISA() ? 4 : 8;
114   case 64:
115     return 4;
116   default:
117     llvm_unreachable("Illegal wavefront size.");
118   }
119 }
120 
121 unsigned AMDGPUSubtarget::getAmdKernelCodeChipID() const {
122   switch(getGeneration()) {
123   default: llvm_unreachable("ChipID unknown");
124   case SEA_ISLANDS: return 12;
125   }
126 }
127 
128 AMDGPU::IsaVersion AMDGPUSubtarget::getIsaVersion() const {
129   return AMDGPU::getIsaVersion(getFeatureBits());
130 }
131 
132 bool AMDGPUSubtarget::isVGPRSpillingEnabled(
133                                        const SIMachineFunctionInfo *MFI) const {
134   return MFI->getShaderType() == ShaderType::COMPUTE || EnableVGPRSpilling;
135 }
136 
137 void AMDGPUSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
138                                           MachineInstr *begin,
139                                           MachineInstr *end,
140                                           unsigned NumRegionInstrs) const {
141   if (getGeneration() >= SOUTHERN_ISLANDS) {
142 
143     // Track register pressure so the scheduler can try to decrease
144     // pressure once register usage is above the threshold defined by
145     // SIRegisterInfo::getRegPressureSetLimit()
146     Policy.ShouldTrackPressure = true;
147 
148     // Enabling both top down and bottom up scheduling seems to give us less
149     // register spills than just using one of these approaches on its own.
150     Policy.OnlyTopDown = false;
151     Policy.OnlyBottomUp = false;
152   }
153 }
154 
155